1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 default: 157 return -EINVAL; 158 } 159 return ret; 160 } 161 162 static int psp_early_init(struct amdgpu_ip_block *ip_block) 163 { 164 struct amdgpu_device *adev = ip_block->adev; 165 struct psp_context *psp = &adev->psp; 166 167 psp->autoload_supported = true; 168 psp->boot_time_tmr = true; 169 170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 171 case IP_VERSION(9, 0, 0): 172 psp_v3_1_set_psp_funcs(psp); 173 psp->autoload_supported = false; 174 psp->boot_time_tmr = false; 175 break; 176 case IP_VERSION(10, 0, 0): 177 case IP_VERSION(10, 0, 1): 178 psp_v10_0_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(11, 0, 2): 183 case IP_VERSION(11, 0, 4): 184 psp_v11_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 0): 189 case IP_VERSION(11, 0, 7): 190 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 191 fallthrough; 192 case IP_VERSION(11, 0, 5): 193 case IP_VERSION(11, 0, 9): 194 case IP_VERSION(11, 0, 11): 195 case IP_VERSION(11, 5, 0): 196 case IP_VERSION(11, 0, 12): 197 case IP_VERSION(11, 0, 13): 198 psp_v11_0_set_psp_funcs(psp); 199 psp->boot_time_tmr = false; 200 break; 201 case IP_VERSION(11, 0, 3): 202 case IP_VERSION(12, 0, 1): 203 psp_v12_0_set_psp_funcs(psp); 204 psp->autoload_supported = false; 205 psp->boot_time_tmr = false; 206 break; 207 case IP_VERSION(13, 0, 2): 208 psp->boot_time_tmr = false; 209 fallthrough; 210 case IP_VERSION(13, 0, 6): 211 case IP_VERSION(13, 0, 14): 212 psp_v13_0_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 break; 215 case IP_VERSION(13, 0, 1): 216 case IP_VERSION(13, 0, 3): 217 case IP_VERSION(13, 0, 5): 218 case IP_VERSION(13, 0, 8): 219 case IP_VERSION(13, 0, 11): 220 case IP_VERSION(14, 0, 0): 221 case IP_VERSION(14, 0, 1): 222 case IP_VERSION(14, 0, 4): 223 psp_v13_0_set_psp_funcs(psp); 224 psp->boot_time_tmr = false; 225 break; 226 case IP_VERSION(11, 0, 8): 227 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 228 psp_v11_0_8_set_psp_funcs(psp); 229 } 230 psp->autoload_supported = false; 231 psp->boot_time_tmr = false; 232 break; 233 case IP_VERSION(13, 0, 0): 234 case IP_VERSION(13, 0, 7): 235 case IP_VERSION(13, 0, 10): 236 psp_v13_0_set_psp_funcs(psp); 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 psp->boot_time_tmr = false; 239 break; 240 case IP_VERSION(13, 0, 4): 241 psp_v13_0_4_set_psp_funcs(psp); 242 psp->boot_time_tmr = false; 243 break; 244 case IP_VERSION(14, 0, 2): 245 case IP_VERSION(14, 0, 3): 246 psp_v14_0_set_psp_funcs(psp); 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 psp->adev = adev; 253 254 adev->psp_timeout = 20000; 255 256 psp_check_pmfw_centralized_cstate_management(psp); 257 258 if (amdgpu_sriov_vf(adev)) 259 return psp_init_sriov_microcode(psp); 260 else 261 return psp_init_microcode(psp); 262 } 263 264 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 265 { 266 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 267 &mem_ctx->shared_buf); 268 mem_ctx->shared_bo = NULL; 269 } 270 271 static void psp_free_shared_bufs(struct psp_context *psp) 272 { 273 void *tmr_buf; 274 void **pptr; 275 276 /* free TMR memory buffer */ 277 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 278 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 279 psp->tmr_bo = NULL; 280 281 /* free xgmi shared memory */ 282 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 283 284 /* free ras shared memory */ 285 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 286 287 /* free hdcp shared memory */ 288 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 289 290 /* free dtm shared memory */ 291 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 292 293 /* free rap shared memory */ 294 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 295 296 /* free securedisplay shared memory */ 297 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 298 299 300 } 301 302 static void psp_memory_training_fini(struct psp_context *psp) 303 { 304 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 305 306 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 307 kfree(ctx->sys_cache); 308 ctx->sys_cache = NULL; 309 } 310 311 static int psp_memory_training_init(struct psp_context *psp) 312 { 313 int ret; 314 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 315 316 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 317 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 318 return 0; 319 } 320 321 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 322 if (ctx->sys_cache == NULL) { 323 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 324 ret = -ENOMEM; 325 goto Err_out; 326 } 327 328 dev_dbg(psp->adev->dev, 329 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 330 ctx->train_data_size, 331 ctx->p2c_train_data_offset, 332 ctx->c2p_train_data_offset); 333 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 334 return 0; 335 336 Err_out: 337 psp_memory_training_fini(psp); 338 return ret; 339 } 340 341 /* 342 * Helper funciton to query psp runtime database entry 343 * 344 * @adev: amdgpu_device pointer 345 * @entry_type: the type of psp runtime database entry 346 * @db_entry: runtime database entry pointer 347 * 348 * Return false if runtime database doesn't exit or entry is invalid 349 * or true if the specific database entry is found, and copy to @db_entry 350 */ 351 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 352 enum psp_runtime_entry_type entry_type, 353 void *db_entry) 354 { 355 uint64_t db_header_pos, db_dir_pos; 356 struct psp_runtime_data_header db_header = {0}; 357 struct psp_runtime_data_directory db_dir = {0}; 358 bool ret = false; 359 int i; 360 361 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 362 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 363 return false; 364 365 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 366 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 367 368 /* read runtime db header from vram */ 369 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 370 sizeof(struct psp_runtime_data_header), false); 371 372 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 373 /* runtime db doesn't exist, exit */ 374 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 375 return false; 376 } 377 378 /* read runtime database entry from vram */ 379 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 380 sizeof(struct psp_runtime_data_directory), false); 381 382 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 383 /* invalid db entry count, exit */ 384 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 385 return false; 386 } 387 388 /* look up for requested entry type */ 389 for (i = 0; i < db_dir.entry_count && !ret; i++) { 390 if (db_dir.entry_list[i].entry_type == entry_type) { 391 switch (entry_type) { 392 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 393 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 394 /* invalid db entry size */ 395 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 396 return false; 397 } 398 /* read runtime database entry */ 399 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 400 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 401 ret = true; 402 break; 403 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 404 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 405 /* invalid db entry size */ 406 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 407 return false; 408 } 409 /* read runtime database entry */ 410 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 411 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 412 ret = true; 413 break; 414 default: 415 ret = false; 416 break; 417 } 418 } 419 } 420 421 return ret; 422 } 423 424 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 425 { 426 struct amdgpu_device *adev = ip_block->adev; 427 struct psp_context *psp = &adev->psp; 428 int ret; 429 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 430 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 431 struct psp_runtime_scpm_entry scpm_entry; 432 433 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 434 if (!psp->cmd) { 435 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 436 ret = -ENOMEM; 437 } 438 439 adev->psp.xgmi_context.supports_extended_data = 440 !adev->gmc.xgmi.connected_to_cpu && 441 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 442 443 memset(&scpm_entry, 0, sizeof(scpm_entry)); 444 if ((psp_get_runtime_db_entry(adev, 445 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 446 &scpm_entry)) && 447 (scpm_entry.scpm_status != SCPM_DISABLE)) { 448 adev->scpm_enabled = true; 449 adev->scpm_status = scpm_entry.scpm_status; 450 } else { 451 adev->scpm_enabled = false; 452 adev->scpm_status = SCPM_DISABLE; 453 } 454 455 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 456 457 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 458 if (psp_get_runtime_db_entry(adev, 459 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 460 &boot_cfg_entry)) { 461 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 462 if ((psp->boot_cfg_bitmask) & 463 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 464 /* If psp runtime database exists, then 465 * only enable two stage memory training 466 * when TWO_STAGE_DRAM_TRAINING bit is set 467 * in runtime database 468 */ 469 mem_training_ctx->enable_mem_training = true; 470 } 471 472 } else { 473 /* If psp runtime database doesn't exist or is 474 * invalid, force enable two stage memory training 475 */ 476 mem_training_ctx->enable_mem_training = true; 477 } 478 479 if (mem_training_ctx->enable_mem_training) { 480 ret = psp_memory_training_init(psp); 481 if (ret) { 482 dev_err(adev->dev, "Failed to initialize memory training!\n"); 483 return ret; 484 } 485 486 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 487 if (ret) { 488 dev_err(adev->dev, "Failed to process memory training!\n"); 489 return ret; 490 } 491 } 492 493 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 494 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 495 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 496 &psp->fw_pri_bo, 497 &psp->fw_pri_mc_addr, 498 &psp->fw_pri_buf); 499 if (ret) 500 return ret; 501 502 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 503 AMDGPU_GEM_DOMAIN_VRAM | 504 AMDGPU_GEM_DOMAIN_GTT, 505 &psp->fence_buf_bo, 506 &psp->fence_buf_mc_addr, 507 &psp->fence_buf); 508 if (ret) 509 goto failed1; 510 511 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 512 AMDGPU_GEM_DOMAIN_VRAM | 513 AMDGPU_GEM_DOMAIN_GTT, 514 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 515 (void **)&psp->cmd_buf_mem); 516 if (ret) 517 goto failed2; 518 519 return 0; 520 521 failed2: 522 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 523 &psp->fence_buf_mc_addr, &psp->fence_buf); 524 failed1: 525 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 526 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 527 return ret; 528 } 529 530 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 531 { 532 struct amdgpu_device *adev = ip_block->adev; 533 struct psp_context *psp = &adev->psp; 534 struct psp_gfx_cmd_resp *cmd = psp->cmd; 535 536 psp_memory_training_fini(psp); 537 538 amdgpu_ucode_release(&psp->sos_fw); 539 amdgpu_ucode_release(&psp->asd_fw); 540 amdgpu_ucode_release(&psp->ta_fw); 541 amdgpu_ucode_release(&psp->cap_fw); 542 amdgpu_ucode_release(&psp->toc_fw); 543 544 kfree(cmd); 545 cmd = NULL; 546 547 psp_free_shared_bufs(psp); 548 549 if (psp->km_ring.ring_mem) 550 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 551 &psp->km_ring.ring_mem_mc_addr, 552 (void **)&psp->km_ring.ring_mem); 553 554 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 555 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 556 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 557 &psp->fence_buf_mc_addr, &psp->fence_buf); 558 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 559 (void **)&psp->cmd_buf_mem); 560 561 return 0; 562 } 563 564 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 565 uint32_t reg_val, uint32_t mask, bool check_changed) 566 { 567 uint32_t val; 568 int i; 569 struct amdgpu_device *adev = psp->adev; 570 571 if (psp->adev->no_hw_access) 572 return 0; 573 574 for (i = 0; i < adev->usec_timeout; i++) { 575 val = RREG32(reg_index); 576 if (check_changed) { 577 if (val != reg_val) 578 return 0; 579 } else { 580 if ((val & mask) == reg_val) 581 return 0; 582 } 583 udelay(1); 584 } 585 586 return -ETIME; 587 } 588 589 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 590 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 591 { 592 uint32_t val; 593 int i; 594 struct amdgpu_device *adev = psp->adev; 595 596 if (psp->adev->no_hw_access) 597 return 0; 598 599 for (i = 0; i < msec_timeout; i++) { 600 val = RREG32(reg_index); 601 if ((val & mask) == reg_val) 602 return 0; 603 msleep(1); 604 } 605 606 return -ETIME; 607 } 608 609 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 610 { 611 switch (cmd_id) { 612 case GFX_CMD_ID_LOAD_TA: 613 return "LOAD_TA"; 614 case GFX_CMD_ID_UNLOAD_TA: 615 return "UNLOAD_TA"; 616 case GFX_CMD_ID_INVOKE_CMD: 617 return "INVOKE_CMD"; 618 case GFX_CMD_ID_LOAD_ASD: 619 return "LOAD_ASD"; 620 case GFX_CMD_ID_SETUP_TMR: 621 return "SETUP_TMR"; 622 case GFX_CMD_ID_LOAD_IP_FW: 623 return "LOAD_IP_FW"; 624 case GFX_CMD_ID_DESTROY_TMR: 625 return "DESTROY_TMR"; 626 case GFX_CMD_ID_SAVE_RESTORE: 627 return "SAVE_RESTORE_IP_FW"; 628 case GFX_CMD_ID_SETUP_VMR: 629 return "SETUP_VMR"; 630 case GFX_CMD_ID_DESTROY_VMR: 631 return "DESTROY_VMR"; 632 case GFX_CMD_ID_PROG_REG: 633 return "PROG_REG"; 634 case GFX_CMD_ID_GET_FW_ATTESTATION: 635 return "GET_FW_ATTESTATION"; 636 case GFX_CMD_ID_LOAD_TOC: 637 return "ID_LOAD_TOC"; 638 case GFX_CMD_ID_AUTOLOAD_RLC: 639 return "AUTOLOAD_RLC"; 640 case GFX_CMD_ID_BOOT_CFG: 641 return "BOOT_CFG"; 642 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 643 return "CONFIG_SQ_PERFMON"; 644 default: 645 return "UNKNOWN CMD"; 646 } 647 } 648 649 static bool psp_err_warn(struct psp_context *psp) 650 { 651 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 652 653 /* This response indicates reg list is already loaded */ 654 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 655 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 656 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 657 cmd->resp.status == TEE_ERROR_CANCEL) 658 return false; 659 660 return true; 661 } 662 663 static int 664 psp_cmd_submit_buf(struct psp_context *psp, 665 struct amdgpu_firmware_info *ucode, 666 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 667 { 668 int ret; 669 int index; 670 int timeout = psp->adev->psp_timeout; 671 bool ras_intr = false; 672 bool skip_unsupport = false; 673 674 if (psp->adev->no_hw_access) 675 return 0; 676 677 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 678 679 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 680 681 index = atomic_inc_return(&psp->fence_value); 682 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 683 if (ret) { 684 atomic_dec(&psp->fence_value); 685 goto exit; 686 } 687 688 amdgpu_device_invalidate_hdp(psp->adev, NULL); 689 while (*((unsigned int *)psp->fence_buf) != index) { 690 if (--timeout == 0) 691 break; 692 /* 693 * Shouldn't wait for timeout when err_event_athub occurs, 694 * because gpu reset thread triggered and lock resource should 695 * be released for psp resume sequence. 696 */ 697 ras_intr = amdgpu_ras_intr_triggered(); 698 if (ras_intr) 699 break; 700 usleep_range(10, 100); 701 amdgpu_device_invalidate_hdp(psp->adev, NULL); 702 } 703 704 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 705 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 706 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 707 708 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 709 710 /* In some cases, psp response status is not 0 even there is no 711 * problem while the command is submitted. Some version of PSP FW 712 * doesn't write 0 to that field. 713 * So here we would like to only print a warning instead of an error 714 * during psp initialization to avoid breaking hw_init and it doesn't 715 * return -EINVAL. 716 */ 717 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 718 if (ucode) 719 dev_warn(psp->adev->dev, 720 "failed to load ucode %s(0x%X) ", 721 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 722 if (psp_err_warn(psp)) 723 dev_warn( 724 psp->adev->dev, 725 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 726 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 727 psp->cmd_buf_mem->cmd_id, 728 psp->cmd_buf_mem->resp.status); 729 /* If any firmware (including CAP) load fails under SRIOV, it should 730 * return failure to stop the VF from initializing. 731 * Also return failure in case of timeout 732 */ 733 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 734 ret = -EINVAL; 735 goto exit; 736 } 737 } 738 739 if (ucode) { 740 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 741 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 742 } 743 744 exit: 745 return ret; 746 } 747 748 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 749 { 750 struct psp_gfx_cmd_resp *cmd = psp->cmd; 751 752 mutex_lock(&psp->mutex); 753 754 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 755 756 return cmd; 757 } 758 759 static void release_psp_cmd_buf(struct psp_context *psp) 760 { 761 mutex_unlock(&psp->mutex); 762 } 763 764 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 765 struct psp_gfx_cmd_resp *cmd, 766 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 767 { 768 struct amdgpu_device *adev = psp->adev; 769 uint32_t size = 0; 770 uint64_t tmr_pa = 0; 771 772 if (tmr_bo) { 773 size = amdgpu_bo_size(tmr_bo); 774 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 775 } 776 777 if (amdgpu_sriov_vf(psp->adev)) 778 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 779 else 780 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 781 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 782 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 783 cmd->cmd.cmd_setup_tmr.buf_size = size; 784 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 785 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 786 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 787 } 788 789 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 790 uint64_t pri_buf_mc, uint32_t size) 791 { 792 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 793 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 794 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 795 cmd->cmd.cmd_load_toc.toc_size = size; 796 } 797 798 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 799 static int psp_load_toc(struct psp_context *psp, 800 uint32_t *tmr_size) 801 { 802 int ret; 803 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 804 805 /* Copy toc to psp firmware private buffer */ 806 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 807 808 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 809 810 ret = psp_cmd_submit_buf(psp, NULL, cmd, 811 psp->fence_buf_mc_addr); 812 if (!ret) 813 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 814 815 release_psp_cmd_buf(psp); 816 817 return ret; 818 } 819 820 /* Set up Trusted Memory Region */ 821 static int psp_tmr_init(struct psp_context *psp) 822 { 823 int ret = 0; 824 int tmr_size; 825 void *tmr_buf; 826 void **pptr; 827 828 /* 829 * According to HW engineer, they prefer the TMR address be "naturally 830 * aligned" , e.g. the start address be an integer divide of TMR size. 831 * 832 * Note: this memory need be reserved till the driver 833 * uninitializes. 834 */ 835 tmr_size = PSP_TMR_SIZE(psp->adev); 836 837 /* For ASICs support RLC autoload, psp will parse the toc 838 * and calculate the total size of TMR needed 839 */ 840 if (!amdgpu_sriov_vf(psp->adev) && 841 psp->toc.start_addr && 842 psp->toc.size_bytes && 843 psp->fw_pri_buf) { 844 ret = psp_load_toc(psp, &tmr_size); 845 if (ret) { 846 dev_err(psp->adev->dev, "Failed to load toc\n"); 847 return ret; 848 } 849 } 850 851 if (!psp->tmr_bo && !psp->boot_time_tmr) { 852 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 853 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 854 PSP_TMR_ALIGNMENT, 855 AMDGPU_HAS_VRAM(psp->adev) ? 856 AMDGPU_GEM_DOMAIN_VRAM : 857 AMDGPU_GEM_DOMAIN_GTT, 858 &psp->tmr_bo, &psp->tmr_mc_addr, 859 pptr); 860 } 861 862 return ret; 863 } 864 865 static bool psp_skip_tmr(struct psp_context *psp) 866 { 867 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 868 case IP_VERSION(11, 0, 9): 869 case IP_VERSION(11, 0, 7): 870 case IP_VERSION(13, 0, 2): 871 case IP_VERSION(13, 0, 6): 872 case IP_VERSION(13, 0, 10): 873 case IP_VERSION(13, 0, 14): 874 return true; 875 default: 876 return false; 877 } 878 } 879 880 static int psp_tmr_load(struct psp_context *psp) 881 { 882 int ret; 883 struct psp_gfx_cmd_resp *cmd; 884 885 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 886 * Already set up by host driver. 887 */ 888 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 889 return 0; 890 891 cmd = acquire_psp_cmd_buf(psp); 892 893 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 894 if (psp->tmr_bo) 895 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 896 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 897 898 ret = psp_cmd_submit_buf(psp, NULL, cmd, 899 psp->fence_buf_mc_addr); 900 901 release_psp_cmd_buf(psp); 902 903 return ret; 904 } 905 906 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 907 struct psp_gfx_cmd_resp *cmd) 908 { 909 if (amdgpu_sriov_vf(psp->adev)) 910 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 911 else 912 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 913 } 914 915 static int psp_tmr_unload(struct psp_context *psp) 916 { 917 int ret; 918 struct psp_gfx_cmd_resp *cmd; 919 920 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 921 * as TMR is not loaded at all 922 */ 923 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 924 return 0; 925 926 cmd = acquire_psp_cmd_buf(psp); 927 928 psp_prep_tmr_unload_cmd_buf(psp, cmd); 929 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, 932 psp->fence_buf_mc_addr); 933 934 release_psp_cmd_buf(psp); 935 936 return ret; 937 } 938 939 static int psp_tmr_terminate(struct psp_context *psp) 940 { 941 return psp_tmr_unload(psp); 942 } 943 944 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 945 uint64_t *output_ptr) 946 { 947 int ret; 948 struct psp_gfx_cmd_resp *cmd; 949 950 if (!output_ptr) 951 return -EINVAL; 952 953 if (amdgpu_sriov_vf(psp->adev)) 954 return 0; 955 956 cmd = acquire_psp_cmd_buf(psp); 957 958 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 959 960 ret = psp_cmd_submit_buf(psp, NULL, cmd, 961 psp->fence_buf_mc_addr); 962 963 if (!ret) { 964 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 965 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 966 } 967 968 release_psp_cmd_buf(psp); 969 970 return ret; 971 } 972 973 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 974 { 975 struct psp_context *psp = &adev->psp; 976 struct psp_gfx_cmd_resp *cmd; 977 int ret; 978 979 if (amdgpu_sriov_vf(adev)) 980 return 0; 981 982 cmd = acquire_psp_cmd_buf(psp); 983 984 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 985 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 986 987 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 988 if (!ret) { 989 *boot_cfg = 990 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 991 } 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 999 { 1000 int ret; 1001 struct psp_context *psp = &adev->psp; 1002 struct psp_gfx_cmd_resp *cmd; 1003 1004 if (amdgpu_sriov_vf(adev)) 1005 return 0; 1006 1007 cmd = acquire_psp_cmd_buf(psp); 1008 1009 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1010 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1011 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1012 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1013 1014 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1015 1016 release_psp_cmd_buf(psp); 1017 1018 return ret; 1019 } 1020 1021 static int psp_rl_load(struct amdgpu_device *adev) 1022 { 1023 int ret; 1024 struct psp_context *psp = &adev->psp; 1025 struct psp_gfx_cmd_resp *cmd; 1026 1027 if (!is_psp_fw_valid(psp->rl)) 1028 return 0; 1029 1030 cmd = acquire_psp_cmd_buf(psp); 1031 1032 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1033 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1034 1035 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1036 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1037 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1038 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1039 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1040 1041 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1042 1043 release_psp_cmd_buf(psp); 1044 1045 return ret; 1046 } 1047 1048 int psp_memory_partition(struct psp_context *psp, int mode) 1049 { 1050 struct psp_gfx_cmd_resp *cmd; 1051 int ret; 1052 1053 if (amdgpu_sriov_vf(psp->adev)) 1054 return 0; 1055 1056 cmd = acquire_psp_cmd_buf(psp); 1057 1058 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1059 cmd->cmd.cmd_memory_part.mode = mode; 1060 1061 dev_info(psp->adev->dev, 1062 "Requesting %d memory partition change through PSP", mode); 1063 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1064 if (ret) 1065 dev_err(psp->adev->dev, 1066 "PSP request failed to change to NPS%d mode\n", mode); 1067 1068 release_psp_cmd_buf(psp); 1069 1070 return ret; 1071 } 1072 1073 int psp_spatial_partition(struct psp_context *psp, int mode) 1074 { 1075 struct psp_gfx_cmd_resp *cmd; 1076 int ret; 1077 1078 if (amdgpu_sriov_vf(psp->adev)) 1079 return 0; 1080 1081 cmd = acquire_psp_cmd_buf(psp); 1082 1083 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1084 cmd->cmd.cmd_spatial_part.mode = mode; 1085 1086 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1087 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1088 1089 release_psp_cmd_buf(psp); 1090 1091 return ret; 1092 } 1093 1094 static int psp_asd_initialize(struct psp_context *psp) 1095 { 1096 int ret; 1097 1098 /* If PSP version doesn't match ASD version, asd loading will be failed. 1099 * add workaround to bypass it for sriov now. 1100 * TODO: add version check to make it common 1101 */ 1102 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1103 return 0; 1104 1105 /* bypass asd if display hardware is not available */ 1106 if (!amdgpu_device_has_display_hardware(psp->adev) && 1107 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1108 return 0; 1109 1110 psp->asd_context.mem_context.shared_mc_addr = 0; 1111 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1112 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1113 1114 ret = psp_ta_load(psp, &psp->asd_context); 1115 if (!ret) 1116 psp->asd_context.initialized = true; 1117 1118 return ret; 1119 } 1120 1121 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1122 uint32_t session_id) 1123 { 1124 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1125 cmd->cmd.cmd_unload_ta.session_id = session_id; 1126 } 1127 1128 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1129 { 1130 int ret; 1131 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1132 1133 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1134 1135 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1136 1137 context->resp_status = cmd->resp.status; 1138 1139 release_psp_cmd_buf(psp); 1140 1141 return ret; 1142 } 1143 1144 static int psp_asd_terminate(struct psp_context *psp) 1145 { 1146 int ret; 1147 1148 if (amdgpu_sriov_vf(psp->adev)) 1149 return 0; 1150 1151 if (!psp->asd_context.initialized) 1152 return 0; 1153 1154 ret = psp_ta_unload(psp, &psp->asd_context); 1155 if (!ret) 1156 psp->asd_context.initialized = false; 1157 1158 return ret; 1159 } 1160 1161 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1162 uint32_t id, uint32_t value) 1163 { 1164 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1165 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1166 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1167 } 1168 1169 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1170 uint32_t value) 1171 { 1172 struct psp_gfx_cmd_resp *cmd; 1173 int ret = 0; 1174 1175 if (reg >= PSP_REG_LAST) 1176 return -EINVAL; 1177 1178 cmd = acquire_psp_cmd_buf(psp); 1179 1180 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1181 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1182 if (ret) 1183 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1184 1185 release_psp_cmd_buf(psp); 1186 1187 return ret; 1188 } 1189 1190 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1191 uint64_t ta_bin_mc, 1192 struct ta_context *context) 1193 { 1194 cmd->cmd_id = context->ta_load_type; 1195 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1196 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1197 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1198 1199 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1200 lower_32_bits(context->mem_context.shared_mc_addr); 1201 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1202 upper_32_bits(context->mem_context.shared_mc_addr); 1203 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1204 } 1205 1206 int psp_ta_init_shared_buf(struct psp_context *psp, 1207 struct ta_mem_context *mem_ctx) 1208 { 1209 /* 1210 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1211 * physical) for ta to host memory 1212 */ 1213 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1214 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1215 AMDGPU_GEM_DOMAIN_GTT, 1216 &mem_ctx->shared_bo, 1217 &mem_ctx->shared_mc_addr, 1218 &mem_ctx->shared_buf); 1219 } 1220 1221 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1222 uint32_t ta_cmd_id, 1223 uint32_t session_id) 1224 { 1225 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1226 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1227 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1228 } 1229 1230 int psp_ta_invoke(struct psp_context *psp, 1231 uint32_t ta_cmd_id, 1232 struct ta_context *context) 1233 { 1234 int ret; 1235 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1236 1237 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1238 1239 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1240 psp->fence_buf_mc_addr); 1241 1242 context->resp_status = cmd->resp.status; 1243 1244 release_psp_cmd_buf(psp); 1245 1246 return ret; 1247 } 1248 1249 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1250 { 1251 int ret; 1252 struct psp_gfx_cmd_resp *cmd; 1253 1254 cmd = acquire_psp_cmd_buf(psp); 1255 1256 psp_copy_fw(psp, context->bin_desc.start_addr, 1257 context->bin_desc.size_bytes); 1258 1259 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1260 1261 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1262 psp->fence_buf_mc_addr); 1263 1264 context->resp_status = cmd->resp.status; 1265 1266 if (!ret) 1267 context->session_id = cmd->resp.session_id; 1268 1269 release_psp_cmd_buf(psp); 1270 1271 return ret; 1272 } 1273 1274 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1275 { 1276 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1277 } 1278 1279 int psp_xgmi_terminate(struct psp_context *psp) 1280 { 1281 int ret; 1282 struct amdgpu_device *adev = psp->adev; 1283 1284 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1285 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1286 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1287 adev->gmc.xgmi.connected_to_cpu)) 1288 return 0; 1289 1290 if (!psp->xgmi_context.context.initialized) 1291 return 0; 1292 1293 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1294 1295 psp->xgmi_context.context.initialized = false; 1296 1297 return ret; 1298 } 1299 1300 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1301 { 1302 struct ta_xgmi_shared_memory *xgmi_cmd; 1303 int ret; 1304 1305 if (!psp->ta_fw || 1306 !psp->xgmi_context.context.bin_desc.size_bytes || 1307 !psp->xgmi_context.context.bin_desc.start_addr) 1308 return -ENOENT; 1309 1310 if (!load_ta) 1311 goto invoke; 1312 1313 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1314 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1315 1316 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1317 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1318 if (ret) 1319 return ret; 1320 } 1321 1322 /* Load XGMI TA */ 1323 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1324 if (!ret) 1325 psp->xgmi_context.context.initialized = true; 1326 else 1327 return ret; 1328 1329 invoke: 1330 /* Initialize XGMI session */ 1331 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1332 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1333 xgmi_cmd->flag_extend_link_record = set_extended_data; 1334 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1335 1336 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1337 /* note down the capbility flag for XGMI TA */ 1338 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1339 1340 return ret; 1341 } 1342 1343 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1344 { 1345 struct ta_xgmi_shared_memory *xgmi_cmd; 1346 int ret; 1347 1348 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1349 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1350 1351 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1352 1353 /* Invoke xgmi ta to get hive id */ 1354 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1355 if (ret) 1356 return ret; 1357 1358 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1359 1360 return 0; 1361 } 1362 1363 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1364 { 1365 struct ta_xgmi_shared_memory *xgmi_cmd; 1366 int ret; 1367 1368 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1369 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1370 1371 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1372 1373 /* Invoke xgmi ta to get the node id */ 1374 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1375 if (ret) 1376 return ret; 1377 1378 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1379 1380 return 0; 1381 } 1382 1383 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1384 { 1385 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1386 IP_VERSION(13, 0, 2) && 1387 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1388 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1389 IP_VERSION(13, 0, 6); 1390 } 1391 1392 /* 1393 * Chips that support extended topology information require the driver to 1394 * reflect topology information in the opposite direction. This is 1395 * because the TA has already exceeded its link record limit and if the 1396 * TA holds bi-directional information, the driver would have to do 1397 * multiple fetches instead of just two. 1398 */ 1399 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1400 struct psp_xgmi_node_info node_info) 1401 { 1402 struct amdgpu_device *mirror_adev; 1403 struct amdgpu_hive_info *hive; 1404 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1405 uint64_t dst_node_id = node_info.node_id; 1406 uint8_t dst_num_hops = node_info.num_hops; 1407 uint8_t dst_num_links = node_info.num_links; 1408 1409 hive = amdgpu_get_xgmi_hive(psp->adev); 1410 if (WARN_ON(!hive)) 1411 return; 1412 1413 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1414 struct psp_xgmi_topology_info *mirror_top_info; 1415 int j; 1416 1417 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1418 continue; 1419 1420 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1421 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1422 if (mirror_top_info->nodes[j].node_id != src_node_id) 1423 continue; 1424 1425 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1426 /* 1427 * prevent 0 num_links value re-reflection since reflection 1428 * criteria is based on num_hops (direct or indirect). 1429 * 1430 */ 1431 if (dst_num_links) 1432 mirror_top_info->nodes[j].num_links = dst_num_links; 1433 1434 break; 1435 } 1436 1437 break; 1438 } 1439 1440 amdgpu_put_xgmi_hive(hive); 1441 } 1442 1443 int psp_xgmi_get_topology_info(struct psp_context *psp, 1444 int number_devices, 1445 struct psp_xgmi_topology_info *topology, 1446 bool get_extended_data) 1447 { 1448 struct ta_xgmi_shared_memory *xgmi_cmd; 1449 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1450 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1451 int i; 1452 int ret; 1453 1454 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1455 return -EINVAL; 1456 1457 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1458 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1459 xgmi_cmd->flag_extend_link_record = get_extended_data; 1460 1461 /* Fill in the shared memory with topology information as input */ 1462 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1463 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1464 topology_info_input->num_nodes = number_devices; 1465 1466 for (i = 0; i < topology_info_input->num_nodes; i++) { 1467 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1468 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1469 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1470 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1471 } 1472 1473 /* Invoke xgmi ta to get the topology information */ 1474 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1475 if (ret) 1476 return ret; 1477 1478 /* Read the output topology information from the shared memory */ 1479 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1480 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1481 for (i = 0; i < topology->num_nodes; i++) { 1482 /* extended data will either be 0 or equal to non-extended data */ 1483 if (topology_info_output->nodes[i].num_hops) 1484 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1485 1486 /* non-extended data gets everything here so no need to update */ 1487 if (!get_extended_data) { 1488 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1489 topology->nodes[i].is_sharing_enabled = 1490 topology_info_output->nodes[i].is_sharing_enabled; 1491 topology->nodes[i].sdma_engine = 1492 topology_info_output->nodes[i].sdma_engine; 1493 } 1494 1495 } 1496 1497 /* Invoke xgmi ta again to get the link information */ 1498 if (psp_xgmi_peer_link_info_supported(psp)) { 1499 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1500 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1501 bool requires_reflection = 1502 (psp->xgmi_context.supports_extended_data && 1503 get_extended_data) || 1504 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1505 IP_VERSION(13, 0, 6) || 1506 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1507 IP_VERSION(13, 0, 14); 1508 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1509 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1510 1511 /* popluate the shared output buffer rather than the cmd input buffer 1512 * with node_ids as the input for GET_PEER_LINKS command execution. 1513 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1514 * The same requirement for GET_EXTEND_PEER_LINKS command. 1515 */ 1516 if (ta_port_num_support) { 1517 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1518 1519 for (i = 0; i < topology->num_nodes; i++) 1520 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1521 1522 link_extend_info_output->num_nodes = topology->num_nodes; 1523 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1524 } else { 1525 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1526 1527 for (i = 0; i < topology->num_nodes; i++) 1528 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1529 1530 link_info_output->num_nodes = topology->num_nodes; 1531 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1532 } 1533 1534 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1535 if (ret) 1536 return ret; 1537 1538 for (i = 0; i < topology->num_nodes; i++) { 1539 uint8_t node_num_links = ta_port_num_support ? 1540 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1541 /* accumulate num_links on extended data */ 1542 if (get_extended_data) { 1543 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1544 } else { 1545 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1546 topology->nodes[i].num_links : node_num_links; 1547 } 1548 /* popluate the connected port num info if supported and available */ 1549 if (ta_port_num_support && topology->nodes[i].num_links) { 1550 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1551 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1552 } 1553 1554 /* reflect the topology information for bi-directionality */ 1555 if (requires_reflection && topology->nodes[i].num_hops) 1556 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1557 } 1558 } 1559 1560 return 0; 1561 } 1562 1563 int psp_xgmi_set_topology_info(struct psp_context *psp, 1564 int number_devices, 1565 struct psp_xgmi_topology_info *topology) 1566 { 1567 struct ta_xgmi_shared_memory *xgmi_cmd; 1568 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1569 int i; 1570 1571 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1572 return -EINVAL; 1573 1574 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1575 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1576 1577 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1578 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1579 topology_info_input->num_nodes = number_devices; 1580 1581 for (i = 0; i < topology_info_input->num_nodes; i++) { 1582 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1583 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1584 topology_info_input->nodes[i].is_sharing_enabled = 1; 1585 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1586 } 1587 1588 /* Invoke xgmi ta to set topology information */ 1589 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1590 } 1591 1592 // ras begin 1593 static void psp_ras_ta_check_status(struct psp_context *psp) 1594 { 1595 struct ta_ras_shared_memory *ras_cmd = 1596 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1597 1598 switch (ras_cmd->ras_status) { 1599 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1600 dev_warn(psp->adev->dev, 1601 "RAS WARNING: cmd failed due to unsupported ip\n"); 1602 break; 1603 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1604 dev_warn(psp->adev->dev, 1605 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1606 break; 1607 case TA_RAS_STATUS__SUCCESS: 1608 break; 1609 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1610 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1611 dev_warn(psp->adev->dev, 1612 "RAS WARNING: Inject error to critical region is not allowed\n"); 1613 break; 1614 default: 1615 dev_warn(psp->adev->dev, 1616 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1617 break; 1618 } 1619 } 1620 1621 static int psp_ras_send_cmd(struct psp_context *psp, 1622 enum ras_command cmd_id, void *in, void *out) 1623 { 1624 struct ta_ras_shared_memory *ras_cmd; 1625 uint32_t cmd = cmd_id; 1626 int ret = 0; 1627 1628 if (!in) 1629 return -EINVAL; 1630 1631 mutex_lock(&psp->ras_context.mutex); 1632 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1633 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1634 1635 switch (cmd) { 1636 case TA_RAS_COMMAND__ENABLE_FEATURES: 1637 case TA_RAS_COMMAND__DISABLE_FEATURES: 1638 memcpy(&ras_cmd->ras_in_message, 1639 in, sizeof(ras_cmd->ras_in_message)); 1640 break; 1641 case TA_RAS_COMMAND__TRIGGER_ERROR: 1642 memcpy(&ras_cmd->ras_in_message.trigger_error, 1643 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1644 break; 1645 case TA_RAS_COMMAND__QUERY_ADDRESS: 1646 memcpy(&ras_cmd->ras_in_message.address, 1647 in, sizeof(ras_cmd->ras_in_message.address)); 1648 break; 1649 default: 1650 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1651 ret = -EINVAL; 1652 goto err_out; 1653 } 1654 1655 ras_cmd->cmd_id = cmd; 1656 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1657 1658 switch (cmd) { 1659 case TA_RAS_COMMAND__TRIGGER_ERROR: 1660 if (!ret && out) 1661 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1662 break; 1663 case TA_RAS_COMMAND__QUERY_ADDRESS: 1664 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1665 ret = -EINVAL; 1666 else if (out) 1667 memcpy(out, 1668 &ras_cmd->ras_out_message.address, 1669 sizeof(ras_cmd->ras_out_message.address)); 1670 break; 1671 default: 1672 break; 1673 } 1674 1675 err_out: 1676 mutex_unlock(&psp->ras_context.mutex); 1677 1678 return ret; 1679 } 1680 1681 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1682 { 1683 struct ta_ras_shared_memory *ras_cmd; 1684 int ret; 1685 1686 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1687 1688 /* 1689 * TODO: bypass the loading in sriov for now 1690 */ 1691 if (amdgpu_sriov_vf(psp->adev)) 1692 return 0; 1693 1694 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1695 1696 if (amdgpu_ras_intr_triggered()) 1697 return ret; 1698 1699 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1700 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1701 return -EINVAL; 1702 } 1703 1704 if (!ret) { 1705 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1706 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1707 1708 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1709 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1710 dev_warn(psp->adev->dev, 1711 "RAS internal register access blocked\n"); 1712 1713 psp_ras_ta_check_status(psp); 1714 } 1715 1716 return ret; 1717 } 1718 1719 int psp_ras_enable_features(struct psp_context *psp, 1720 union ta_ras_cmd_input *info, bool enable) 1721 { 1722 enum ras_command cmd_id; 1723 int ret; 1724 1725 if (!psp->ras_context.context.initialized || !info) 1726 return -EINVAL; 1727 1728 cmd_id = enable ? 1729 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1730 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1731 if (ret) 1732 return -EINVAL; 1733 1734 return 0; 1735 } 1736 1737 int psp_ras_terminate(struct psp_context *psp) 1738 { 1739 int ret; 1740 1741 /* 1742 * TODO: bypass the terminate in sriov for now 1743 */ 1744 if (amdgpu_sriov_vf(psp->adev)) 1745 return 0; 1746 1747 if (!psp->ras_context.context.initialized) 1748 return 0; 1749 1750 ret = psp_ta_unload(psp, &psp->ras_context.context); 1751 1752 psp->ras_context.context.initialized = false; 1753 1754 mutex_destroy(&psp->ras_context.mutex); 1755 1756 return ret; 1757 } 1758 1759 int psp_ras_initialize(struct psp_context *psp) 1760 { 1761 int ret; 1762 uint32_t boot_cfg = 0xFF; 1763 struct amdgpu_device *adev = psp->adev; 1764 struct ta_ras_shared_memory *ras_cmd; 1765 1766 /* 1767 * TODO: bypass the initialize in sriov for now 1768 */ 1769 if (amdgpu_sriov_vf(adev)) 1770 return 0; 1771 1772 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1773 !adev->psp.ras_context.context.bin_desc.start_addr) { 1774 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1775 return 0; 1776 } 1777 1778 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1779 /* query GECC enablement status from boot config 1780 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1781 */ 1782 ret = psp_boot_config_get(adev, &boot_cfg); 1783 if (ret) 1784 dev_warn(adev->dev, "PSP get boot config failed\n"); 1785 1786 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1787 if (!boot_cfg) { 1788 dev_info(adev->dev, "GECC is disabled\n"); 1789 } else { 1790 /* disable GECC in next boot cycle if ras is 1791 * disabled by module parameter amdgpu_ras_enable 1792 * and/or amdgpu_ras_mask, or boot_config_get call 1793 * is failed 1794 */ 1795 ret = psp_boot_config_set(adev, 0); 1796 if (ret) 1797 dev_warn(adev->dev, "PSP set boot config failed\n"); 1798 else 1799 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1800 } 1801 } else { 1802 if (boot_cfg == 1) { 1803 dev_info(adev->dev, "GECC is enabled\n"); 1804 } else { 1805 /* enable GECC in next boot cycle if it is disabled 1806 * in boot config, or force enable GECC if failed to 1807 * get boot configuration 1808 */ 1809 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1810 if (ret) 1811 dev_warn(adev->dev, "PSP set boot config failed\n"); 1812 else 1813 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1814 } 1815 } 1816 } 1817 1818 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1819 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1820 1821 if (!psp->ras_context.context.mem_context.shared_buf) { 1822 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1823 if (ret) 1824 return ret; 1825 } 1826 1827 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1828 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1829 1830 if (amdgpu_ras_is_poison_mode_supported(adev)) 1831 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1832 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1833 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1834 ras_cmd->ras_in_message.init_flags.xcc_mask = 1835 adev->gfx.xcc_mask; 1836 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1837 1838 ret = psp_ta_load(psp, &psp->ras_context.context); 1839 1840 if (!ret && !ras_cmd->ras_status) { 1841 psp->ras_context.context.initialized = true; 1842 mutex_init(&psp->ras_context.mutex); 1843 } else { 1844 if (ras_cmd->ras_status) 1845 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1846 1847 /* fail to load RAS TA */ 1848 psp->ras_context.context.initialized = false; 1849 } 1850 1851 return ret; 1852 } 1853 1854 int psp_ras_trigger_error(struct psp_context *psp, 1855 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1856 { 1857 struct amdgpu_device *adev = psp->adev; 1858 int ret; 1859 uint32_t dev_mask; 1860 uint32_t ras_status = 0; 1861 1862 if (!psp->ras_context.context.initialized || !info) 1863 return -EINVAL; 1864 1865 switch (info->block_id) { 1866 case TA_RAS_BLOCK__GFX: 1867 dev_mask = GET_MASK(GC, instance_mask); 1868 break; 1869 case TA_RAS_BLOCK__SDMA: 1870 dev_mask = GET_MASK(SDMA0, instance_mask); 1871 break; 1872 case TA_RAS_BLOCK__VCN: 1873 case TA_RAS_BLOCK__JPEG: 1874 dev_mask = GET_MASK(VCN, instance_mask); 1875 break; 1876 default: 1877 dev_mask = instance_mask; 1878 break; 1879 } 1880 1881 /* reuse sub_block_index for backward compatibility */ 1882 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1883 dev_mask &= AMDGPU_RAS_INST_MASK; 1884 info->sub_block_index |= dev_mask; 1885 1886 ret = psp_ras_send_cmd(psp, 1887 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 1888 if (ret) 1889 return -EINVAL; 1890 1891 /* If err_event_athub occurs error inject was successful, however 1892 * return status from TA is no long reliable 1893 */ 1894 if (amdgpu_ras_intr_triggered()) 1895 return 0; 1896 1897 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1898 return -EACCES; 1899 else if (ras_status) 1900 return -EINVAL; 1901 1902 return 0; 1903 } 1904 1905 int psp_ras_query_address(struct psp_context *psp, 1906 struct ta_ras_query_address_input *addr_in, 1907 struct ta_ras_query_address_output *addr_out) 1908 { 1909 int ret; 1910 1911 if (!psp->ras_context.context.initialized || 1912 !addr_in || !addr_out) 1913 return -EINVAL; 1914 1915 ret = psp_ras_send_cmd(psp, 1916 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 1917 1918 return ret; 1919 } 1920 // ras end 1921 1922 // HDCP start 1923 static int psp_hdcp_initialize(struct psp_context *psp) 1924 { 1925 int ret; 1926 1927 /* 1928 * TODO: bypass the initialize in sriov for now 1929 */ 1930 if (amdgpu_sriov_vf(psp->adev)) 1931 return 0; 1932 1933 /* bypass hdcp initialization if dmu is harvested */ 1934 if (!amdgpu_device_has_display_hardware(psp->adev)) 1935 return 0; 1936 1937 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1938 !psp->hdcp_context.context.bin_desc.start_addr) { 1939 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1940 return 0; 1941 } 1942 1943 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1944 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1945 1946 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1947 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1948 if (ret) 1949 return ret; 1950 } 1951 1952 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1953 if (!ret) { 1954 psp->hdcp_context.context.initialized = true; 1955 mutex_init(&psp->hdcp_context.mutex); 1956 } 1957 1958 return ret; 1959 } 1960 1961 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1962 { 1963 /* 1964 * TODO: bypass the loading in sriov for now 1965 */ 1966 if (amdgpu_sriov_vf(psp->adev)) 1967 return 0; 1968 1969 if (!psp->hdcp_context.context.initialized) 1970 return 0; 1971 1972 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1973 } 1974 1975 static int psp_hdcp_terminate(struct psp_context *psp) 1976 { 1977 int ret; 1978 1979 /* 1980 * TODO: bypass the terminate in sriov for now 1981 */ 1982 if (amdgpu_sriov_vf(psp->adev)) 1983 return 0; 1984 1985 if (!psp->hdcp_context.context.initialized) 1986 return 0; 1987 1988 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1989 1990 psp->hdcp_context.context.initialized = false; 1991 1992 return ret; 1993 } 1994 // HDCP end 1995 1996 // DTM start 1997 static int psp_dtm_initialize(struct psp_context *psp) 1998 { 1999 int ret; 2000 2001 /* 2002 * TODO: bypass the initialize in sriov for now 2003 */ 2004 if (amdgpu_sriov_vf(psp->adev)) 2005 return 0; 2006 2007 /* bypass dtm initialization if dmu is harvested */ 2008 if (!amdgpu_device_has_display_hardware(psp->adev)) 2009 return 0; 2010 2011 if (!psp->dtm_context.context.bin_desc.size_bytes || 2012 !psp->dtm_context.context.bin_desc.start_addr) { 2013 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2014 return 0; 2015 } 2016 2017 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2018 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2019 2020 if (!psp->dtm_context.context.mem_context.shared_buf) { 2021 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2022 if (ret) 2023 return ret; 2024 } 2025 2026 ret = psp_ta_load(psp, &psp->dtm_context.context); 2027 if (!ret) { 2028 psp->dtm_context.context.initialized = true; 2029 mutex_init(&psp->dtm_context.mutex); 2030 } 2031 2032 return ret; 2033 } 2034 2035 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2036 { 2037 /* 2038 * TODO: bypass the loading in sriov for now 2039 */ 2040 if (amdgpu_sriov_vf(psp->adev)) 2041 return 0; 2042 2043 if (!psp->dtm_context.context.initialized) 2044 return 0; 2045 2046 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2047 } 2048 2049 static int psp_dtm_terminate(struct psp_context *psp) 2050 { 2051 int ret; 2052 2053 /* 2054 * TODO: bypass the terminate in sriov for now 2055 */ 2056 if (amdgpu_sriov_vf(psp->adev)) 2057 return 0; 2058 2059 if (!psp->dtm_context.context.initialized) 2060 return 0; 2061 2062 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2063 2064 psp->dtm_context.context.initialized = false; 2065 2066 return ret; 2067 } 2068 // DTM end 2069 2070 // RAP start 2071 static int psp_rap_initialize(struct psp_context *psp) 2072 { 2073 int ret; 2074 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2075 2076 /* 2077 * TODO: bypass the initialize in sriov for now 2078 */ 2079 if (amdgpu_sriov_vf(psp->adev)) 2080 return 0; 2081 2082 if (!psp->rap_context.context.bin_desc.size_bytes || 2083 !psp->rap_context.context.bin_desc.start_addr) { 2084 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2085 return 0; 2086 } 2087 2088 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2089 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2090 2091 if (!psp->rap_context.context.mem_context.shared_buf) { 2092 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2093 if (ret) 2094 return ret; 2095 } 2096 2097 ret = psp_ta_load(psp, &psp->rap_context.context); 2098 if (!ret) { 2099 psp->rap_context.context.initialized = true; 2100 mutex_init(&psp->rap_context.mutex); 2101 } else 2102 return ret; 2103 2104 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2105 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2106 psp_rap_terminate(psp); 2107 /* free rap shared memory */ 2108 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2109 2110 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2111 ret, status); 2112 2113 return ret; 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int psp_rap_terminate(struct psp_context *psp) 2120 { 2121 int ret; 2122 2123 if (!psp->rap_context.context.initialized) 2124 return 0; 2125 2126 ret = psp_ta_unload(psp, &psp->rap_context.context); 2127 2128 psp->rap_context.context.initialized = false; 2129 2130 return ret; 2131 } 2132 2133 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2134 { 2135 struct ta_rap_shared_memory *rap_cmd; 2136 int ret = 0; 2137 2138 if (!psp->rap_context.context.initialized) 2139 return 0; 2140 2141 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2142 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2143 return -EINVAL; 2144 2145 mutex_lock(&psp->rap_context.mutex); 2146 2147 rap_cmd = (struct ta_rap_shared_memory *) 2148 psp->rap_context.context.mem_context.shared_buf; 2149 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2150 2151 rap_cmd->cmd_id = ta_cmd_id; 2152 rap_cmd->validation_method_id = METHOD_A; 2153 2154 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2155 if (ret) 2156 goto out_unlock; 2157 2158 if (status) 2159 *status = rap_cmd->rap_status; 2160 2161 out_unlock: 2162 mutex_unlock(&psp->rap_context.mutex); 2163 2164 return ret; 2165 } 2166 // RAP end 2167 2168 /* securedisplay start */ 2169 static int psp_securedisplay_initialize(struct psp_context *psp) 2170 { 2171 int ret; 2172 struct ta_securedisplay_cmd *securedisplay_cmd; 2173 2174 /* 2175 * TODO: bypass the initialize in sriov for now 2176 */ 2177 if (amdgpu_sriov_vf(psp->adev)) 2178 return 0; 2179 2180 /* bypass securedisplay initialization if dmu is harvested */ 2181 if (!amdgpu_device_has_display_hardware(psp->adev)) 2182 return 0; 2183 2184 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2185 !psp->securedisplay_context.context.bin_desc.start_addr) { 2186 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2187 return 0; 2188 } 2189 2190 psp->securedisplay_context.context.mem_context.shared_mem_size = 2191 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2192 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2193 2194 if (!psp->securedisplay_context.context.initialized) { 2195 ret = psp_ta_init_shared_buf(psp, 2196 &psp->securedisplay_context.context.mem_context); 2197 if (ret) 2198 return ret; 2199 } 2200 2201 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2202 if (!ret) { 2203 psp->securedisplay_context.context.initialized = true; 2204 mutex_init(&psp->securedisplay_context.mutex); 2205 } else 2206 return ret; 2207 2208 mutex_lock(&psp->securedisplay_context.mutex); 2209 2210 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2211 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2212 2213 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2214 2215 mutex_unlock(&psp->securedisplay_context.mutex); 2216 2217 if (ret) { 2218 psp_securedisplay_terminate(psp); 2219 /* free securedisplay shared memory */ 2220 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2221 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2222 return -EINVAL; 2223 } 2224 2225 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2226 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2227 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2228 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2229 /* don't try again */ 2230 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2231 } 2232 2233 return 0; 2234 } 2235 2236 static int psp_securedisplay_terminate(struct psp_context *psp) 2237 { 2238 int ret; 2239 2240 /* 2241 * TODO:bypass the terminate in sriov for now 2242 */ 2243 if (amdgpu_sriov_vf(psp->adev)) 2244 return 0; 2245 2246 if (!psp->securedisplay_context.context.initialized) 2247 return 0; 2248 2249 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2250 2251 psp->securedisplay_context.context.initialized = false; 2252 2253 return ret; 2254 } 2255 2256 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2257 { 2258 int ret; 2259 2260 if (!psp->securedisplay_context.context.initialized) 2261 return -EINVAL; 2262 2263 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2264 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2265 return -EINVAL; 2266 2267 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2268 2269 return ret; 2270 } 2271 /* SECUREDISPLAY end */ 2272 2273 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2274 { 2275 struct psp_context *psp = &adev->psp; 2276 int ret = 0; 2277 2278 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2279 ret = psp->funcs->wait_for_bootloader(psp); 2280 2281 return ret; 2282 } 2283 2284 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2285 { 2286 if (psp->funcs && 2287 psp->funcs->get_ras_capability) { 2288 return psp->funcs->get_ras_capability(psp); 2289 } else { 2290 return false; 2291 } 2292 } 2293 2294 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2295 { 2296 struct psp_context *psp = &adev->psp; 2297 2298 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2299 return false; 2300 2301 if (psp->funcs && psp->funcs->is_reload_needed) 2302 return psp->funcs->is_reload_needed(psp); 2303 2304 return false; 2305 } 2306 2307 static int psp_hw_start(struct psp_context *psp) 2308 { 2309 struct amdgpu_device *adev = psp->adev; 2310 int ret; 2311 2312 if (!amdgpu_sriov_vf(adev)) { 2313 if ((is_psp_fw_valid(psp->kdb)) && 2314 (psp->funcs->bootloader_load_kdb != NULL)) { 2315 ret = psp_bootloader_load_kdb(psp); 2316 if (ret) { 2317 dev_err(adev->dev, "PSP load kdb failed!\n"); 2318 return ret; 2319 } 2320 } 2321 2322 if ((is_psp_fw_valid(psp->spl)) && 2323 (psp->funcs->bootloader_load_spl != NULL)) { 2324 ret = psp_bootloader_load_spl(psp); 2325 if (ret) { 2326 dev_err(adev->dev, "PSP load spl failed!\n"); 2327 return ret; 2328 } 2329 } 2330 2331 if ((is_psp_fw_valid(psp->sys)) && 2332 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2333 ret = psp_bootloader_load_sysdrv(psp); 2334 if (ret) { 2335 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2336 return ret; 2337 } 2338 } 2339 2340 if ((is_psp_fw_valid(psp->soc_drv)) && 2341 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2342 ret = psp_bootloader_load_soc_drv(psp); 2343 if (ret) { 2344 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2345 return ret; 2346 } 2347 } 2348 2349 if ((is_psp_fw_valid(psp->intf_drv)) && 2350 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2351 ret = psp_bootloader_load_intf_drv(psp); 2352 if (ret) { 2353 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2354 return ret; 2355 } 2356 } 2357 2358 if ((is_psp_fw_valid(psp->dbg_drv)) && 2359 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2360 ret = psp_bootloader_load_dbg_drv(psp); 2361 if (ret) { 2362 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2363 return ret; 2364 } 2365 } 2366 2367 if ((is_psp_fw_valid(psp->ras_drv)) && 2368 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2369 ret = psp_bootloader_load_ras_drv(psp); 2370 if (ret) { 2371 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2372 return ret; 2373 } 2374 } 2375 2376 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2377 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2378 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2379 if (ret) { 2380 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2381 return ret; 2382 } 2383 } 2384 2385 if ((is_psp_fw_valid(psp->sos)) && 2386 (psp->funcs->bootloader_load_sos != NULL)) { 2387 ret = psp_bootloader_load_sos(psp); 2388 if (ret) { 2389 dev_err(adev->dev, "PSP load sos failed!\n"); 2390 return ret; 2391 } 2392 } 2393 } 2394 2395 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2396 if (ret) { 2397 dev_err(adev->dev, "PSP create ring failed!\n"); 2398 return ret; 2399 } 2400 2401 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2402 goto skip_pin_bo; 2403 2404 if (!psp->boot_time_tmr || psp->autoload_supported) { 2405 ret = psp_tmr_init(psp); 2406 if (ret) { 2407 dev_err(adev->dev, "PSP tmr init failed!\n"); 2408 return ret; 2409 } 2410 } 2411 2412 skip_pin_bo: 2413 /* 2414 * For ASICs with DF Cstate management centralized 2415 * to PMFW, TMR setup should be performed after PMFW 2416 * loaded and before other non-psp firmware loaded. 2417 */ 2418 if (psp->pmfw_centralized_cstate_management) { 2419 ret = psp_load_smu_fw(psp); 2420 if (ret) 2421 return ret; 2422 } 2423 2424 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2425 ret = psp_tmr_load(psp); 2426 if (ret) { 2427 dev_err(adev->dev, "PSP load tmr failed!\n"); 2428 return ret; 2429 } 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2436 enum psp_gfx_fw_type *type) 2437 { 2438 switch (ucode->ucode_id) { 2439 case AMDGPU_UCODE_ID_CAP: 2440 *type = GFX_FW_TYPE_CAP; 2441 break; 2442 case AMDGPU_UCODE_ID_SDMA0: 2443 *type = GFX_FW_TYPE_SDMA0; 2444 break; 2445 case AMDGPU_UCODE_ID_SDMA1: 2446 *type = GFX_FW_TYPE_SDMA1; 2447 break; 2448 case AMDGPU_UCODE_ID_SDMA2: 2449 *type = GFX_FW_TYPE_SDMA2; 2450 break; 2451 case AMDGPU_UCODE_ID_SDMA3: 2452 *type = GFX_FW_TYPE_SDMA3; 2453 break; 2454 case AMDGPU_UCODE_ID_SDMA4: 2455 *type = GFX_FW_TYPE_SDMA4; 2456 break; 2457 case AMDGPU_UCODE_ID_SDMA5: 2458 *type = GFX_FW_TYPE_SDMA5; 2459 break; 2460 case AMDGPU_UCODE_ID_SDMA6: 2461 *type = GFX_FW_TYPE_SDMA6; 2462 break; 2463 case AMDGPU_UCODE_ID_SDMA7: 2464 *type = GFX_FW_TYPE_SDMA7; 2465 break; 2466 case AMDGPU_UCODE_ID_CP_MES: 2467 *type = GFX_FW_TYPE_CP_MES; 2468 break; 2469 case AMDGPU_UCODE_ID_CP_MES_DATA: 2470 *type = GFX_FW_TYPE_MES_STACK; 2471 break; 2472 case AMDGPU_UCODE_ID_CP_MES1: 2473 *type = GFX_FW_TYPE_CP_MES_KIQ; 2474 break; 2475 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2476 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2477 break; 2478 case AMDGPU_UCODE_ID_CP_CE: 2479 *type = GFX_FW_TYPE_CP_CE; 2480 break; 2481 case AMDGPU_UCODE_ID_CP_PFP: 2482 *type = GFX_FW_TYPE_CP_PFP; 2483 break; 2484 case AMDGPU_UCODE_ID_CP_ME: 2485 *type = GFX_FW_TYPE_CP_ME; 2486 break; 2487 case AMDGPU_UCODE_ID_CP_MEC1: 2488 *type = GFX_FW_TYPE_CP_MEC; 2489 break; 2490 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2491 *type = GFX_FW_TYPE_CP_MEC_ME1; 2492 break; 2493 case AMDGPU_UCODE_ID_CP_MEC2: 2494 *type = GFX_FW_TYPE_CP_MEC; 2495 break; 2496 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2497 *type = GFX_FW_TYPE_CP_MEC_ME2; 2498 break; 2499 case AMDGPU_UCODE_ID_RLC_P: 2500 *type = GFX_FW_TYPE_RLC_P; 2501 break; 2502 case AMDGPU_UCODE_ID_RLC_V: 2503 *type = GFX_FW_TYPE_RLC_V; 2504 break; 2505 case AMDGPU_UCODE_ID_RLC_G: 2506 *type = GFX_FW_TYPE_RLC_G; 2507 break; 2508 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2509 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2510 break; 2511 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2512 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2513 break; 2514 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2515 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2516 break; 2517 case AMDGPU_UCODE_ID_RLC_IRAM: 2518 *type = GFX_FW_TYPE_RLC_IRAM; 2519 break; 2520 case AMDGPU_UCODE_ID_RLC_DRAM: 2521 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2522 break; 2523 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2524 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2525 break; 2526 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2527 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2528 break; 2529 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2530 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2531 break; 2532 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2533 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2534 break; 2535 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2536 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2537 break; 2538 case AMDGPU_UCODE_ID_SMC: 2539 *type = GFX_FW_TYPE_SMU; 2540 break; 2541 case AMDGPU_UCODE_ID_PPTABLE: 2542 *type = GFX_FW_TYPE_PPTABLE; 2543 break; 2544 case AMDGPU_UCODE_ID_UVD: 2545 *type = GFX_FW_TYPE_UVD; 2546 break; 2547 case AMDGPU_UCODE_ID_UVD1: 2548 *type = GFX_FW_TYPE_UVD1; 2549 break; 2550 case AMDGPU_UCODE_ID_VCE: 2551 *type = GFX_FW_TYPE_VCE; 2552 break; 2553 case AMDGPU_UCODE_ID_VCN: 2554 *type = GFX_FW_TYPE_VCN; 2555 break; 2556 case AMDGPU_UCODE_ID_VCN1: 2557 *type = GFX_FW_TYPE_VCN1; 2558 break; 2559 case AMDGPU_UCODE_ID_DMCU_ERAM: 2560 *type = GFX_FW_TYPE_DMCU_ERAM; 2561 break; 2562 case AMDGPU_UCODE_ID_DMCU_INTV: 2563 *type = GFX_FW_TYPE_DMCU_ISR; 2564 break; 2565 case AMDGPU_UCODE_ID_VCN0_RAM: 2566 *type = GFX_FW_TYPE_VCN0_RAM; 2567 break; 2568 case AMDGPU_UCODE_ID_VCN1_RAM: 2569 *type = GFX_FW_TYPE_VCN1_RAM; 2570 break; 2571 case AMDGPU_UCODE_ID_DMCUB: 2572 *type = GFX_FW_TYPE_DMUB; 2573 break; 2574 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2575 case AMDGPU_UCODE_ID_SDMA_RS64: 2576 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2577 break; 2578 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2579 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2580 break; 2581 case AMDGPU_UCODE_ID_IMU_I: 2582 *type = GFX_FW_TYPE_IMU_I; 2583 break; 2584 case AMDGPU_UCODE_ID_IMU_D: 2585 *type = GFX_FW_TYPE_IMU_D; 2586 break; 2587 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2588 *type = GFX_FW_TYPE_RS64_PFP; 2589 break; 2590 case AMDGPU_UCODE_ID_CP_RS64_ME: 2591 *type = GFX_FW_TYPE_RS64_ME; 2592 break; 2593 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2594 *type = GFX_FW_TYPE_RS64_MEC; 2595 break; 2596 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2597 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2598 break; 2599 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2600 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2601 break; 2602 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2603 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2604 break; 2605 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2606 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2607 break; 2608 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2609 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2610 break; 2611 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2612 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2613 break; 2614 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2615 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2616 break; 2617 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2618 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2619 break; 2620 case AMDGPU_UCODE_ID_VPE_CTX: 2621 *type = GFX_FW_TYPE_VPEC_FW1; 2622 break; 2623 case AMDGPU_UCODE_ID_VPE_CTL: 2624 *type = GFX_FW_TYPE_VPEC_FW2; 2625 break; 2626 case AMDGPU_UCODE_ID_VPE: 2627 *type = GFX_FW_TYPE_VPE; 2628 break; 2629 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2630 *type = GFX_FW_TYPE_UMSCH_UCODE; 2631 break; 2632 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2633 *type = GFX_FW_TYPE_UMSCH_DATA; 2634 break; 2635 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2636 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2637 break; 2638 case AMDGPU_UCODE_ID_P2S_TABLE: 2639 *type = GFX_FW_TYPE_P2S_TABLE; 2640 break; 2641 case AMDGPU_UCODE_ID_JPEG_RAM: 2642 *type = GFX_FW_TYPE_JPEG_RAM; 2643 break; 2644 case AMDGPU_UCODE_ID_ISP: 2645 *type = GFX_FW_TYPE_ISP; 2646 break; 2647 case AMDGPU_UCODE_ID_MAXIMUM: 2648 default: 2649 return -EINVAL; 2650 } 2651 2652 return 0; 2653 } 2654 2655 static void psp_print_fw_hdr(struct psp_context *psp, 2656 struct amdgpu_firmware_info *ucode) 2657 { 2658 struct amdgpu_device *adev = psp->adev; 2659 struct common_firmware_header *hdr; 2660 2661 switch (ucode->ucode_id) { 2662 case AMDGPU_UCODE_ID_SDMA0: 2663 case AMDGPU_UCODE_ID_SDMA1: 2664 case AMDGPU_UCODE_ID_SDMA2: 2665 case AMDGPU_UCODE_ID_SDMA3: 2666 case AMDGPU_UCODE_ID_SDMA4: 2667 case AMDGPU_UCODE_ID_SDMA5: 2668 case AMDGPU_UCODE_ID_SDMA6: 2669 case AMDGPU_UCODE_ID_SDMA7: 2670 hdr = (struct common_firmware_header *) 2671 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2672 amdgpu_ucode_print_sdma_hdr(hdr); 2673 break; 2674 case AMDGPU_UCODE_ID_CP_CE: 2675 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2676 amdgpu_ucode_print_gfx_hdr(hdr); 2677 break; 2678 case AMDGPU_UCODE_ID_CP_PFP: 2679 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2680 amdgpu_ucode_print_gfx_hdr(hdr); 2681 break; 2682 case AMDGPU_UCODE_ID_CP_ME: 2683 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2684 amdgpu_ucode_print_gfx_hdr(hdr); 2685 break; 2686 case AMDGPU_UCODE_ID_CP_MEC1: 2687 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2688 amdgpu_ucode_print_gfx_hdr(hdr); 2689 break; 2690 case AMDGPU_UCODE_ID_RLC_G: 2691 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2692 amdgpu_ucode_print_rlc_hdr(hdr); 2693 break; 2694 case AMDGPU_UCODE_ID_SMC: 2695 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2696 amdgpu_ucode_print_smc_hdr(hdr); 2697 break; 2698 default: 2699 break; 2700 } 2701 } 2702 2703 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2704 struct amdgpu_firmware_info *ucode, 2705 struct psp_gfx_cmd_resp *cmd) 2706 { 2707 int ret; 2708 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2709 2710 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2711 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2712 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2713 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2714 2715 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2716 if (ret) 2717 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2718 2719 return ret; 2720 } 2721 2722 int psp_execute_ip_fw_load(struct psp_context *psp, 2723 struct amdgpu_firmware_info *ucode) 2724 { 2725 int ret = 0; 2726 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2727 2728 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2729 if (!ret) { 2730 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2731 psp->fence_buf_mc_addr); 2732 } 2733 2734 release_psp_cmd_buf(psp); 2735 2736 return ret; 2737 } 2738 2739 static int psp_load_p2s_table(struct psp_context *psp) 2740 { 2741 int ret; 2742 struct amdgpu_device *adev = psp->adev; 2743 struct amdgpu_firmware_info *ucode = 2744 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2745 2746 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2747 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2748 return 0; 2749 2750 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2751 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2752 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2753 0x0036003C; 2754 if (psp->sos.fw_version < supp_vers) 2755 return 0; 2756 } 2757 2758 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2759 return 0; 2760 2761 ret = psp_execute_ip_fw_load(psp, ucode); 2762 2763 return ret; 2764 } 2765 2766 static int psp_load_smu_fw(struct psp_context *psp) 2767 { 2768 int ret; 2769 struct amdgpu_device *adev = psp->adev; 2770 struct amdgpu_firmware_info *ucode = 2771 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2772 struct amdgpu_ras *ras = psp->ras_context.ras; 2773 2774 /* 2775 * Skip SMU FW reloading in case of using BACO for runpm only, 2776 * as SMU is always alive. 2777 */ 2778 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2779 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2780 return 0; 2781 2782 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2783 return 0; 2784 2785 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2786 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2787 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2788 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2789 if (ret) 2790 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2791 } 2792 2793 ret = psp_execute_ip_fw_load(psp, ucode); 2794 2795 if (ret) 2796 dev_err(adev->dev, "PSP load smu failed!\n"); 2797 2798 return ret; 2799 } 2800 2801 static bool fw_load_skip_check(struct psp_context *psp, 2802 struct amdgpu_firmware_info *ucode) 2803 { 2804 if (!ucode->fw || !ucode->ucode_size) 2805 return true; 2806 2807 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2808 return true; 2809 2810 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2811 (psp_smu_reload_quirk(psp) || 2812 psp->autoload_supported || 2813 psp->pmfw_centralized_cstate_management)) 2814 return true; 2815 2816 if (amdgpu_sriov_vf(psp->adev) && 2817 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2818 return true; 2819 2820 if (psp->autoload_supported && 2821 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2822 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2823 /* skip mec JT when autoload is enabled */ 2824 return true; 2825 2826 return false; 2827 } 2828 2829 int psp_load_fw_list(struct psp_context *psp, 2830 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2831 { 2832 int ret = 0, i; 2833 struct amdgpu_firmware_info *ucode; 2834 2835 for (i = 0; i < ucode_count; ++i) { 2836 ucode = ucode_list[i]; 2837 psp_print_fw_hdr(psp, ucode); 2838 ret = psp_execute_ip_fw_load(psp, ucode); 2839 if (ret) 2840 return ret; 2841 } 2842 return ret; 2843 } 2844 2845 static int psp_load_non_psp_fw(struct psp_context *psp) 2846 { 2847 int i, ret; 2848 struct amdgpu_firmware_info *ucode; 2849 struct amdgpu_device *adev = psp->adev; 2850 2851 if (psp->autoload_supported && 2852 !psp->pmfw_centralized_cstate_management) { 2853 ret = psp_load_smu_fw(psp); 2854 if (ret) 2855 return ret; 2856 } 2857 2858 /* Load P2S table first if it's available */ 2859 psp_load_p2s_table(psp); 2860 2861 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2862 ucode = &adev->firmware.ucode[i]; 2863 2864 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2865 !fw_load_skip_check(psp, ucode)) { 2866 ret = psp_load_smu_fw(psp); 2867 if (ret) 2868 return ret; 2869 continue; 2870 } 2871 2872 if (fw_load_skip_check(psp, ucode)) 2873 continue; 2874 2875 if (psp->autoload_supported && 2876 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2877 IP_VERSION(11, 0, 7) || 2878 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2879 IP_VERSION(11, 0, 11) || 2880 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2881 IP_VERSION(11, 0, 12)) && 2882 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2883 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2884 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2885 /* PSP only receive one SDMA fw for sienna_cichlid, 2886 * as all four sdma fw are same 2887 */ 2888 continue; 2889 2890 psp_print_fw_hdr(psp, ucode); 2891 2892 ret = psp_execute_ip_fw_load(psp, ucode); 2893 if (ret) 2894 return ret; 2895 2896 /* Start rlc autoload after psp received all the gfx firmware */ 2897 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2898 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2899 ret = psp_rlc_autoload_start(psp); 2900 if (ret) { 2901 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2902 return ret; 2903 } 2904 } 2905 } 2906 2907 return 0; 2908 } 2909 2910 static int psp_load_fw(struct amdgpu_device *adev) 2911 { 2912 int ret; 2913 struct psp_context *psp = &adev->psp; 2914 2915 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2916 /* should not destroy ring, only stop */ 2917 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2918 } else { 2919 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2920 2921 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2922 if (ret) { 2923 dev_err(adev->dev, "PSP ring init failed!\n"); 2924 goto failed; 2925 } 2926 } 2927 2928 ret = psp_hw_start(psp); 2929 if (ret) 2930 goto failed; 2931 2932 ret = psp_load_non_psp_fw(psp); 2933 if (ret) 2934 goto failed1; 2935 2936 ret = psp_asd_initialize(psp); 2937 if (ret) { 2938 dev_err(adev->dev, "PSP load asd failed!\n"); 2939 goto failed1; 2940 } 2941 2942 ret = psp_rl_load(adev); 2943 if (ret) { 2944 dev_err(adev->dev, "PSP load RL failed!\n"); 2945 goto failed1; 2946 } 2947 2948 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2949 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2950 ret = psp_xgmi_initialize(psp, false, true); 2951 /* Warning the XGMI seesion initialize failure 2952 * Instead of stop driver initialization 2953 */ 2954 if (ret) 2955 dev_err(psp->adev->dev, 2956 "XGMI: Failed to initialize XGMI session\n"); 2957 } 2958 } 2959 2960 if (psp->ta_fw) { 2961 ret = psp_ras_initialize(psp); 2962 if (ret) 2963 dev_err(psp->adev->dev, 2964 "RAS: Failed to initialize RAS\n"); 2965 2966 ret = psp_hdcp_initialize(psp); 2967 if (ret) 2968 dev_err(psp->adev->dev, 2969 "HDCP: Failed to initialize HDCP\n"); 2970 2971 ret = psp_dtm_initialize(psp); 2972 if (ret) 2973 dev_err(psp->adev->dev, 2974 "DTM: Failed to initialize DTM\n"); 2975 2976 ret = psp_rap_initialize(psp); 2977 if (ret) 2978 dev_err(psp->adev->dev, 2979 "RAP: Failed to initialize RAP\n"); 2980 2981 ret = psp_securedisplay_initialize(psp); 2982 if (ret) 2983 dev_err(psp->adev->dev, 2984 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2985 } 2986 2987 return 0; 2988 2989 failed1: 2990 psp_free_shared_bufs(psp); 2991 failed: 2992 /* 2993 * all cleanup jobs (xgmi terminate, ras terminate, 2994 * ring destroy, cmd/fence/fw buffers destory, 2995 * psp->cmd destory) are delayed to psp_hw_fini 2996 */ 2997 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2998 return ret; 2999 } 3000 3001 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3002 { 3003 int ret; 3004 struct amdgpu_device *adev = ip_block->adev; 3005 3006 mutex_lock(&adev->firmware.mutex); 3007 /* 3008 * This sequence is just used on hw_init only once, no need on 3009 * resume. 3010 */ 3011 ret = amdgpu_ucode_init_bo(adev); 3012 if (ret) 3013 goto failed; 3014 3015 ret = psp_load_fw(adev); 3016 if (ret) { 3017 dev_err(adev->dev, "PSP firmware loading failed\n"); 3018 goto failed; 3019 } 3020 3021 mutex_unlock(&adev->firmware.mutex); 3022 return 0; 3023 3024 failed: 3025 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3026 mutex_unlock(&adev->firmware.mutex); 3027 return -EINVAL; 3028 } 3029 3030 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3031 { 3032 struct amdgpu_device *adev = ip_block->adev; 3033 struct psp_context *psp = &adev->psp; 3034 3035 if (psp->ta_fw) { 3036 psp_ras_terminate(psp); 3037 psp_securedisplay_terminate(psp); 3038 psp_rap_terminate(psp); 3039 psp_dtm_terminate(psp); 3040 psp_hdcp_terminate(psp); 3041 3042 if (adev->gmc.xgmi.num_physical_nodes > 1) 3043 psp_xgmi_terminate(psp); 3044 } 3045 3046 psp_asd_terminate(psp); 3047 psp_tmr_terminate(psp); 3048 3049 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3050 3051 return 0; 3052 } 3053 3054 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3055 { 3056 int ret = 0; 3057 struct amdgpu_device *adev = ip_block->adev; 3058 struct psp_context *psp = &adev->psp; 3059 3060 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3061 psp->xgmi_context.context.initialized) { 3062 ret = psp_xgmi_terminate(psp); 3063 if (ret) { 3064 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3065 goto out; 3066 } 3067 } 3068 3069 if (psp->ta_fw) { 3070 ret = psp_ras_terminate(psp); 3071 if (ret) { 3072 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3073 goto out; 3074 } 3075 ret = psp_hdcp_terminate(psp); 3076 if (ret) { 3077 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3078 goto out; 3079 } 3080 ret = psp_dtm_terminate(psp); 3081 if (ret) { 3082 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3083 goto out; 3084 } 3085 ret = psp_rap_terminate(psp); 3086 if (ret) { 3087 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3088 goto out; 3089 } 3090 ret = psp_securedisplay_terminate(psp); 3091 if (ret) { 3092 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3093 goto out; 3094 } 3095 } 3096 3097 ret = psp_asd_terminate(psp); 3098 if (ret) { 3099 dev_err(adev->dev, "Failed to terminate asd\n"); 3100 goto out; 3101 } 3102 3103 ret = psp_tmr_terminate(psp); 3104 if (ret) { 3105 dev_err(adev->dev, "Failed to terminate tmr\n"); 3106 goto out; 3107 } 3108 3109 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3110 if (ret) 3111 dev_err(adev->dev, "PSP ring stop failed\n"); 3112 3113 out: 3114 return ret; 3115 } 3116 3117 static int psp_resume(struct amdgpu_ip_block *ip_block) 3118 { 3119 int ret; 3120 struct amdgpu_device *adev = ip_block->adev; 3121 struct psp_context *psp = &adev->psp; 3122 3123 dev_info(adev->dev, "PSP is resuming...\n"); 3124 3125 if (psp->mem_train_ctx.enable_mem_training) { 3126 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3127 if (ret) { 3128 dev_err(adev->dev, "Failed to process memory training!\n"); 3129 return ret; 3130 } 3131 } 3132 3133 mutex_lock(&adev->firmware.mutex); 3134 3135 ret = psp_hw_start(psp); 3136 if (ret) 3137 goto failed; 3138 3139 ret = psp_load_non_psp_fw(psp); 3140 if (ret) 3141 goto failed; 3142 3143 ret = psp_asd_initialize(psp); 3144 if (ret) { 3145 dev_err(adev->dev, "PSP load asd failed!\n"); 3146 goto failed; 3147 } 3148 3149 ret = psp_rl_load(adev); 3150 if (ret) { 3151 dev_err(adev->dev, "PSP load RL failed!\n"); 3152 goto failed; 3153 } 3154 3155 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3156 ret = psp_xgmi_initialize(psp, false, true); 3157 /* Warning the XGMI seesion initialize failure 3158 * Instead of stop driver initialization 3159 */ 3160 if (ret) 3161 dev_err(psp->adev->dev, 3162 "XGMI: Failed to initialize XGMI session\n"); 3163 } 3164 3165 if (psp->ta_fw) { 3166 ret = psp_ras_initialize(psp); 3167 if (ret) 3168 dev_err(psp->adev->dev, 3169 "RAS: Failed to initialize RAS\n"); 3170 3171 ret = psp_hdcp_initialize(psp); 3172 if (ret) 3173 dev_err(psp->adev->dev, 3174 "HDCP: Failed to initialize HDCP\n"); 3175 3176 ret = psp_dtm_initialize(psp); 3177 if (ret) 3178 dev_err(psp->adev->dev, 3179 "DTM: Failed to initialize DTM\n"); 3180 3181 ret = psp_rap_initialize(psp); 3182 if (ret) 3183 dev_err(psp->adev->dev, 3184 "RAP: Failed to initialize RAP\n"); 3185 3186 ret = psp_securedisplay_initialize(psp); 3187 if (ret) 3188 dev_err(psp->adev->dev, 3189 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3190 } 3191 3192 mutex_unlock(&adev->firmware.mutex); 3193 3194 return 0; 3195 3196 failed: 3197 dev_err(adev->dev, "PSP resume failed\n"); 3198 mutex_unlock(&adev->firmware.mutex); 3199 return ret; 3200 } 3201 3202 int psp_gpu_reset(struct amdgpu_device *adev) 3203 { 3204 int ret; 3205 3206 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3207 return 0; 3208 3209 mutex_lock(&adev->psp.mutex); 3210 ret = psp_mode1_reset(&adev->psp); 3211 mutex_unlock(&adev->psp.mutex); 3212 3213 return ret; 3214 } 3215 3216 int psp_rlc_autoload_start(struct psp_context *psp) 3217 { 3218 int ret; 3219 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3220 3221 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3222 3223 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3224 psp->fence_buf_mc_addr); 3225 3226 release_psp_cmd_buf(psp); 3227 3228 return ret; 3229 } 3230 3231 int psp_ring_cmd_submit(struct psp_context *psp, 3232 uint64_t cmd_buf_mc_addr, 3233 uint64_t fence_mc_addr, 3234 int index) 3235 { 3236 unsigned int psp_write_ptr_reg = 0; 3237 struct psp_gfx_rb_frame *write_frame; 3238 struct psp_ring *ring = &psp->km_ring; 3239 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3240 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3241 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3242 struct amdgpu_device *adev = psp->adev; 3243 uint32_t ring_size_dw = ring->ring_size / 4; 3244 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3245 3246 /* KM (GPCOM) prepare write pointer */ 3247 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3248 3249 /* Update KM RB frame pointer to new frame */ 3250 /* write_frame ptr increments by size of rb_frame in bytes */ 3251 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3252 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3253 write_frame = ring_buffer_start; 3254 else 3255 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3256 /* Check invalid write_frame ptr address */ 3257 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3258 dev_err(adev->dev, 3259 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3260 ring_buffer_start, ring_buffer_end, write_frame); 3261 dev_err(adev->dev, 3262 "write_frame is pointing to address out of bounds\n"); 3263 return -EINVAL; 3264 } 3265 3266 /* Initialize KM RB frame */ 3267 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3268 3269 /* Update KM RB frame */ 3270 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3271 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3272 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3273 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3274 write_frame->fence_value = index; 3275 amdgpu_device_flush_hdp(adev, NULL); 3276 3277 /* Update the write Pointer in DWORDs */ 3278 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3279 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3280 return 0; 3281 } 3282 3283 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3284 { 3285 struct amdgpu_device *adev = psp->adev; 3286 const struct psp_firmware_header_v1_0 *asd_hdr; 3287 int err = 0; 3288 3289 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, "amdgpu/%s_asd.bin", chip_name); 3290 if (err) 3291 goto out; 3292 3293 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3294 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3295 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3296 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3297 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3298 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3299 return 0; 3300 out: 3301 amdgpu_ucode_release(&adev->psp.asd_fw); 3302 return err; 3303 } 3304 3305 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3306 { 3307 struct amdgpu_device *adev = psp->adev; 3308 const struct psp_firmware_header_v1_0 *toc_hdr; 3309 int err = 0; 3310 3311 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, "amdgpu/%s_toc.bin", chip_name); 3312 if (err) 3313 goto out; 3314 3315 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3316 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3317 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3318 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3319 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3320 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3321 return 0; 3322 out: 3323 amdgpu_ucode_release(&adev->psp.toc_fw); 3324 return err; 3325 } 3326 3327 static int parse_sos_bin_descriptor(struct psp_context *psp, 3328 const struct psp_fw_bin_desc *desc, 3329 const struct psp_firmware_header_v2_0 *sos_hdr) 3330 { 3331 uint8_t *ucode_start_addr = NULL; 3332 3333 if (!psp || !desc || !sos_hdr) 3334 return -EINVAL; 3335 3336 ucode_start_addr = (uint8_t *)sos_hdr + 3337 le32_to_cpu(desc->offset_bytes) + 3338 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3339 3340 switch (desc->fw_type) { 3341 case PSP_FW_TYPE_PSP_SOS: 3342 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3343 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3344 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3345 psp->sos.start_addr = ucode_start_addr; 3346 break; 3347 case PSP_FW_TYPE_PSP_SYS_DRV: 3348 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3349 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3350 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3351 psp->sys.start_addr = ucode_start_addr; 3352 break; 3353 case PSP_FW_TYPE_PSP_KDB: 3354 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3355 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3356 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3357 psp->kdb.start_addr = ucode_start_addr; 3358 break; 3359 case PSP_FW_TYPE_PSP_TOC: 3360 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3361 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3362 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3363 psp->toc.start_addr = ucode_start_addr; 3364 break; 3365 case PSP_FW_TYPE_PSP_SPL: 3366 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3367 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3368 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3369 psp->spl.start_addr = ucode_start_addr; 3370 break; 3371 case PSP_FW_TYPE_PSP_RL: 3372 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3373 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3374 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3375 psp->rl.start_addr = ucode_start_addr; 3376 break; 3377 case PSP_FW_TYPE_PSP_SOC_DRV: 3378 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3379 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3380 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3381 psp->soc_drv.start_addr = ucode_start_addr; 3382 break; 3383 case PSP_FW_TYPE_PSP_INTF_DRV: 3384 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3385 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3386 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3387 psp->intf_drv.start_addr = ucode_start_addr; 3388 break; 3389 case PSP_FW_TYPE_PSP_DBG_DRV: 3390 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3391 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3392 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3393 psp->dbg_drv.start_addr = ucode_start_addr; 3394 break; 3395 case PSP_FW_TYPE_PSP_RAS_DRV: 3396 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3397 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3398 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3399 psp->ras_drv.start_addr = ucode_start_addr; 3400 break; 3401 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3402 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3403 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3404 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3405 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3406 break; 3407 default: 3408 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3409 break; 3410 } 3411 3412 return 0; 3413 } 3414 3415 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3416 { 3417 const struct psp_firmware_header_v1_0 *sos_hdr; 3418 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3419 uint8_t *ucode_array_start_addr; 3420 3421 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3422 ucode_array_start_addr = (uint8_t *)sos_hdr + 3423 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3424 3425 if (adev->gmc.xgmi.connected_to_cpu || 3426 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3427 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3428 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3429 3430 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3431 adev->psp.sys.start_addr = ucode_array_start_addr; 3432 3433 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3434 adev->psp.sos.start_addr = ucode_array_start_addr + 3435 le32_to_cpu(sos_hdr->sos.offset_bytes); 3436 } else { 3437 /* Load alternate PSP SOS FW */ 3438 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3439 3440 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3441 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3442 3443 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3444 adev->psp.sys.start_addr = ucode_array_start_addr + 3445 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3446 3447 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3448 adev->psp.sos.start_addr = ucode_array_start_addr + 3449 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3450 } 3451 3452 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3453 dev_warn(adev->dev, "PSP SOS FW not available"); 3454 return -EINVAL; 3455 } 3456 3457 return 0; 3458 } 3459 3460 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3461 { 3462 struct amdgpu_device *adev = psp->adev; 3463 const struct psp_firmware_header_v1_0 *sos_hdr; 3464 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3465 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3466 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3467 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3468 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3469 int fw_index, fw_bin_count, start_index = 0; 3470 const struct psp_fw_bin_desc *fw_bin; 3471 uint8_t *ucode_array_start_addr; 3472 int err = 0; 3473 3474 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name); 3475 if (err) 3476 goto out; 3477 3478 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3479 ucode_array_start_addr = (uint8_t *)sos_hdr + 3480 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3481 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3482 3483 switch (sos_hdr->header.header_version_major) { 3484 case 1: 3485 err = psp_init_sos_base_fw(adev); 3486 if (err) 3487 goto out; 3488 3489 if (sos_hdr->header.header_version_minor == 1) { 3490 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3491 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3492 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3493 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3494 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3495 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3496 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3497 } 3498 if (sos_hdr->header.header_version_minor == 2) { 3499 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3500 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3501 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3502 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3503 } 3504 if (sos_hdr->header.header_version_minor == 3) { 3505 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3506 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3507 adev->psp.toc.start_addr = ucode_array_start_addr + 3508 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3509 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3510 adev->psp.kdb.start_addr = ucode_array_start_addr + 3511 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3512 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3513 adev->psp.spl.start_addr = ucode_array_start_addr + 3514 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3515 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3516 adev->psp.rl.start_addr = ucode_array_start_addr + 3517 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3518 } 3519 break; 3520 case 2: 3521 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3522 3523 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3524 3525 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3526 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3527 err = -EINVAL; 3528 goto out; 3529 } 3530 3531 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3532 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3533 3534 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3535 3536 if (psp_is_aux_sos_load_required(psp)) 3537 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3538 else 3539 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3540 3541 } else { 3542 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3543 } 3544 3545 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3546 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3547 sos_hdr_v2_0); 3548 if (err) 3549 goto out; 3550 } 3551 break; 3552 default: 3553 dev_err(adev->dev, 3554 "unsupported psp sos firmware\n"); 3555 err = -EINVAL; 3556 goto out; 3557 } 3558 3559 return 0; 3560 out: 3561 amdgpu_ucode_release(&adev->psp.sos_fw); 3562 3563 return err; 3564 } 3565 3566 static int parse_ta_bin_descriptor(struct psp_context *psp, 3567 const struct psp_fw_bin_desc *desc, 3568 const struct ta_firmware_header_v2_0 *ta_hdr) 3569 { 3570 uint8_t *ucode_start_addr = NULL; 3571 3572 if (!psp || !desc || !ta_hdr) 3573 return -EINVAL; 3574 3575 ucode_start_addr = (uint8_t *)ta_hdr + 3576 le32_to_cpu(desc->offset_bytes) + 3577 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3578 3579 switch (desc->fw_type) { 3580 case TA_FW_TYPE_PSP_ASD: 3581 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3582 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3583 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3584 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3585 break; 3586 case TA_FW_TYPE_PSP_XGMI: 3587 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3588 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3589 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3590 break; 3591 case TA_FW_TYPE_PSP_RAS: 3592 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3593 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3594 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3595 break; 3596 case TA_FW_TYPE_PSP_HDCP: 3597 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3598 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3599 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3600 break; 3601 case TA_FW_TYPE_PSP_DTM: 3602 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3603 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3604 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3605 break; 3606 case TA_FW_TYPE_PSP_RAP: 3607 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3608 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3609 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3610 break; 3611 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3612 psp->securedisplay_context.context.bin_desc.fw_version = 3613 le32_to_cpu(desc->fw_version); 3614 psp->securedisplay_context.context.bin_desc.size_bytes = 3615 le32_to_cpu(desc->size_bytes); 3616 psp->securedisplay_context.context.bin_desc.start_addr = 3617 ucode_start_addr; 3618 break; 3619 default: 3620 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3621 break; 3622 } 3623 3624 return 0; 3625 } 3626 3627 static int parse_ta_v1_microcode(struct psp_context *psp) 3628 { 3629 const struct ta_firmware_header_v1_0 *ta_hdr; 3630 struct amdgpu_device *adev = psp->adev; 3631 3632 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3633 3634 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3635 return -EINVAL; 3636 3637 adev->psp.xgmi_context.context.bin_desc.fw_version = 3638 le32_to_cpu(ta_hdr->xgmi.fw_version); 3639 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3640 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3641 adev->psp.xgmi_context.context.bin_desc.start_addr = 3642 (uint8_t *)ta_hdr + 3643 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3644 3645 adev->psp.ras_context.context.bin_desc.fw_version = 3646 le32_to_cpu(ta_hdr->ras.fw_version); 3647 adev->psp.ras_context.context.bin_desc.size_bytes = 3648 le32_to_cpu(ta_hdr->ras.size_bytes); 3649 adev->psp.ras_context.context.bin_desc.start_addr = 3650 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3651 le32_to_cpu(ta_hdr->ras.offset_bytes); 3652 3653 adev->psp.hdcp_context.context.bin_desc.fw_version = 3654 le32_to_cpu(ta_hdr->hdcp.fw_version); 3655 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3656 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3657 adev->psp.hdcp_context.context.bin_desc.start_addr = 3658 (uint8_t *)ta_hdr + 3659 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3660 3661 adev->psp.dtm_context.context.bin_desc.fw_version = 3662 le32_to_cpu(ta_hdr->dtm.fw_version); 3663 adev->psp.dtm_context.context.bin_desc.size_bytes = 3664 le32_to_cpu(ta_hdr->dtm.size_bytes); 3665 adev->psp.dtm_context.context.bin_desc.start_addr = 3666 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3667 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3668 3669 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3670 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3671 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3672 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3673 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3674 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3675 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3676 3677 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3678 3679 return 0; 3680 } 3681 3682 static int parse_ta_v2_microcode(struct psp_context *psp) 3683 { 3684 const struct ta_firmware_header_v2_0 *ta_hdr; 3685 struct amdgpu_device *adev = psp->adev; 3686 int err = 0; 3687 int ta_index = 0; 3688 3689 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3690 3691 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3692 return -EINVAL; 3693 3694 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3695 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3696 return -EINVAL; 3697 } 3698 3699 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3700 err = parse_ta_bin_descriptor(psp, 3701 &ta_hdr->ta_fw_bin[ta_index], 3702 ta_hdr); 3703 if (err) 3704 return err; 3705 } 3706 3707 return 0; 3708 } 3709 3710 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3711 { 3712 const struct common_firmware_header *hdr; 3713 struct amdgpu_device *adev = psp->adev; 3714 int err; 3715 3716 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, "amdgpu/%s_ta.bin", chip_name); 3717 if (err) 3718 return err; 3719 3720 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3721 switch (le16_to_cpu(hdr->header_version_major)) { 3722 case 1: 3723 err = parse_ta_v1_microcode(psp); 3724 break; 3725 case 2: 3726 err = parse_ta_v2_microcode(psp); 3727 break; 3728 default: 3729 dev_err(adev->dev, "unsupported TA header version\n"); 3730 err = -EINVAL; 3731 } 3732 3733 if (err) 3734 amdgpu_ucode_release(&adev->psp.ta_fw); 3735 3736 return err; 3737 } 3738 3739 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3740 { 3741 struct amdgpu_device *adev = psp->adev; 3742 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3743 struct amdgpu_firmware_info *info = NULL; 3744 int err = 0; 3745 3746 if (!amdgpu_sriov_vf(adev)) { 3747 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3748 return -EINVAL; 3749 } 3750 3751 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, "amdgpu/%s_cap.bin", chip_name); 3752 if (err) { 3753 if (err == -ENODEV) { 3754 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3755 err = 0; 3756 goto out; 3757 } 3758 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3759 } 3760 3761 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3762 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3763 info->fw = adev->psp.cap_fw; 3764 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3765 adev->psp.cap_fw->data; 3766 adev->firmware.fw_size += ALIGN( 3767 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3768 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3769 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3770 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3771 3772 return 0; 3773 3774 out: 3775 amdgpu_ucode_release(&adev->psp.cap_fw); 3776 return err; 3777 } 3778 3779 int psp_config_sq_perfmon(struct psp_context *psp, 3780 uint32_t xcp_id, bool core_override_enable, 3781 bool reg_override_enable, bool perfmon_override_enable) 3782 { 3783 int ret; 3784 3785 if (amdgpu_sriov_vf(psp->adev)) 3786 return 0; 3787 3788 if (xcp_id > MAX_XCP) { 3789 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 3790 return -EINVAL; 3791 } 3792 3793 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 3794 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 3795 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 3796 return -EINVAL; 3797 } 3798 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3799 3800 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 3801 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 3802 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 3803 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 3804 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 3805 3806 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 3807 if (ret) 3808 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 3809 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 3810 3811 release_psp_cmd_buf(psp); 3812 return ret; 3813 } 3814 3815 static int psp_set_clockgating_state(void *handle, 3816 enum amd_clockgating_state state) 3817 { 3818 return 0; 3819 } 3820 3821 static int psp_set_powergating_state(void *handle, 3822 enum amd_powergating_state state) 3823 { 3824 return 0; 3825 } 3826 3827 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3828 struct device_attribute *attr, 3829 char *buf) 3830 { 3831 struct drm_device *ddev = dev_get_drvdata(dev); 3832 struct amdgpu_device *adev = drm_to_adev(ddev); 3833 uint32_t fw_ver; 3834 int ret; 3835 3836 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3837 dev_info(adev->dev, "PSP block is not ready yet\n."); 3838 return -EBUSY; 3839 } 3840 3841 mutex_lock(&adev->psp.mutex); 3842 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3843 mutex_unlock(&adev->psp.mutex); 3844 3845 if (ret) { 3846 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3847 return ret; 3848 } 3849 3850 return sysfs_emit(buf, "%x\n", fw_ver); 3851 } 3852 3853 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3854 struct device_attribute *attr, 3855 const char *buf, 3856 size_t count) 3857 { 3858 struct drm_device *ddev = dev_get_drvdata(dev); 3859 struct amdgpu_device *adev = drm_to_adev(ddev); 3860 int ret, idx; 3861 const struct firmware *usbc_pd_fw; 3862 struct amdgpu_bo *fw_buf_bo = NULL; 3863 uint64_t fw_pri_mc_addr; 3864 void *fw_pri_cpu_addr; 3865 3866 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3867 dev_err(adev->dev, "PSP block is not ready yet."); 3868 return -EBUSY; 3869 } 3870 3871 if (!drm_dev_enter(ddev, &idx)) 3872 return -ENODEV; 3873 3874 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, "amdgpu/%s", buf); 3875 if (ret) 3876 goto fail; 3877 3878 /* LFB address which is aligned to 1MB boundary per PSP request */ 3879 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3880 AMDGPU_GEM_DOMAIN_VRAM | 3881 AMDGPU_GEM_DOMAIN_GTT, 3882 &fw_buf_bo, &fw_pri_mc_addr, 3883 &fw_pri_cpu_addr); 3884 if (ret) 3885 goto rel_buf; 3886 3887 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3888 3889 mutex_lock(&adev->psp.mutex); 3890 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3891 mutex_unlock(&adev->psp.mutex); 3892 3893 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3894 3895 rel_buf: 3896 amdgpu_ucode_release(&usbc_pd_fw); 3897 fail: 3898 if (ret) { 3899 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3900 count = ret; 3901 } 3902 3903 drm_dev_exit(idx); 3904 return count; 3905 } 3906 3907 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3908 { 3909 int idx; 3910 3911 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3912 return; 3913 3914 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3915 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3916 3917 drm_dev_exit(idx); 3918 } 3919 3920 /** 3921 * DOC: usbc_pd_fw 3922 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3923 * this file will trigger the update process. 3924 */ 3925 static DEVICE_ATTR(usbc_pd_fw, 0644, 3926 psp_usbc_pd_fw_sysfs_read, 3927 psp_usbc_pd_fw_sysfs_write); 3928 3929 int is_psp_fw_valid(struct psp_bin_desc bin) 3930 { 3931 return bin.size_bytes; 3932 } 3933 3934 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3935 struct bin_attribute *bin_attr, 3936 char *buffer, loff_t pos, size_t count) 3937 { 3938 struct device *dev = kobj_to_dev(kobj); 3939 struct drm_device *ddev = dev_get_drvdata(dev); 3940 struct amdgpu_device *adev = drm_to_adev(ddev); 3941 3942 adev->psp.vbflash_done = false; 3943 3944 /* Safeguard against memory drain */ 3945 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3946 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 3947 kvfree(adev->psp.vbflash_tmp_buf); 3948 adev->psp.vbflash_tmp_buf = NULL; 3949 adev->psp.vbflash_image_size = 0; 3950 return -ENOMEM; 3951 } 3952 3953 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3954 if (!adev->psp.vbflash_tmp_buf) { 3955 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3956 if (!adev->psp.vbflash_tmp_buf) 3957 return -ENOMEM; 3958 } 3959 3960 mutex_lock(&adev->psp.mutex); 3961 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3962 adev->psp.vbflash_image_size += count; 3963 mutex_unlock(&adev->psp.mutex); 3964 3965 dev_dbg(adev->dev, "IFWI staged for update\n"); 3966 3967 return count; 3968 } 3969 3970 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3971 struct bin_attribute *bin_attr, char *buffer, 3972 loff_t pos, size_t count) 3973 { 3974 struct device *dev = kobj_to_dev(kobj); 3975 struct drm_device *ddev = dev_get_drvdata(dev); 3976 struct amdgpu_device *adev = drm_to_adev(ddev); 3977 struct amdgpu_bo *fw_buf_bo = NULL; 3978 uint64_t fw_pri_mc_addr; 3979 void *fw_pri_cpu_addr; 3980 int ret; 3981 3982 if (adev->psp.vbflash_image_size == 0) 3983 return -EINVAL; 3984 3985 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 3986 3987 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3988 AMDGPU_GPU_PAGE_SIZE, 3989 AMDGPU_GEM_DOMAIN_VRAM, 3990 &fw_buf_bo, 3991 &fw_pri_mc_addr, 3992 &fw_pri_cpu_addr); 3993 if (ret) 3994 goto rel_buf; 3995 3996 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3997 3998 mutex_lock(&adev->psp.mutex); 3999 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4000 mutex_unlock(&adev->psp.mutex); 4001 4002 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4003 4004 rel_buf: 4005 kvfree(adev->psp.vbflash_tmp_buf); 4006 adev->psp.vbflash_tmp_buf = NULL; 4007 adev->psp.vbflash_image_size = 0; 4008 4009 if (ret) { 4010 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4011 return ret; 4012 } 4013 4014 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4015 return 0; 4016 } 4017 4018 /** 4019 * DOC: psp_vbflash 4020 * Writing to this file will stage an IFWI for update. Reading from this file 4021 * will trigger the update process. 4022 */ 4023 static struct bin_attribute psp_vbflash_bin_attr = { 4024 .attr = {.name = "psp_vbflash", .mode = 0660}, 4025 .size = 0, 4026 .write = amdgpu_psp_vbflash_write, 4027 .read = amdgpu_psp_vbflash_read, 4028 }; 4029 4030 /** 4031 * DOC: psp_vbflash_status 4032 * The status of the flash process. 4033 * 0: IFWI flash not complete. 4034 * 1: IFWI flash complete. 4035 */ 4036 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4037 struct device_attribute *attr, 4038 char *buf) 4039 { 4040 struct drm_device *ddev = dev_get_drvdata(dev); 4041 struct amdgpu_device *adev = drm_to_adev(ddev); 4042 uint32_t vbflash_status; 4043 4044 vbflash_status = psp_vbflash_status(&adev->psp); 4045 if (!adev->psp.vbflash_done) 4046 vbflash_status = 0; 4047 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4048 vbflash_status = 1; 4049 4050 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4051 } 4052 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4053 4054 static struct bin_attribute *bin_flash_attrs[] = { 4055 &psp_vbflash_bin_attr, 4056 NULL 4057 }; 4058 4059 static struct attribute *flash_attrs[] = { 4060 &dev_attr_psp_vbflash_status.attr, 4061 &dev_attr_usbc_pd_fw.attr, 4062 NULL 4063 }; 4064 4065 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4066 { 4067 struct device *dev = kobj_to_dev(kobj); 4068 struct drm_device *ddev = dev_get_drvdata(dev); 4069 struct amdgpu_device *adev = drm_to_adev(ddev); 4070 4071 if (attr == &dev_attr_usbc_pd_fw.attr) 4072 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4073 4074 return adev->psp.sup_ifwi_up ? 0440 : 0; 4075 } 4076 4077 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4078 struct bin_attribute *attr, 4079 int idx) 4080 { 4081 struct device *dev = kobj_to_dev(kobj); 4082 struct drm_device *ddev = dev_get_drvdata(dev); 4083 struct amdgpu_device *adev = drm_to_adev(ddev); 4084 4085 return adev->psp.sup_ifwi_up ? 0660 : 0; 4086 } 4087 4088 const struct attribute_group amdgpu_flash_attr_group = { 4089 .attrs = flash_attrs, 4090 .bin_attrs = bin_flash_attrs, 4091 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4092 .is_visible = amdgpu_flash_attr_is_visible, 4093 }; 4094 4095 const struct amd_ip_funcs psp_ip_funcs = { 4096 .name = "psp", 4097 .early_init = psp_early_init, 4098 .sw_init = psp_sw_init, 4099 .sw_fini = psp_sw_fini, 4100 .hw_init = psp_hw_init, 4101 .hw_fini = psp_hw_fini, 4102 .suspend = psp_suspend, 4103 .resume = psp_resume, 4104 .set_clockgating_state = psp_set_clockgating_state, 4105 .set_powergating_state = psp_set_powergating_state, 4106 }; 4107 4108 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4109 .type = AMD_IP_BLOCK_TYPE_PSP, 4110 .major = 3, 4111 .minor = 1, 4112 .rev = 0, 4113 .funcs = &psp_ip_funcs, 4114 }; 4115 4116 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4117 .type = AMD_IP_BLOCK_TYPE_PSP, 4118 .major = 10, 4119 .minor = 0, 4120 .rev = 0, 4121 .funcs = &psp_ip_funcs, 4122 }; 4123 4124 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4125 .type = AMD_IP_BLOCK_TYPE_PSP, 4126 .major = 11, 4127 .minor = 0, 4128 .rev = 0, 4129 .funcs = &psp_ip_funcs, 4130 }; 4131 4132 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4133 .type = AMD_IP_BLOCK_TYPE_PSP, 4134 .major = 11, 4135 .minor = 0, 4136 .rev = 8, 4137 .funcs = &psp_ip_funcs, 4138 }; 4139 4140 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4141 .type = AMD_IP_BLOCK_TYPE_PSP, 4142 .major = 12, 4143 .minor = 0, 4144 .rev = 0, 4145 .funcs = &psp_ip_funcs, 4146 }; 4147 4148 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4149 .type = AMD_IP_BLOCK_TYPE_PSP, 4150 .major = 13, 4151 .minor = 0, 4152 .rev = 0, 4153 .funcs = &psp_ip_funcs, 4154 }; 4155 4156 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4157 .type = AMD_IP_BLOCK_TYPE_PSP, 4158 .major = 13, 4159 .minor = 0, 4160 .rev = 4, 4161 .funcs = &psp_ip_funcs, 4162 }; 4163 4164 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4165 .type = AMD_IP_BLOCK_TYPE_PSP, 4166 .major = 14, 4167 .minor = 0, 4168 .rev = 0, 4169 .funcs = &psp_ip_funcs, 4170 }; 4171