1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 psp_v15_0_0_set_psp_funcs(psp); 279 psp->boot_time_tmr = false; 280 break; 281 case IP_VERSION(15, 0, 8): 282 psp_v15_0_8_set_psp_funcs(psp); 283 break; 284 default: 285 return -EINVAL; 286 } 287 288 psp->adev = adev; 289 290 adev->psp_timeout = 20000; 291 292 psp_check_pmfw_centralized_cstate_management(psp); 293 294 if (amdgpu_sriov_vf(adev)) 295 return psp_init_sriov_microcode(psp); 296 else 297 return psp_init_microcode(psp); 298 } 299 300 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 301 { 302 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 303 &mem_ctx->shared_buf); 304 mem_ctx->shared_bo = NULL; 305 } 306 307 static void psp_free_shared_bufs(struct psp_context *psp) 308 { 309 void *tmr_buf; 310 void **pptr; 311 312 /* free TMR memory buffer */ 313 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 314 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 315 psp->tmr_bo = NULL; 316 317 /* free xgmi shared memory */ 318 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 319 320 /* free ras shared memory */ 321 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 322 323 /* free hdcp shared memory */ 324 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 325 326 /* free dtm shared memory */ 327 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 328 329 /* free rap shared memory */ 330 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 331 332 /* free securedisplay shared memory */ 333 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 334 335 336 } 337 338 static void psp_memory_training_fini(struct psp_context *psp) 339 { 340 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 341 342 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 343 kfree(ctx->sys_cache); 344 ctx->sys_cache = NULL; 345 } 346 347 static int psp_memory_training_init(struct psp_context *psp) 348 { 349 int ret; 350 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 351 352 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 353 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 354 return 0; 355 } 356 357 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 358 if (ctx->sys_cache == NULL) { 359 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 360 ret = -ENOMEM; 361 goto Err_out; 362 } 363 364 dev_dbg(psp->adev->dev, 365 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 366 ctx->train_data_size, 367 ctx->p2c_train_data_offset, 368 ctx->c2p_train_data_offset); 369 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 370 return 0; 371 372 Err_out: 373 psp_memory_training_fini(psp); 374 return ret; 375 } 376 377 /* 378 * Helper funciton to query psp runtime database entry 379 * 380 * @adev: amdgpu_device pointer 381 * @entry_type: the type of psp runtime database entry 382 * @db_entry: runtime database entry pointer 383 * 384 * Return false if runtime database doesn't exit or entry is invalid 385 * or true if the specific database entry is found, and copy to @db_entry 386 */ 387 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 388 enum psp_runtime_entry_type entry_type, 389 void *db_entry) 390 { 391 uint64_t db_header_pos, db_dir_pos; 392 struct psp_runtime_data_header db_header = {0}; 393 struct psp_runtime_data_directory db_dir = {0}; 394 bool ret = false; 395 int i; 396 397 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 398 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 399 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 401 return false; 402 403 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 404 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 405 406 /* read runtime db header from vram */ 407 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 408 sizeof(struct psp_runtime_data_header), false); 409 410 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 411 /* runtime db doesn't exist, exit */ 412 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 413 return false; 414 } 415 416 /* read runtime database entry from vram */ 417 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 418 sizeof(struct psp_runtime_data_directory), false); 419 420 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 421 /* invalid db entry count, exit */ 422 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 423 return false; 424 } 425 426 /* look up for requested entry type */ 427 for (i = 0; i < db_dir.entry_count && !ret; i++) { 428 if (db_dir.entry_list[i].entry_type == entry_type) { 429 switch (entry_type) { 430 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 431 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 432 /* invalid db entry size */ 433 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 434 return false; 435 } 436 /* read runtime database entry */ 437 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 438 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 439 ret = true; 440 break; 441 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 442 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 443 /* invalid db entry size */ 444 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 445 return false; 446 } 447 /* read runtime database entry */ 448 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 449 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 450 ret = true; 451 break; 452 default: 453 ret = false; 454 break; 455 } 456 } 457 } 458 459 return ret; 460 } 461 462 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 463 { 464 struct amdgpu_device *adev = ip_block->adev; 465 struct psp_context *psp = &adev->psp; 466 int ret; 467 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 468 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 469 struct psp_runtime_scpm_entry scpm_entry; 470 471 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 472 if (!psp->cmd) { 473 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 474 return -ENOMEM; 475 } 476 477 adev->psp.xgmi_context.supports_extended_data = 478 !adev->gmc.xgmi.connected_to_cpu && 479 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 480 481 memset(&scpm_entry, 0, sizeof(scpm_entry)); 482 if ((psp_get_runtime_db_entry(adev, 483 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 484 &scpm_entry)) && 485 (scpm_entry.scpm_status != SCPM_DISABLE)) { 486 adev->scpm_enabled = true; 487 adev->scpm_status = scpm_entry.scpm_status; 488 } else { 489 adev->scpm_enabled = false; 490 adev->scpm_status = SCPM_DISABLE; 491 } 492 493 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 494 495 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 496 if (psp_get_runtime_db_entry(adev, 497 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 498 &boot_cfg_entry)) { 499 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 500 if ((psp->boot_cfg_bitmask) & 501 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 502 /* If psp runtime database exists, then 503 * only enable two stage memory training 504 * when TWO_STAGE_DRAM_TRAINING bit is set 505 * in runtime database 506 */ 507 mem_training_ctx->enable_mem_training = true; 508 } 509 510 } else { 511 /* If psp runtime database doesn't exist or is 512 * invalid, force enable two stage memory training 513 */ 514 mem_training_ctx->enable_mem_training = true; 515 } 516 517 if (mem_training_ctx->enable_mem_training) { 518 ret = psp_memory_training_init(psp); 519 if (ret) { 520 dev_err(adev->dev, "Failed to initialize memory training!\n"); 521 return ret; 522 } 523 524 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 525 if (ret) { 526 dev_err(adev->dev, "Failed to process memory training!\n"); 527 return ret; 528 } 529 } 530 531 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 532 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 533 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 534 &psp->fw_pri_bo, 535 &psp->fw_pri_mc_addr, 536 &psp->fw_pri_buf); 537 if (ret) 538 return ret; 539 540 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 541 AMDGPU_GEM_DOMAIN_VRAM | 542 AMDGPU_GEM_DOMAIN_GTT, 543 &psp->fence_buf_bo, 544 &psp->fence_buf_mc_addr, 545 &psp->fence_buf); 546 if (ret) 547 goto failed1; 548 549 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 550 AMDGPU_GEM_DOMAIN_VRAM | 551 AMDGPU_GEM_DOMAIN_GTT, 552 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 553 (void **)&psp->cmd_buf_mem); 554 if (ret) 555 goto failed2; 556 557 return 0; 558 559 failed2: 560 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 561 &psp->fence_buf_mc_addr, &psp->fence_buf); 562 failed1: 563 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 564 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 565 return ret; 566 } 567 568 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 569 { 570 struct amdgpu_device *adev = ip_block->adev; 571 struct psp_context *psp = &adev->psp; 572 573 psp_memory_training_fini(psp); 574 575 amdgpu_ucode_release(&psp->sos_fw); 576 amdgpu_ucode_release(&psp->asd_fw); 577 amdgpu_ucode_release(&psp->ta_fw); 578 amdgpu_ucode_release(&psp->cap_fw); 579 amdgpu_ucode_release(&psp->toc_fw); 580 581 kfree(psp->cmd); 582 psp->cmd = NULL; 583 584 psp_free_shared_bufs(psp); 585 586 if (psp->km_ring.ring_mem) 587 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 588 &psp->km_ring.ring_mem_mc_addr, 589 (void **)&psp->km_ring.ring_mem); 590 591 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 592 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 593 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 594 &psp->fence_buf_mc_addr, &psp->fence_buf); 595 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 596 (void **)&psp->cmd_buf_mem); 597 598 return 0; 599 } 600 601 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 602 uint32_t mask, uint32_t flags) 603 { 604 bool check_changed = flags & PSP_WAITREG_CHANGED; 605 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 606 uint32_t val; 607 int i; 608 struct amdgpu_device *adev = psp->adev; 609 610 if (psp->adev->no_hw_access) 611 return 0; 612 613 for (i = 0; i < adev->usec_timeout; i++) { 614 val = RREG32(reg_index); 615 if (check_changed) { 616 if (val != reg_val) 617 return 0; 618 } else { 619 if ((val & mask) == reg_val) 620 return 0; 621 } 622 udelay(1); 623 } 624 625 if (verbose) 626 dev_err(adev->dev, 627 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 628 reg_index, mask, val, reg_val); 629 630 return -ETIME; 631 } 632 633 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 634 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 635 { 636 uint32_t val; 637 int i; 638 struct amdgpu_device *adev = psp->adev; 639 640 if (psp->adev->no_hw_access) 641 return 0; 642 643 for (i = 0; i < msec_timeout; i++) { 644 val = RREG32(reg_index); 645 if ((val & mask) == reg_val) 646 return 0; 647 msleep(1); 648 } 649 650 return -ETIME; 651 } 652 653 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 654 { 655 switch (cmd_id) { 656 case GFX_CMD_ID_LOAD_TA: 657 return "LOAD_TA"; 658 case GFX_CMD_ID_UNLOAD_TA: 659 return "UNLOAD_TA"; 660 case GFX_CMD_ID_INVOKE_CMD: 661 return "INVOKE_CMD"; 662 case GFX_CMD_ID_LOAD_ASD: 663 return "LOAD_ASD"; 664 case GFX_CMD_ID_SETUP_TMR: 665 return "SETUP_TMR"; 666 case GFX_CMD_ID_LOAD_IP_FW: 667 return "LOAD_IP_FW"; 668 case GFX_CMD_ID_DESTROY_TMR: 669 return "DESTROY_TMR"; 670 case GFX_CMD_ID_SAVE_RESTORE: 671 return "SAVE_RESTORE_IP_FW"; 672 case GFX_CMD_ID_SETUP_VMR: 673 return "SETUP_VMR"; 674 case GFX_CMD_ID_DESTROY_VMR: 675 return "DESTROY_VMR"; 676 case GFX_CMD_ID_PROG_REG: 677 return "PROG_REG"; 678 case GFX_CMD_ID_GET_FW_ATTESTATION: 679 return "GET_FW_ATTESTATION"; 680 case GFX_CMD_ID_LOAD_TOC: 681 return "ID_LOAD_TOC"; 682 case GFX_CMD_ID_AUTOLOAD_RLC: 683 return "AUTOLOAD_RLC"; 684 case GFX_CMD_ID_BOOT_CFG: 685 return "BOOT_CFG"; 686 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 687 return "CONFIG_SQ_PERFMON"; 688 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 689 return "FB_FW_RESERV_ADDR"; 690 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 691 return "FB_FW_RESERV_EXT_ADDR"; 692 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 693 return "SPATIAL_PARTITION"; 694 case GFX_CMD_ID_FB_NPS_MODE: 695 return "NPS_MODE_CHANGE"; 696 case GFX_CMD_ID_PERF_HW: 697 return "PERF MONITORING HW"; 698 default: 699 return "UNKNOWN CMD"; 700 } 701 } 702 703 static bool psp_err_warn(struct psp_context *psp) 704 { 705 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 706 707 /* This response indicates reg list is already loaded */ 708 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 709 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 710 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 711 cmd->resp.status == TEE_ERROR_CANCEL) 712 return false; 713 714 return true; 715 } 716 717 static int 718 psp_cmd_submit_buf(struct psp_context *psp, 719 struct amdgpu_firmware_info *ucode, 720 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 721 { 722 int ret; 723 int index; 724 int timeout = psp->adev->psp_timeout; 725 bool ras_intr = false; 726 bool skip_unsupport = false; 727 728 if (psp->adev->no_hw_access) 729 return 0; 730 731 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 732 733 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 734 735 index = atomic_inc_return(&psp->fence_value); 736 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 737 if (ret) { 738 atomic_dec(&psp->fence_value); 739 goto exit; 740 } 741 742 amdgpu_device_invalidate_hdp(psp->adev, NULL); 743 while (*((unsigned int *)psp->fence_buf) != index) { 744 if (--timeout == 0) 745 break; 746 /* 747 * Shouldn't wait for timeout when err_event_athub occurs, 748 * because gpu reset thread triggered and lock resource should 749 * be released for psp resume sequence. 750 */ 751 ras_intr = amdgpu_ras_intr_triggered(); 752 if (ras_intr) 753 break; 754 usleep_range(60, 100); 755 amdgpu_device_invalidate_hdp(psp->adev, NULL); 756 } 757 758 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 759 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 760 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 761 762 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 763 764 /* In some cases, psp response status is not 0 even there is no 765 * problem while the command is submitted. Some version of PSP FW 766 * doesn't write 0 to that field. 767 * So here we would like to only print a warning instead of an error 768 * during psp initialization to avoid breaking hw_init and it doesn't 769 * return -EINVAL. 770 */ 771 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 772 if (ucode) 773 dev_warn(psp->adev->dev, 774 "failed to load ucode %s(0x%X) ", 775 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 776 if (psp_err_warn(psp)) 777 dev_warn( 778 psp->adev->dev, 779 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 780 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 781 psp->cmd_buf_mem->cmd_id, 782 psp->cmd_buf_mem->resp.status); 783 /* If any firmware (including CAP) load fails under SRIOV, it should 784 * return failure to stop the VF from initializing. 785 * Also return failure in case of timeout 786 */ 787 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 788 ret = -EINVAL; 789 goto exit; 790 } 791 } 792 793 if (ucode) { 794 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 795 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 796 } 797 798 exit: 799 return ret; 800 } 801 802 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 803 { 804 struct psp_gfx_cmd_resp *cmd = psp->cmd; 805 806 mutex_lock(&psp->mutex); 807 808 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 809 810 return cmd; 811 } 812 813 static void release_psp_cmd_buf(struct psp_context *psp) 814 { 815 mutex_unlock(&psp->mutex); 816 } 817 818 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 819 struct psp_gfx_cmd_resp *cmd, 820 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 821 { 822 struct amdgpu_device *adev = psp->adev; 823 uint32_t size = 0; 824 uint64_t tmr_pa = 0; 825 826 if (tmr_bo) { 827 size = amdgpu_bo_size(tmr_bo); 828 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 829 } 830 831 if (amdgpu_sriov_vf(psp->adev)) 832 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 833 else 834 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 835 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 836 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 837 cmd->cmd.cmd_setup_tmr.buf_size = size; 838 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 839 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 840 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 841 } 842 843 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 844 uint64_t pri_buf_mc, uint32_t size) 845 { 846 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 847 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 848 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 849 cmd->cmd.cmd_load_toc.toc_size = size; 850 } 851 852 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 853 static int psp_load_toc(struct psp_context *psp, 854 uint32_t *tmr_size) 855 { 856 int ret; 857 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 858 859 /* Copy toc to psp firmware private buffer */ 860 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 861 862 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 863 864 ret = psp_cmd_submit_buf(psp, NULL, cmd, 865 psp->fence_buf_mc_addr); 866 if (!ret) 867 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 868 869 release_psp_cmd_buf(psp); 870 871 return ret; 872 } 873 874 /* Set up Trusted Memory Region */ 875 static int psp_tmr_init(struct psp_context *psp) 876 { 877 int ret = 0; 878 int tmr_size; 879 void *tmr_buf; 880 void **pptr; 881 882 /* 883 * According to HW engineer, they prefer the TMR address be "naturally 884 * aligned" , e.g. the start address be an integer divide of TMR size. 885 * 886 * Note: this memory need be reserved till the driver 887 * uninitializes. 888 */ 889 tmr_size = PSP_TMR_SIZE(psp->adev); 890 891 /* For ASICs support RLC autoload, psp will parse the toc 892 * and calculate the total size of TMR needed 893 */ 894 if (!amdgpu_sriov_vf(psp->adev) && 895 psp->toc.start_addr && 896 psp->toc.size_bytes && 897 psp->fw_pri_buf) { 898 ret = psp_load_toc(psp, &tmr_size); 899 if (ret) { 900 dev_err(psp->adev->dev, "Failed to load toc\n"); 901 return ret; 902 } 903 } 904 905 if (!psp->tmr_bo && !psp->boot_time_tmr) { 906 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 907 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 908 PSP_TMR_ALIGNMENT, 909 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 910 &psp->tmr_bo, &psp->tmr_mc_addr, 911 pptr); 912 } 913 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 914 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 915 916 return ret; 917 } 918 919 static bool psp_skip_tmr(struct psp_context *psp) 920 { 921 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 922 923 if (amdgpu_sriov_vf(psp->adev)) 924 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 925 else 926 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 927 } 928 929 static int psp_tmr_load(struct psp_context *psp) 930 { 931 int ret; 932 struct psp_gfx_cmd_resp *cmd; 933 934 if (psp_skip_tmr(psp)) 935 return 0; 936 937 cmd = acquire_psp_cmd_buf(psp); 938 939 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 940 if (psp->tmr_bo) 941 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 942 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 943 944 ret = psp_cmd_submit_buf(psp, NULL, cmd, 945 psp->fence_buf_mc_addr); 946 947 release_psp_cmd_buf(psp); 948 949 return ret; 950 } 951 952 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 953 struct psp_gfx_cmd_resp *cmd) 954 { 955 if (amdgpu_sriov_vf(psp->adev)) 956 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 957 else 958 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 959 } 960 961 static int psp_tmr_unload(struct psp_context *psp) 962 { 963 int ret; 964 struct psp_gfx_cmd_resp *cmd; 965 966 if (psp_skip_tmr(psp)) 967 return 0; 968 969 cmd = acquire_psp_cmd_buf(psp); 970 971 psp_prep_tmr_unload_cmd_buf(psp, cmd); 972 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 973 974 ret = psp_cmd_submit_buf(psp, NULL, cmd, 975 psp->fence_buf_mc_addr); 976 977 release_psp_cmd_buf(psp); 978 979 return ret; 980 } 981 982 static int psp_tmr_terminate(struct psp_context *psp) 983 { 984 return psp_tmr_unload(psp); 985 } 986 987 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 988 uint64_t *output_ptr) 989 { 990 int ret; 991 struct psp_gfx_cmd_resp *cmd; 992 993 if (!output_ptr) 994 return -EINVAL; 995 996 if (amdgpu_sriov_vf(psp->adev)) 997 return 0; 998 999 cmd = acquire_psp_cmd_buf(psp); 1000 1001 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1002 1003 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1004 psp->fence_buf_mc_addr); 1005 1006 if (!ret) { 1007 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1008 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1009 } 1010 1011 release_psp_cmd_buf(psp); 1012 1013 return ret; 1014 } 1015 1016 static int psp_get_fw_reservation_info(struct psp_context *psp, 1017 uint32_t cmd_id, 1018 uint64_t *addr, 1019 uint32_t *size) 1020 { 1021 int ret; 1022 uint32_t status; 1023 struct psp_gfx_cmd_resp *cmd; 1024 1025 cmd = acquire_psp_cmd_buf(psp); 1026 1027 cmd->cmd_id = cmd_id; 1028 1029 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1030 psp->fence_buf_mc_addr); 1031 if (ret) { 1032 release_psp_cmd_buf(psp); 1033 return ret; 1034 } 1035 1036 status = cmd->resp.status; 1037 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1038 release_psp_cmd_buf(psp); 1039 *addr = 0; 1040 *size = 0; 1041 return 0; 1042 } 1043 1044 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1045 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1046 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1047 1048 release_psp_cmd_buf(psp); 1049 1050 return 0; 1051 } 1052 1053 int psp_update_fw_reservation(struct psp_context *psp) 1054 { 1055 int ret; 1056 uint64_t reserv_addr, reserv_addr_ext; 1057 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1058 struct amdgpu_device *adev = psp->adev; 1059 1060 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1061 1062 if (amdgpu_sriov_vf(psp->adev)) 1063 return 0; 1064 1065 switch (mp0_ip_ver) { 1066 case IP_VERSION(14, 0, 2): 1067 if (adev->psp.sos.fw_version < 0x3b0e0d) 1068 return 0; 1069 break; 1070 1071 case IP_VERSION(14, 0, 3): 1072 if (adev->psp.sos.fw_version < 0x3a0e14) 1073 return 0; 1074 break; 1075 1076 default: 1077 return 0; 1078 } 1079 1080 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1081 if (ret) 1082 return ret; 1083 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1084 if (ret) 1085 return ret; 1086 1087 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1088 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1089 return 0; 1090 } 1091 1092 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1093 1094 reserv_size = roundup(reserv_size, SZ_1M); 1095 1096 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1097 reserv_addr, reserv_size, false); 1098 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1099 if (ret) { 1100 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1101 return ret; 1102 } 1103 1104 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1105 1106 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1107 reserv_addr_ext, reserv_size_ext, false); 1108 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1109 if (ret) { 1110 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1111 return ret; 1112 } 1113 1114 return 0; 1115 } 1116 1117 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1118 { 1119 struct psp_context *psp = &adev->psp; 1120 struct psp_gfx_cmd_resp *cmd; 1121 int ret; 1122 1123 if (amdgpu_sriov_vf(adev)) 1124 return 0; 1125 1126 cmd = acquire_psp_cmd_buf(psp); 1127 1128 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1129 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1130 1131 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1132 if (!ret) { 1133 *boot_cfg = 1134 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1135 } 1136 1137 release_psp_cmd_buf(psp); 1138 1139 return ret; 1140 } 1141 1142 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1143 { 1144 int ret; 1145 struct psp_context *psp = &adev->psp; 1146 struct psp_gfx_cmd_resp *cmd; 1147 1148 if (amdgpu_sriov_vf(adev)) 1149 return 0; 1150 1151 cmd = acquire_psp_cmd_buf(psp); 1152 1153 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1154 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1155 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1156 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1157 1158 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1159 1160 release_psp_cmd_buf(psp); 1161 1162 return ret; 1163 } 1164 1165 static int psp_rl_load(struct amdgpu_device *adev) 1166 { 1167 int ret; 1168 struct psp_context *psp = &adev->psp; 1169 struct psp_gfx_cmd_resp *cmd; 1170 1171 if (!is_psp_fw_valid(psp->rl)) 1172 return 0; 1173 1174 cmd = acquire_psp_cmd_buf(psp); 1175 1176 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1177 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1178 1179 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1180 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1181 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1182 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1183 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1184 1185 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1186 1187 release_psp_cmd_buf(psp); 1188 1189 return ret; 1190 } 1191 1192 int psp_memory_partition(struct psp_context *psp, int mode) 1193 { 1194 struct psp_gfx_cmd_resp *cmd; 1195 int ret; 1196 1197 if (amdgpu_sriov_vf(psp->adev)) 1198 return 0; 1199 1200 cmd = acquire_psp_cmd_buf(psp); 1201 1202 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1203 cmd->cmd.cmd_memory_part.mode = mode; 1204 1205 dev_info(psp->adev->dev, 1206 "Requesting %d memory partition change through PSP", mode); 1207 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1208 if (ret) 1209 dev_err(psp->adev->dev, 1210 "PSP request failed to change to NPS%d mode\n", mode); 1211 1212 release_psp_cmd_buf(psp); 1213 1214 return ret; 1215 } 1216 1217 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1218 uint32_t *ptl_fmt) 1219 { 1220 struct amdgpu_device *adev = psp->adev; 1221 1222 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1223 return -EINVAL; 1224 1225 switch (fmt) { 1226 case AMDGPU_PTL_FMT_I8: 1227 *ptl_fmt = GFX_FTYPE_I8; 1228 break; 1229 case AMDGPU_PTL_FMT_F16: 1230 *ptl_fmt = GFX_FTYPE_F16; 1231 break; 1232 case AMDGPU_PTL_FMT_BF16: 1233 *ptl_fmt = GFX_FTYPE_BF16; 1234 break; 1235 case AMDGPU_PTL_FMT_F32: 1236 *ptl_fmt = GFX_FTYPE_F32; 1237 break; 1238 case AMDGPU_PTL_FMT_F64: 1239 *ptl_fmt = GFX_FTYPE_F64; 1240 break; 1241 case AMDGPU_PTL_FMT_F8: 1242 *ptl_fmt = GFX_FTYPE_F8; 1243 break; 1244 case AMDGPU_PTL_FMT_VECTOR: 1245 *ptl_fmt = GFX_FTYPE_VECTOR; 1246 break; 1247 default: 1248 return -EINVAL; 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1255 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1256 { 1257 struct psp_gfx_cmd_resp *cmd; 1258 struct amdgpu_ptl *ptl = &psp->ptl; 1259 int ret; 1260 1261 cmd = acquire_psp_cmd_buf(psp); 1262 1263 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1264 cmd->cmd.cmd_req_perf_hw.req = req_code; 1265 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1266 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1267 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1268 1269 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1270 if (ret) 1271 goto out; 1272 1273 /* 1274 * Check response status explicitly to avoid 1275 * updating cached PTL state with invalid data. 1276 */ 1277 if (cmd->resp.status) { 1278 dev_err(psp->adev->dev, 1279 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1280 req_code, cmd->resp.status, 1281 cmd->resp.uresp.perf_hw_info.resp); 1282 ret = -EIO; 1283 goto out; 1284 } 1285 1286 /* Parse response */ 1287 switch (req_code) { 1288 case PSP_PTL_PERF_MON_QUERY: 1289 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1290 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1291 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1292 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1293 *ptl_state, *fmt1, *fmt2); 1294 break; 1295 case PSP_PTL_PERF_MON_SET: 1296 /* Update cached state only on success */ 1297 ptl->enabled = *ptl_state; 1298 ptl->fmt1 = *fmt1; 1299 ptl->fmt2 = *fmt2; 1300 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1301 *ptl_state, *fmt1, *fmt2); 1302 break; 1303 } 1304 1305 out: 1306 release_psp_cmd_buf(psp); 1307 return ret; 1308 } 1309 1310 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1311 uint32_t *ptl_state, 1312 enum amdgpu_ptl_fmt *fmt1, 1313 enum amdgpu_ptl_fmt *fmt2) 1314 { 1315 uint32_t ptl_fmt1, ptl_fmt2; 1316 struct psp_context *psp; 1317 struct amdgpu_ptl *ptl; 1318 int ret; 1319 1320 if (!adev || !ptl_state || !fmt1 || !fmt2) 1321 return -EINVAL; 1322 1323 if (amdgpu_sriov_vf(adev)) 1324 return 0; 1325 1326 psp = &adev->psp; 1327 ptl = &psp->ptl; 1328 1329 if (ptl->permanently_disabled && *ptl_state == 1) 1330 return 0; 1331 1332 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1333 psp->sos.fw_version < 0x0036081a) 1334 return -EOPNOTSUPP; 1335 1336 /* Verify formats */ 1337 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1338 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1339 return -EINVAL; 1340 1341 /* 1342 * Add check to skip if state and formats are identical to current ones 1343 */ 1344 if (req_code == PSP_PTL_PERF_MON_SET && 1345 ptl->enabled == *ptl_state && 1346 ptl->fmt1 == ptl_fmt1 && 1347 ptl->fmt2 == ptl_fmt2) 1348 return 0; 1349 1350 /* If enabling PTL, check disable bitmap */ 1351 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1352 if (!bitmap_empty(ptl->disable_bitmap, 1353 AMDGPU_PTL_DISABLE_MAX)) { 1354 dev_dbg(adev->dev, 1355 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1356 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1357 ptl->disable_bitmap), 1358 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1359 ptl->disable_bitmap), 1360 atomic_read(&ptl->disable_ref)); 1361 return 0; 1362 } 1363 } 1364 1365 if (req_code == PSP_PTL_PERF_MON_SET) { 1366 amdgpu_amdkfd_stop_sched_all(adev); 1367 /* Wait for GFX engine idle before PTL state transition */ 1368 ret = amdgpu_device_ip_wait_for_idle(adev, 1369 AMD_IP_BLOCK_TYPE_GFX); 1370 if (ret) { 1371 amdgpu_amdkfd_start_sched_all(adev); 1372 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1373 return ret; 1374 } 1375 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1376 amdgpu_amdkfd_start_sched_all(adev); 1377 } else { 1378 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1379 } 1380 1381 return ret; 1382 } 1383 1384 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1385 { 1386 int i; 1387 1388 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1389 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1390 return (enum amdgpu_ptl_fmt)i; 1391 } 1392 1393 return AMDGPU_PTL_FMT_INVALID; 1394 } 1395 1396 static ssize_t ptl_supported_formats_show(struct device *dev, 1397 struct device_attribute *attr, char *buf) 1398 { 1399 ssize_t len = 0; 1400 1401 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1402 const char *fmt = amdgpu_ptl_fmt_str[i]; 1403 1404 len += sysfs_emit_at(buf, len, "%s%s", 1405 fmt ? fmt : "UNKNOWN", 1406 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1407 } 1408 1409 return len; 1410 } 1411 1412 static ssize_t ptl_enable_store(struct device *dev, 1413 struct device_attribute *attr, 1414 const char *buf, size_t count) 1415 { 1416 struct drm_device *ddev = dev_get_drvdata(dev); 1417 struct amdgpu_device *adev = drm_to_adev(ddev); 1418 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1419 uint32_t ptl_state, fmt1, fmt2; 1420 int ret; 1421 bool enable; 1422 bool bit_changed = false; 1423 1424 mutex_lock(&ptl->mutex); 1425 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1426 enable = true; 1427 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1428 enable = false; 1429 } else { 1430 mutex_unlock(&ptl->mutex); 1431 return -EINVAL; 1432 } 1433 1434 /* Block enable when permanently disabled */ 1435 if (ptl->permanently_disabled) { 1436 mutex_unlock(&ptl->mutex); 1437 return -EPERM; 1438 } 1439 1440 fmt1 = ptl->fmt1; 1441 fmt2 = ptl->fmt2; 1442 ptl_state = enable ? 1 : 0; 1443 1444 if (enable) 1445 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1446 ptl->disable_bitmap); 1447 1448 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1449 if (ret) { 1450 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1451 if (enable && bit_changed) 1452 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1453 mutex_unlock(&ptl->mutex); 1454 return ret; 1455 } 1456 1457 if (!enable) 1458 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1459 1460 mutex_unlock(&ptl->mutex); 1461 1462 return count; 1463 } 1464 1465 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1466 { 1467 struct drm_device *ddev = dev_get_drvdata(dev); 1468 struct amdgpu_device *adev = drm_to_adev(ddev); 1469 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1470 1471 if (ptl->permanently_disabled) 1472 return sysfs_emit(buf, "permanently disabled\n"); 1473 1474 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1475 } 1476 1477 static ssize_t ptl_format_store(struct device *dev, 1478 struct device_attribute *attr, 1479 const char *buf, size_t count) 1480 { 1481 struct drm_device *ddev = dev_get_drvdata(dev); 1482 struct amdgpu_device *adev = drm_to_adev(ddev); 1483 char fmt1_str[8], fmt2_str[8]; 1484 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1485 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1486 uint32_t ptl_state, fmt1, fmt2; 1487 int ret; 1488 1489 /* Only allow format update when PTL is enabled */ 1490 if (!ptl->enabled) 1491 return -EPERM; 1492 1493 mutex_lock(&ptl->mutex); 1494 /* Parse input, expecting "FMT1,FMT2" */ 1495 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1496 mutex_unlock(&ptl->mutex); 1497 return -EINVAL; 1498 } 1499 1500 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1501 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1502 1503 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1504 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1505 fmt1_enum == fmt2_enum) { 1506 mutex_unlock(&ptl->mutex); 1507 return -EINVAL; 1508 } 1509 1510 ptl_state = ptl->enabled; 1511 fmt1 = fmt1_enum; 1512 fmt2 = fmt2_enum; 1513 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1514 if (ret) { 1515 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1516 mutex_unlock(&ptl->mutex); 1517 return ret; 1518 } 1519 mutex_unlock(&ptl->mutex); 1520 1521 return count; 1522 } 1523 1524 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1525 { 1526 struct drm_device *ddev = dev_get_drvdata(dev); 1527 struct amdgpu_device *adev = drm_to_adev(ddev); 1528 struct psp_context *psp = &adev->psp; 1529 1530 return sysfs_emit(buf, "%s,%s\n", 1531 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1532 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1533 } 1534 1535 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1536 { 1537 struct device *dev = kobj_to_dev(kobj); 1538 struct drm_device *ddev = dev_get_drvdata(dev); 1539 struct amdgpu_device *adev = drm_to_adev(ddev); 1540 1541 /* Only show PTL sysfs files if PTL hardware is supported */ 1542 if (!adev->psp.ptl.hw_supported) 1543 return 0; 1544 1545 return attr->mode; 1546 } 1547 1548 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1549 { 1550 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1551 int ret; 1552 1553 if (!ptl->hw_supported) 1554 return 0; 1555 1556 if (ptl->ptl_sysfs_created) 1557 return 0; 1558 1559 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1560 if (!ret) 1561 ptl->ptl_sysfs_created = true; 1562 1563 return ret; 1564 } 1565 1566 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1567 { 1568 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1569 1570 if (!ptl->hw_supported) 1571 return; 1572 1573 if (!ptl->ptl_sysfs_created) 1574 return; 1575 1576 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1577 ptl->ptl_sysfs_created = false; 1578 } 1579 1580 int psp_spatial_partition(struct psp_context *psp, int mode) 1581 { 1582 struct psp_gfx_cmd_resp *cmd; 1583 int ret; 1584 1585 if (amdgpu_sriov_vf(psp->adev)) 1586 return 0; 1587 1588 cmd = acquire_psp_cmd_buf(psp); 1589 1590 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1591 cmd->cmd.cmd_spatial_part.mode = mode; 1592 1593 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1594 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1595 1596 release_psp_cmd_buf(psp); 1597 1598 return ret; 1599 } 1600 1601 static int psp_asd_initialize(struct psp_context *psp) 1602 { 1603 int ret; 1604 1605 /* If PSP version doesn't match ASD version, asd loading will be failed. 1606 * add workaround to bypass it for sriov now. 1607 * TODO: add version check to make it common 1608 */ 1609 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1610 return 0; 1611 1612 /* bypass asd if display hardware is not available */ 1613 if (!amdgpu_device_has_display_hardware(psp->adev) && 1614 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1615 return 0; 1616 1617 psp->asd_context.mem_context.shared_mc_addr = 0; 1618 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1619 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1620 1621 ret = psp_ta_load(psp, &psp->asd_context); 1622 if (!ret) 1623 psp->asd_context.initialized = true; 1624 1625 return ret; 1626 } 1627 1628 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1629 uint32_t session_id) 1630 { 1631 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1632 cmd->cmd.cmd_unload_ta.session_id = session_id; 1633 } 1634 1635 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1636 { 1637 int ret; 1638 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1639 1640 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1641 1642 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1643 1644 context->resp_status = cmd->resp.status; 1645 1646 release_psp_cmd_buf(psp); 1647 1648 return ret; 1649 } 1650 1651 static int psp_asd_terminate(struct psp_context *psp) 1652 { 1653 int ret; 1654 1655 if (amdgpu_sriov_vf(psp->adev)) 1656 return 0; 1657 1658 if (!psp->asd_context.initialized) 1659 return 0; 1660 1661 ret = psp_ta_unload(psp, &psp->asd_context); 1662 if (!ret) 1663 psp->asd_context.initialized = false; 1664 1665 return ret; 1666 } 1667 1668 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1669 uint32_t id, uint32_t value) 1670 { 1671 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1672 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1673 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1674 } 1675 1676 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1677 uint32_t value) 1678 { 1679 struct psp_gfx_cmd_resp *cmd; 1680 int ret = 0; 1681 1682 if (reg >= PSP_REG_LAST) 1683 return -EINVAL; 1684 1685 cmd = acquire_psp_cmd_buf(psp); 1686 1687 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1688 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1689 if (ret) 1690 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1691 1692 release_psp_cmd_buf(psp); 1693 1694 return ret; 1695 } 1696 1697 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1698 uint64_t ta_bin_mc, 1699 struct ta_context *context) 1700 { 1701 cmd->cmd_id = context->ta_load_type; 1702 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1703 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1704 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1705 1706 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1707 lower_32_bits(context->mem_context.shared_mc_addr); 1708 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1709 upper_32_bits(context->mem_context.shared_mc_addr); 1710 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1711 } 1712 1713 int psp_ta_init_shared_buf(struct psp_context *psp, 1714 struct ta_mem_context *mem_ctx) 1715 { 1716 /* 1717 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1718 * physical) for ta to host memory 1719 */ 1720 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1721 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1722 AMDGPU_GEM_DOMAIN_GTT, 1723 &mem_ctx->shared_bo, 1724 &mem_ctx->shared_mc_addr, 1725 &mem_ctx->shared_buf); 1726 } 1727 1728 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1729 uint32_t ta_cmd_id, 1730 uint32_t session_id) 1731 { 1732 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1733 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1734 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1735 } 1736 1737 int psp_ta_invoke(struct psp_context *psp, 1738 uint32_t ta_cmd_id, 1739 struct ta_context *context) 1740 { 1741 int ret; 1742 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1743 1744 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1745 1746 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1747 psp->fence_buf_mc_addr); 1748 1749 context->resp_status = cmd->resp.status; 1750 1751 release_psp_cmd_buf(psp); 1752 1753 return ret; 1754 } 1755 1756 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1757 { 1758 int ret; 1759 struct psp_gfx_cmd_resp *cmd; 1760 1761 cmd = acquire_psp_cmd_buf(psp); 1762 1763 psp_copy_fw(psp, context->bin_desc.start_addr, 1764 context->bin_desc.size_bytes); 1765 1766 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1767 context->mem_context.shared_bo) 1768 context->mem_context.shared_mc_addr = 1769 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1770 1771 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1772 1773 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1774 psp->fence_buf_mc_addr); 1775 1776 context->resp_status = cmd->resp.status; 1777 1778 if (!ret) 1779 context->session_id = cmd->resp.session_id; 1780 1781 release_psp_cmd_buf(psp); 1782 1783 return ret; 1784 } 1785 1786 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1787 { 1788 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1789 } 1790 1791 int psp_xgmi_terminate(struct psp_context *psp) 1792 { 1793 int ret; 1794 struct amdgpu_device *adev = psp->adev; 1795 1796 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1797 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1798 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1799 adev->gmc.xgmi.connected_to_cpu)) 1800 return 0; 1801 1802 if (!psp->xgmi_context.context.initialized) 1803 return 0; 1804 1805 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1806 1807 psp->xgmi_context.context.initialized = false; 1808 1809 return ret; 1810 } 1811 1812 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1813 { 1814 struct ta_xgmi_shared_memory *xgmi_cmd; 1815 int ret; 1816 1817 if (!psp->ta_fw || 1818 !psp->xgmi_context.context.bin_desc.size_bytes || 1819 !psp->xgmi_context.context.bin_desc.start_addr) 1820 return -ENOENT; 1821 1822 if (!load_ta) 1823 goto invoke; 1824 1825 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1826 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1827 1828 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1829 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1830 if (ret) 1831 return ret; 1832 } 1833 1834 /* Load XGMI TA */ 1835 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1836 if (!ret) 1837 psp->xgmi_context.context.initialized = true; 1838 else 1839 return ret; 1840 1841 invoke: 1842 /* Initialize XGMI session */ 1843 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1844 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1845 xgmi_cmd->flag_extend_link_record = set_extended_data; 1846 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1847 1848 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1849 /* note down the capbility flag for XGMI TA */ 1850 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1851 1852 return ret; 1853 } 1854 1855 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1856 { 1857 struct ta_xgmi_shared_memory *xgmi_cmd; 1858 int ret; 1859 1860 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1861 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1862 1863 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1864 1865 /* Invoke xgmi ta to get hive id */ 1866 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1867 if (ret) 1868 return ret; 1869 1870 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1871 1872 return 0; 1873 } 1874 1875 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1876 { 1877 struct ta_xgmi_shared_memory *xgmi_cmd; 1878 int ret; 1879 1880 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1881 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1882 1883 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1884 1885 /* Invoke xgmi ta to get the node id */ 1886 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1887 if (ret) 1888 return ret; 1889 1890 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1891 1892 return 0; 1893 } 1894 1895 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1896 { 1897 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1898 IP_VERSION(13, 0, 2) && 1899 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1900 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1901 IP_VERSION(13, 0, 6); 1902 } 1903 1904 /* 1905 * Chips that support extended topology information require the driver to 1906 * reflect topology information in the opposite direction. This is 1907 * because the TA has already exceeded its link record limit and if the 1908 * TA holds bi-directional information, the driver would have to do 1909 * multiple fetches instead of just two. 1910 */ 1911 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1912 struct psp_xgmi_node_info node_info) 1913 { 1914 struct amdgpu_device *mirror_adev; 1915 struct amdgpu_hive_info *hive; 1916 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1917 uint64_t dst_node_id = node_info.node_id; 1918 uint8_t dst_num_hops = node_info.num_hops; 1919 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1920 uint8_t dst_num_links = node_info.num_links; 1921 1922 hive = amdgpu_get_xgmi_hive(psp->adev); 1923 if (WARN_ON(!hive)) 1924 return; 1925 1926 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1927 struct psp_xgmi_topology_info *mirror_top_info; 1928 int j; 1929 1930 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1931 continue; 1932 1933 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1934 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1935 if (mirror_top_info->nodes[j].node_id != src_node_id) 1936 continue; 1937 1938 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1939 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1940 /* prevent 0 num_links value re-reflection since reflection 1941 * criteria is based on num_hops (direct or indirect). 1942 */ 1943 if (dst_num_links) { 1944 mirror_top_info->nodes[j].num_links = dst_num_links; 1945 /* swap src and dst due to frame of reference */ 1946 for (int k = 0; k < dst_num_links; k++) { 1947 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1948 node_info.port_num[k].dst_xgmi_port_num; 1949 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1950 node_info.port_num[k].src_xgmi_port_num; 1951 } 1952 } 1953 1954 break; 1955 } 1956 1957 break; 1958 } 1959 1960 amdgpu_put_xgmi_hive(hive); 1961 } 1962 1963 int psp_xgmi_get_topology_info(struct psp_context *psp, 1964 int number_devices, 1965 struct psp_xgmi_topology_info *topology, 1966 bool get_extended_data) 1967 { 1968 struct ta_xgmi_shared_memory *xgmi_cmd; 1969 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1970 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1971 int i; 1972 int ret; 1973 1974 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1975 return -EINVAL; 1976 1977 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1978 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1979 xgmi_cmd->flag_extend_link_record = get_extended_data; 1980 1981 /* Fill in the shared memory with topology information as input */ 1982 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1983 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1984 topology_info_input->num_nodes = number_devices; 1985 1986 for (i = 0; i < topology_info_input->num_nodes; i++) { 1987 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1988 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1989 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1990 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1991 } 1992 1993 /* Invoke xgmi ta to get the topology information */ 1994 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1995 if (ret) 1996 return ret; 1997 1998 /* Read the output topology information from the shared memory */ 1999 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2000 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2001 for (i = 0; i < topology->num_nodes; i++) { 2002 /* extended data will either be 0 or equal to non-extended data */ 2003 if (topology_info_output->nodes[i].num_hops) 2004 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2005 2006 /* non-extended data gets everything here so no need to update */ 2007 if (!get_extended_data) { 2008 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2009 topology->nodes[i].is_sharing_enabled = 2010 topology_info_output->nodes[i].is_sharing_enabled; 2011 topology->nodes[i].sdma_engine = 2012 topology_info_output->nodes[i].sdma_engine; 2013 } 2014 2015 } 2016 2017 /* Invoke xgmi ta again to get the link information */ 2018 if (psp_xgmi_peer_link_info_supported(psp)) { 2019 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2020 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2021 bool requires_reflection = 2022 (psp->xgmi_context.supports_extended_data && 2023 get_extended_data) || 2024 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2025 IP_VERSION(13, 0, 6) || 2026 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2027 IP_VERSION(13, 0, 14) || 2028 amdgpu_sriov_vf(psp->adev); 2029 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 2030 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 2031 2032 /* popluate the shared output buffer rather than the cmd input buffer 2033 * with node_ids as the input for GET_PEER_LINKS command execution. 2034 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2035 * The same requirement for GET_EXTEND_PEER_LINKS command. 2036 */ 2037 if (ta_port_num_support) { 2038 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2039 2040 for (i = 0; i < topology->num_nodes; i++) 2041 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2042 2043 link_extend_info_output->num_nodes = topology->num_nodes; 2044 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2045 } else { 2046 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2047 2048 for (i = 0; i < topology->num_nodes; i++) 2049 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2050 2051 link_info_output->num_nodes = topology->num_nodes; 2052 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2053 } 2054 2055 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2056 if (ret) 2057 return ret; 2058 2059 for (i = 0; i < topology->num_nodes; i++) { 2060 uint8_t node_num_links = ta_port_num_support ? 2061 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2062 /* accumulate num_links on extended data */ 2063 if (get_extended_data) { 2064 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2065 } else { 2066 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2067 topology->nodes[i].num_links : node_num_links; 2068 } 2069 /* popluate the connected port num info if supported and available */ 2070 if (ta_port_num_support && topology->nodes[i].num_links) { 2071 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2072 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2073 } 2074 2075 /* reflect the topology information for bi-directionality */ 2076 if (requires_reflection && topology->nodes[i].num_hops) 2077 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2078 } 2079 } 2080 2081 return 0; 2082 } 2083 2084 int psp_xgmi_set_topology_info(struct psp_context *psp, 2085 int number_devices, 2086 struct psp_xgmi_topology_info *topology) 2087 { 2088 struct ta_xgmi_shared_memory *xgmi_cmd; 2089 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2090 int i; 2091 2092 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2093 return -EINVAL; 2094 2095 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2096 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2097 2098 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2099 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2100 topology_info_input->num_nodes = number_devices; 2101 2102 for (i = 0; i < topology_info_input->num_nodes; i++) { 2103 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2104 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2105 topology_info_input->nodes[i].is_sharing_enabled = 1; 2106 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2107 } 2108 2109 /* Invoke xgmi ta to set topology information */ 2110 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2111 } 2112 2113 // ras begin 2114 static void psp_ras_ta_check_status(struct psp_context *psp) 2115 { 2116 struct ta_ras_shared_memory *ras_cmd = 2117 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2118 2119 switch (ras_cmd->ras_status) { 2120 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2121 dev_warn(psp->adev->dev, 2122 "RAS WARNING: cmd failed due to unsupported ip\n"); 2123 break; 2124 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2125 dev_warn(psp->adev->dev, 2126 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2127 break; 2128 case TA_RAS_STATUS__SUCCESS: 2129 break; 2130 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2131 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2132 dev_warn(psp->adev->dev, 2133 "RAS WARNING: Inject error to critical region is not allowed\n"); 2134 break; 2135 default: 2136 dev_warn(psp->adev->dev, 2137 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2138 break; 2139 } 2140 } 2141 2142 static int psp_ras_send_cmd(struct psp_context *psp, 2143 enum ras_command cmd_id, void *in, void *out) 2144 { 2145 struct ta_ras_shared_memory *ras_cmd; 2146 uint32_t cmd = cmd_id; 2147 int ret = 0; 2148 2149 if (!in) 2150 return -EINVAL; 2151 2152 mutex_lock(&psp->ras_context.mutex); 2153 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2154 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2155 2156 switch (cmd) { 2157 case TA_RAS_COMMAND__ENABLE_FEATURES: 2158 case TA_RAS_COMMAND__DISABLE_FEATURES: 2159 memcpy(&ras_cmd->ras_in_message, 2160 in, sizeof(ras_cmd->ras_in_message)); 2161 break; 2162 case TA_RAS_COMMAND__TRIGGER_ERROR: 2163 memcpy(&ras_cmd->ras_in_message.trigger_error, 2164 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2165 break; 2166 case TA_RAS_COMMAND__QUERY_ADDRESS: 2167 memcpy(&ras_cmd->ras_in_message.address, 2168 in, sizeof(ras_cmd->ras_in_message.address)); 2169 break; 2170 default: 2171 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2172 ret = -EINVAL; 2173 goto err_out; 2174 } 2175 2176 ras_cmd->cmd_id = cmd; 2177 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2178 2179 switch (cmd) { 2180 case TA_RAS_COMMAND__TRIGGER_ERROR: 2181 if (!ret && out) 2182 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2183 break; 2184 case TA_RAS_COMMAND__QUERY_ADDRESS: 2185 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2186 ret = -EINVAL; 2187 else if (out) 2188 memcpy(out, 2189 &ras_cmd->ras_out_message.address, 2190 sizeof(ras_cmd->ras_out_message.address)); 2191 break; 2192 default: 2193 break; 2194 } 2195 2196 err_out: 2197 mutex_unlock(&psp->ras_context.mutex); 2198 2199 return ret; 2200 } 2201 2202 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2203 { 2204 struct ta_ras_shared_memory *ras_cmd; 2205 int ret; 2206 2207 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2208 2209 /* 2210 * TODO: bypass the loading in sriov for now 2211 */ 2212 if (amdgpu_sriov_vf(psp->adev)) 2213 return 0; 2214 2215 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2216 2217 if (amdgpu_ras_intr_triggered()) 2218 return ret; 2219 2220 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2221 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2222 return -EINVAL; 2223 } 2224 2225 if (!ret) { 2226 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2227 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2228 2229 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2230 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2231 dev_warn(psp->adev->dev, 2232 "RAS internal register access blocked\n"); 2233 2234 psp_ras_ta_check_status(psp); 2235 } 2236 2237 return ret; 2238 } 2239 2240 int psp_ras_enable_features(struct psp_context *psp, 2241 union ta_ras_cmd_input *info, bool enable) 2242 { 2243 enum ras_command cmd_id; 2244 int ret; 2245 2246 if (!psp->ras_context.context.initialized || !info) 2247 return -EINVAL; 2248 2249 cmd_id = enable ? 2250 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2251 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2252 if (ret) 2253 return -EINVAL; 2254 2255 return 0; 2256 } 2257 2258 int psp_ras_terminate(struct psp_context *psp) 2259 { 2260 int ret; 2261 2262 /* 2263 * TODO: bypass the terminate in sriov for now 2264 */ 2265 if (amdgpu_sriov_vf(psp->adev)) 2266 return 0; 2267 2268 if (!psp->ras_context.context.initialized) 2269 return 0; 2270 2271 ret = psp_ta_unload(psp, &psp->ras_context.context); 2272 2273 psp->ras_context.context.initialized = false; 2274 2275 mutex_destroy(&psp->ras_context.mutex); 2276 2277 return ret; 2278 } 2279 2280 int psp_ras_initialize(struct psp_context *psp) 2281 { 2282 int ret; 2283 uint32_t boot_cfg = 0xFF; 2284 struct amdgpu_device *adev = psp->adev; 2285 struct ta_ras_shared_memory *ras_cmd; 2286 2287 /* 2288 * TODO: bypass the initialize in sriov for now 2289 */ 2290 if (amdgpu_sriov_vf(adev)) 2291 return 0; 2292 2293 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2294 !adev->psp.ras_context.context.bin_desc.start_addr) { 2295 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2296 return 0; 2297 } 2298 2299 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2300 /* query GECC enablement status from boot config 2301 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2302 */ 2303 ret = psp_boot_config_get(adev, &boot_cfg); 2304 if (ret) 2305 dev_warn(adev->dev, "PSP get boot config failed\n"); 2306 2307 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2308 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2309 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2310 dev_warn(adev->dev, 2311 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2312 } else { 2313 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2314 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2315 if (boot_cfg == 1) { 2316 dev_info(adev->dev, "GECC is enabled\n"); 2317 } else { 2318 /* enable GECC in next boot cycle if it is disabled 2319 * in boot config, or force enable GECC if failed to 2320 * get boot configuration 2321 */ 2322 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2323 if (ret) 2324 dev_warn(adev->dev, "PSP set boot config failed\n"); 2325 else 2326 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2327 } 2328 } else { 2329 if (!boot_cfg) { 2330 if (!adev->ras_default_ecc_enabled && 2331 amdgpu_ras_enable != 1 && 2332 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2333 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2334 else 2335 dev_info(adev->dev, "GECC is disabled\n"); 2336 } else { 2337 /* disable GECC in next boot cycle if ras is 2338 * disabled by module parameter amdgpu_ras_enable 2339 * and/or amdgpu_ras_mask, or boot_config_get call 2340 * is failed 2341 */ 2342 ret = psp_boot_config_set(adev, 0); 2343 if (ret) 2344 dev_warn(adev->dev, "PSP set boot config failed\n"); 2345 else 2346 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2347 } 2348 } 2349 } 2350 } 2351 2352 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2353 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2354 2355 if (!psp->ras_context.context.mem_context.shared_buf) { 2356 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2357 if (ret) 2358 return ret; 2359 } 2360 2361 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2362 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2363 2364 if (amdgpu_ras_is_poison_mode_supported(adev)) 2365 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2366 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2367 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2368 ras_cmd->ras_in_message.init_flags.xcc_mask = 2369 adev->gfx.xcc_mask; 2370 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2371 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2372 ras_cmd->ras_in_message.init_flags.nps_mode = 2373 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2374 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2375 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2376 2377 ret = psp_ta_load(psp, &psp->ras_context.context); 2378 2379 if (!ret && !ras_cmd->ras_status) { 2380 psp->ras_context.context.initialized = true; 2381 mutex_init(&psp->ras_context.mutex); 2382 } else { 2383 if (ras_cmd->ras_status) 2384 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2385 2386 /* fail to load RAS TA */ 2387 psp->ras_context.context.initialized = false; 2388 } 2389 2390 return ret; 2391 } 2392 2393 int psp_ras_trigger_error(struct psp_context *psp, 2394 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2395 { 2396 struct amdgpu_device *adev = psp->adev; 2397 int ret; 2398 uint32_t dev_mask; 2399 uint32_t ras_status = 0; 2400 2401 if (!psp->ras_context.context.initialized || !info) 2402 return -EINVAL; 2403 2404 switch (info->block_id) { 2405 case TA_RAS_BLOCK__GFX: 2406 dev_mask = GET_MASK(GC, instance_mask); 2407 break; 2408 case TA_RAS_BLOCK__SDMA: 2409 dev_mask = GET_MASK(SDMA0, instance_mask); 2410 break; 2411 case TA_RAS_BLOCK__VCN: 2412 case TA_RAS_BLOCK__JPEG: 2413 dev_mask = GET_MASK(VCN, instance_mask); 2414 break; 2415 default: 2416 dev_mask = instance_mask; 2417 break; 2418 } 2419 2420 /* reuse sub_block_index for backward compatibility */ 2421 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2422 dev_mask &= AMDGPU_RAS_INST_MASK; 2423 info->sub_block_index |= dev_mask; 2424 2425 ret = psp_ras_send_cmd(psp, 2426 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2427 if (ret) 2428 return -EINVAL; 2429 2430 /* If err_event_athub occurs error inject was successful, however 2431 * return status from TA is no long reliable 2432 */ 2433 if (amdgpu_ras_intr_triggered()) 2434 return 0; 2435 2436 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2437 return -EACCES; 2438 else if (ras_status) 2439 return -EINVAL; 2440 2441 return 0; 2442 } 2443 2444 int psp_ras_query_address(struct psp_context *psp, 2445 struct ta_ras_query_address_input *addr_in, 2446 struct ta_ras_query_address_output *addr_out) 2447 { 2448 int ret; 2449 2450 if (!psp->ras_context.context.initialized || 2451 !addr_in || !addr_out) 2452 return -EINVAL; 2453 2454 ret = psp_ras_send_cmd(psp, 2455 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2456 2457 return ret; 2458 } 2459 // ras end 2460 2461 // HDCP start 2462 static int psp_hdcp_initialize(struct psp_context *psp) 2463 { 2464 int ret; 2465 2466 /* 2467 * TODO: bypass the initialize in sriov for now 2468 */ 2469 if (amdgpu_sriov_vf(psp->adev)) 2470 return 0; 2471 2472 /* bypass hdcp initialization if dmu is harvested */ 2473 if (!amdgpu_device_has_display_hardware(psp->adev)) 2474 return 0; 2475 2476 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2477 !psp->hdcp_context.context.bin_desc.start_addr) { 2478 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2479 return 0; 2480 } 2481 2482 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2483 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2484 2485 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2486 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2487 if (ret) 2488 return ret; 2489 } 2490 2491 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2492 if (!ret) { 2493 psp->hdcp_context.context.initialized = true; 2494 mutex_init(&psp->hdcp_context.mutex); 2495 } 2496 2497 return ret; 2498 } 2499 2500 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2501 { 2502 /* 2503 * TODO: bypass the loading in sriov for now 2504 */ 2505 if (amdgpu_sriov_vf(psp->adev)) 2506 return 0; 2507 2508 if (!psp->hdcp_context.context.initialized) 2509 return 0; 2510 2511 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2512 } 2513 2514 static int psp_hdcp_terminate(struct psp_context *psp) 2515 { 2516 int ret; 2517 2518 /* 2519 * TODO: bypass the terminate in sriov for now 2520 */ 2521 if (amdgpu_sriov_vf(psp->adev)) 2522 return 0; 2523 2524 if (!psp->hdcp_context.context.initialized) 2525 return 0; 2526 2527 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2528 2529 psp->hdcp_context.context.initialized = false; 2530 2531 return ret; 2532 } 2533 // HDCP end 2534 2535 // DTM start 2536 static int psp_dtm_initialize(struct psp_context *psp) 2537 { 2538 int ret; 2539 2540 /* 2541 * TODO: bypass the initialize in sriov for now 2542 */ 2543 if (amdgpu_sriov_vf(psp->adev)) 2544 return 0; 2545 2546 /* bypass dtm initialization if dmu is harvested */ 2547 if (!amdgpu_device_has_display_hardware(psp->adev)) 2548 return 0; 2549 2550 if (!psp->dtm_context.context.bin_desc.size_bytes || 2551 !psp->dtm_context.context.bin_desc.start_addr) { 2552 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2553 return 0; 2554 } 2555 2556 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2557 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2558 2559 if (!psp->dtm_context.context.mem_context.shared_buf) { 2560 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2561 if (ret) 2562 return ret; 2563 } 2564 2565 ret = psp_ta_load(psp, &psp->dtm_context.context); 2566 if (!ret) { 2567 psp->dtm_context.context.initialized = true; 2568 mutex_init(&psp->dtm_context.mutex); 2569 } 2570 2571 return ret; 2572 } 2573 2574 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2575 { 2576 /* 2577 * TODO: bypass the loading in sriov for now 2578 */ 2579 if (amdgpu_sriov_vf(psp->adev)) 2580 return 0; 2581 2582 if (!psp->dtm_context.context.initialized) 2583 return 0; 2584 2585 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2586 } 2587 2588 static int psp_dtm_terminate(struct psp_context *psp) 2589 { 2590 int ret; 2591 2592 /* 2593 * TODO: bypass the terminate in sriov for now 2594 */ 2595 if (amdgpu_sriov_vf(psp->adev)) 2596 return 0; 2597 2598 if (!psp->dtm_context.context.initialized) 2599 return 0; 2600 2601 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2602 2603 psp->dtm_context.context.initialized = false; 2604 2605 return ret; 2606 } 2607 // DTM end 2608 2609 // RAP start 2610 static int psp_rap_initialize(struct psp_context *psp) 2611 { 2612 int ret; 2613 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2614 2615 /* 2616 * TODO: bypass the initialize in sriov for now 2617 */ 2618 if (amdgpu_sriov_vf(psp->adev)) 2619 return 0; 2620 2621 if (!psp->rap_context.context.bin_desc.size_bytes || 2622 !psp->rap_context.context.bin_desc.start_addr) { 2623 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2624 return 0; 2625 } 2626 2627 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2628 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2629 2630 if (!psp->rap_context.context.mem_context.shared_buf) { 2631 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2632 if (ret) 2633 return ret; 2634 } 2635 2636 ret = psp_ta_load(psp, &psp->rap_context.context); 2637 if (!ret) { 2638 psp->rap_context.context.initialized = true; 2639 mutex_init(&psp->rap_context.mutex); 2640 } else 2641 return ret; 2642 2643 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2644 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2645 psp_rap_terminate(psp); 2646 /* free rap shared memory */ 2647 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2648 2649 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2650 ret, status); 2651 2652 return ret; 2653 } 2654 2655 return 0; 2656 } 2657 2658 static int psp_rap_terminate(struct psp_context *psp) 2659 { 2660 int ret; 2661 2662 if (!psp->rap_context.context.initialized) 2663 return 0; 2664 2665 ret = psp_ta_unload(psp, &psp->rap_context.context); 2666 2667 psp->rap_context.context.initialized = false; 2668 2669 return ret; 2670 } 2671 2672 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2673 { 2674 struct ta_rap_shared_memory *rap_cmd; 2675 int ret = 0; 2676 2677 if (!psp->rap_context.context.initialized) 2678 return 0; 2679 2680 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2681 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2682 return -EINVAL; 2683 2684 mutex_lock(&psp->rap_context.mutex); 2685 2686 rap_cmd = (struct ta_rap_shared_memory *) 2687 psp->rap_context.context.mem_context.shared_buf; 2688 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2689 2690 rap_cmd->cmd_id = ta_cmd_id; 2691 rap_cmd->validation_method_id = METHOD_A; 2692 2693 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2694 if (ret) 2695 goto out_unlock; 2696 2697 if (status) 2698 *status = rap_cmd->rap_status; 2699 2700 out_unlock: 2701 mutex_unlock(&psp->rap_context.mutex); 2702 2703 return ret; 2704 } 2705 // RAP end 2706 2707 /* securedisplay start */ 2708 static int psp_securedisplay_initialize(struct psp_context *psp) 2709 { 2710 int ret; 2711 struct ta_securedisplay_cmd *securedisplay_cmd; 2712 2713 /* 2714 * TODO: bypass the initialize in sriov for now 2715 */ 2716 if (amdgpu_sriov_vf(psp->adev)) 2717 return 0; 2718 2719 /* bypass securedisplay initialization if dmu is harvested */ 2720 if (!amdgpu_device_has_display_hardware(psp->adev)) 2721 return 0; 2722 2723 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2724 !psp->securedisplay_context.context.bin_desc.start_addr) { 2725 dev_info(psp->adev->dev, 2726 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2727 return 0; 2728 } 2729 2730 psp->securedisplay_context.context.mem_context.shared_mem_size = 2731 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2732 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2733 2734 if (!psp->securedisplay_context.context.initialized) { 2735 ret = psp_ta_init_shared_buf(psp, 2736 &psp->securedisplay_context.context.mem_context); 2737 if (ret) 2738 return ret; 2739 } 2740 2741 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2742 if (!ret && !psp->securedisplay_context.context.resp_status) { 2743 psp->securedisplay_context.context.initialized = true; 2744 mutex_init(&psp->securedisplay_context.mutex); 2745 } else { 2746 /* don't try again */ 2747 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2748 return ret; 2749 } 2750 2751 mutex_lock(&psp->securedisplay_context.mutex); 2752 2753 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2754 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2755 2756 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2757 2758 mutex_unlock(&psp->securedisplay_context.mutex); 2759 2760 if (ret) { 2761 psp_securedisplay_terminate(psp); 2762 /* free securedisplay shared memory */ 2763 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2764 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2765 return -EINVAL; 2766 } 2767 2768 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2769 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2770 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2771 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2772 /* don't try again */ 2773 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int psp_securedisplay_terminate(struct psp_context *psp) 2780 { 2781 int ret; 2782 2783 /* 2784 * TODO:bypass the terminate in sriov for now 2785 */ 2786 if (amdgpu_sriov_vf(psp->adev)) 2787 return 0; 2788 2789 if (!psp->securedisplay_context.context.initialized) 2790 return 0; 2791 2792 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2793 2794 psp->securedisplay_context.context.initialized = false; 2795 2796 return ret; 2797 } 2798 2799 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2800 { 2801 int ret; 2802 2803 if (!psp->securedisplay_context.context.initialized) 2804 return -EINVAL; 2805 2806 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2807 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2808 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2809 return -EINVAL; 2810 2811 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2812 2813 return ret; 2814 } 2815 /* SECUREDISPLAY end */ 2816 2817 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2818 { 2819 struct psp_context *psp = &adev->psp; 2820 int ret = 0; 2821 2822 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2823 ret = psp->funcs->wait_for_bootloader(psp); 2824 2825 return ret; 2826 } 2827 2828 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2829 { 2830 if (psp->funcs && 2831 psp->funcs->get_ras_capability) { 2832 return psp->funcs->get_ras_capability(psp); 2833 } else { 2834 return false; 2835 } 2836 } 2837 2838 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2839 { 2840 struct psp_context *psp = &adev->psp; 2841 2842 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2843 return false; 2844 2845 if (psp->funcs && psp->funcs->is_reload_needed) 2846 return psp->funcs->is_reload_needed(psp); 2847 2848 return false; 2849 } 2850 2851 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2852 { 2853 struct psp_context *psp = &adev->psp; 2854 2855 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2856 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2857 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2858 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2859 } 2860 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2861 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2862 } 2863 2864 static int psp_hw_start(struct psp_context *psp) 2865 { 2866 struct amdgpu_device *adev = psp->adev; 2867 int ret; 2868 2869 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2870 psp_update_gpu_addresses(adev); 2871 2872 if (!amdgpu_sriov_vf(adev)) { 2873 if ((is_psp_fw_valid(psp->kdb)) && 2874 (psp->funcs->bootloader_load_kdb != NULL)) { 2875 ret = psp_bootloader_load_kdb(psp); 2876 if (ret) { 2877 dev_err(adev->dev, "PSP load kdb failed!\n"); 2878 return ret; 2879 } 2880 } 2881 2882 if ((is_psp_fw_valid(psp->spl)) && 2883 (psp->funcs->bootloader_load_spl != NULL)) { 2884 ret = psp_bootloader_load_spl(psp); 2885 if (ret) { 2886 dev_err(adev->dev, "PSP load spl failed!\n"); 2887 return ret; 2888 } 2889 } 2890 2891 if ((is_psp_fw_valid(psp->sys)) && 2892 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2893 ret = psp_bootloader_load_sysdrv(psp); 2894 if (ret) { 2895 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2896 return ret; 2897 } 2898 } 2899 2900 if ((is_psp_fw_valid(psp->soc_drv)) && 2901 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2902 ret = psp_bootloader_load_soc_drv(psp); 2903 if (ret) { 2904 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2905 return ret; 2906 } 2907 } 2908 2909 if ((is_psp_fw_valid(psp->intf_drv)) && 2910 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2911 ret = psp_bootloader_load_intf_drv(psp); 2912 if (ret) { 2913 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2914 return ret; 2915 } 2916 } 2917 2918 if ((is_psp_fw_valid(psp->dbg_drv)) && 2919 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2920 ret = psp_bootloader_load_dbg_drv(psp); 2921 if (ret) { 2922 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2923 return ret; 2924 } 2925 } 2926 2927 if ((is_psp_fw_valid(psp->ras_drv)) && 2928 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2929 ret = psp_bootloader_load_ras_drv(psp); 2930 if (ret) { 2931 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2932 return ret; 2933 } 2934 } 2935 2936 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2937 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2938 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2939 if (ret) { 2940 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2941 return ret; 2942 } 2943 } 2944 2945 if ((is_psp_fw_valid(psp->spdm_drv)) && 2946 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2947 ret = psp_bootloader_load_spdm_drv(psp); 2948 if (ret) { 2949 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2950 return ret; 2951 } 2952 } 2953 2954 if ((is_psp_fw_valid(psp->sos)) && 2955 (psp->funcs->bootloader_load_sos != NULL)) { 2956 ret = psp_bootloader_load_sos(psp); 2957 if (ret) { 2958 dev_err(adev->dev, "PSP load sos failed!\n"); 2959 return ret; 2960 } 2961 } 2962 } 2963 2964 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2965 if (ret) { 2966 dev_err(adev->dev, "PSP create ring failed!\n"); 2967 return ret; 2968 } 2969 2970 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2971 ret = psp_update_fw_reservation(psp); 2972 if (ret) { 2973 dev_err(adev->dev, "update fw reservation failed!\n"); 2974 return ret; 2975 } 2976 } 2977 2978 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2979 goto skip_pin_bo; 2980 2981 if (!psp->boot_time_tmr || psp->autoload_supported) { 2982 ret = psp_tmr_init(psp); 2983 if (ret) { 2984 dev_err(adev->dev, "PSP tmr init failed!\n"); 2985 return ret; 2986 } 2987 } 2988 2989 skip_pin_bo: 2990 /* 2991 * For ASICs with DF Cstate management centralized 2992 * to PMFW, TMR setup should be performed after PMFW 2993 * loaded and before other non-psp firmware loaded. 2994 */ 2995 if (psp->pmfw_centralized_cstate_management) { 2996 ret = psp_load_smu_fw(psp); 2997 if (ret) 2998 return ret; 2999 } 3000 3001 ret = psp_tmr_load(psp); 3002 if (ret) { 3003 dev_err(adev->dev, "PSP load tmr failed!\n"); 3004 return ret; 3005 } 3006 3007 return 0; 3008 } 3009 3010 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3011 enum psp_gfx_fw_type *type) 3012 { 3013 switch (ucode->ucode_id) { 3014 case AMDGPU_UCODE_ID_CAP: 3015 *type = GFX_FW_TYPE_CAP; 3016 break; 3017 case AMDGPU_UCODE_ID_SDMA0: 3018 *type = GFX_FW_TYPE_SDMA0; 3019 break; 3020 case AMDGPU_UCODE_ID_SDMA1: 3021 *type = GFX_FW_TYPE_SDMA1; 3022 break; 3023 case AMDGPU_UCODE_ID_SDMA2: 3024 *type = GFX_FW_TYPE_SDMA2; 3025 break; 3026 case AMDGPU_UCODE_ID_SDMA3: 3027 *type = GFX_FW_TYPE_SDMA3; 3028 break; 3029 case AMDGPU_UCODE_ID_SDMA4: 3030 *type = GFX_FW_TYPE_SDMA4; 3031 break; 3032 case AMDGPU_UCODE_ID_SDMA5: 3033 *type = GFX_FW_TYPE_SDMA5; 3034 break; 3035 case AMDGPU_UCODE_ID_SDMA6: 3036 *type = GFX_FW_TYPE_SDMA6; 3037 break; 3038 case AMDGPU_UCODE_ID_SDMA7: 3039 *type = GFX_FW_TYPE_SDMA7; 3040 break; 3041 case AMDGPU_UCODE_ID_CP_MES: 3042 *type = GFX_FW_TYPE_CP_MES; 3043 break; 3044 case AMDGPU_UCODE_ID_CP_MES_DATA: 3045 *type = GFX_FW_TYPE_MES_STACK; 3046 break; 3047 case AMDGPU_UCODE_ID_CP_MES1: 3048 *type = GFX_FW_TYPE_CP_MES_KIQ; 3049 break; 3050 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3051 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3052 break; 3053 case AMDGPU_UCODE_ID_CP_CE: 3054 *type = GFX_FW_TYPE_CP_CE; 3055 break; 3056 case AMDGPU_UCODE_ID_CP_PFP: 3057 *type = GFX_FW_TYPE_CP_PFP; 3058 break; 3059 case AMDGPU_UCODE_ID_CP_ME: 3060 *type = GFX_FW_TYPE_CP_ME; 3061 break; 3062 case AMDGPU_UCODE_ID_CP_MEC1: 3063 *type = GFX_FW_TYPE_CP_MEC; 3064 break; 3065 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3066 *type = GFX_FW_TYPE_CP_MEC_ME1; 3067 break; 3068 case AMDGPU_UCODE_ID_CP_MEC2: 3069 *type = GFX_FW_TYPE_CP_MEC; 3070 break; 3071 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3072 *type = GFX_FW_TYPE_CP_MEC_ME2; 3073 break; 3074 case AMDGPU_UCODE_ID_RLC_P: 3075 *type = GFX_FW_TYPE_RLC_P; 3076 break; 3077 case AMDGPU_UCODE_ID_RLC_V: 3078 *type = GFX_FW_TYPE_RLC_V; 3079 break; 3080 case AMDGPU_UCODE_ID_RLC_G: 3081 *type = GFX_FW_TYPE_RLC_G; 3082 break; 3083 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3084 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3085 break; 3086 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3087 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3088 break; 3089 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3090 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3091 break; 3092 case AMDGPU_UCODE_ID_RLC_IRAM: 3093 *type = GFX_FW_TYPE_RLC_IRAM; 3094 break; 3095 case AMDGPU_UCODE_ID_RLC_DRAM: 3096 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3097 break; 3098 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3099 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3100 break; 3101 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3102 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3103 break; 3104 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3105 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3106 break; 3107 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3108 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3109 break; 3110 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3111 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3112 break; 3113 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3114 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3115 break; 3116 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3117 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3118 break; 3119 case AMDGPU_UCODE_ID_SMC: 3120 *type = GFX_FW_TYPE_SMU; 3121 break; 3122 case AMDGPU_UCODE_ID_PPTABLE: 3123 *type = GFX_FW_TYPE_PPTABLE; 3124 break; 3125 case AMDGPU_UCODE_ID_UVD: 3126 *type = GFX_FW_TYPE_UVD; 3127 break; 3128 case AMDGPU_UCODE_ID_UVD1: 3129 *type = GFX_FW_TYPE_UVD1; 3130 break; 3131 case AMDGPU_UCODE_ID_VCE: 3132 *type = GFX_FW_TYPE_VCE; 3133 break; 3134 case AMDGPU_UCODE_ID_VCN: 3135 *type = GFX_FW_TYPE_VCN; 3136 break; 3137 case AMDGPU_UCODE_ID_VCN1: 3138 *type = GFX_FW_TYPE_VCN1; 3139 break; 3140 case AMDGPU_UCODE_ID_DMCU_ERAM: 3141 *type = GFX_FW_TYPE_DMCU_ERAM; 3142 break; 3143 case AMDGPU_UCODE_ID_DMCU_INTV: 3144 *type = GFX_FW_TYPE_DMCU_ISR; 3145 break; 3146 case AMDGPU_UCODE_ID_VCN0_RAM: 3147 *type = GFX_FW_TYPE_VCN0_RAM; 3148 break; 3149 case AMDGPU_UCODE_ID_VCN1_RAM: 3150 *type = GFX_FW_TYPE_VCN1_RAM; 3151 break; 3152 case AMDGPU_UCODE_ID_DMCUB: 3153 *type = GFX_FW_TYPE_DMUB; 3154 break; 3155 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3156 case AMDGPU_UCODE_ID_SDMA_RS64: 3157 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3158 break; 3159 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3160 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3161 break; 3162 case AMDGPU_UCODE_ID_IMU_I: 3163 *type = GFX_FW_TYPE_IMU_I; 3164 break; 3165 case AMDGPU_UCODE_ID_IMU_D: 3166 *type = GFX_FW_TYPE_IMU_D; 3167 break; 3168 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3169 *type = GFX_FW_TYPE_RS64_PFP; 3170 break; 3171 case AMDGPU_UCODE_ID_CP_RS64_ME: 3172 *type = GFX_FW_TYPE_RS64_ME; 3173 break; 3174 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3175 *type = GFX_FW_TYPE_RS64_MEC; 3176 break; 3177 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3178 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3179 break; 3180 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3181 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3182 break; 3183 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3184 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3185 break; 3186 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3187 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3188 break; 3189 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3190 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3191 break; 3192 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3193 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3194 break; 3195 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3196 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3197 break; 3198 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3199 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3200 break; 3201 case AMDGPU_UCODE_ID_VPE_CTX: 3202 *type = GFX_FW_TYPE_VPEC_FW1; 3203 break; 3204 case AMDGPU_UCODE_ID_VPE_CTL: 3205 *type = GFX_FW_TYPE_VPEC_FW2; 3206 break; 3207 case AMDGPU_UCODE_ID_VPE: 3208 *type = GFX_FW_TYPE_VPE; 3209 break; 3210 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3211 *type = GFX_FW_TYPE_UMSCH_UCODE; 3212 break; 3213 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3214 *type = GFX_FW_TYPE_UMSCH_DATA; 3215 break; 3216 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3217 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3218 break; 3219 case AMDGPU_UCODE_ID_P2S_TABLE: 3220 *type = GFX_FW_TYPE_P2S_TABLE; 3221 break; 3222 case AMDGPU_UCODE_ID_JPEG_RAM: 3223 *type = GFX_FW_TYPE_JPEG_RAM; 3224 break; 3225 case AMDGPU_UCODE_ID_ISP: 3226 *type = GFX_FW_TYPE_ISP; 3227 break; 3228 case AMDGPU_UCODE_ID_MAXIMUM: 3229 default: 3230 return -EINVAL; 3231 } 3232 3233 return 0; 3234 } 3235 3236 static void psp_print_fw_hdr(struct psp_context *psp, 3237 struct amdgpu_firmware_info *ucode) 3238 { 3239 struct amdgpu_device *adev = psp->adev; 3240 struct common_firmware_header *hdr; 3241 3242 switch (ucode->ucode_id) { 3243 case AMDGPU_UCODE_ID_SDMA0: 3244 case AMDGPU_UCODE_ID_SDMA1: 3245 case AMDGPU_UCODE_ID_SDMA2: 3246 case AMDGPU_UCODE_ID_SDMA3: 3247 case AMDGPU_UCODE_ID_SDMA4: 3248 case AMDGPU_UCODE_ID_SDMA5: 3249 case AMDGPU_UCODE_ID_SDMA6: 3250 case AMDGPU_UCODE_ID_SDMA7: 3251 hdr = (struct common_firmware_header *) 3252 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3253 amdgpu_ucode_print_sdma_hdr(hdr); 3254 break; 3255 case AMDGPU_UCODE_ID_CP_CE: 3256 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3257 amdgpu_ucode_print_gfx_hdr(hdr); 3258 break; 3259 case AMDGPU_UCODE_ID_CP_PFP: 3260 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3261 amdgpu_ucode_print_gfx_hdr(hdr); 3262 break; 3263 case AMDGPU_UCODE_ID_CP_ME: 3264 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3265 amdgpu_ucode_print_gfx_hdr(hdr); 3266 break; 3267 case AMDGPU_UCODE_ID_CP_MEC1: 3268 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3269 amdgpu_ucode_print_gfx_hdr(hdr); 3270 break; 3271 case AMDGPU_UCODE_ID_RLC_G: 3272 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3273 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3274 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3275 amdgpu_ucode_print_rlc_hdr(hdr); 3276 break; 3277 case AMDGPU_UCODE_ID_SMC: 3278 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3279 amdgpu_ucode_print_smc_hdr(hdr); 3280 break; 3281 default: 3282 break; 3283 } 3284 } 3285 3286 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3287 struct amdgpu_firmware_info *ucode, 3288 struct psp_gfx_cmd_resp *cmd) 3289 { 3290 int ret; 3291 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3292 3293 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3294 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3295 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3296 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3297 3298 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3299 if (ret) 3300 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3301 return ret; 3302 } 3303 3304 int psp_execute_ip_fw_load(struct psp_context *psp, 3305 struct amdgpu_firmware_info *ucode) 3306 { 3307 int ret = 0; 3308 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3309 3310 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3311 if (!ret) { 3312 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3313 psp->fence_buf_mc_addr); 3314 } 3315 3316 release_psp_cmd_buf(psp); 3317 3318 return ret; 3319 } 3320 3321 static int psp_load_p2s_table(struct psp_context *psp) 3322 { 3323 int ret; 3324 struct amdgpu_device *adev = psp->adev; 3325 struct amdgpu_firmware_info *ucode = 3326 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3327 3328 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3329 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3330 return 0; 3331 3332 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3333 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3334 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3335 0x0036003C; 3336 if (psp->sos.fw_version < supp_vers) 3337 return 0; 3338 } 3339 3340 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3341 return 0; 3342 3343 ret = psp_execute_ip_fw_load(psp, ucode); 3344 3345 return ret; 3346 } 3347 3348 static int psp_load_smu_fw(struct psp_context *psp) 3349 { 3350 int ret; 3351 struct amdgpu_device *adev = psp->adev; 3352 struct amdgpu_firmware_info *ucode = 3353 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3354 struct amdgpu_ras *ras = psp->ras_context.ras; 3355 3356 /* 3357 * Skip SMU FW reloading in case of using BACO for runpm only, 3358 * as SMU is always alive. 3359 */ 3360 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3361 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3362 return 0; 3363 3364 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3365 return 0; 3366 3367 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3368 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3369 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3370 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3371 if (ret) 3372 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3373 } 3374 3375 ret = psp_execute_ip_fw_load(psp, ucode); 3376 3377 if (ret) 3378 dev_err(adev->dev, "PSP load smu failed!\n"); 3379 3380 return ret; 3381 } 3382 3383 static bool fw_load_skip_check(struct psp_context *psp, 3384 struct amdgpu_firmware_info *ucode) 3385 { 3386 if (!ucode->fw || !ucode->ucode_size) 3387 return true; 3388 3389 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3390 return true; 3391 3392 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3393 (psp_smu_reload_quirk(psp) || 3394 psp->autoload_supported || 3395 psp->pmfw_centralized_cstate_management)) 3396 return true; 3397 3398 if (amdgpu_sriov_vf(psp->adev) && 3399 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3400 return true; 3401 3402 if (psp->autoload_supported && 3403 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3404 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3405 /* skip mec JT when autoload is enabled */ 3406 return true; 3407 3408 return false; 3409 } 3410 3411 int psp_load_fw_list(struct psp_context *psp, 3412 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3413 { 3414 int ret = 0, i; 3415 struct amdgpu_firmware_info *ucode; 3416 3417 for (i = 0; i < ucode_count; ++i) { 3418 ucode = ucode_list[i]; 3419 psp_print_fw_hdr(psp, ucode); 3420 ret = psp_execute_ip_fw_load(psp, ucode); 3421 if (ret) 3422 return ret; 3423 } 3424 return ret; 3425 } 3426 3427 static int psp_load_non_psp_fw(struct psp_context *psp) 3428 { 3429 int i, ret; 3430 struct amdgpu_firmware_info *ucode; 3431 struct amdgpu_device *adev = psp->adev; 3432 3433 if (psp->autoload_supported && 3434 !psp->pmfw_centralized_cstate_management) { 3435 ret = psp_load_smu_fw(psp); 3436 if (ret) 3437 return ret; 3438 } 3439 3440 /* Load P2S table first if it's available */ 3441 psp_load_p2s_table(psp); 3442 3443 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3444 ucode = &adev->firmware.ucode[i]; 3445 3446 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3447 !fw_load_skip_check(psp, ucode)) { 3448 ret = psp_load_smu_fw(psp); 3449 if (ret) 3450 return ret; 3451 continue; 3452 } 3453 3454 if (fw_load_skip_check(psp, ucode)) 3455 continue; 3456 3457 if (psp->autoload_supported && 3458 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3459 IP_VERSION(11, 0, 7) || 3460 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3461 IP_VERSION(11, 0, 11) || 3462 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3463 IP_VERSION(11, 0, 12) || 3464 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3465 IP_VERSION(15, 0, 0) || 3466 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3467 IP_VERSION(15, 0, 8)) && 3468 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3469 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3470 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3471 /* PSP only receive one SDMA fw for sienna_cichlid, 3472 * as all four sdma fw are same 3473 */ 3474 continue; 3475 3476 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3477 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3478 IP_VERSION(15, 0, 8) && 3479 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3480 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3481 continue; 3482 3483 psp_print_fw_hdr(psp, ucode); 3484 3485 ret = psp_execute_ip_fw_load(psp, ucode); 3486 if (ret) 3487 return ret; 3488 3489 /* Start rlc autoload after psp received all the gfx firmware */ 3490 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3491 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3492 ret = psp_rlc_autoload_start(psp); 3493 if (ret) { 3494 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3495 return ret; 3496 } 3497 } 3498 } 3499 3500 return 0; 3501 } 3502 3503 static int psp_load_fw(struct amdgpu_device *adev) 3504 { 3505 int ret; 3506 struct psp_context *psp = &adev->psp; 3507 3508 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3509 /* should not destroy ring, only stop */ 3510 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3511 } else { 3512 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3513 3514 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3515 if (ret) { 3516 dev_err(adev->dev, "PSP ring init failed!\n"); 3517 goto failed; 3518 } 3519 } 3520 3521 ret = psp_hw_start(psp); 3522 if (ret) 3523 goto failed; 3524 3525 ret = psp_load_non_psp_fw(psp); 3526 if (ret) 3527 goto failed1; 3528 3529 ret = psp_asd_initialize(psp); 3530 if (ret) { 3531 dev_err(adev->dev, "PSP load asd failed!\n"); 3532 goto failed1; 3533 } 3534 3535 ret = psp_rl_load(adev); 3536 if (ret) { 3537 dev_err(adev->dev, "PSP load RL failed!\n"); 3538 goto failed1; 3539 } 3540 3541 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3542 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3543 ret = psp_xgmi_initialize(psp, false, true); 3544 /* Warning the XGMI seesion initialize failure 3545 * Instead of stop driver initialization 3546 */ 3547 if (ret) 3548 dev_err(psp->adev->dev, 3549 "XGMI: Failed to initialize XGMI session\n"); 3550 } 3551 } 3552 3553 if (psp->ta_fw) { 3554 ret = psp_ras_initialize(psp); 3555 if (ret) 3556 dev_err(psp->adev->dev, 3557 "RAS: Failed to initialize RAS\n"); 3558 3559 ret = psp_hdcp_initialize(psp); 3560 if (ret) 3561 dev_err(psp->adev->dev, 3562 "HDCP: Failed to initialize HDCP\n"); 3563 3564 ret = psp_dtm_initialize(psp); 3565 if (ret) 3566 dev_err(psp->adev->dev, 3567 "DTM: Failed to initialize DTM\n"); 3568 3569 ret = psp_rap_initialize(psp); 3570 if (ret) 3571 dev_err(psp->adev->dev, 3572 "RAP: Failed to initialize RAP\n"); 3573 3574 ret = psp_securedisplay_initialize(psp); 3575 if (ret) 3576 dev_err(psp->adev->dev, 3577 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3578 } 3579 3580 return 0; 3581 3582 failed1: 3583 psp_free_shared_bufs(psp); 3584 failed: 3585 /* 3586 * all cleanup jobs (xgmi terminate, ras terminate, 3587 * ring destroy, cmd/fence/fw buffers destory, 3588 * psp->cmd destory) are delayed to psp_hw_fini 3589 */ 3590 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3591 return ret; 3592 } 3593 3594 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3595 { 3596 int ret; 3597 struct amdgpu_device *adev = ip_block->adev; 3598 3599 mutex_lock(&adev->firmware.mutex); 3600 3601 ret = amdgpu_ucode_init_bo(adev); 3602 if (ret) 3603 goto failed; 3604 3605 ret = psp_load_fw(adev); 3606 if (ret) { 3607 dev_err(adev->dev, "PSP firmware loading failed\n"); 3608 goto failed; 3609 } 3610 3611 mutex_unlock(&adev->firmware.mutex); 3612 return 0; 3613 3614 failed: 3615 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3616 mutex_unlock(&adev->firmware.mutex); 3617 return -EINVAL; 3618 } 3619 3620 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3621 { 3622 struct amdgpu_device *adev = ip_block->adev; 3623 struct psp_context *psp = &adev->psp; 3624 3625 if (psp->ta_fw) { 3626 psp_ras_terminate(psp); 3627 psp_securedisplay_terminate(psp); 3628 psp_rap_terminate(psp); 3629 psp_dtm_terminate(psp); 3630 psp_hdcp_terminate(psp); 3631 3632 if (adev->gmc.xgmi.num_physical_nodes > 1) 3633 psp_xgmi_terminate(psp); 3634 } 3635 3636 psp_asd_terminate(psp); 3637 psp_tmr_terminate(psp); 3638 3639 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3640 3641 return 0; 3642 } 3643 3644 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3645 { 3646 int ret = 0; 3647 struct amdgpu_device *adev = ip_block->adev; 3648 struct psp_context *psp = &adev->psp; 3649 3650 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3651 psp->xgmi_context.context.initialized) { 3652 ret = psp_xgmi_terminate(psp); 3653 if (ret) { 3654 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3655 goto out; 3656 } 3657 } 3658 3659 if (psp->ta_fw) { 3660 ret = psp_ras_terminate(psp); 3661 if (ret) { 3662 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3663 goto out; 3664 } 3665 ret = psp_hdcp_terminate(psp); 3666 if (ret) { 3667 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3668 goto out; 3669 } 3670 ret = psp_dtm_terminate(psp); 3671 if (ret) { 3672 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3673 goto out; 3674 } 3675 ret = psp_rap_terminate(psp); 3676 if (ret) { 3677 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3678 goto out; 3679 } 3680 ret = psp_securedisplay_terminate(psp); 3681 if (ret) { 3682 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3683 goto out; 3684 } 3685 } 3686 3687 ret = psp_asd_terminate(psp); 3688 if (ret) { 3689 dev_err(adev->dev, "Failed to terminate asd\n"); 3690 goto out; 3691 } 3692 3693 ret = psp_tmr_terminate(psp); 3694 if (ret) { 3695 dev_err(adev->dev, "Failed to terminate tmr\n"); 3696 goto out; 3697 } 3698 3699 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3700 if (ret) 3701 dev_err(adev->dev, "PSP ring stop failed\n"); 3702 3703 out: 3704 return ret; 3705 } 3706 3707 static int psp_resume(struct amdgpu_ip_block *ip_block) 3708 { 3709 int ret; 3710 struct amdgpu_device *adev = ip_block->adev; 3711 struct psp_context *psp = &adev->psp; 3712 3713 dev_info(adev->dev, "PSP is resuming...\n"); 3714 3715 if (psp->mem_train_ctx.enable_mem_training) { 3716 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3717 if (ret) { 3718 dev_err(adev->dev, "Failed to process memory training!\n"); 3719 return ret; 3720 } 3721 } 3722 3723 mutex_lock(&adev->firmware.mutex); 3724 3725 ret = amdgpu_ucode_init_bo(adev); 3726 if (ret) 3727 goto failed; 3728 3729 ret = psp_hw_start(psp); 3730 if (ret) 3731 goto failed; 3732 3733 ret = psp_load_non_psp_fw(psp); 3734 if (ret) 3735 goto failed; 3736 3737 ret = psp_asd_initialize(psp); 3738 if (ret) { 3739 dev_err(adev->dev, "PSP load asd failed!\n"); 3740 goto failed; 3741 } 3742 3743 ret = psp_rl_load(adev); 3744 if (ret) { 3745 dev_err(adev->dev, "PSP load RL failed!\n"); 3746 goto failed; 3747 } 3748 3749 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3750 ret = psp_xgmi_initialize(psp, false, true); 3751 /* Warning the XGMI seesion initialize failure 3752 * Instead of stop driver initialization 3753 */ 3754 if (ret) 3755 dev_err(psp->adev->dev, 3756 "XGMI: Failed to initialize XGMI session\n"); 3757 } 3758 3759 if (psp->ta_fw) { 3760 ret = psp_ras_initialize(psp); 3761 if (ret) 3762 dev_err(psp->adev->dev, 3763 "RAS: Failed to initialize RAS\n"); 3764 3765 ret = psp_hdcp_initialize(psp); 3766 if (ret) 3767 dev_err(psp->adev->dev, 3768 "HDCP: Failed to initialize HDCP\n"); 3769 3770 ret = psp_dtm_initialize(psp); 3771 if (ret) 3772 dev_err(psp->adev->dev, 3773 "DTM: Failed to initialize DTM\n"); 3774 3775 ret = psp_rap_initialize(psp); 3776 if (ret) 3777 dev_err(psp->adev->dev, 3778 "RAP: Failed to initialize RAP\n"); 3779 3780 ret = psp_securedisplay_initialize(psp); 3781 if (ret) 3782 dev_err(psp->adev->dev, 3783 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3784 } 3785 3786 mutex_unlock(&adev->firmware.mutex); 3787 3788 return 0; 3789 3790 failed: 3791 dev_err(adev->dev, "PSP resume failed\n"); 3792 mutex_unlock(&adev->firmware.mutex); 3793 return ret; 3794 } 3795 3796 int psp_gpu_reset(struct amdgpu_device *adev) 3797 { 3798 int ret; 3799 3800 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3801 return 0; 3802 3803 mutex_lock(&adev->psp.mutex); 3804 ret = psp_mode1_reset(&adev->psp); 3805 mutex_unlock(&adev->psp.mutex); 3806 3807 return ret; 3808 } 3809 3810 int psp_rlc_autoload_start(struct psp_context *psp) 3811 { 3812 int ret; 3813 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3814 3815 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3816 3817 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3818 psp->fence_buf_mc_addr); 3819 3820 release_psp_cmd_buf(psp); 3821 3822 return ret; 3823 } 3824 3825 int psp_ring_cmd_submit(struct psp_context *psp, 3826 uint64_t cmd_buf_mc_addr, 3827 uint64_t fence_mc_addr, 3828 int index) 3829 { 3830 unsigned int psp_write_ptr_reg = 0; 3831 struct psp_gfx_rb_frame *write_frame; 3832 struct psp_ring *ring = &psp->km_ring; 3833 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3834 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3835 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3836 struct amdgpu_device *adev = psp->adev; 3837 uint32_t ring_size_dw = ring->ring_size / 4; 3838 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3839 3840 /* KM (GPCOM) prepare write pointer */ 3841 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3842 3843 /* Update KM RB frame pointer to new frame */ 3844 /* write_frame ptr increments by size of rb_frame in bytes */ 3845 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3846 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3847 write_frame = ring_buffer_start; 3848 else 3849 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3850 /* Check invalid write_frame ptr address */ 3851 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3852 dev_err(adev->dev, 3853 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3854 ring_buffer_start, ring_buffer_end, write_frame); 3855 dev_err(adev->dev, 3856 "write_frame is pointing to address out of bounds\n"); 3857 return -EINVAL; 3858 } 3859 3860 /* Initialize KM RB frame */ 3861 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3862 3863 /* Update KM RB frame */ 3864 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3865 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3866 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3867 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3868 write_frame->fence_value = index; 3869 amdgpu_device_flush_hdp(adev, NULL); 3870 3871 /* Update the write Pointer in DWORDs */ 3872 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3873 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3874 return 0; 3875 } 3876 3877 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3878 { 3879 struct amdgpu_device *adev = psp->adev; 3880 const struct psp_firmware_header_v1_0 *asd_hdr; 3881 int err = 0; 3882 3883 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3884 "amdgpu/%s_asd.bin", chip_name); 3885 if (err) 3886 goto out; 3887 3888 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3889 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3890 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3891 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3892 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3893 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3894 return 0; 3895 out: 3896 amdgpu_ucode_release(&adev->psp.asd_fw); 3897 return err; 3898 } 3899 3900 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3901 { 3902 struct amdgpu_device *adev = psp->adev; 3903 const struct psp_firmware_header_v1_0 *toc_hdr; 3904 int err = 0; 3905 3906 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3907 adev->rev_id == 0) 3908 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3909 "amdgpu/%s_toc_1.bin", chip_name); 3910 else 3911 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3912 "amdgpu/%s_toc.bin", chip_name); 3913 if (err) 3914 goto out; 3915 3916 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3917 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3918 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3919 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3920 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3921 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3922 return 0; 3923 out: 3924 amdgpu_ucode_release(&adev->psp.toc_fw); 3925 return err; 3926 } 3927 3928 static int parse_sos_bin_descriptor(struct psp_context *psp, 3929 const struct psp_fw_bin_desc *desc, 3930 const struct psp_firmware_header_v2_0 *sos_hdr) 3931 { 3932 uint8_t *ucode_start_addr = NULL; 3933 3934 if (!psp || !desc || !sos_hdr) 3935 return -EINVAL; 3936 3937 ucode_start_addr = (uint8_t *)sos_hdr + 3938 le32_to_cpu(desc->offset_bytes) + 3939 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3940 3941 switch (desc->fw_type) { 3942 case PSP_FW_TYPE_PSP_SOS: 3943 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3944 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3945 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3946 psp->sos.start_addr = ucode_start_addr; 3947 break; 3948 case PSP_FW_TYPE_PSP_SYS_DRV: 3949 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3950 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3951 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3952 psp->sys.start_addr = ucode_start_addr; 3953 break; 3954 case PSP_FW_TYPE_PSP_KDB: 3955 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3956 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3957 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3958 psp->kdb.start_addr = ucode_start_addr; 3959 break; 3960 case PSP_FW_TYPE_PSP_TOC: 3961 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3962 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3963 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3964 psp->toc.start_addr = ucode_start_addr; 3965 break; 3966 case PSP_FW_TYPE_PSP_SPL: 3967 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3968 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3969 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3970 psp->spl.start_addr = ucode_start_addr; 3971 break; 3972 case PSP_FW_TYPE_PSP_RL: 3973 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3974 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3975 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3976 psp->rl.start_addr = ucode_start_addr; 3977 break; 3978 case PSP_FW_TYPE_PSP_SOC_DRV: 3979 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3980 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3981 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3982 psp->soc_drv.start_addr = ucode_start_addr; 3983 break; 3984 case PSP_FW_TYPE_PSP_INTF_DRV: 3985 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3986 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3987 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3988 psp->intf_drv.start_addr = ucode_start_addr; 3989 break; 3990 case PSP_FW_TYPE_PSP_DBG_DRV: 3991 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3992 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3993 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3994 psp->dbg_drv.start_addr = ucode_start_addr; 3995 break; 3996 case PSP_FW_TYPE_PSP_RAS_DRV: 3997 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3998 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3999 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4000 psp->ras_drv.start_addr = ucode_start_addr; 4001 break; 4002 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4003 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4004 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4005 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4006 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4007 break; 4008 case PSP_FW_TYPE_PSP_SPDM_DRV: 4009 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4010 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4011 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4012 psp->spdm_drv.start_addr = ucode_start_addr; 4013 break; 4014 default: 4015 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4016 break; 4017 } 4018 4019 return 0; 4020 } 4021 4022 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4023 { 4024 const struct psp_firmware_header_v1_0 *sos_hdr; 4025 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4026 uint8_t *ucode_array_start_addr; 4027 4028 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4029 ucode_array_start_addr = (uint8_t *)sos_hdr + 4030 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4031 4032 if (adev->gmc.xgmi.connected_to_cpu || 4033 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4034 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4035 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4036 4037 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4038 adev->psp.sys.start_addr = ucode_array_start_addr; 4039 4040 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4041 adev->psp.sos.start_addr = ucode_array_start_addr + 4042 le32_to_cpu(sos_hdr->sos.offset_bytes); 4043 } else { 4044 /* Load alternate PSP SOS FW */ 4045 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4046 4047 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4048 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4049 4050 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4051 adev->psp.sys.start_addr = ucode_array_start_addr + 4052 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4053 4054 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4055 adev->psp.sos.start_addr = ucode_array_start_addr + 4056 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4057 } 4058 4059 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4060 dev_warn(adev->dev, "PSP SOS FW not available"); 4061 return -EINVAL; 4062 } 4063 4064 return 0; 4065 } 4066 4067 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4068 { 4069 struct amdgpu_device *adev = psp->adev; 4070 const struct psp_firmware_header_v1_0 *sos_hdr; 4071 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4072 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4073 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4074 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4075 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4076 int fw_index, fw_bin_count, start_index = 0; 4077 const struct psp_fw_bin_desc *fw_bin; 4078 uint8_t *ucode_array_start_addr; 4079 int err = 0; 4080 4081 if (amdgpu_is_kicker_fw(adev)) 4082 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4083 "amdgpu/%s_sos_kicker.bin", chip_name); 4084 else 4085 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4086 "amdgpu/%s_sos.bin", chip_name); 4087 if (err) 4088 goto out; 4089 4090 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4091 ucode_array_start_addr = (uint8_t *)sos_hdr + 4092 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4093 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4094 4095 switch (sos_hdr->header.header_version_major) { 4096 case 1: 4097 err = psp_init_sos_base_fw(adev); 4098 if (err) 4099 goto out; 4100 4101 if (sos_hdr->header.header_version_minor == 1) { 4102 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4103 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4104 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4105 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4106 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4107 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4108 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4109 } 4110 if (sos_hdr->header.header_version_minor == 2) { 4111 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4112 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4113 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4114 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4115 } 4116 if (sos_hdr->header.header_version_minor == 3) { 4117 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4118 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4119 adev->psp.toc.start_addr = ucode_array_start_addr + 4120 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4121 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4122 adev->psp.kdb.start_addr = ucode_array_start_addr + 4123 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4124 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4125 adev->psp.spl.start_addr = ucode_array_start_addr + 4126 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4127 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4128 adev->psp.rl.start_addr = ucode_array_start_addr + 4129 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4130 } 4131 break; 4132 case 2: 4133 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4134 4135 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4136 4137 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4138 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4139 err = -EINVAL; 4140 goto out; 4141 } 4142 4143 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4144 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4145 4146 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4147 4148 if (psp_is_aux_sos_load_required(psp)) 4149 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4150 else 4151 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4152 4153 } else { 4154 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4155 } 4156 4157 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4158 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4159 sos_hdr_v2_0); 4160 if (err) 4161 goto out; 4162 } 4163 break; 4164 default: 4165 dev_err(adev->dev, 4166 "unsupported psp sos firmware\n"); 4167 err = -EINVAL; 4168 goto out; 4169 } 4170 4171 return 0; 4172 out: 4173 amdgpu_ucode_release(&adev->psp.sos_fw); 4174 4175 return err; 4176 } 4177 4178 static bool is_ta_fw_applicable(struct psp_context *psp, 4179 const struct psp_fw_bin_desc *desc) 4180 { 4181 struct amdgpu_device *adev = psp->adev; 4182 uint32_t fw_version; 4183 4184 switch (desc->fw_type) { 4185 case TA_FW_TYPE_PSP_XGMI: 4186 case TA_FW_TYPE_PSP_XGMI_AUX: 4187 /* for now, AUX TA only exists on 13.0.6 ta bin, 4188 * from v20.00.0x.14 4189 */ 4190 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4191 IP_VERSION(13, 0, 6)) { 4192 fw_version = le32_to_cpu(desc->fw_version); 4193 4194 if (adev->flags & AMD_IS_APU && 4195 (fw_version & 0xff) >= 0x14) 4196 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4197 else 4198 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4199 } 4200 break; 4201 default: 4202 break; 4203 } 4204 4205 return true; 4206 } 4207 4208 static int parse_ta_bin_descriptor(struct psp_context *psp, 4209 const struct psp_fw_bin_desc *desc, 4210 const struct ta_firmware_header_v2_0 *ta_hdr) 4211 { 4212 uint8_t *ucode_start_addr = NULL; 4213 4214 if (!psp || !desc || !ta_hdr) 4215 return -EINVAL; 4216 4217 if (!is_ta_fw_applicable(psp, desc)) 4218 return 0; 4219 4220 ucode_start_addr = (uint8_t *)ta_hdr + 4221 le32_to_cpu(desc->offset_bytes) + 4222 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4223 4224 switch (desc->fw_type) { 4225 case TA_FW_TYPE_PSP_ASD: 4226 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4227 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4228 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4229 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4230 break; 4231 case TA_FW_TYPE_PSP_XGMI: 4232 case TA_FW_TYPE_PSP_XGMI_AUX: 4233 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4234 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4235 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4236 break; 4237 case TA_FW_TYPE_PSP_RAS: 4238 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4239 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4240 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4241 break; 4242 case TA_FW_TYPE_PSP_HDCP: 4243 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4244 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4245 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4246 break; 4247 case TA_FW_TYPE_PSP_DTM: 4248 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4249 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4250 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4251 break; 4252 case TA_FW_TYPE_PSP_RAP: 4253 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4254 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4255 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4256 break; 4257 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4258 psp->securedisplay_context.context.bin_desc.fw_version = 4259 le32_to_cpu(desc->fw_version); 4260 psp->securedisplay_context.context.bin_desc.size_bytes = 4261 le32_to_cpu(desc->size_bytes); 4262 psp->securedisplay_context.context.bin_desc.start_addr = 4263 ucode_start_addr; 4264 break; 4265 default: 4266 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4267 break; 4268 } 4269 4270 return 0; 4271 } 4272 4273 static int parse_ta_v1_microcode(struct psp_context *psp) 4274 { 4275 const struct ta_firmware_header_v1_0 *ta_hdr; 4276 struct amdgpu_device *adev = psp->adev; 4277 4278 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4279 4280 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4281 return -EINVAL; 4282 4283 adev->psp.xgmi_context.context.bin_desc.fw_version = 4284 le32_to_cpu(ta_hdr->xgmi.fw_version); 4285 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4286 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4287 adev->psp.xgmi_context.context.bin_desc.start_addr = 4288 (uint8_t *)ta_hdr + 4289 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4290 4291 adev->psp.ras_context.context.bin_desc.fw_version = 4292 le32_to_cpu(ta_hdr->ras.fw_version); 4293 adev->psp.ras_context.context.bin_desc.size_bytes = 4294 le32_to_cpu(ta_hdr->ras.size_bytes); 4295 adev->psp.ras_context.context.bin_desc.start_addr = 4296 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4297 le32_to_cpu(ta_hdr->ras.offset_bytes); 4298 4299 adev->psp.hdcp_context.context.bin_desc.fw_version = 4300 le32_to_cpu(ta_hdr->hdcp.fw_version); 4301 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4302 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4303 adev->psp.hdcp_context.context.bin_desc.start_addr = 4304 (uint8_t *)ta_hdr + 4305 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4306 4307 adev->psp.dtm_context.context.bin_desc.fw_version = 4308 le32_to_cpu(ta_hdr->dtm.fw_version); 4309 adev->psp.dtm_context.context.bin_desc.size_bytes = 4310 le32_to_cpu(ta_hdr->dtm.size_bytes); 4311 adev->psp.dtm_context.context.bin_desc.start_addr = 4312 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4313 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4314 4315 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4316 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4317 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4318 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4319 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4320 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4321 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4322 4323 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4324 4325 return 0; 4326 } 4327 4328 static int parse_ta_v2_microcode(struct psp_context *psp) 4329 { 4330 const struct ta_firmware_header_v2_0 *ta_hdr; 4331 struct amdgpu_device *adev = psp->adev; 4332 int err = 0; 4333 int ta_index = 0; 4334 4335 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4336 4337 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4338 return -EINVAL; 4339 4340 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4341 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4342 return -EINVAL; 4343 } 4344 4345 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4346 err = parse_ta_bin_descriptor(psp, 4347 &ta_hdr->ta_fw_bin[ta_index], 4348 ta_hdr); 4349 if (err) 4350 return err; 4351 } 4352 4353 return 0; 4354 } 4355 4356 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4357 { 4358 const struct common_firmware_header *hdr; 4359 struct amdgpu_device *adev = psp->adev; 4360 int err; 4361 4362 if (amdgpu_is_kicker_fw(adev)) 4363 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4364 "amdgpu/%s_ta_kicker.bin", chip_name); 4365 else 4366 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4367 "amdgpu/%s_ta.bin", chip_name); 4368 if (err) 4369 return err; 4370 4371 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4372 switch (le16_to_cpu(hdr->header_version_major)) { 4373 case 1: 4374 err = parse_ta_v1_microcode(psp); 4375 break; 4376 case 2: 4377 err = parse_ta_v2_microcode(psp); 4378 break; 4379 default: 4380 dev_err(adev->dev, "unsupported TA header version\n"); 4381 err = -EINVAL; 4382 } 4383 4384 if (err) 4385 amdgpu_ucode_release(&adev->psp.ta_fw); 4386 4387 return err; 4388 } 4389 4390 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4391 { 4392 struct amdgpu_device *adev = psp->adev; 4393 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4394 struct amdgpu_firmware_info *info = NULL; 4395 int err = 0; 4396 4397 if (!amdgpu_sriov_vf(adev)) { 4398 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4399 return -EINVAL; 4400 } 4401 4402 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4403 "amdgpu/%s_cap.bin", chip_name); 4404 if (err) { 4405 if (err == -ENODEV) { 4406 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4407 err = 0; 4408 } else { 4409 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4410 } 4411 goto out; 4412 } 4413 4414 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4415 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4416 info->fw = adev->psp.cap_fw; 4417 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4418 adev->psp.cap_fw->data; 4419 adev->firmware.fw_size += ALIGN( 4420 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4421 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4422 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4423 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4424 4425 return 0; 4426 4427 out: 4428 amdgpu_ucode_release(&adev->psp.cap_fw); 4429 return err; 4430 } 4431 4432 int psp_config_sq_perfmon(struct psp_context *psp, 4433 uint32_t xcp_id, bool core_override_enable, 4434 bool reg_override_enable, bool perfmon_override_enable) 4435 { 4436 int ret; 4437 4438 if (amdgpu_sriov_vf(psp->adev)) 4439 return 0; 4440 4441 if (xcp_id > MAX_XCP) { 4442 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4443 return -EINVAL; 4444 } 4445 4446 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4447 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4448 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4449 return -EINVAL; 4450 } 4451 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4452 4453 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4454 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4455 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4456 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4457 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4458 4459 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4460 if (ret) 4461 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4462 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4463 4464 release_psp_cmd_buf(psp); 4465 return ret; 4466 } 4467 4468 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4469 enum amd_clockgating_state state) 4470 { 4471 return 0; 4472 } 4473 4474 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4475 enum amd_powergating_state state) 4476 { 4477 return 0; 4478 } 4479 4480 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4481 struct device_attribute *attr, 4482 char *buf) 4483 { 4484 struct drm_device *ddev = dev_get_drvdata(dev); 4485 struct amdgpu_device *adev = drm_to_adev(ddev); 4486 struct amdgpu_ip_block *ip_block; 4487 uint32_t fw_ver; 4488 int ret; 4489 4490 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4491 if (!ip_block || !ip_block->status.late_initialized) { 4492 dev_info(adev->dev, "PSP block is not ready yet\n."); 4493 return -EBUSY; 4494 } 4495 4496 mutex_lock(&adev->psp.mutex); 4497 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4498 mutex_unlock(&adev->psp.mutex); 4499 4500 if (ret) { 4501 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4502 return ret; 4503 } 4504 4505 return sysfs_emit(buf, "%x\n", fw_ver); 4506 } 4507 4508 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4509 struct device_attribute *attr, 4510 const char *buf, 4511 size_t count) 4512 { 4513 struct drm_device *ddev = dev_get_drvdata(dev); 4514 struct amdgpu_device *adev = drm_to_adev(ddev); 4515 int ret, idx; 4516 const struct firmware *usbc_pd_fw; 4517 struct amdgpu_bo *fw_buf_bo = NULL; 4518 uint64_t fw_pri_mc_addr; 4519 void *fw_pri_cpu_addr; 4520 struct amdgpu_ip_block *ip_block; 4521 4522 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4523 if (!ip_block || !ip_block->status.late_initialized) { 4524 dev_err(adev->dev, "PSP block is not ready yet."); 4525 return -EBUSY; 4526 } 4527 4528 if (!drm_dev_enter(ddev, &idx)) 4529 return -ENODEV; 4530 4531 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4532 "amdgpu/%s", buf); 4533 if (ret) 4534 goto fail; 4535 4536 /* LFB address which is aligned to 1MB boundary per PSP request */ 4537 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4538 AMDGPU_GEM_DOMAIN_VRAM | 4539 AMDGPU_GEM_DOMAIN_GTT, 4540 &fw_buf_bo, &fw_pri_mc_addr, 4541 &fw_pri_cpu_addr); 4542 if (ret) 4543 goto rel_buf; 4544 4545 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4546 4547 mutex_lock(&adev->psp.mutex); 4548 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4549 mutex_unlock(&adev->psp.mutex); 4550 4551 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4552 4553 rel_buf: 4554 amdgpu_ucode_release(&usbc_pd_fw); 4555 fail: 4556 if (ret) { 4557 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4558 count = ret; 4559 } 4560 4561 drm_dev_exit(idx); 4562 return count; 4563 } 4564 4565 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4566 { 4567 int idx; 4568 4569 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4570 return; 4571 4572 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4573 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4574 4575 drm_dev_exit(idx); 4576 } 4577 4578 /** 4579 * DOC: usbc_pd_fw 4580 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4581 * this file will trigger the update process. 4582 */ 4583 static DEVICE_ATTR(usbc_pd_fw, 0644, 4584 psp_usbc_pd_fw_sysfs_read, 4585 psp_usbc_pd_fw_sysfs_write); 4586 /** 4587 * DOC: PTL sysfs attributes 4588 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4589 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4590 * formats for each GPU. 4591 */ 4592 static DEVICE_ATTR(ptl_enable, 0644, 4593 ptl_enable_show, ptl_enable_store); 4594 static DEVICE_ATTR(ptl_format, 0644, 4595 ptl_format_show, ptl_format_store); 4596 static DEVICE_ATTR(ptl_supported_formats, 0444, 4597 ptl_supported_formats_show, NULL); 4598 4599 static struct attribute *ptl_attrs[] = { 4600 &dev_attr_ptl_enable.attr, 4601 &dev_attr_ptl_format.attr, 4602 &dev_attr_ptl_supported_formats.attr, 4603 NULL, 4604 }; 4605 4606 const struct attribute_group amdgpu_ptl_attr_group = { 4607 .name = "ptl", 4608 .attrs = ptl_attrs, 4609 .is_visible = amdgpu_ptl_is_visible, 4610 }; 4611 4612 int is_psp_fw_valid(struct psp_bin_desc bin) 4613 { 4614 return bin.size_bytes; 4615 } 4616 4617 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4618 const struct bin_attribute *bin_attr, 4619 char *buffer, loff_t pos, size_t count) 4620 { 4621 struct device *dev = kobj_to_dev(kobj); 4622 struct drm_device *ddev = dev_get_drvdata(dev); 4623 struct amdgpu_device *adev = drm_to_adev(ddev); 4624 4625 adev->psp.vbflash_done = false; 4626 4627 /* Safeguard against memory drain */ 4628 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4629 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4630 kvfree(adev->psp.vbflash_tmp_buf); 4631 adev->psp.vbflash_tmp_buf = NULL; 4632 adev->psp.vbflash_image_size = 0; 4633 return -ENOMEM; 4634 } 4635 4636 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4637 if (!adev->psp.vbflash_tmp_buf) { 4638 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4639 if (!adev->psp.vbflash_tmp_buf) 4640 return -ENOMEM; 4641 } 4642 4643 mutex_lock(&adev->psp.mutex); 4644 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4645 adev->psp.vbflash_image_size += count; 4646 mutex_unlock(&adev->psp.mutex); 4647 4648 dev_dbg(adev->dev, "IFWI staged for update\n"); 4649 4650 return count; 4651 } 4652 4653 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4654 const struct bin_attribute *bin_attr, char *buffer, 4655 loff_t pos, size_t count) 4656 { 4657 struct device *dev = kobj_to_dev(kobj); 4658 struct drm_device *ddev = dev_get_drvdata(dev); 4659 struct amdgpu_device *adev = drm_to_adev(ddev); 4660 struct amdgpu_bo *fw_buf_bo = NULL; 4661 uint64_t fw_pri_mc_addr; 4662 void *fw_pri_cpu_addr; 4663 int ret; 4664 4665 if (adev->psp.vbflash_image_size == 0) 4666 return -EINVAL; 4667 4668 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4669 4670 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4671 AMDGPU_GPU_PAGE_SIZE, 4672 AMDGPU_GEM_DOMAIN_VRAM, 4673 &fw_buf_bo, 4674 &fw_pri_mc_addr, 4675 &fw_pri_cpu_addr); 4676 if (ret) 4677 goto rel_buf; 4678 4679 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4680 4681 mutex_lock(&adev->psp.mutex); 4682 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4683 mutex_unlock(&adev->psp.mutex); 4684 4685 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4686 4687 rel_buf: 4688 kvfree(adev->psp.vbflash_tmp_buf); 4689 adev->psp.vbflash_tmp_buf = NULL; 4690 adev->psp.vbflash_image_size = 0; 4691 4692 if (ret) { 4693 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4694 return ret; 4695 } 4696 4697 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4698 return 0; 4699 } 4700 4701 /** 4702 * DOC: psp_vbflash 4703 * Writing to this file will stage an IFWI for update. Reading from this file 4704 * will trigger the update process. 4705 */ 4706 static const struct bin_attribute psp_vbflash_bin_attr = { 4707 .attr = {.name = "psp_vbflash", .mode = 0660}, 4708 .size = 0, 4709 .write = amdgpu_psp_vbflash_write, 4710 .read = amdgpu_psp_vbflash_read, 4711 }; 4712 4713 /** 4714 * DOC: psp_vbflash_status 4715 * The status of the flash process. 4716 * 0: IFWI flash not complete. 4717 * 1: IFWI flash complete. 4718 */ 4719 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4720 struct device_attribute *attr, 4721 char *buf) 4722 { 4723 struct drm_device *ddev = dev_get_drvdata(dev); 4724 struct amdgpu_device *adev = drm_to_adev(ddev); 4725 uint32_t vbflash_status; 4726 4727 vbflash_status = psp_vbflash_status(&adev->psp); 4728 if (!adev->psp.vbflash_done) 4729 vbflash_status = 0; 4730 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4731 vbflash_status = 1; 4732 4733 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4734 } 4735 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4736 4737 static const struct bin_attribute *const bin_flash_attrs[] = { 4738 &psp_vbflash_bin_attr, 4739 NULL 4740 }; 4741 4742 static struct attribute *flash_attrs[] = { 4743 &dev_attr_psp_vbflash_status.attr, 4744 &dev_attr_usbc_pd_fw.attr, 4745 NULL 4746 }; 4747 4748 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4749 { 4750 struct device *dev = kobj_to_dev(kobj); 4751 struct drm_device *ddev = dev_get_drvdata(dev); 4752 struct amdgpu_device *adev = drm_to_adev(ddev); 4753 4754 if (attr == &dev_attr_usbc_pd_fw.attr) 4755 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4756 4757 return adev->psp.sup_ifwi_up ? 0440 : 0; 4758 } 4759 4760 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4761 const struct bin_attribute *attr, 4762 int idx) 4763 { 4764 struct device *dev = kobj_to_dev(kobj); 4765 struct drm_device *ddev = dev_get_drvdata(dev); 4766 struct amdgpu_device *adev = drm_to_adev(ddev); 4767 4768 return adev->psp.sup_ifwi_up ? 0660 : 0; 4769 } 4770 4771 const struct attribute_group amdgpu_flash_attr_group = { 4772 .attrs = flash_attrs, 4773 .bin_attrs = bin_flash_attrs, 4774 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4775 .is_visible = amdgpu_flash_attr_is_visible, 4776 }; 4777 4778 #if defined(CONFIG_DEBUG_FS) 4779 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4780 { 4781 struct amdgpu_device *adev = filp->f_inode->i_private; 4782 struct spirom_bo *bo_triplet; 4783 int ret; 4784 4785 /* serialize the open() file calling */ 4786 if (!mutex_trylock(&adev->psp.mutex)) 4787 return -EBUSY; 4788 4789 /* 4790 * make sure only one userpace process is alive for dumping so that 4791 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4792 * let's say the case where one process try opening the file while 4793 * another one has proceeded to read or release. In this way, eliminate 4794 * the use of mutex for read() or release() callback as well. 4795 */ 4796 if (adev->psp.spirom_dump_trip) { 4797 mutex_unlock(&adev->psp.mutex); 4798 return -EBUSY; 4799 } 4800 4801 bo_triplet = kzalloc_obj(struct spirom_bo); 4802 if (!bo_triplet) { 4803 mutex_unlock(&adev->psp.mutex); 4804 return -ENOMEM; 4805 } 4806 4807 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4808 AMDGPU_GPU_PAGE_SIZE, 4809 AMDGPU_GEM_DOMAIN_GTT, 4810 &bo_triplet->bo, 4811 &bo_triplet->mc_addr, 4812 &bo_triplet->cpu_addr); 4813 if (ret) 4814 goto rel_trip; 4815 4816 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4817 if (ret) 4818 goto rel_bo; 4819 4820 adev->psp.spirom_dump_trip = bo_triplet; 4821 mutex_unlock(&adev->psp.mutex); 4822 return 0; 4823 rel_bo: 4824 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4825 &bo_triplet->cpu_addr); 4826 rel_trip: 4827 kfree(bo_triplet); 4828 mutex_unlock(&adev->psp.mutex); 4829 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4830 return ret; 4831 } 4832 4833 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4834 loff_t *pos) 4835 { 4836 struct amdgpu_device *adev = filp->f_inode->i_private; 4837 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4838 4839 if (!bo_triplet) 4840 return -EINVAL; 4841 4842 return simple_read_from_buffer(buf, 4843 size, 4844 pos, bo_triplet->cpu_addr, 4845 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4846 } 4847 4848 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4849 { 4850 struct amdgpu_device *adev = filp->f_inode->i_private; 4851 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4852 4853 if (bo_triplet) { 4854 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4855 &bo_triplet->cpu_addr); 4856 kfree(bo_triplet); 4857 } 4858 4859 adev->psp.spirom_dump_trip = NULL; 4860 return 0; 4861 } 4862 4863 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4864 .owner = THIS_MODULE, 4865 .open = psp_read_spirom_debugfs_open, 4866 .read = psp_read_spirom_debugfs_read, 4867 .release = psp_read_spirom_debugfs_release, 4868 .llseek = default_llseek, 4869 }; 4870 #endif 4871 4872 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4873 { 4874 #if defined(CONFIG_DEBUG_FS) 4875 struct drm_minor *minor = adev_to_drm(adev)->primary; 4876 4877 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4878 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4879 #endif 4880 } 4881 4882 const struct amd_ip_funcs psp_ip_funcs = { 4883 .name = "psp", 4884 .early_init = psp_early_init, 4885 .sw_init = psp_sw_init, 4886 .sw_fini = psp_sw_fini, 4887 .hw_init = psp_hw_init, 4888 .hw_fini = psp_hw_fini, 4889 .suspend = psp_suspend, 4890 .resume = psp_resume, 4891 .set_clockgating_state = psp_set_clockgating_state, 4892 .set_powergating_state = psp_set_powergating_state, 4893 }; 4894 4895 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4896 .type = AMD_IP_BLOCK_TYPE_PSP, 4897 .major = 3, 4898 .minor = 1, 4899 .rev = 0, 4900 .funcs = &psp_ip_funcs, 4901 }; 4902 4903 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4904 .type = AMD_IP_BLOCK_TYPE_PSP, 4905 .major = 10, 4906 .minor = 0, 4907 .rev = 0, 4908 .funcs = &psp_ip_funcs, 4909 }; 4910 4911 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4912 .type = AMD_IP_BLOCK_TYPE_PSP, 4913 .major = 11, 4914 .minor = 0, 4915 .rev = 0, 4916 .funcs = &psp_ip_funcs, 4917 }; 4918 4919 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4920 .type = AMD_IP_BLOCK_TYPE_PSP, 4921 .major = 11, 4922 .minor = 0, 4923 .rev = 8, 4924 .funcs = &psp_ip_funcs, 4925 }; 4926 4927 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4928 .type = AMD_IP_BLOCK_TYPE_PSP, 4929 .major = 12, 4930 .minor = 0, 4931 .rev = 0, 4932 .funcs = &psp_ip_funcs, 4933 }; 4934 4935 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4936 .type = AMD_IP_BLOCK_TYPE_PSP, 4937 .major = 13, 4938 .minor = 0, 4939 .rev = 0, 4940 .funcs = &psp_ip_funcs, 4941 }; 4942 4943 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4944 .type = AMD_IP_BLOCK_TYPE_PSP, 4945 .major = 13, 4946 .minor = 0, 4947 .rev = 4, 4948 .funcs = &psp_ip_funcs, 4949 }; 4950 4951 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4952 .type = AMD_IP_BLOCK_TYPE_PSP, 4953 .major = 14, 4954 .minor = 0, 4955 .rev = 0, 4956 .funcs = &psp_ip_funcs, 4957 }; 4958 4959 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 4960 .type = AMD_IP_BLOCK_TYPE_PSP, 4961 .major = 15, 4962 .minor = 0, 4963 .rev = 0, 4964 .funcs = &psp_ip_funcs, 4965 }; 4966 4967 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 4968 .type = AMD_IP_BLOCK_TYPE_PSP, 4969 .major = 15, 4970 .minor = 0, 4971 .rev = 8, 4972 .funcs = &psp_ip_funcs, 4973 }; 4974