1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 #include <drm/drm_drv.h> 45 46 static int psp_sysfs_init(struct amdgpu_device *adev); 47 static void psp_sysfs_fini(struct amdgpu_device *adev); 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 51 /* 52 * Due to DF Cstate management centralized to PMFW, the firmware 53 * loading sequence will be updated as below: 54 * - Load KDB 55 * - Load SYS_DRV 56 * - Load tOS 57 * - Load PMFW 58 * - Setup TMR 59 * - Load other non-psp fw 60 * - Load ASD 61 * - Load XGMI/RAS/HDCP/DTM TA if any 62 * 63 * This new sequence is required for 64 * - Arcturus and onwards 65 * - Navi12 and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 psp->pmfw_centralized_cstate_management = false; 72 73 if (amdgpu_sriov_vf(adev)) 74 return; 75 76 if (adev->flags & AMD_IS_APU) 77 return; 78 79 if ((adev->asic_type >= CHIP_ARCTURUS) || 80 (adev->asic_type >= CHIP_NAVI12)) 81 psp->pmfw_centralized_cstate_management = true; 82 } 83 84 static int psp_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 struct psp_context *psp = &adev->psp; 88 89 switch (adev->asic_type) { 90 case CHIP_VEGA10: 91 case CHIP_VEGA12: 92 psp_v3_1_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_RAVEN: 96 psp_v10_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_VEGA20: 100 case CHIP_ARCTURUS: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case CHIP_NAVI10: 105 case CHIP_NAVI14: 106 case CHIP_NAVI12: 107 case CHIP_SIENNA_CICHLID: 108 case CHIP_NAVY_FLOUNDER: 109 case CHIP_VANGOGH: 110 case CHIP_DIMGREY_CAVEFISH: 111 case CHIP_BEIGE_GOBY: 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = true; 114 break; 115 case CHIP_RENOIR: 116 psp_v12_0_set_psp_funcs(psp); 117 break; 118 case CHIP_ALDEBARAN: 119 psp_v13_0_set_psp_funcs(psp); 120 break; 121 case CHIP_YELLOW_CARP: 122 psp_v13_0_set_psp_funcs(psp); 123 psp->autoload_supported = true; 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 psp->adev = adev; 130 131 psp_check_pmfw_centralized_cstate_management(psp); 132 133 return 0; 134 } 135 136 static void psp_memory_training_fini(struct psp_context *psp) 137 { 138 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 139 140 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 141 kfree(ctx->sys_cache); 142 ctx->sys_cache = NULL; 143 } 144 145 static int psp_memory_training_init(struct psp_context *psp) 146 { 147 int ret; 148 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 149 150 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 151 DRM_DEBUG("memory training is not supported!\n"); 152 return 0; 153 } 154 155 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 156 if (ctx->sys_cache == NULL) { 157 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 158 ret = -ENOMEM; 159 goto Err_out; 160 } 161 162 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 163 ctx->train_data_size, 164 ctx->p2c_train_data_offset, 165 ctx->c2p_train_data_offset); 166 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 167 return 0; 168 169 Err_out: 170 psp_memory_training_fini(psp); 171 return ret; 172 } 173 174 static int psp_sw_init(void *handle) 175 { 176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 177 struct psp_context *psp = &adev->psp; 178 int ret; 179 180 if (!amdgpu_sriov_vf(adev)) { 181 ret = psp_init_microcode(psp); 182 if (ret) { 183 DRM_ERROR("Failed to load psp firmware!\n"); 184 return ret; 185 } 186 } 187 188 ret = psp_memory_training_init(psp); 189 if (ret) { 190 DRM_ERROR("Failed to initialize memory training!\n"); 191 return ret; 192 } 193 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 194 if (ret) { 195 DRM_ERROR("Failed to process memory training!\n"); 196 return ret; 197 } 198 199 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 200 ret= psp_sysfs_init(adev); 201 if (ret) { 202 return ret; 203 } 204 } 205 206 return 0; 207 } 208 209 static int psp_sw_fini(void *handle) 210 { 211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 213 psp_memory_training_fini(&adev->psp); 214 if (adev->psp.sos_fw) { 215 release_firmware(adev->psp.sos_fw); 216 adev->psp.sos_fw = NULL; 217 } 218 if (adev->psp.asd_fw) { 219 release_firmware(adev->psp.asd_fw); 220 adev->psp.asd_fw = NULL; 221 } 222 if (adev->psp.ta_fw) { 223 release_firmware(adev->psp.ta_fw); 224 adev->psp.ta_fw = NULL; 225 } 226 227 if (adev->asic_type == CHIP_NAVI10 || 228 adev->asic_type == CHIP_SIENNA_CICHLID) 229 psp_sysfs_fini(adev); 230 231 return 0; 232 } 233 234 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 235 uint32_t reg_val, uint32_t mask, bool check_changed) 236 { 237 uint32_t val; 238 int i; 239 struct amdgpu_device *adev = psp->adev; 240 241 if (psp->adev->no_hw_access) 242 return 0; 243 244 for (i = 0; i < adev->usec_timeout; i++) { 245 val = RREG32(reg_index); 246 if (check_changed) { 247 if (val != reg_val) 248 return 0; 249 } else { 250 if ((val & mask) == reg_val) 251 return 0; 252 } 253 udelay(1); 254 } 255 256 return -ETIME; 257 } 258 259 static int 260 psp_cmd_submit_buf(struct psp_context *psp, 261 struct amdgpu_firmware_info *ucode, 262 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 263 { 264 int ret; 265 int index, idx; 266 int timeout = 20000; 267 bool ras_intr = false; 268 bool skip_unsupport = false; 269 270 if (psp->adev->no_hw_access) 271 return 0; 272 273 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 274 return 0; 275 276 mutex_lock(&psp->mutex); 277 278 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 279 280 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 281 282 index = atomic_inc_return(&psp->fence_value); 283 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 284 if (ret) { 285 atomic_dec(&psp->fence_value); 286 goto exit; 287 } 288 289 amdgpu_device_invalidate_hdp(psp->adev, NULL); 290 while (*((unsigned int *)psp->fence_buf) != index) { 291 if (--timeout == 0) 292 break; 293 /* 294 * Shouldn't wait for timeout when err_event_athub occurs, 295 * because gpu reset thread triggered and lock resource should 296 * be released for psp resume sequence. 297 */ 298 ras_intr = amdgpu_ras_intr_triggered(); 299 if (ras_intr) 300 break; 301 usleep_range(10, 100); 302 amdgpu_device_invalidate_hdp(psp->adev, NULL); 303 } 304 305 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 306 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 307 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 308 309 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 310 311 /* In some cases, psp response status is not 0 even there is no 312 * problem while the command is submitted. Some version of PSP FW 313 * doesn't write 0 to that field. 314 * So here we would like to only print a warning instead of an error 315 * during psp initialization to avoid breaking hw_init and it doesn't 316 * return -EINVAL. 317 */ 318 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 319 if (ucode) 320 DRM_WARN("failed to load ucode id (%d) ", 321 ucode->ucode_id); 322 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 323 psp->cmd_buf_mem->cmd_id, 324 psp->cmd_buf_mem->resp.status); 325 if (!timeout) { 326 ret = -EINVAL; 327 goto exit; 328 } 329 } 330 331 if (ucode) { 332 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 333 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 334 } 335 336 exit: 337 mutex_unlock(&psp->mutex); 338 drm_dev_exit(idx); 339 return ret; 340 } 341 342 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 343 struct psp_gfx_cmd_resp *cmd, 344 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 345 { 346 struct amdgpu_device *adev = psp->adev; 347 uint32_t size = amdgpu_bo_size(tmr_bo); 348 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 349 350 if (amdgpu_sriov_vf(psp->adev)) 351 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 352 else 353 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 354 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 355 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 356 cmd->cmd.cmd_setup_tmr.buf_size = size; 357 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 358 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 359 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 360 } 361 362 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 363 uint64_t pri_buf_mc, uint32_t size) 364 { 365 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 366 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 367 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 368 cmd->cmd.cmd_load_toc.toc_size = size; 369 } 370 371 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 372 static int psp_load_toc(struct psp_context *psp, 373 uint32_t *tmr_size) 374 { 375 int ret; 376 struct psp_gfx_cmd_resp *cmd; 377 378 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 379 if (!cmd) 380 return -ENOMEM; 381 /* Copy toc to psp firmware private buffer */ 382 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); 383 384 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 385 386 ret = psp_cmd_submit_buf(psp, NULL, cmd, 387 psp->fence_buf_mc_addr); 388 if (!ret) 389 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 390 kfree(cmd); 391 return ret; 392 } 393 394 /* Set up Trusted Memory Region */ 395 static int psp_tmr_init(struct psp_context *psp) 396 { 397 int ret; 398 int tmr_size; 399 void *tmr_buf; 400 void **pptr; 401 402 /* 403 * According to HW engineer, they prefer the TMR address be "naturally 404 * aligned" , e.g. the start address be an integer divide of TMR size. 405 * 406 * Note: this memory need be reserved till the driver 407 * uninitializes. 408 */ 409 tmr_size = PSP_TMR_SIZE(psp->adev); 410 411 /* For ASICs support RLC autoload, psp will parse the toc 412 * and calculate the total size of TMR needed */ 413 if (!amdgpu_sriov_vf(psp->adev) && 414 psp->toc_start_addr && 415 psp->toc_bin_size && 416 psp->fw_pri_buf) { 417 ret = psp_load_toc(psp, &tmr_size); 418 if (ret) { 419 DRM_ERROR("Failed to load toc\n"); 420 return ret; 421 } 422 } 423 424 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 425 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 426 AMDGPU_GEM_DOMAIN_VRAM, 427 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 428 429 return ret; 430 } 431 432 static bool psp_skip_tmr(struct psp_context *psp) 433 { 434 switch (psp->adev->asic_type) { 435 case CHIP_NAVI12: 436 case CHIP_SIENNA_CICHLID: 437 case CHIP_ALDEBARAN: 438 return true; 439 default: 440 return false; 441 } 442 } 443 444 static int psp_tmr_load(struct psp_context *psp) 445 { 446 int ret; 447 struct psp_gfx_cmd_resp *cmd; 448 449 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 450 * Already set up by host driver. 451 */ 452 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 453 return 0; 454 455 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 456 if (!cmd) 457 return -ENOMEM; 458 459 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 460 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 461 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 462 463 ret = psp_cmd_submit_buf(psp, NULL, cmd, 464 psp->fence_buf_mc_addr); 465 466 kfree(cmd); 467 468 return ret; 469 } 470 471 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 472 struct psp_gfx_cmd_resp *cmd) 473 { 474 if (amdgpu_sriov_vf(psp->adev)) 475 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 476 else 477 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 478 } 479 480 static int psp_tmr_unload(struct psp_context *psp) 481 { 482 int ret; 483 struct psp_gfx_cmd_resp *cmd; 484 485 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 486 if (!cmd) 487 return -ENOMEM; 488 489 psp_prep_tmr_unload_cmd_buf(psp, cmd); 490 DRM_INFO("free PSP TMR buffer\n"); 491 492 ret = psp_cmd_submit_buf(psp, NULL, cmd, 493 psp->fence_buf_mc_addr); 494 495 kfree(cmd); 496 497 return ret; 498 } 499 500 static int psp_tmr_terminate(struct psp_context *psp) 501 { 502 int ret; 503 void *tmr_buf; 504 void **pptr; 505 506 ret = psp_tmr_unload(psp); 507 if (ret) 508 return ret; 509 510 /* free TMR memory buffer */ 511 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 512 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 513 514 return 0; 515 } 516 517 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 518 uint64_t *output_ptr) 519 { 520 int ret; 521 struct psp_gfx_cmd_resp *cmd; 522 523 if (!output_ptr) 524 return -EINVAL; 525 526 if (amdgpu_sriov_vf(psp->adev)) 527 return 0; 528 529 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 530 if (!cmd) 531 return -ENOMEM; 532 533 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 534 535 ret = psp_cmd_submit_buf(psp, NULL, cmd, 536 psp->fence_buf_mc_addr); 537 538 if (!ret) { 539 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 540 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 541 } 542 543 kfree(cmd); 544 545 return ret; 546 } 547 548 static int psp_boot_config_set(struct amdgpu_device *adev) 549 { 550 struct psp_context *psp = &adev->psp; 551 struct psp_gfx_cmd_resp *cmd = psp->cmd; 552 553 if (amdgpu_sriov_vf(adev)) 554 return 0; 555 556 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 557 558 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 559 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 560 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 561 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 562 563 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 564 } 565 566 static int psp_rl_load(struct amdgpu_device *adev) 567 { 568 struct psp_context *psp = &adev->psp; 569 struct psp_gfx_cmd_resp *cmd = psp->cmd; 570 571 if (psp->rl_bin_size == 0) 572 return 0; 573 574 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 575 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 576 577 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 578 579 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 580 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 581 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 582 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 583 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 584 585 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 586 } 587 588 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 589 uint64_t asd_mc, uint32_t size) 590 { 591 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 592 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 593 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 594 cmd->cmd.cmd_load_ta.app_len = size; 595 596 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 597 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 598 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 599 } 600 601 static int psp_asd_load(struct psp_context *psp) 602 { 603 int ret; 604 struct psp_gfx_cmd_resp *cmd; 605 606 /* If PSP version doesn't match ASD version, asd loading will be failed. 607 * add workaround to bypass it for sriov now. 608 * TODO: add version check to make it common 609 */ 610 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 611 return 0; 612 613 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 614 if (!cmd) 615 return -ENOMEM; 616 617 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 618 619 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 620 psp->asd_ucode_size); 621 622 ret = psp_cmd_submit_buf(psp, NULL, cmd, 623 psp->fence_buf_mc_addr); 624 if (!ret) { 625 psp->asd_context.asd_initialized = true; 626 psp->asd_context.session_id = cmd->resp.session_id; 627 } 628 629 kfree(cmd); 630 631 return ret; 632 } 633 634 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 635 uint32_t session_id) 636 { 637 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 638 cmd->cmd.cmd_unload_ta.session_id = session_id; 639 } 640 641 static int psp_asd_unload(struct psp_context *psp) 642 { 643 int ret; 644 struct psp_gfx_cmd_resp *cmd; 645 646 if (amdgpu_sriov_vf(psp->adev)) 647 return 0; 648 649 if (!psp->asd_context.asd_initialized) 650 return 0; 651 652 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 653 if (!cmd) 654 return -ENOMEM; 655 656 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 657 658 ret = psp_cmd_submit_buf(psp, NULL, cmd, 659 psp->fence_buf_mc_addr); 660 if (!ret) 661 psp->asd_context.asd_initialized = false; 662 663 kfree(cmd); 664 665 return ret; 666 } 667 668 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 669 uint32_t id, uint32_t value) 670 { 671 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 672 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 673 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 674 } 675 676 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 677 uint32_t value) 678 { 679 struct psp_gfx_cmd_resp *cmd = NULL; 680 int ret = 0; 681 682 if (reg >= PSP_REG_LAST) 683 return -EINVAL; 684 685 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 686 if (!cmd) 687 return -ENOMEM; 688 689 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 690 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 691 692 kfree(cmd); 693 return ret; 694 } 695 696 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 697 uint64_t ta_bin_mc, 698 uint32_t ta_bin_size, 699 uint64_t ta_shared_mc, 700 uint32_t ta_shared_size) 701 { 702 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 703 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 704 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 705 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 706 707 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 708 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 709 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 710 } 711 712 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 713 { 714 int ret; 715 716 /* 717 * Allocate 16k memory aligned to 4k from Frame Buffer (local 718 * physical) for xgmi ta <-> Driver 719 */ 720 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 721 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 722 &psp->xgmi_context.xgmi_shared_bo, 723 &psp->xgmi_context.xgmi_shared_mc_addr, 724 &psp->xgmi_context.xgmi_shared_buf); 725 726 return ret; 727 } 728 729 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 730 uint32_t ta_cmd_id, 731 uint32_t session_id) 732 { 733 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 734 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 735 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 736 } 737 738 static int psp_ta_invoke(struct psp_context *psp, 739 uint32_t ta_cmd_id, 740 uint32_t session_id) 741 { 742 int ret; 743 struct psp_gfx_cmd_resp *cmd; 744 745 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 746 if (!cmd) 747 return -ENOMEM; 748 749 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 750 751 ret = psp_cmd_submit_buf(psp, NULL, cmd, 752 psp->fence_buf_mc_addr); 753 754 kfree(cmd); 755 756 return ret; 757 } 758 759 static int psp_xgmi_load(struct psp_context *psp) 760 { 761 int ret; 762 struct psp_gfx_cmd_resp *cmd; 763 764 /* 765 * TODO: bypass the loading in sriov for now 766 */ 767 768 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 769 if (!cmd) 770 return -ENOMEM; 771 772 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 773 774 psp_prep_ta_load_cmd_buf(cmd, 775 psp->fw_pri_mc_addr, 776 psp->ta_xgmi_ucode_size, 777 psp->xgmi_context.xgmi_shared_mc_addr, 778 PSP_XGMI_SHARED_MEM_SIZE); 779 780 ret = psp_cmd_submit_buf(psp, NULL, cmd, 781 psp->fence_buf_mc_addr); 782 783 if (!ret) { 784 psp->xgmi_context.initialized = 1; 785 psp->xgmi_context.session_id = cmd->resp.session_id; 786 } 787 788 kfree(cmd); 789 790 return ret; 791 } 792 793 static int psp_xgmi_unload(struct psp_context *psp) 794 { 795 int ret; 796 struct psp_gfx_cmd_resp *cmd; 797 struct amdgpu_device *adev = psp->adev; 798 799 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 800 if (adev->asic_type == CHIP_ARCTURUS || 801 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 802 return 0; 803 804 /* 805 * TODO: bypass the unloading in sriov for now 806 */ 807 808 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 809 if (!cmd) 810 return -ENOMEM; 811 812 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 813 814 ret = psp_cmd_submit_buf(psp, NULL, cmd, 815 psp->fence_buf_mc_addr); 816 817 kfree(cmd); 818 819 return ret; 820 } 821 822 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 823 { 824 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 825 } 826 827 int psp_xgmi_terminate(struct psp_context *psp) 828 { 829 int ret; 830 831 if (!psp->xgmi_context.initialized) 832 return 0; 833 834 ret = psp_xgmi_unload(psp); 835 if (ret) 836 return ret; 837 838 psp->xgmi_context.initialized = 0; 839 840 /* free xgmi shared memory */ 841 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 842 &psp->xgmi_context.xgmi_shared_mc_addr, 843 &psp->xgmi_context.xgmi_shared_buf); 844 845 return 0; 846 } 847 848 int psp_xgmi_initialize(struct psp_context *psp) 849 { 850 struct ta_xgmi_shared_memory *xgmi_cmd; 851 int ret; 852 853 if (!psp->adev->psp.ta_fw || 854 !psp->adev->psp.ta_xgmi_ucode_size || 855 !psp->adev->psp.ta_xgmi_start_addr) 856 return -ENOENT; 857 858 if (!psp->xgmi_context.initialized) { 859 ret = psp_xgmi_init_shared_buf(psp); 860 if (ret) 861 return ret; 862 } 863 864 /* Load XGMI TA */ 865 ret = psp_xgmi_load(psp); 866 if (ret) 867 return ret; 868 869 /* Initialize XGMI session */ 870 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 871 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 872 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 873 874 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 875 876 return ret; 877 } 878 879 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 880 { 881 struct ta_xgmi_shared_memory *xgmi_cmd; 882 int ret; 883 884 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 885 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 886 887 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 888 889 /* Invoke xgmi ta to get hive id */ 890 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 891 if (ret) 892 return ret; 893 894 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 895 896 return 0; 897 } 898 899 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 900 { 901 struct ta_xgmi_shared_memory *xgmi_cmd; 902 int ret; 903 904 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 905 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 906 907 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 908 909 /* Invoke xgmi ta to get the node id */ 910 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 911 if (ret) 912 return ret; 913 914 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 915 916 return 0; 917 } 918 919 int psp_xgmi_get_topology_info(struct psp_context *psp, 920 int number_devices, 921 struct psp_xgmi_topology_info *topology) 922 { 923 struct ta_xgmi_shared_memory *xgmi_cmd; 924 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 925 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 926 int i; 927 int ret; 928 929 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 930 return -EINVAL; 931 932 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 933 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 934 935 /* Fill in the shared memory with topology information as input */ 936 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 937 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 938 topology_info_input->num_nodes = number_devices; 939 940 for (i = 0; i < topology_info_input->num_nodes; i++) { 941 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 942 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 943 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 944 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 945 } 946 947 /* Invoke xgmi ta to get the topology information */ 948 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 949 if (ret) 950 return ret; 951 952 /* Read the output topology information from the shared memory */ 953 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 954 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 955 for (i = 0; i < topology->num_nodes; i++) { 956 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 957 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 958 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 959 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 960 } 961 962 return 0; 963 } 964 965 int psp_xgmi_set_topology_info(struct psp_context *psp, 966 int number_devices, 967 struct psp_xgmi_topology_info *topology) 968 { 969 struct ta_xgmi_shared_memory *xgmi_cmd; 970 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 971 int i; 972 973 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 974 return -EINVAL; 975 976 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 977 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 978 979 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 980 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 981 topology_info_input->num_nodes = number_devices; 982 983 for (i = 0; i < topology_info_input->num_nodes; i++) { 984 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 985 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 986 topology_info_input->nodes[i].is_sharing_enabled = 1; 987 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 988 } 989 990 /* Invoke xgmi ta to set topology information */ 991 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 992 } 993 994 // ras begin 995 static int psp_ras_init_shared_buf(struct psp_context *psp) 996 { 997 int ret; 998 999 /* 1000 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1001 * physical) for ras ta <-> Driver 1002 */ 1003 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1004 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1005 &psp->ras.ras_shared_bo, 1006 &psp->ras.ras_shared_mc_addr, 1007 &psp->ras.ras_shared_buf); 1008 1009 return ret; 1010 } 1011 1012 static int psp_ras_load(struct psp_context *psp) 1013 { 1014 int ret; 1015 struct psp_gfx_cmd_resp *cmd; 1016 struct ta_ras_shared_memory *ras_cmd; 1017 1018 /* 1019 * TODO: bypass the loading in sriov for now 1020 */ 1021 if (amdgpu_sriov_vf(psp->adev)) 1022 return 0; 1023 1024 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1025 if (!cmd) 1026 return -ENOMEM; 1027 1028 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1029 1030 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1031 1032 if (psp->adev->gmc.xgmi.connected_to_cpu) 1033 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1034 else 1035 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1036 1037 psp_prep_ta_load_cmd_buf(cmd, 1038 psp->fw_pri_mc_addr, 1039 psp->ta_ras_ucode_size, 1040 psp->ras.ras_shared_mc_addr, 1041 PSP_RAS_SHARED_MEM_SIZE); 1042 1043 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1044 psp->fence_buf_mc_addr); 1045 1046 if (!ret) { 1047 psp->ras.session_id = cmd->resp.session_id; 1048 1049 if (!ras_cmd->ras_status) 1050 psp->ras.ras_initialized = true; 1051 else 1052 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1053 } 1054 1055 if (ret || ras_cmd->ras_status) 1056 amdgpu_ras_fini(psp->adev); 1057 1058 kfree(cmd); 1059 1060 return ret; 1061 } 1062 1063 static int psp_ras_unload(struct psp_context *psp) 1064 { 1065 int ret; 1066 struct psp_gfx_cmd_resp *cmd; 1067 1068 /* 1069 * TODO: bypass the unloading in sriov for now 1070 */ 1071 if (amdgpu_sriov_vf(psp->adev)) 1072 return 0; 1073 1074 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1075 if (!cmd) 1076 return -ENOMEM; 1077 1078 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1079 1080 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1081 psp->fence_buf_mc_addr); 1082 1083 kfree(cmd); 1084 1085 return ret; 1086 } 1087 1088 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1089 { 1090 struct ta_ras_shared_memory *ras_cmd; 1091 int ret; 1092 1093 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1094 1095 /* 1096 * TODO: bypass the loading in sriov for now 1097 */ 1098 if (amdgpu_sriov_vf(psp->adev)) 1099 return 0; 1100 1101 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1102 1103 if (amdgpu_ras_intr_triggered()) 1104 return ret; 1105 1106 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1107 { 1108 DRM_WARN("RAS: Unsupported Interface"); 1109 return -EINVAL; 1110 } 1111 1112 if (!ret) { 1113 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1114 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1115 1116 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1117 } 1118 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1119 dev_warn(psp->adev->dev, 1120 "RAS internal register access blocked\n"); 1121 } 1122 1123 return ret; 1124 } 1125 1126 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1127 enum ta_ras_status ras_status) 1128 { 1129 int ret = -EINVAL; 1130 1131 switch (ras_status) { 1132 case TA_RAS_STATUS__SUCCESS: 1133 ret = 0; 1134 break; 1135 case TA_RAS_STATUS__RESET_NEEDED: 1136 ret = -EAGAIN; 1137 break; 1138 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1139 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1140 break; 1141 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1142 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1143 break; 1144 default: 1145 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1146 } 1147 1148 return ret; 1149 } 1150 1151 int psp_ras_enable_features(struct psp_context *psp, 1152 union ta_ras_cmd_input *info, bool enable) 1153 { 1154 struct ta_ras_shared_memory *ras_cmd; 1155 int ret; 1156 1157 if (!psp->ras.ras_initialized) 1158 return -EINVAL; 1159 1160 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1161 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1162 1163 if (enable) 1164 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1165 else 1166 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1167 1168 ras_cmd->ras_in_message = *info; 1169 1170 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1171 if (ret) 1172 return -EINVAL; 1173 1174 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1175 } 1176 1177 static int psp_ras_terminate(struct psp_context *psp) 1178 { 1179 int ret; 1180 1181 /* 1182 * TODO: bypass the terminate in sriov for now 1183 */ 1184 if (amdgpu_sriov_vf(psp->adev)) 1185 return 0; 1186 1187 if (!psp->ras.ras_initialized) 1188 return 0; 1189 1190 ret = psp_ras_unload(psp); 1191 if (ret) 1192 return ret; 1193 1194 psp->ras.ras_initialized = false; 1195 1196 /* free ras shared memory */ 1197 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1198 &psp->ras.ras_shared_mc_addr, 1199 &psp->ras.ras_shared_buf); 1200 1201 return 0; 1202 } 1203 1204 static int psp_ras_initialize(struct psp_context *psp) 1205 { 1206 int ret; 1207 1208 /* 1209 * TODO: bypass the initialize in sriov for now 1210 */ 1211 if (amdgpu_sriov_vf(psp->adev)) 1212 return 0; 1213 1214 if (!psp->adev->psp.ta_ras_ucode_size || 1215 !psp->adev->psp.ta_ras_start_addr) { 1216 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1217 return 0; 1218 } 1219 1220 if (!psp->ras.ras_initialized) { 1221 ret = psp_ras_init_shared_buf(psp); 1222 if (ret) 1223 return ret; 1224 } 1225 1226 ret = psp_ras_load(psp); 1227 if (ret) 1228 return ret; 1229 1230 return 0; 1231 } 1232 1233 int psp_ras_trigger_error(struct psp_context *psp, 1234 struct ta_ras_trigger_error_input *info) 1235 { 1236 struct ta_ras_shared_memory *ras_cmd; 1237 int ret; 1238 1239 if (!psp->ras.ras_initialized) 1240 return -EINVAL; 1241 1242 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1243 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1244 1245 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1246 ras_cmd->ras_in_message.trigger_error = *info; 1247 1248 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1249 if (ret) 1250 return -EINVAL; 1251 1252 /* If err_event_athub occurs error inject was successful, however 1253 return status from TA is no long reliable */ 1254 if (amdgpu_ras_intr_triggered()) 1255 return 0; 1256 1257 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1258 } 1259 // ras end 1260 1261 // HDCP start 1262 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1263 { 1264 int ret; 1265 1266 /* 1267 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1268 * physical) for hdcp ta <-> Driver 1269 */ 1270 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1271 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1272 &psp->hdcp_context.hdcp_shared_bo, 1273 &psp->hdcp_context.hdcp_shared_mc_addr, 1274 &psp->hdcp_context.hdcp_shared_buf); 1275 1276 return ret; 1277 } 1278 1279 static int psp_hdcp_load(struct psp_context *psp) 1280 { 1281 int ret; 1282 struct psp_gfx_cmd_resp *cmd; 1283 1284 /* 1285 * TODO: bypass the loading in sriov for now 1286 */ 1287 if (amdgpu_sriov_vf(psp->adev)) 1288 return 0; 1289 1290 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1291 if (!cmd) 1292 return -ENOMEM; 1293 1294 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1295 psp->ta_hdcp_ucode_size); 1296 1297 psp_prep_ta_load_cmd_buf(cmd, 1298 psp->fw_pri_mc_addr, 1299 psp->ta_hdcp_ucode_size, 1300 psp->hdcp_context.hdcp_shared_mc_addr, 1301 PSP_HDCP_SHARED_MEM_SIZE); 1302 1303 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1304 1305 if (!ret) { 1306 psp->hdcp_context.hdcp_initialized = true; 1307 psp->hdcp_context.session_id = cmd->resp.session_id; 1308 mutex_init(&psp->hdcp_context.mutex); 1309 } 1310 1311 kfree(cmd); 1312 1313 return ret; 1314 } 1315 static int psp_hdcp_initialize(struct psp_context *psp) 1316 { 1317 int ret; 1318 1319 /* 1320 * TODO: bypass the initialize in sriov for now 1321 */ 1322 if (amdgpu_sriov_vf(psp->adev)) 1323 return 0; 1324 1325 if (!psp->adev->psp.ta_hdcp_ucode_size || 1326 !psp->adev->psp.ta_hdcp_start_addr) { 1327 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1328 return 0; 1329 } 1330 1331 if (!psp->hdcp_context.hdcp_initialized) { 1332 ret = psp_hdcp_init_shared_buf(psp); 1333 if (ret) 1334 return ret; 1335 } 1336 1337 ret = psp_hdcp_load(psp); 1338 if (ret) 1339 return ret; 1340 1341 return 0; 1342 } 1343 1344 static int psp_hdcp_unload(struct psp_context *psp) 1345 { 1346 int ret; 1347 struct psp_gfx_cmd_resp *cmd; 1348 1349 /* 1350 * TODO: bypass the unloading in sriov for now 1351 */ 1352 if (amdgpu_sriov_vf(psp->adev)) 1353 return 0; 1354 1355 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1356 if (!cmd) 1357 return -ENOMEM; 1358 1359 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1360 1361 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1362 1363 kfree(cmd); 1364 1365 return ret; 1366 } 1367 1368 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1369 { 1370 /* 1371 * TODO: bypass the loading in sriov for now 1372 */ 1373 if (amdgpu_sriov_vf(psp->adev)) 1374 return 0; 1375 1376 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1377 } 1378 1379 static int psp_hdcp_terminate(struct psp_context *psp) 1380 { 1381 int ret; 1382 1383 /* 1384 * TODO: bypass the terminate in sriov for now 1385 */ 1386 if (amdgpu_sriov_vf(psp->adev)) 1387 return 0; 1388 1389 if (!psp->hdcp_context.hdcp_initialized) { 1390 if (psp->hdcp_context.hdcp_shared_buf) 1391 goto out; 1392 else 1393 return 0; 1394 } 1395 1396 ret = psp_hdcp_unload(psp); 1397 if (ret) 1398 return ret; 1399 1400 psp->hdcp_context.hdcp_initialized = false; 1401 1402 out: 1403 /* free hdcp shared memory */ 1404 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1405 &psp->hdcp_context.hdcp_shared_mc_addr, 1406 &psp->hdcp_context.hdcp_shared_buf); 1407 1408 return 0; 1409 } 1410 // HDCP end 1411 1412 // DTM start 1413 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1414 { 1415 int ret; 1416 1417 /* 1418 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1419 * physical) for dtm ta <-> Driver 1420 */ 1421 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1422 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1423 &psp->dtm_context.dtm_shared_bo, 1424 &psp->dtm_context.dtm_shared_mc_addr, 1425 &psp->dtm_context.dtm_shared_buf); 1426 1427 return ret; 1428 } 1429 1430 static int psp_dtm_load(struct psp_context *psp) 1431 { 1432 int ret; 1433 struct psp_gfx_cmd_resp *cmd; 1434 1435 /* 1436 * TODO: bypass the loading in sriov for now 1437 */ 1438 if (amdgpu_sriov_vf(psp->adev)) 1439 return 0; 1440 1441 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1442 if (!cmd) 1443 return -ENOMEM; 1444 1445 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1446 1447 psp_prep_ta_load_cmd_buf(cmd, 1448 psp->fw_pri_mc_addr, 1449 psp->ta_dtm_ucode_size, 1450 psp->dtm_context.dtm_shared_mc_addr, 1451 PSP_DTM_SHARED_MEM_SIZE); 1452 1453 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1454 1455 if (!ret) { 1456 psp->dtm_context.dtm_initialized = true; 1457 psp->dtm_context.session_id = cmd->resp.session_id; 1458 mutex_init(&psp->dtm_context.mutex); 1459 } 1460 1461 kfree(cmd); 1462 1463 return ret; 1464 } 1465 1466 static int psp_dtm_initialize(struct psp_context *psp) 1467 { 1468 int ret; 1469 1470 /* 1471 * TODO: bypass the initialize in sriov for now 1472 */ 1473 if (amdgpu_sriov_vf(psp->adev)) 1474 return 0; 1475 1476 if (!psp->adev->psp.ta_dtm_ucode_size || 1477 !psp->adev->psp.ta_dtm_start_addr) { 1478 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1479 return 0; 1480 } 1481 1482 if (!psp->dtm_context.dtm_initialized) { 1483 ret = psp_dtm_init_shared_buf(psp); 1484 if (ret) 1485 return ret; 1486 } 1487 1488 ret = psp_dtm_load(psp); 1489 if (ret) 1490 return ret; 1491 1492 return 0; 1493 } 1494 1495 static int psp_dtm_unload(struct psp_context *psp) 1496 { 1497 int ret; 1498 struct psp_gfx_cmd_resp *cmd; 1499 1500 /* 1501 * TODO: bypass the unloading in sriov for now 1502 */ 1503 if (amdgpu_sriov_vf(psp->adev)) 1504 return 0; 1505 1506 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1507 if (!cmd) 1508 return -ENOMEM; 1509 1510 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1511 1512 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1513 1514 kfree(cmd); 1515 1516 return ret; 1517 } 1518 1519 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1520 { 1521 /* 1522 * TODO: bypass the loading in sriov for now 1523 */ 1524 if (amdgpu_sriov_vf(psp->adev)) 1525 return 0; 1526 1527 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1528 } 1529 1530 static int psp_dtm_terminate(struct psp_context *psp) 1531 { 1532 int ret; 1533 1534 /* 1535 * TODO: bypass the terminate in sriov for now 1536 */ 1537 if (amdgpu_sriov_vf(psp->adev)) 1538 return 0; 1539 1540 if (!psp->dtm_context.dtm_initialized) { 1541 if (psp->dtm_context.dtm_shared_buf) 1542 goto out; 1543 else 1544 return 0; 1545 } 1546 1547 ret = psp_dtm_unload(psp); 1548 if (ret) 1549 return ret; 1550 1551 psp->dtm_context.dtm_initialized = false; 1552 1553 out: 1554 /* free hdcp shared memory */ 1555 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1556 &psp->dtm_context.dtm_shared_mc_addr, 1557 &psp->dtm_context.dtm_shared_buf); 1558 1559 return 0; 1560 } 1561 // DTM end 1562 1563 // RAP start 1564 static int psp_rap_init_shared_buf(struct psp_context *psp) 1565 { 1566 int ret; 1567 1568 /* 1569 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1570 * physical) for rap ta <-> Driver 1571 */ 1572 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1573 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1574 &psp->rap_context.rap_shared_bo, 1575 &psp->rap_context.rap_shared_mc_addr, 1576 &psp->rap_context.rap_shared_buf); 1577 1578 return ret; 1579 } 1580 1581 static int psp_rap_load(struct psp_context *psp) 1582 { 1583 int ret; 1584 struct psp_gfx_cmd_resp *cmd; 1585 1586 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1587 if (!cmd) 1588 return -ENOMEM; 1589 1590 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1591 1592 psp_prep_ta_load_cmd_buf(cmd, 1593 psp->fw_pri_mc_addr, 1594 psp->ta_rap_ucode_size, 1595 psp->rap_context.rap_shared_mc_addr, 1596 PSP_RAP_SHARED_MEM_SIZE); 1597 1598 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1599 1600 if (!ret) { 1601 psp->rap_context.rap_initialized = true; 1602 psp->rap_context.session_id = cmd->resp.session_id; 1603 mutex_init(&psp->rap_context.mutex); 1604 } 1605 1606 kfree(cmd); 1607 1608 return ret; 1609 } 1610 1611 static int psp_rap_unload(struct psp_context *psp) 1612 { 1613 int ret; 1614 struct psp_gfx_cmd_resp *cmd; 1615 1616 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1617 if (!cmd) 1618 return -ENOMEM; 1619 1620 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1621 1622 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1623 1624 kfree(cmd); 1625 1626 return ret; 1627 } 1628 1629 static int psp_rap_initialize(struct psp_context *psp) 1630 { 1631 int ret; 1632 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1633 1634 /* 1635 * TODO: bypass the initialize in sriov for now 1636 */ 1637 if (amdgpu_sriov_vf(psp->adev)) 1638 return 0; 1639 1640 if (!psp->adev->psp.ta_rap_ucode_size || 1641 !psp->adev->psp.ta_rap_start_addr) { 1642 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1643 return 0; 1644 } 1645 1646 if (!psp->rap_context.rap_initialized) { 1647 ret = psp_rap_init_shared_buf(psp); 1648 if (ret) 1649 return ret; 1650 } 1651 1652 ret = psp_rap_load(psp); 1653 if (ret) 1654 return ret; 1655 1656 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1657 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1658 psp_rap_unload(psp); 1659 1660 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1661 &psp->rap_context.rap_shared_mc_addr, 1662 &psp->rap_context.rap_shared_buf); 1663 1664 psp->rap_context.rap_initialized = false; 1665 1666 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1667 ret, status); 1668 1669 return ret; 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int psp_rap_terminate(struct psp_context *psp) 1676 { 1677 int ret; 1678 1679 if (!psp->rap_context.rap_initialized) 1680 return 0; 1681 1682 ret = psp_rap_unload(psp); 1683 1684 psp->rap_context.rap_initialized = false; 1685 1686 /* free rap shared memory */ 1687 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1688 &psp->rap_context.rap_shared_mc_addr, 1689 &psp->rap_context.rap_shared_buf); 1690 1691 return ret; 1692 } 1693 1694 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1695 { 1696 struct ta_rap_shared_memory *rap_cmd; 1697 int ret = 0; 1698 1699 if (!psp->rap_context.rap_initialized) 1700 return 0; 1701 1702 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1703 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1704 return -EINVAL; 1705 1706 mutex_lock(&psp->rap_context.mutex); 1707 1708 rap_cmd = (struct ta_rap_shared_memory *) 1709 psp->rap_context.rap_shared_buf; 1710 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1711 1712 rap_cmd->cmd_id = ta_cmd_id; 1713 rap_cmd->validation_method_id = METHOD_A; 1714 1715 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1716 if (ret) 1717 goto out_unlock; 1718 1719 if (status) 1720 *status = rap_cmd->rap_status; 1721 1722 out_unlock: 1723 mutex_unlock(&psp->rap_context.mutex); 1724 1725 return ret; 1726 } 1727 // RAP end 1728 1729 /* securedisplay start */ 1730 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1731 { 1732 int ret; 1733 1734 /* 1735 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1736 * physical) for sa ta <-> Driver 1737 */ 1738 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1739 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1740 &psp->securedisplay_context.securedisplay_shared_bo, 1741 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1742 &psp->securedisplay_context.securedisplay_shared_buf); 1743 1744 return ret; 1745 } 1746 1747 static int psp_securedisplay_load(struct psp_context *psp) 1748 { 1749 int ret; 1750 struct psp_gfx_cmd_resp *cmd; 1751 1752 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1753 if (!cmd) 1754 return -ENOMEM; 1755 1756 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1757 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1758 1759 psp_prep_ta_load_cmd_buf(cmd, 1760 psp->fw_pri_mc_addr, 1761 psp->ta_securedisplay_ucode_size, 1762 psp->securedisplay_context.securedisplay_shared_mc_addr, 1763 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1764 1765 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1766 1767 if (ret) 1768 goto failed; 1769 1770 psp->securedisplay_context.securedisplay_initialized = true; 1771 psp->securedisplay_context.session_id = cmd->resp.session_id; 1772 mutex_init(&psp->securedisplay_context.mutex); 1773 1774 failed: 1775 kfree(cmd); 1776 return ret; 1777 } 1778 1779 static int psp_securedisplay_unload(struct psp_context *psp) 1780 { 1781 int ret; 1782 struct psp_gfx_cmd_resp *cmd; 1783 1784 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1785 if (!cmd) 1786 return -ENOMEM; 1787 1788 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1789 1790 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1791 1792 kfree(cmd); 1793 1794 return ret; 1795 } 1796 1797 static int psp_securedisplay_initialize(struct psp_context *psp) 1798 { 1799 int ret; 1800 struct securedisplay_cmd *securedisplay_cmd; 1801 1802 /* 1803 * TODO: bypass the initialize in sriov for now 1804 */ 1805 if (amdgpu_sriov_vf(psp->adev)) 1806 return 0; 1807 1808 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1809 !psp->adev->psp.ta_securedisplay_start_addr) { 1810 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1811 return 0; 1812 } 1813 1814 if (!psp->securedisplay_context.securedisplay_initialized) { 1815 ret = psp_securedisplay_init_shared_buf(psp); 1816 if (ret) 1817 return ret; 1818 } 1819 1820 ret = psp_securedisplay_load(psp); 1821 if (ret) 1822 return ret; 1823 1824 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1825 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1826 1827 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1828 if (ret) { 1829 psp_securedisplay_unload(psp); 1830 1831 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1832 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1833 &psp->securedisplay_context.securedisplay_shared_buf); 1834 1835 psp->securedisplay_context.securedisplay_initialized = false; 1836 1837 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1838 return -EINVAL; 1839 } 1840 1841 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1842 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1843 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1844 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1845 } 1846 1847 return 0; 1848 } 1849 1850 static int psp_securedisplay_terminate(struct psp_context *psp) 1851 { 1852 int ret; 1853 1854 /* 1855 * TODO:bypass the terminate in sriov for now 1856 */ 1857 if (amdgpu_sriov_vf(psp->adev)) 1858 return 0; 1859 1860 if (!psp->securedisplay_context.securedisplay_initialized) 1861 return 0; 1862 1863 ret = psp_securedisplay_unload(psp); 1864 if (ret) 1865 return ret; 1866 1867 psp->securedisplay_context.securedisplay_initialized = false; 1868 1869 /* free securedisplay shared memory */ 1870 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1871 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1872 &psp->securedisplay_context.securedisplay_shared_buf); 1873 1874 return ret; 1875 } 1876 1877 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1878 { 1879 int ret; 1880 1881 if (!psp->securedisplay_context.securedisplay_initialized) 1882 return -EINVAL; 1883 1884 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1885 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1886 return -EINVAL; 1887 1888 mutex_lock(&psp->securedisplay_context.mutex); 1889 1890 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1891 1892 mutex_unlock(&psp->securedisplay_context.mutex); 1893 1894 return ret; 1895 } 1896 /* SECUREDISPLAY end */ 1897 1898 static int psp_hw_start(struct psp_context *psp) 1899 { 1900 struct amdgpu_device *adev = psp->adev; 1901 int ret; 1902 1903 if (!amdgpu_sriov_vf(adev)) { 1904 if (psp->kdb_bin_size && 1905 (psp->funcs->bootloader_load_kdb != NULL)) { 1906 ret = psp_bootloader_load_kdb(psp); 1907 if (ret) { 1908 DRM_ERROR("PSP load kdb failed!\n"); 1909 return ret; 1910 } 1911 } 1912 1913 if (psp->spl_bin_size) { 1914 ret = psp_bootloader_load_spl(psp); 1915 if (ret) { 1916 DRM_ERROR("PSP load spl failed!\n"); 1917 return ret; 1918 } 1919 } 1920 1921 ret = psp_bootloader_load_sysdrv(psp); 1922 if (ret) { 1923 DRM_ERROR("PSP load sysdrv failed!\n"); 1924 return ret; 1925 } 1926 1927 ret = psp_bootloader_load_sos(psp); 1928 if (ret) { 1929 DRM_ERROR("PSP load sos failed!\n"); 1930 return ret; 1931 } 1932 } 1933 1934 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1935 if (ret) { 1936 DRM_ERROR("PSP create ring failed!\n"); 1937 return ret; 1938 } 1939 1940 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1941 ret = psp_boot_config_set(adev); 1942 if (ret) 1943 dev_warn(adev->dev, "PSP set boot config failed\n"); 1944 } 1945 1946 ret = psp_tmr_init(psp); 1947 if (ret) { 1948 DRM_ERROR("PSP tmr init failed!\n"); 1949 return ret; 1950 } 1951 1952 /* 1953 * For ASICs with DF Cstate management centralized 1954 * to PMFW, TMR setup should be performed after PMFW 1955 * loaded and before other non-psp firmware loaded. 1956 */ 1957 if (psp->pmfw_centralized_cstate_management) { 1958 ret = psp_load_smu_fw(psp); 1959 if (ret) 1960 return ret; 1961 } 1962 1963 ret = psp_tmr_load(psp); 1964 if (ret) { 1965 DRM_ERROR("PSP load tmr failed!\n"); 1966 return ret; 1967 } 1968 1969 return 0; 1970 } 1971 1972 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1973 enum psp_gfx_fw_type *type) 1974 { 1975 switch (ucode->ucode_id) { 1976 case AMDGPU_UCODE_ID_SDMA0: 1977 *type = GFX_FW_TYPE_SDMA0; 1978 break; 1979 case AMDGPU_UCODE_ID_SDMA1: 1980 *type = GFX_FW_TYPE_SDMA1; 1981 break; 1982 case AMDGPU_UCODE_ID_SDMA2: 1983 *type = GFX_FW_TYPE_SDMA2; 1984 break; 1985 case AMDGPU_UCODE_ID_SDMA3: 1986 *type = GFX_FW_TYPE_SDMA3; 1987 break; 1988 case AMDGPU_UCODE_ID_SDMA4: 1989 *type = GFX_FW_TYPE_SDMA4; 1990 break; 1991 case AMDGPU_UCODE_ID_SDMA5: 1992 *type = GFX_FW_TYPE_SDMA5; 1993 break; 1994 case AMDGPU_UCODE_ID_SDMA6: 1995 *type = GFX_FW_TYPE_SDMA6; 1996 break; 1997 case AMDGPU_UCODE_ID_SDMA7: 1998 *type = GFX_FW_TYPE_SDMA7; 1999 break; 2000 case AMDGPU_UCODE_ID_CP_MES: 2001 *type = GFX_FW_TYPE_CP_MES; 2002 break; 2003 case AMDGPU_UCODE_ID_CP_MES_DATA: 2004 *type = GFX_FW_TYPE_MES_STACK; 2005 break; 2006 case AMDGPU_UCODE_ID_CP_CE: 2007 *type = GFX_FW_TYPE_CP_CE; 2008 break; 2009 case AMDGPU_UCODE_ID_CP_PFP: 2010 *type = GFX_FW_TYPE_CP_PFP; 2011 break; 2012 case AMDGPU_UCODE_ID_CP_ME: 2013 *type = GFX_FW_TYPE_CP_ME; 2014 break; 2015 case AMDGPU_UCODE_ID_CP_MEC1: 2016 *type = GFX_FW_TYPE_CP_MEC; 2017 break; 2018 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2019 *type = GFX_FW_TYPE_CP_MEC_ME1; 2020 break; 2021 case AMDGPU_UCODE_ID_CP_MEC2: 2022 *type = GFX_FW_TYPE_CP_MEC; 2023 break; 2024 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2025 *type = GFX_FW_TYPE_CP_MEC_ME2; 2026 break; 2027 case AMDGPU_UCODE_ID_RLC_G: 2028 *type = GFX_FW_TYPE_RLC_G; 2029 break; 2030 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2031 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2032 break; 2033 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2034 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2035 break; 2036 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2037 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2038 break; 2039 case AMDGPU_UCODE_ID_RLC_IRAM: 2040 *type = GFX_FW_TYPE_RLC_IRAM; 2041 break; 2042 case AMDGPU_UCODE_ID_RLC_DRAM: 2043 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2044 break; 2045 case AMDGPU_UCODE_ID_SMC: 2046 *type = GFX_FW_TYPE_SMU; 2047 break; 2048 case AMDGPU_UCODE_ID_UVD: 2049 *type = GFX_FW_TYPE_UVD; 2050 break; 2051 case AMDGPU_UCODE_ID_UVD1: 2052 *type = GFX_FW_TYPE_UVD1; 2053 break; 2054 case AMDGPU_UCODE_ID_VCE: 2055 *type = GFX_FW_TYPE_VCE; 2056 break; 2057 case AMDGPU_UCODE_ID_VCN: 2058 *type = GFX_FW_TYPE_VCN; 2059 break; 2060 case AMDGPU_UCODE_ID_VCN1: 2061 *type = GFX_FW_TYPE_VCN1; 2062 break; 2063 case AMDGPU_UCODE_ID_DMCU_ERAM: 2064 *type = GFX_FW_TYPE_DMCU_ERAM; 2065 break; 2066 case AMDGPU_UCODE_ID_DMCU_INTV: 2067 *type = GFX_FW_TYPE_DMCU_ISR; 2068 break; 2069 case AMDGPU_UCODE_ID_VCN0_RAM: 2070 *type = GFX_FW_TYPE_VCN0_RAM; 2071 break; 2072 case AMDGPU_UCODE_ID_VCN1_RAM: 2073 *type = GFX_FW_TYPE_VCN1_RAM; 2074 break; 2075 case AMDGPU_UCODE_ID_DMCUB: 2076 *type = GFX_FW_TYPE_DMUB; 2077 break; 2078 case AMDGPU_UCODE_ID_MAXIMUM: 2079 default: 2080 return -EINVAL; 2081 } 2082 2083 return 0; 2084 } 2085 2086 static void psp_print_fw_hdr(struct psp_context *psp, 2087 struct amdgpu_firmware_info *ucode) 2088 { 2089 struct amdgpu_device *adev = psp->adev; 2090 struct common_firmware_header *hdr; 2091 2092 switch (ucode->ucode_id) { 2093 case AMDGPU_UCODE_ID_SDMA0: 2094 case AMDGPU_UCODE_ID_SDMA1: 2095 case AMDGPU_UCODE_ID_SDMA2: 2096 case AMDGPU_UCODE_ID_SDMA3: 2097 case AMDGPU_UCODE_ID_SDMA4: 2098 case AMDGPU_UCODE_ID_SDMA5: 2099 case AMDGPU_UCODE_ID_SDMA6: 2100 case AMDGPU_UCODE_ID_SDMA7: 2101 hdr = (struct common_firmware_header *) 2102 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2103 amdgpu_ucode_print_sdma_hdr(hdr); 2104 break; 2105 case AMDGPU_UCODE_ID_CP_CE: 2106 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2107 amdgpu_ucode_print_gfx_hdr(hdr); 2108 break; 2109 case AMDGPU_UCODE_ID_CP_PFP: 2110 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2111 amdgpu_ucode_print_gfx_hdr(hdr); 2112 break; 2113 case AMDGPU_UCODE_ID_CP_ME: 2114 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2115 amdgpu_ucode_print_gfx_hdr(hdr); 2116 break; 2117 case AMDGPU_UCODE_ID_CP_MEC1: 2118 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2119 amdgpu_ucode_print_gfx_hdr(hdr); 2120 break; 2121 case AMDGPU_UCODE_ID_RLC_G: 2122 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2123 amdgpu_ucode_print_rlc_hdr(hdr); 2124 break; 2125 case AMDGPU_UCODE_ID_SMC: 2126 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2127 amdgpu_ucode_print_smc_hdr(hdr); 2128 break; 2129 default: 2130 break; 2131 } 2132 } 2133 2134 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2135 struct psp_gfx_cmd_resp *cmd) 2136 { 2137 int ret; 2138 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2139 2140 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2141 2142 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2143 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2144 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2145 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2146 2147 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2148 if (ret) 2149 DRM_ERROR("Unknown firmware type\n"); 2150 2151 return ret; 2152 } 2153 2154 static int psp_execute_np_fw_load(struct psp_context *psp, 2155 struct amdgpu_firmware_info *ucode) 2156 { 2157 int ret = 0; 2158 2159 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2160 if (ret) 2161 return ret; 2162 2163 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2164 psp->fence_buf_mc_addr); 2165 2166 return ret; 2167 } 2168 2169 static int psp_load_smu_fw(struct psp_context *psp) 2170 { 2171 int ret; 2172 struct amdgpu_device *adev = psp->adev; 2173 struct amdgpu_firmware_info *ucode = 2174 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2175 struct amdgpu_ras *ras = psp->ras.ras; 2176 2177 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2178 return 0; 2179 2180 if ((amdgpu_in_reset(adev) && 2181 ras && adev->ras_enabled && 2182 (adev->asic_type == CHIP_ARCTURUS || 2183 adev->asic_type == CHIP_VEGA20)) || 2184 (adev->in_runpm && 2185 adev->asic_type >= CHIP_NAVI10 && 2186 adev->asic_type <= CHIP_NAVI12)) { 2187 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2188 if (ret) { 2189 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2190 } 2191 } 2192 2193 ret = psp_execute_np_fw_load(psp, ucode); 2194 2195 if (ret) 2196 DRM_ERROR("PSP load smu failed!\n"); 2197 2198 return ret; 2199 } 2200 2201 static bool fw_load_skip_check(struct psp_context *psp, 2202 struct amdgpu_firmware_info *ucode) 2203 { 2204 if (!ucode->fw) 2205 return true; 2206 2207 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2208 (psp_smu_reload_quirk(psp) || 2209 psp->autoload_supported || 2210 psp->pmfw_centralized_cstate_management)) 2211 return true; 2212 2213 if (amdgpu_sriov_vf(psp->adev) && 2214 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2215 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2216 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2217 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2218 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2219 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2220 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2221 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2222 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2223 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2224 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2225 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2226 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2227 /*skip ucode loading in SRIOV VF */ 2228 return true; 2229 2230 if (psp->autoload_supported && 2231 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2232 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2233 /* skip mec JT when autoload is enabled */ 2234 return true; 2235 2236 return false; 2237 } 2238 2239 int psp_load_fw_list(struct psp_context *psp, 2240 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2241 { 2242 int ret = 0, i; 2243 struct amdgpu_firmware_info *ucode; 2244 2245 for (i = 0; i < ucode_count; ++i) { 2246 ucode = ucode_list[i]; 2247 psp_print_fw_hdr(psp, ucode); 2248 ret = psp_execute_np_fw_load(psp, ucode); 2249 if (ret) 2250 return ret; 2251 } 2252 return ret; 2253 } 2254 2255 static int psp_np_fw_load(struct psp_context *psp) 2256 { 2257 int i, ret; 2258 struct amdgpu_firmware_info *ucode; 2259 struct amdgpu_device *adev = psp->adev; 2260 2261 if (psp->autoload_supported && 2262 !psp->pmfw_centralized_cstate_management) { 2263 ret = psp_load_smu_fw(psp); 2264 if (ret) 2265 return ret; 2266 } 2267 2268 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2269 ucode = &adev->firmware.ucode[i]; 2270 2271 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2272 !fw_load_skip_check(psp, ucode)) { 2273 ret = psp_load_smu_fw(psp); 2274 if (ret) 2275 return ret; 2276 continue; 2277 } 2278 2279 if (fw_load_skip_check(psp, ucode)) 2280 continue; 2281 2282 if (psp->autoload_supported && 2283 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2284 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2285 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2286 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2287 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2288 /* PSP only receive one SDMA fw for sienna_cichlid, 2289 * as all four sdma fw are same */ 2290 continue; 2291 2292 psp_print_fw_hdr(psp, ucode); 2293 2294 ret = psp_execute_np_fw_load(psp, ucode); 2295 if (ret) 2296 return ret; 2297 2298 /* Start rlc autoload after psp recieved all the gfx firmware */ 2299 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2300 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2301 ret = psp_rlc_autoload_start(psp); 2302 if (ret) { 2303 DRM_ERROR("Failed to start rlc autoload\n"); 2304 return ret; 2305 } 2306 } 2307 } 2308 2309 return 0; 2310 } 2311 2312 static int psp_load_fw(struct amdgpu_device *adev) 2313 { 2314 int ret; 2315 struct psp_context *psp = &adev->psp; 2316 2317 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2318 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2319 goto skip_memalloc; 2320 } 2321 2322 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2323 if (!psp->cmd) 2324 return -ENOMEM; 2325 2326 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2327 AMDGPU_GEM_DOMAIN_GTT, 2328 &psp->fw_pri_bo, 2329 &psp->fw_pri_mc_addr, 2330 &psp->fw_pri_buf); 2331 if (ret) 2332 goto failed; 2333 2334 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2335 AMDGPU_GEM_DOMAIN_VRAM, 2336 &psp->fence_buf_bo, 2337 &psp->fence_buf_mc_addr, 2338 &psp->fence_buf); 2339 if (ret) 2340 goto failed; 2341 2342 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2343 AMDGPU_GEM_DOMAIN_VRAM, 2344 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2345 (void **)&psp->cmd_buf_mem); 2346 if (ret) 2347 goto failed; 2348 2349 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2350 2351 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2352 if (ret) { 2353 DRM_ERROR("PSP ring init failed!\n"); 2354 goto failed; 2355 } 2356 2357 skip_memalloc: 2358 ret = psp_hw_start(psp); 2359 if (ret) 2360 goto failed; 2361 2362 ret = psp_np_fw_load(psp); 2363 if (ret) 2364 goto failed; 2365 2366 ret = psp_asd_load(psp); 2367 if (ret) { 2368 DRM_ERROR("PSP load asd failed!\n"); 2369 return ret; 2370 } 2371 2372 ret = psp_rl_load(adev); 2373 if (ret) { 2374 DRM_ERROR("PSP load RL failed!\n"); 2375 return ret; 2376 } 2377 2378 if (psp->adev->psp.ta_fw) { 2379 ret = psp_ras_initialize(psp); 2380 if (ret) 2381 dev_err(psp->adev->dev, 2382 "RAS: Failed to initialize RAS\n"); 2383 2384 ret = psp_hdcp_initialize(psp); 2385 if (ret) 2386 dev_err(psp->adev->dev, 2387 "HDCP: Failed to initialize HDCP\n"); 2388 2389 ret = psp_dtm_initialize(psp); 2390 if (ret) 2391 dev_err(psp->adev->dev, 2392 "DTM: Failed to initialize DTM\n"); 2393 2394 ret = psp_rap_initialize(psp); 2395 if (ret) 2396 dev_err(psp->adev->dev, 2397 "RAP: Failed to initialize RAP\n"); 2398 2399 ret = psp_securedisplay_initialize(psp); 2400 if (ret) 2401 dev_err(psp->adev->dev, 2402 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2403 } 2404 2405 return 0; 2406 2407 failed: 2408 /* 2409 * all cleanup jobs (xgmi terminate, ras terminate, 2410 * ring destroy, cmd/fence/fw buffers destory, 2411 * psp->cmd destory) are delayed to psp_hw_fini 2412 */ 2413 return ret; 2414 } 2415 2416 static int psp_hw_init(void *handle) 2417 { 2418 int ret; 2419 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2420 2421 mutex_lock(&adev->firmware.mutex); 2422 /* 2423 * This sequence is just used on hw_init only once, no need on 2424 * resume. 2425 */ 2426 ret = amdgpu_ucode_init_bo(adev); 2427 if (ret) 2428 goto failed; 2429 2430 ret = psp_load_fw(adev); 2431 if (ret) { 2432 DRM_ERROR("PSP firmware loading failed\n"); 2433 goto failed; 2434 } 2435 2436 mutex_unlock(&adev->firmware.mutex); 2437 return 0; 2438 2439 failed: 2440 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2441 mutex_unlock(&adev->firmware.mutex); 2442 return -EINVAL; 2443 } 2444 2445 static int psp_hw_fini(void *handle) 2446 { 2447 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2448 struct psp_context *psp = &adev->psp; 2449 2450 if (psp->adev->psp.ta_fw) { 2451 psp_ras_terminate(psp); 2452 psp_securedisplay_terminate(psp); 2453 psp_rap_terminate(psp); 2454 psp_dtm_terminate(psp); 2455 psp_hdcp_terminate(psp); 2456 } 2457 2458 psp_asd_unload(psp); 2459 2460 psp_tmr_terminate(psp); 2461 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2462 2463 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2464 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2465 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2466 &psp->fence_buf_mc_addr, &psp->fence_buf); 2467 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2468 (void **)&psp->cmd_buf_mem); 2469 2470 kfree(psp->cmd); 2471 psp->cmd = NULL; 2472 2473 return 0; 2474 } 2475 2476 static int psp_suspend(void *handle) 2477 { 2478 int ret; 2479 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2480 struct psp_context *psp = &adev->psp; 2481 2482 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2483 psp->xgmi_context.initialized == 1) { 2484 ret = psp_xgmi_terminate(psp); 2485 if (ret) { 2486 DRM_ERROR("Failed to terminate xgmi ta\n"); 2487 return ret; 2488 } 2489 } 2490 2491 if (psp->adev->psp.ta_fw) { 2492 ret = psp_ras_terminate(psp); 2493 if (ret) { 2494 DRM_ERROR("Failed to terminate ras ta\n"); 2495 return ret; 2496 } 2497 ret = psp_hdcp_terminate(psp); 2498 if (ret) { 2499 DRM_ERROR("Failed to terminate hdcp ta\n"); 2500 return ret; 2501 } 2502 ret = psp_dtm_terminate(psp); 2503 if (ret) { 2504 DRM_ERROR("Failed to terminate dtm ta\n"); 2505 return ret; 2506 } 2507 ret = psp_rap_terminate(psp); 2508 if (ret) { 2509 DRM_ERROR("Failed to terminate rap ta\n"); 2510 return ret; 2511 } 2512 ret = psp_securedisplay_terminate(psp); 2513 if (ret) { 2514 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2515 return ret; 2516 } 2517 } 2518 2519 ret = psp_asd_unload(psp); 2520 if (ret) { 2521 DRM_ERROR("Failed to unload asd\n"); 2522 return ret; 2523 } 2524 2525 ret = psp_tmr_terminate(psp); 2526 if (ret) { 2527 DRM_ERROR("Failed to terminate tmr\n"); 2528 return ret; 2529 } 2530 2531 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2532 if (ret) { 2533 DRM_ERROR("PSP ring stop failed\n"); 2534 return ret; 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int psp_resume(void *handle) 2541 { 2542 int ret; 2543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2544 struct psp_context *psp = &adev->psp; 2545 2546 DRM_INFO("PSP is resuming...\n"); 2547 2548 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2549 if (ret) { 2550 DRM_ERROR("Failed to process memory training!\n"); 2551 return ret; 2552 } 2553 2554 mutex_lock(&adev->firmware.mutex); 2555 2556 ret = psp_hw_start(psp); 2557 if (ret) 2558 goto failed; 2559 2560 ret = psp_np_fw_load(psp); 2561 if (ret) 2562 goto failed; 2563 2564 ret = psp_asd_load(psp); 2565 if (ret) { 2566 DRM_ERROR("PSP load asd failed!\n"); 2567 goto failed; 2568 } 2569 2570 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2571 ret = psp_xgmi_initialize(psp); 2572 /* Warning the XGMI seesion initialize failure 2573 * Instead of stop driver initialization 2574 */ 2575 if (ret) 2576 dev_err(psp->adev->dev, 2577 "XGMI: Failed to initialize XGMI session\n"); 2578 } 2579 2580 if (psp->adev->psp.ta_fw) { 2581 ret = psp_ras_initialize(psp); 2582 if (ret) 2583 dev_err(psp->adev->dev, 2584 "RAS: Failed to initialize RAS\n"); 2585 2586 ret = psp_hdcp_initialize(psp); 2587 if (ret) 2588 dev_err(psp->adev->dev, 2589 "HDCP: Failed to initialize HDCP\n"); 2590 2591 ret = psp_dtm_initialize(psp); 2592 if (ret) 2593 dev_err(psp->adev->dev, 2594 "DTM: Failed to initialize DTM\n"); 2595 2596 ret = psp_rap_initialize(psp); 2597 if (ret) 2598 dev_err(psp->adev->dev, 2599 "RAP: Failed to initialize RAP\n"); 2600 2601 ret = psp_securedisplay_initialize(psp); 2602 if (ret) 2603 dev_err(psp->adev->dev, 2604 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2605 } 2606 2607 mutex_unlock(&adev->firmware.mutex); 2608 2609 return 0; 2610 2611 failed: 2612 DRM_ERROR("PSP resume failed\n"); 2613 mutex_unlock(&adev->firmware.mutex); 2614 return ret; 2615 } 2616 2617 int psp_gpu_reset(struct amdgpu_device *adev) 2618 { 2619 int ret; 2620 2621 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2622 return 0; 2623 2624 mutex_lock(&adev->psp.mutex); 2625 ret = psp_mode1_reset(&adev->psp); 2626 mutex_unlock(&adev->psp.mutex); 2627 2628 return ret; 2629 } 2630 2631 int psp_rlc_autoload_start(struct psp_context *psp) 2632 { 2633 int ret; 2634 struct psp_gfx_cmd_resp *cmd; 2635 2636 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2637 if (!cmd) 2638 return -ENOMEM; 2639 2640 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2641 2642 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2643 psp->fence_buf_mc_addr); 2644 kfree(cmd); 2645 return ret; 2646 } 2647 2648 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2649 uint64_t cmd_gpu_addr, int cmd_size) 2650 { 2651 struct amdgpu_firmware_info ucode = {0}; 2652 2653 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2654 AMDGPU_UCODE_ID_VCN0_RAM; 2655 ucode.mc_addr = cmd_gpu_addr; 2656 ucode.ucode_size = cmd_size; 2657 2658 return psp_execute_np_fw_load(&adev->psp, &ucode); 2659 } 2660 2661 int psp_ring_cmd_submit(struct psp_context *psp, 2662 uint64_t cmd_buf_mc_addr, 2663 uint64_t fence_mc_addr, 2664 int index) 2665 { 2666 unsigned int psp_write_ptr_reg = 0; 2667 struct psp_gfx_rb_frame *write_frame; 2668 struct psp_ring *ring = &psp->km_ring; 2669 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2670 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2671 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2672 struct amdgpu_device *adev = psp->adev; 2673 uint32_t ring_size_dw = ring->ring_size / 4; 2674 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2675 2676 /* KM (GPCOM) prepare write pointer */ 2677 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2678 2679 /* Update KM RB frame pointer to new frame */ 2680 /* write_frame ptr increments by size of rb_frame in bytes */ 2681 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2682 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2683 write_frame = ring_buffer_start; 2684 else 2685 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2686 /* Check invalid write_frame ptr address */ 2687 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2688 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2689 ring_buffer_start, ring_buffer_end, write_frame); 2690 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2691 return -EINVAL; 2692 } 2693 2694 /* Initialize KM RB frame */ 2695 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2696 2697 /* Update KM RB frame */ 2698 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2699 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2700 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2701 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2702 write_frame->fence_value = index; 2703 amdgpu_device_flush_hdp(adev, NULL); 2704 2705 /* Update the write Pointer in DWORDs */ 2706 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2707 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2708 return 0; 2709 } 2710 2711 int psp_init_asd_microcode(struct psp_context *psp, 2712 const char *chip_name) 2713 { 2714 struct amdgpu_device *adev = psp->adev; 2715 char fw_name[PSP_FW_NAME_LEN]; 2716 const struct psp_firmware_header_v1_0 *asd_hdr; 2717 int err = 0; 2718 2719 if (!chip_name) { 2720 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2721 return -EINVAL; 2722 } 2723 2724 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2725 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2726 if (err) 2727 goto out; 2728 2729 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2730 if (err) 2731 goto out; 2732 2733 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2734 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2735 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2736 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2737 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2738 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2739 return 0; 2740 out: 2741 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2742 release_firmware(adev->psp.asd_fw); 2743 adev->psp.asd_fw = NULL; 2744 return err; 2745 } 2746 2747 int psp_init_toc_microcode(struct psp_context *psp, 2748 const char *chip_name) 2749 { 2750 struct amdgpu_device *adev = psp->adev; 2751 char fw_name[30]; 2752 const struct psp_firmware_header_v1_0 *toc_hdr; 2753 int err = 0; 2754 2755 if (!chip_name) { 2756 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2757 return -EINVAL; 2758 } 2759 2760 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2761 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2762 if (err) 2763 goto out; 2764 2765 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2766 if (err) 2767 goto out; 2768 2769 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2770 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2771 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2772 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2773 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2774 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2775 return 0; 2776 out: 2777 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2778 release_firmware(adev->psp.toc_fw); 2779 adev->psp.toc_fw = NULL; 2780 return err; 2781 } 2782 2783 int psp_init_sos_microcode(struct psp_context *psp, 2784 const char *chip_name) 2785 { 2786 struct amdgpu_device *adev = psp->adev; 2787 char fw_name[PSP_FW_NAME_LEN]; 2788 const struct psp_firmware_header_v1_0 *sos_hdr; 2789 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2790 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2791 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2792 int err = 0; 2793 2794 if (!chip_name) { 2795 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2796 return -EINVAL; 2797 } 2798 2799 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2800 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2801 if (err) 2802 goto out; 2803 2804 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2805 if (err) 2806 goto out; 2807 2808 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2809 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2810 2811 switch (sos_hdr->header.header_version_major) { 2812 case 1: 2813 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2814 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2815 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2816 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2817 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2818 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2819 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2820 le32_to_cpu(sos_hdr->sos_offset_bytes); 2821 if (sos_hdr->header.header_version_minor == 1) { 2822 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2823 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2824 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2825 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2826 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2827 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2828 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2829 } 2830 if (sos_hdr->header.header_version_minor == 2) { 2831 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2832 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2833 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2834 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2835 } 2836 if (sos_hdr->header.header_version_minor == 3) { 2837 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2838 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2839 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2840 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2841 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2842 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2843 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2844 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2845 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2846 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2847 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2848 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2849 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2850 } 2851 break; 2852 default: 2853 dev_err(adev->dev, 2854 "unsupported psp sos firmware\n"); 2855 err = -EINVAL; 2856 goto out; 2857 } 2858 2859 return 0; 2860 out: 2861 dev_err(adev->dev, 2862 "failed to init sos firmware\n"); 2863 release_firmware(adev->psp.sos_fw); 2864 adev->psp.sos_fw = NULL; 2865 2866 return err; 2867 } 2868 2869 static int parse_ta_bin_descriptor(struct psp_context *psp, 2870 const struct ta_fw_bin_desc *desc, 2871 const struct ta_firmware_header_v2_0 *ta_hdr) 2872 { 2873 uint8_t *ucode_start_addr = NULL; 2874 2875 if (!psp || !desc || !ta_hdr) 2876 return -EINVAL; 2877 2878 ucode_start_addr = (uint8_t *)ta_hdr + 2879 le32_to_cpu(desc->offset_bytes) + 2880 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2881 2882 switch (desc->fw_type) { 2883 case TA_FW_TYPE_PSP_ASD: 2884 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2885 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2886 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2887 psp->asd_start_addr = ucode_start_addr; 2888 break; 2889 case TA_FW_TYPE_PSP_XGMI: 2890 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2891 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2892 psp->ta_xgmi_start_addr = ucode_start_addr; 2893 break; 2894 case TA_FW_TYPE_PSP_RAS: 2895 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2896 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2897 psp->ta_ras_start_addr = ucode_start_addr; 2898 break; 2899 case TA_FW_TYPE_PSP_HDCP: 2900 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2901 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2902 psp->ta_hdcp_start_addr = ucode_start_addr; 2903 break; 2904 case TA_FW_TYPE_PSP_DTM: 2905 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2906 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2907 psp->ta_dtm_start_addr = ucode_start_addr; 2908 break; 2909 case TA_FW_TYPE_PSP_RAP: 2910 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2911 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2912 psp->ta_rap_start_addr = ucode_start_addr; 2913 break; 2914 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2915 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2916 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2917 psp->ta_securedisplay_start_addr = ucode_start_addr; 2918 break; 2919 default: 2920 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2921 break; 2922 } 2923 2924 return 0; 2925 } 2926 2927 int psp_init_ta_microcode(struct psp_context *psp, 2928 const char *chip_name) 2929 { 2930 struct amdgpu_device *adev = psp->adev; 2931 char fw_name[PSP_FW_NAME_LEN]; 2932 const struct ta_firmware_header_v2_0 *ta_hdr; 2933 int err = 0; 2934 int ta_index = 0; 2935 2936 if (!chip_name) { 2937 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2938 return -EINVAL; 2939 } 2940 2941 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2942 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2943 if (err) 2944 goto out; 2945 2946 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2947 if (err) 2948 goto out; 2949 2950 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2951 2952 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2953 dev_err(adev->dev, "unsupported TA header version\n"); 2954 err = -EINVAL; 2955 goto out; 2956 } 2957 2958 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2959 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2960 err = -EINVAL; 2961 goto out; 2962 } 2963 2964 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2965 err = parse_ta_bin_descriptor(psp, 2966 &ta_hdr->ta_fw_bin[ta_index], 2967 ta_hdr); 2968 if (err) 2969 goto out; 2970 } 2971 2972 return 0; 2973 out: 2974 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2975 release_firmware(adev->psp.ta_fw); 2976 adev->psp.ta_fw = NULL; 2977 return err; 2978 } 2979 2980 static int psp_set_clockgating_state(void *handle, 2981 enum amd_clockgating_state state) 2982 { 2983 return 0; 2984 } 2985 2986 static int psp_set_powergating_state(void *handle, 2987 enum amd_powergating_state state) 2988 { 2989 return 0; 2990 } 2991 2992 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2993 struct device_attribute *attr, 2994 char *buf) 2995 { 2996 struct drm_device *ddev = dev_get_drvdata(dev); 2997 struct amdgpu_device *adev = drm_to_adev(ddev); 2998 uint32_t fw_ver; 2999 int ret; 3000 3001 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3002 DRM_INFO("PSP block is not ready yet."); 3003 return -EBUSY; 3004 } 3005 3006 mutex_lock(&adev->psp.mutex); 3007 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3008 mutex_unlock(&adev->psp.mutex); 3009 3010 if (ret) { 3011 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3012 return ret; 3013 } 3014 3015 return sysfs_emit(buf, "%x\n", fw_ver); 3016 } 3017 3018 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3019 struct device_attribute *attr, 3020 const char *buf, 3021 size_t count) 3022 { 3023 struct drm_device *ddev = dev_get_drvdata(dev); 3024 struct amdgpu_device *adev = drm_to_adev(ddev); 3025 void *cpu_addr; 3026 dma_addr_t dma_addr; 3027 int ret, idx; 3028 char fw_name[100]; 3029 const struct firmware *usbc_pd_fw; 3030 3031 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3032 DRM_INFO("PSP block is not ready yet."); 3033 return -EBUSY; 3034 } 3035 3036 if (!drm_dev_enter(ddev, &idx)) 3037 return -ENODEV; 3038 3039 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3040 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3041 if (ret) 3042 goto fail; 3043 3044 /* We need contiguous physical mem to place the FW for psp to access */ 3045 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3046 3047 ret = dma_mapping_error(adev->dev, dma_addr); 3048 if (ret) 3049 goto rel_buf; 3050 3051 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3052 3053 /* 3054 * x86 specific workaround. 3055 * Without it the buffer is invisible in PSP. 3056 * 3057 * TODO Remove once PSP starts snooping CPU cache 3058 */ 3059 #ifdef CONFIG_X86 3060 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3061 #endif 3062 3063 mutex_lock(&adev->psp.mutex); 3064 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3065 mutex_unlock(&adev->psp.mutex); 3066 3067 rel_buf: 3068 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3069 release_firmware(usbc_pd_fw); 3070 fail: 3071 if (ret) { 3072 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3073 count = ret; 3074 } 3075 3076 drm_dev_exit(idx); 3077 return count; 3078 } 3079 3080 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3081 { 3082 int idx; 3083 3084 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3085 return; 3086 3087 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3088 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3089 3090 drm_dev_exit(idx); 3091 } 3092 3093 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3094 psp_usbc_pd_fw_sysfs_read, 3095 psp_usbc_pd_fw_sysfs_write); 3096 3097 3098 3099 const struct amd_ip_funcs psp_ip_funcs = { 3100 .name = "psp", 3101 .early_init = psp_early_init, 3102 .late_init = NULL, 3103 .sw_init = psp_sw_init, 3104 .sw_fini = psp_sw_fini, 3105 .hw_init = psp_hw_init, 3106 .hw_fini = psp_hw_fini, 3107 .suspend = psp_suspend, 3108 .resume = psp_resume, 3109 .is_idle = NULL, 3110 .check_soft_reset = NULL, 3111 .wait_for_idle = NULL, 3112 .soft_reset = NULL, 3113 .set_clockgating_state = psp_set_clockgating_state, 3114 .set_powergating_state = psp_set_powergating_state, 3115 }; 3116 3117 static int psp_sysfs_init(struct amdgpu_device *adev) 3118 { 3119 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3120 3121 if (ret) 3122 DRM_ERROR("Failed to create USBC PD FW control file!"); 3123 3124 return ret; 3125 } 3126 3127 static void psp_sysfs_fini(struct amdgpu_device *adev) 3128 { 3129 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3130 } 3131 3132 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3133 { 3134 .type = AMD_IP_BLOCK_TYPE_PSP, 3135 .major = 3, 3136 .minor = 1, 3137 .rev = 0, 3138 .funcs = &psp_ip_funcs, 3139 }; 3140 3141 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3142 { 3143 .type = AMD_IP_BLOCK_TYPE_PSP, 3144 .major = 10, 3145 .minor = 0, 3146 .rev = 0, 3147 .funcs = &psp_ip_funcs, 3148 }; 3149 3150 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3151 { 3152 .type = AMD_IP_BLOCK_TYPE_PSP, 3153 .major = 11, 3154 .minor = 0, 3155 .rev = 0, 3156 .funcs = &psp_ip_funcs, 3157 }; 3158 3159 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3160 { 3161 .type = AMD_IP_BLOCK_TYPE_PSP, 3162 .major = 12, 3163 .minor = 0, 3164 .rev = 0, 3165 .funcs = &psp_ip_funcs, 3166 }; 3167 3168 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3169 .type = AMD_IP_BLOCK_TYPE_PSP, 3170 .major = 13, 3171 .minor = 0, 3172 .rev = 0, 3173 .funcs = &psp_ip_funcs, 3174 }; 3175