1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 /* 53 * Due to DF Cstate management centralized to PMFW, the firmware 54 * loading sequence will be updated as below: 55 * - Load KDB 56 * - Load SYS_DRV 57 * - Load tOS 58 * - Load PMFW 59 * - Setup TMR 60 * - Load other non-psp fw 61 * - Load ASD 62 * - Load XGMI/RAS/HDCP/DTM TA if any 63 * 64 * This new sequence is required for 65 * - Arcturus and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 if (amdgpu_sriov_vf(adev)) { 72 psp->pmfw_centralized_cstate_management = false; 73 return; 74 } 75 76 switch (adev->ip_versions[MP0_HWIP][0]) { 77 case IP_VERSION(11, 0, 0): 78 case IP_VERSION(11, 0, 4): 79 case IP_VERSION(11, 0, 5): 80 case IP_VERSION(11, 0, 7): 81 case IP_VERSION(11, 0, 9): 82 case IP_VERSION(11, 0, 11): 83 case IP_VERSION(11, 0, 12): 84 case IP_VERSION(11, 0, 13): 85 case IP_VERSION(13, 0, 0): 86 case IP_VERSION(13, 0, 2): 87 case IP_VERSION(13, 0, 7): 88 psp->pmfw_centralized_cstate_management = true; 89 break; 90 default: 91 psp->pmfw_centralized_cstate_management = false; 92 break; 93 } 94 } 95 96 static int psp_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 struct psp_context *psp = &adev->psp; 100 101 switch (adev->ip_versions[MP0_HWIP][0]) { 102 case IP_VERSION(9, 0, 0): 103 psp_v3_1_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case IP_VERSION(10, 0, 0): 107 case IP_VERSION(10, 0, 1): 108 psp_v10_0_set_psp_funcs(psp); 109 psp->autoload_supported = false; 110 break; 111 case IP_VERSION(11, 0, 2): 112 case IP_VERSION(11, 0, 4): 113 psp_v11_0_set_psp_funcs(psp); 114 psp->autoload_supported = false; 115 break; 116 case IP_VERSION(11, 0, 0): 117 case IP_VERSION(11, 0, 5): 118 case IP_VERSION(11, 0, 9): 119 case IP_VERSION(11, 0, 7): 120 case IP_VERSION(11, 0, 11): 121 case IP_VERSION(11, 5, 0): 122 case IP_VERSION(11, 0, 12): 123 case IP_VERSION(11, 0, 13): 124 psp_v11_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case IP_VERSION(11, 0, 3): 128 case IP_VERSION(12, 0, 1): 129 psp_v12_0_set_psp_funcs(psp); 130 break; 131 case IP_VERSION(13, 0, 2): 132 psp_v13_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 1): 135 case IP_VERSION(13, 0, 3): 136 case IP_VERSION(13, 0, 5): 137 case IP_VERSION(13, 0, 8): 138 psp_v13_0_set_psp_funcs(psp); 139 psp->autoload_supported = true; 140 break; 141 case IP_VERSION(11, 0, 8): 142 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 143 psp_v11_0_8_set_psp_funcs(psp); 144 psp->autoload_supported = false; 145 } 146 break; 147 case IP_VERSION(13, 0, 0): 148 case IP_VERSION(13, 0, 7): 149 psp_v13_0_set_psp_funcs(psp); 150 psp->autoload_supported = true; 151 break; 152 default: 153 return -EINVAL; 154 } 155 156 psp->adev = adev; 157 158 psp_check_pmfw_centralized_cstate_management(psp); 159 160 return 0; 161 } 162 163 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 164 { 165 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 166 &mem_ctx->shared_buf); 167 } 168 169 static void psp_free_shared_bufs(struct psp_context *psp) 170 { 171 void *tmr_buf; 172 void **pptr; 173 174 /* free TMR memory buffer */ 175 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 176 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 177 178 /* free xgmi shared memory */ 179 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 180 181 /* free ras shared memory */ 182 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 183 184 /* free hdcp shared memory */ 185 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 186 187 /* free dtm shared memory */ 188 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 189 190 /* free rap shared memory */ 191 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 192 193 /* free securedisplay shared memory */ 194 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 195 196 197 } 198 199 static void psp_memory_training_fini(struct psp_context *psp) 200 { 201 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 202 203 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 204 kfree(ctx->sys_cache); 205 ctx->sys_cache = NULL; 206 } 207 208 static int psp_memory_training_init(struct psp_context *psp) 209 { 210 int ret; 211 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 212 213 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 214 DRM_DEBUG("memory training is not supported!\n"); 215 return 0; 216 } 217 218 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 219 if (ctx->sys_cache == NULL) { 220 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 221 ret = -ENOMEM; 222 goto Err_out; 223 } 224 225 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 226 ctx->train_data_size, 227 ctx->p2c_train_data_offset, 228 ctx->c2p_train_data_offset); 229 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 230 return 0; 231 232 Err_out: 233 psp_memory_training_fini(psp); 234 return ret; 235 } 236 237 /* 238 * Helper funciton to query psp runtime database entry 239 * 240 * @adev: amdgpu_device pointer 241 * @entry_type: the type of psp runtime database entry 242 * @db_entry: runtime database entry pointer 243 * 244 * Return false if runtime database doesn't exit or entry is invalid 245 * or true if the specific database entry is found, and copy to @db_entry 246 */ 247 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 248 enum psp_runtime_entry_type entry_type, 249 void *db_entry) 250 { 251 uint64_t db_header_pos, db_dir_pos; 252 struct psp_runtime_data_header db_header = {0}; 253 struct psp_runtime_data_directory db_dir = {0}; 254 bool ret = false; 255 int i; 256 257 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 258 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 259 260 /* read runtime db header from vram */ 261 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 262 sizeof(struct psp_runtime_data_header), false); 263 264 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 265 /* runtime db doesn't exist, exit */ 266 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 267 return false; 268 } 269 270 /* read runtime database entry from vram */ 271 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 272 sizeof(struct psp_runtime_data_directory), false); 273 274 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 275 /* invalid db entry count, exit */ 276 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 277 return false; 278 } 279 280 /* look up for requested entry type */ 281 for (i = 0; i < db_dir.entry_count && !ret; i++) { 282 if (db_dir.entry_list[i].entry_type == entry_type) { 283 switch (entry_type) { 284 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 285 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 286 /* invalid db entry size */ 287 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 288 return false; 289 } 290 /* read runtime database entry */ 291 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 292 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 293 ret = true; 294 break; 295 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 296 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 297 /* invalid db entry size */ 298 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 299 return false; 300 } 301 /* read runtime database entry */ 302 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 303 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 304 ret = true; 305 break; 306 default: 307 ret = false; 308 break; 309 } 310 } 311 } 312 313 return ret; 314 } 315 316 static int psp_init_sriov_microcode(struct psp_context *psp) 317 { 318 struct amdgpu_device *adev = psp->adev; 319 int ret = 0; 320 321 switch (adev->ip_versions[MP0_HWIP][0]) { 322 case IP_VERSION(9, 0, 0): 323 ret = psp_init_cap_microcode(psp, "vega10"); 324 break; 325 case IP_VERSION(11, 0, 9): 326 ret = psp_init_cap_microcode(psp, "navi12"); 327 break; 328 case IP_VERSION(11, 0, 7): 329 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 330 break; 331 case IP_VERSION(13, 0, 2): 332 ret = psp_init_cap_microcode(psp, "aldebaran"); 333 ret &= psp_init_ta_microcode(psp, "aldebaran"); 334 break; 335 default: 336 BUG(); 337 break; 338 } 339 340 return ret; 341 } 342 343 static int psp_sw_init(void *handle) 344 { 345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 346 struct psp_context *psp = &adev->psp; 347 int ret; 348 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 349 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 350 struct psp_runtime_scpm_entry scpm_entry; 351 352 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 353 if (!psp->cmd) { 354 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 355 ret = -ENOMEM; 356 } 357 358 if (amdgpu_sriov_vf(adev)) 359 ret = psp_init_sriov_microcode(psp); 360 else 361 ret = psp_init_microcode(psp); 362 if (ret) { 363 DRM_ERROR("Failed to load psp firmware!\n"); 364 return ret; 365 } 366 367 adev->psp.xgmi_context.supports_extended_data = 368 !adev->gmc.xgmi.connected_to_cpu && 369 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 370 371 memset(&scpm_entry, 0, sizeof(scpm_entry)); 372 if ((psp_get_runtime_db_entry(adev, 373 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 374 &scpm_entry)) && 375 (SCPM_DISABLE != scpm_entry.scpm_status)) { 376 adev->scpm_enabled = true; 377 adev->scpm_status = scpm_entry.scpm_status; 378 } else { 379 adev->scpm_enabled = false; 380 adev->scpm_status = SCPM_DISABLE; 381 } 382 383 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 384 385 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 386 if (psp_get_runtime_db_entry(adev, 387 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 388 &boot_cfg_entry)) { 389 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 390 if ((psp->boot_cfg_bitmask) & 391 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 392 /* If psp runtime database exists, then 393 * only enable two stage memory training 394 * when TWO_STAGE_DRAM_TRAINING bit is set 395 * in runtime database */ 396 mem_training_ctx->enable_mem_training = true; 397 } 398 399 } else { 400 /* If psp runtime database doesn't exist or 401 * is invalid, force enable two stage memory 402 * training */ 403 mem_training_ctx->enable_mem_training = true; 404 } 405 406 if (mem_training_ctx->enable_mem_training) { 407 ret = psp_memory_training_init(psp); 408 if (ret) { 409 DRM_ERROR("Failed to initialize memory training!\n"); 410 return ret; 411 } 412 413 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 414 if (ret) { 415 DRM_ERROR("Failed to process memory training!\n"); 416 return ret; 417 } 418 } 419 420 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 421 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 422 ret= psp_sysfs_init(adev); 423 if (ret) { 424 return ret; 425 } 426 } 427 428 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 429 amdgpu_sriov_vf(adev) ? 430 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 431 &psp->fw_pri_bo, 432 &psp->fw_pri_mc_addr, 433 &psp->fw_pri_buf); 434 if (ret) 435 return ret; 436 437 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 438 AMDGPU_GEM_DOMAIN_VRAM, 439 &psp->fence_buf_bo, 440 &psp->fence_buf_mc_addr, 441 &psp->fence_buf); 442 if (ret) 443 goto failed1; 444 445 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 446 AMDGPU_GEM_DOMAIN_VRAM, 447 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 448 (void **)&psp->cmd_buf_mem); 449 if (ret) 450 goto failed2; 451 452 return 0; 453 454 failed2: 455 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 456 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 457 failed1: 458 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 459 &psp->fence_buf_mc_addr, &psp->fence_buf); 460 return ret; 461 } 462 463 static int psp_sw_fini(void *handle) 464 { 465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 466 struct psp_context *psp = &adev->psp; 467 struct psp_gfx_cmd_resp *cmd = psp->cmd; 468 469 psp_memory_training_fini(psp); 470 if (psp->sos_fw) { 471 release_firmware(psp->sos_fw); 472 psp->sos_fw = NULL; 473 } 474 if (psp->asd_fw) { 475 release_firmware(psp->asd_fw); 476 psp->asd_fw = NULL; 477 } 478 if (psp->ta_fw) { 479 release_firmware(psp->ta_fw); 480 psp->ta_fw = NULL; 481 } 482 if (adev->psp.cap_fw) { 483 release_firmware(psp->cap_fw); 484 psp->cap_fw = NULL; 485 } 486 487 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 488 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 489 psp_sysfs_fini(adev); 490 491 kfree(cmd); 492 cmd = NULL; 493 494 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 495 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 496 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 497 &psp->fence_buf_mc_addr, &psp->fence_buf); 498 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 499 (void **)&psp->cmd_buf_mem); 500 501 return 0; 502 } 503 504 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 505 uint32_t reg_val, uint32_t mask, bool check_changed) 506 { 507 uint32_t val; 508 int i; 509 struct amdgpu_device *adev = psp->adev; 510 511 if (psp->adev->no_hw_access) 512 return 0; 513 514 for (i = 0; i < adev->usec_timeout; i++) { 515 val = RREG32(reg_index); 516 if (check_changed) { 517 if (val != reg_val) 518 return 0; 519 } else { 520 if ((val & mask) == reg_val) 521 return 0; 522 } 523 udelay(1); 524 } 525 526 return -ETIME; 527 } 528 529 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 530 { 531 switch (cmd_id) { 532 case GFX_CMD_ID_LOAD_TA: 533 return "LOAD_TA"; 534 case GFX_CMD_ID_UNLOAD_TA: 535 return "UNLOAD_TA"; 536 case GFX_CMD_ID_INVOKE_CMD: 537 return "INVOKE_CMD"; 538 case GFX_CMD_ID_LOAD_ASD: 539 return "LOAD_ASD"; 540 case GFX_CMD_ID_SETUP_TMR: 541 return "SETUP_TMR"; 542 case GFX_CMD_ID_LOAD_IP_FW: 543 return "LOAD_IP_FW"; 544 case GFX_CMD_ID_DESTROY_TMR: 545 return "DESTROY_TMR"; 546 case GFX_CMD_ID_SAVE_RESTORE: 547 return "SAVE_RESTORE_IP_FW"; 548 case GFX_CMD_ID_SETUP_VMR: 549 return "SETUP_VMR"; 550 case GFX_CMD_ID_DESTROY_VMR: 551 return "DESTROY_VMR"; 552 case GFX_CMD_ID_PROG_REG: 553 return "PROG_REG"; 554 case GFX_CMD_ID_GET_FW_ATTESTATION: 555 return "GET_FW_ATTESTATION"; 556 case GFX_CMD_ID_LOAD_TOC: 557 return "ID_LOAD_TOC"; 558 case GFX_CMD_ID_AUTOLOAD_RLC: 559 return "AUTOLOAD_RLC"; 560 case GFX_CMD_ID_BOOT_CFG: 561 return "BOOT_CFG"; 562 default: 563 return "UNKNOWN CMD"; 564 } 565 } 566 567 static int 568 psp_cmd_submit_buf(struct psp_context *psp, 569 struct amdgpu_firmware_info *ucode, 570 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 571 { 572 int ret; 573 int index, idx; 574 int timeout = 20000; 575 bool ras_intr = false; 576 bool skip_unsupport = false; 577 578 if (psp->adev->no_hw_access) 579 return 0; 580 581 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 582 return 0; 583 584 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 585 586 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 587 588 index = atomic_inc_return(&psp->fence_value); 589 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 590 if (ret) { 591 atomic_dec(&psp->fence_value); 592 goto exit; 593 } 594 595 amdgpu_device_invalidate_hdp(psp->adev, NULL); 596 while (*((unsigned int *)psp->fence_buf) != index) { 597 if (--timeout == 0) 598 break; 599 /* 600 * Shouldn't wait for timeout when err_event_athub occurs, 601 * because gpu reset thread triggered and lock resource should 602 * be released for psp resume sequence. 603 */ 604 ras_intr = amdgpu_ras_intr_triggered(); 605 if (ras_intr) 606 break; 607 usleep_range(10, 100); 608 amdgpu_device_invalidate_hdp(psp->adev, NULL); 609 } 610 611 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 612 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 613 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 614 615 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 616 617 /* In some cases, psp response status is not 0 even there is no 618 * problem while the command is submitted. Some version of PSP FW 619 * doesn't write 0 to that field. 620 * So here we would like to only print a warning instead of an error 621 * during psp initialization to avoid breaking hw_init and it doesn't 622 * return -EINVAL. 623 */ 624 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 625 if (ucode) 626 DRM_WARN("failed to load ucode %s(0x%X) ", 627 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 628 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 629 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 630 psp->cmd_buf_mem->resp.status); 631 /* If we load CAP FW, PSP must return 0 under SRIOV 632 * also return failure in case of timeout 633 */ 634 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 635 ret = -EINVAL; 636 goto exit; 637 } 638 } 639 640 if (ucode) { 641 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 642 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 643 } 644 645 exit: 646 drm_dev_exit(idx); 647 return ret; 648 } 649 650 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 651 { 652 struct psp_gfx_cmd_resp *cmd = psp->cmd; 653 654 mutex_lock(&psp->mutex); 655 656 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 657 658 return cmd; 659 } 660 661 static void release_psp_cmd_buf(struct psp_context *psp) 662 { 663 mutex_unlock(&psp->mutex); 664 } 665 666 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 667 struct psp_gfx_cmd_resp *cmd, 668 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 669 { 670 struct amdgpu_device *adev = psp->adev; 671 uint32_t size = amdgpu_bo_size(tmr_bo); 672 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 673 674 if (amdgpu_sriov_vf(psp->adev)) 675 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 676 else 677 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 678 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 679 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 680 cmd->cmd.cmd_setup_tmr.buf_size = size; 681 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 682 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 683 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 684 } 685 686 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 687 uint64_t pri_buf_mc, uint32_t size) 688 { 689 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 690 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 691 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 692 cmd->cmd.cmd_load_toc.toc_size = size; 693 } 694 695 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 696 static int psp_load_toc(struct psp_context *psp, 697 uint32_t *tmr_size) 698 { 699 int ret; 700 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 701 702 /* Copy toc to psp firmware private buffer */ 703 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 704 705 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 706 707 ret = psp_cmd_submit_buf(psp, NULL, cmd, 708 psp->fence_buf_mc_addr); 709 if (!ret) 710 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 711 712 release_psp_cmd_buf(psp); 713 714 return ret; 715 } 716 717 /* Set up Trusted Memory Region */ 718 static int psp_tmr_init(struct psp_context *psp) 719 { 720 int ret; 721 int tmr_size; 722 void *tmr_buf; 723 void **pptr; 724 725 /* 726 * According to HW engineer, they prefer the TMR address be "naturally 727 * aligned" , e.g. the start address be an integer divide of TMR size. 728 * 729 * Note: this memory need be reserved till the driver 730 * uninitializes. 731 */ 732 tmr_size = PSP_TMR_SIZE(psp->adev); 733 734 /* For ASICs support RLC autoload, psp will parse the toc 735 * and calculate the total size of TMR needed */ 736 if (!amdgpu_sriov_vf(psp->adev) && 737 psp->toc.start_addr && 738 psp->toc.size_bytes && 739 psp->fw_pri_buf) { 740 ret = psp_load_toc(psp, &tmr_size); 741 if (ret) { 742 DRM_ERROR("Failed to load toc\n"); 743 return ret; 744 } 745 } 746 747 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 748 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 749 AMDGPU_GEM_DOMAIN_VRAM, 750 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 751 752 return ret; 753 } 754 755 static bool psp_skip_tmr(struct psp_context *psp) 756 { 757 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 758 case IP_VERSION(11, 0, 9): 759 case IP_VERSION(11, 0, 7): 760 case IP_VERSION(13, 0, 2): 761 return true; 762 default: 763 return false; 764 } 765 } 766 767 static int psp_tmr_load(struct psp_context *psp) 768 { 769 int ret; 770 struct psp_gfx_cmd_resp *cmd; 771 772 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 773 * Already set up by host driver. 774 */ 775 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 776 return 0; 777 778 cmd = acquire_psp_cmd_buf(psp); 779 780 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 781 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 782 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 783 784 ret = psp_cmd_submit_buf(psp, NULL, cmd, 785 psp->fence_buf_mc_addr); 786 787 release_psp_cmd_buf(psp); 788 789 return ret; 790 } 791 792 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 793 struct psp_gfx_cmd_resp *cmd) 794 { 795 if (amdgpu_sriov_vf(psp->adev)) 796 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 797 else 798 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 799 } 800 801 static int psp_tmr_unload(struct psp_context *psp) 802 { 803 int ret; 804 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 805 806 psp_prep_tmr_unload_cmd_buf(psp, cmd); 807 DRM_INFO("free PSP TMR buffer\n"); 808 809 ret = psp_cmd_submit_buf(psp, NULL, cmd, 810 psp->fence_buf_mc_addr); 811 812 release_psp_cmd_buf(psp); 813 814 return ret; 815 } 816 817 static int psp_tmr_terminate(struct psp_context *psp) 818 { 819 return psp_tmr_unload(psp); 820 } 821 822 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 823 uint64_t *output_ptr) 824 { 825 int ret; 826 struct psp_gfx_cmd_resp *cmd; 827 828 if (!output_ptr) 829 return -EINVAL; 830 831 if (amdgpu_sriov_vf(psp->adev)) 832 return 0; 833 834 cmd = acquire_psp_cmd_buf(psp); 835 836 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 837 838 ret = psp_cmd_submit_buf(psp, NULL, cmd, 839 psp->fence_buf_mc_addr); 840 841 if (!ret) { 842 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 843 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 844 } 845 846 release_psp_cmd_buf(psp); 847 848 return ret; 849 } 850 851 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 852 { 853 struct psp_context *psp = &adev->psp; 854 struct psp_gfx_cmd_resp *cmd; 855 int ret; 856 857 if (amdgpu_sriov_vf(adev)) 858 return 0; 859 860 cmd = acquire_psp_cmd_buf(psp); 861 862 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 863 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 864 865 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 866 if (!ret) { 867 *boot_cfg = 868 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 869 } 870 871 release_psp_cmd_buf(psp); 872 873 return ret; 874 } 875 876 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 877 { 878 int ret; 879 struct psp_context *psp = &adev->psp; 880 struct psp_gfx_cmd_resp *cmd; 881 882 if (amdgpu_sriov_vf(adev)) 883 return 0; 884 885 cmd = acquire_psp_cmd_buf(psp); 886 887 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 888 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 889 cmd->cmd.boot_cfg.boot_config = boot_cfg; 890 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 891 892 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 893 894 release_psp_cmd_buf(psp); 895 896 return ret; 897 } 898 899 static int psp_rl_load(struct amdgpu_device *adev) 900 { 901 int ret; 902 struct psp_context *psp = &adev->psp; 903 struct psp_gfx_cmd_resp *cmd; 904 905 if (!is_psp_fw_valid(psp->rl)) 906 return 0; 907 908 cmd = acquire_psp_cmd_buf(psp); 909 910 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 911 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 912 913 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 914 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 915 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 916 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 917 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 918 919 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 920 921 release_psp_cmd_buf(psp); 922 923 return ret; 924 } 925 926 static int psp_asd_initialize(struct psp_context *psp) 927 { 928 int ret; 929 930 /* If PSP version doesn't match ASD version, asd loading will be failed. 931 * add workaround to bypass it for sriov now. 932 * TODO: add version check to make it common 933 */ 934 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 935 return 0; 936 937 psp->asd_context.mem_context.shared_mc_addr = 0; 938 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 939 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 940 941 ret = psp_ta_load(psp, &psp->asd_context); 942 if (!ret) 943 psp->asd_context.initialized = true; 944 945 return ret; 946 } 947 948 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 949 uint32_t session_id) 950 { 951 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 952 cmd->cmd.cmd_unload_ta.session_id = session_id; 953 } 954 955 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 956 { 957 int ret; 958 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 959 960 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 961 962 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 963 964 release_psp_cmd_buf(psp); 965 966 return ret; 967 } 968 969 static int psp_asd_terminate(struct psp_context *psp) 970 { 971 int ret; 972 973 if (amdgpu_sriov_vf(psp->adev)) 974 return 0; 975 976 if (!psp->asd_context.initialized) 977 return 0; 978 979 ret = psp_ta_unload(psp, &psp->asd_context); 980 if (!ret) 981 psp->asd_context.initialized = false; 982 983 return ret; 984 } 985 986 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 987 uint32_t id, uint32_t value) 988 { 989 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 990 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 991 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 992 } 993 994 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 995 uint32_t value) 996 { 997 struct psp_gfx_cmd_resp *cmd; 998 int ret = 0; 999 1000 if (reg >= PSP_REG_LAST) 1001 return -EINVAL; 1002 1003 cmd = acquire_psp_cmd_buf(psp); 1004 1005 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1006 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1007 if (ret) 1008 DRM_ERROR("PSP failed to program reg id %d", reg); 1009 1010 release_psp_cmd_buf(psp); 1011 1012 return ret; 1013 } 1014 1015 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1016 uint64_t ta_bin_mc, 1017 struct ta_context *context) 1018 { 1019 cmd->cmd_id = context->ta_load_type; 1020 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1021 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1022 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1023 1024 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1025 lower_32_bits(context->mem_context.shared_mc_addr); 1026 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1027 upper_32_bits(context->mem_context.shared_mc_addr); 1028 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1029 } 1030 1031 int psp_ta_init_shared_buf(struct psp_context *psp, 1032 struct ta_mem_context *mem_ctx) 1033 { 1034 /* 1035 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1036 * physical) for ta to host memory 1037 */ 1038 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1039 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1040 &mem_ctx->shared_bo, 1041 &mem_ctx->shared_mc_addr, 1042 &mem_ctx->shared_buf); 1043 } 1044 1045 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1046 uint32_t ta_cmd_id, 1047 struct ta_context *context) 1048 { 1049 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1050 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1051 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1052 1053 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1054 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1055 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1056 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1057 lower_32_bits(context->mem_context.shared_mc_addr); 1058 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1059 upper_32_bits(context->mem_context.shared_mc_addr); 1060 } 1061 1062 int psp_ta_invoke_indirect(struct psp_context *psp, 1063 uint32_t ta_cmd_id, 1064 struct ta_context *context) 1065 { 1066 int ret; 1067 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1068 1069 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1070 1071 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1072 psp->fence_buf_mc_addr); 1073 1074 context->resp_status = cmd->resp.status; 1075 1076 release_psp_cmd_buf(psp); 1077 1078 return ret; 1079 } 1080 1081 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1082 uint32_t ta_cmd_id, 1083 uint32_t session_id) 1084 { 1085 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1086 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1087 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1088 } 1089 1090 int psp_ta_invoke(struct psp_context *psp, 1091 uint32_t ta_cmd_id, 1092 struct ta_context *context) 1093 { 1094 int ret; 1095 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1096 1097 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1098 1099 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1100 psp->fence_buf_mc_addr); 1101 1102 context->resp_status = cmd->resp.status; 1103 1104 release_psp_cmd_buf(psp); 1105 1106 return ret; 1107 } 1108 1109 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1110 { 1111 int ret; 1112 struct psp_gfx_cmd_resp *cmd; 1113 1114 cmd = acquire_psp_cmd_buf(psp); 1115 1116 psp_copy_fw(psp, context->bin_desc.start_addr, 1117 context->bin_desc.size_bytes); 1118 1119 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1120 1121 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1122 psp->fence_buf_mc_addr); 1123 1124 context->resp_status = cmd->resp.status; 1125 1126 if (!ret) { 1127 context->session_id = cmd->resp.session_id; 1128 } 1129 1130 release_psp_cmd_buf(psp); 1131 1132 return ret; 1133 } 1134 1135 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1136 { 1137 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1138 } 1139 1140 int psp_xgmi_terminate(struct psp_context *psp) 1141 { 1142 int ret; 1143 struct amdgpu_device *adev = psp->adev; 1144 1145 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1146 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1147 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1148 adev->gmc.xgmi.connected_to_cpu)) 1149 return 0; 1150 1151 if (!psp->xgmi_context.context.initialized) 1152 return 0; 1153 1154 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1155 1156 psp->xgmi_context.context.initialized = false; 1157 1158 return ret; 1159 } 1160 1161 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1162 { 1163 struct ta_xgmi_shared_memory *xgmi_cmd; 1164 int ret; 1165 1166 if (!psp->ta_fw || 1167 !psp->xgmi_context.context.bin_desc.size_bytes || 1168 !psp->xgmi_context.context.bin_desc.start_addr) 1169 return -ENOENT; 1170 1171 if (!load_ta) 1172 goto invoke; 1173 1174 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1175 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1176 1177 if (!psp->xgmi_context.context.initialized) { 1178 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1179 if (ret) 1180 return ret; 1181 } 1182 1183 /* Load XGMI TA */ 1184 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1185 if (!ret) 1186 psp->xgmi_context.context.initialized = true; 1187 else 1188 return ret; 1189 1190 invoke: 1191 /* Initialize XGMI session */ 1192 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1193 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1194 xgmi_cmd->flag_extend_link_record = set_extended_data; 1195 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1196 1197 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1198 1199 return ret; 1200 } 1201 1202 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1203 { 1204 struct ta_xgmi_shared_memory *xgmi_cmd; 1205 int ret; 1206 1207 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1208 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1209 1210 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1211 1212 /* Invoke xgmi ta to get hive id */ 1213 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1214 if (ret) 1215 return ret; 1216 1217 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1218 1219 return 0; 1220 } 1221 1222 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1223 { 1224 struct ta_xgmi_shared_memory *xgmi_cmd; 1225 int ret; 1226 1227 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1228 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1229 1230 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1231 1232 /* Invoke xgmi ta to get the node id */ 1233 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1234 if (ret) 1235 return ret; 1236 1237 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1238 1239 return 0; 1240 } 1241 1242 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1243 { 1244 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1245 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1246 } 1247 1248 /* 1249 * Chips that support extended topology information require the driver to 1250 * reflect topology information in the opposite direction. This is 1251 * because the TA has already exceeded its link record limit and if the 1252 * TA holds bi-directional information, the driver would have to do 1253 * multiple fetches instead of just two. 1254 */ 1255 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1256 struct psp_xgmi_node_info node_info) 1257 { 1258 struct amdgpu_device *mirror_adev; 1259 struct amdgpu_hive_info *hive; 1260 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1261 uint64_t dst_node_id = node_info.node_id; 1262 uint8_t dst_num_hops = node_info.num_hops; 1263 uint8_t dst_num_links = node_info.num_links; 1264 1265 hive = amdgpu_get_xgmi_hive(psp->adev); 1266 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1267 struct psp_xgmi_topology_info *mirror_top_info; 1268 int j; 1269 1270 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1271 continue; 1272 1273 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1274 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1275 if (mirror_top_info->nodes[j].node_id != src_node_id) 1276 continue; 1277 1278 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1279 /* 1280 * prevent 0 num_links value re-reflection since reflection 1281 * criteria is based on num_hops (direct or indirect). 1282 * 1283 */ 1284 if (dst_num_links) 1285 mirror_top_info->nodes[j].num_links = dst_num_links; 1286 1287 break; 1288 } 1289 1290 break; 1291 } 1292 } 1293 1294 int psp_xgmi_get_topology_info(struct psp_context *psp, 1295 int number_devices, 1296 struct psp_xgmi_topology_info *topology, 1297 bool get_extended_data) 1298 { 1299 struct ta_xgmi_shared_memory *xgmi_cmd; 1300 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1301 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1302 int i; 1303 int ret; 1304 1305 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1306 return -EINVAL; 1307 1308 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1309 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1310 xgmi_cmd->flag_extend_link_record = get_extended_data; 1311 1312 /* Fill in the shared memory with topology information as input */ 1313 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1314 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1315 topology_info_input->num_nodes = number_devices; 1316 1317 for (i = 0; i < topology_info_input->num_nodes; i++) { 1318 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1319 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1320 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1321 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1322 } 1323 1324 /* Invoke xgmi ta to get the topology information */ 1325 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1326 if (ret) 1327 return ret; 1328 1329 /* Read the output topology information from the shared memory */ 1330 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1331 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1332 for (i = 0; i < topology->num_nodes; i++) { 1333 /* extended data will either be 0 or equal to non-extended data */ 1334 if (topology_info_output->nodes[i].num_hops) 1335 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1336 1337 /* non-extended data gets everything here so no need to update */ 1338 if (!get_extended_data) { 1339 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1340 topology->nodes[i].is_sharing_enabled = 1341 topology_info_output->nodes[i].is_sharing_enabled; 1342 topology->nodes[i].sdma_engine = 1343 topology_info_output->nodes[i].sdma_engine; 1344 } 1345 1346 } 1347 1348 /* Invoke xgmi ta again to get the link information */ 1349 if (psp_xgmi_peer_link_info_supported(psp)) { 1350 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1351 1352 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1353 1354 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1355 1356 if (ret) 1357 return ret; 1358 1359 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1360 for (i = 0; i < topology->num_nodes; i++) { 1361 /* accumulate num_links on extended data */ 1362 topology->nodes[i].num_links = get_extended_data ? 1363 topology->nodes[i].num_links + 1364 link_info_output->nodes[i].num_links : 1365 link_info_output->nodes[i].num_links; 1366 1367 /* reflect the topology information for bi-directionality */ 1368 if (psp->xgmi_context.supports_extended_data && 1369 get_extended_data && topology->nodes[i].num_hops) 1370 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1371 } 1372 } 1373 1374 return 0; 1375 } 1376 1377 int psp_xgmi_set_topology_info(struct psp_context *psp, 1378 int number_devices, 1379 struct psp_xgmi_topology_info *topology) 1380 { 1381 struct ta_xgmi_shared_memory *xgmi_cmd; 1382 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1383 int i; 1384 1385 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1386 return -EINVAL; 1387 1388 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1389 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1390 1391 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1392 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1393 topology_info_input->num_nodes = number_devices; 1394 1395 for (i = 0; i < topology_info_input->num_nodes; i++) { 1396 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1397 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1398 topology_info_input->nodes[i].is_sharing_enabled = 1; 1399 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1400 } 1401 1402 /* Invoke xgmi ta to set topology information */ 1403 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1404 } 1405 1406 // ras begin 1407 static void psp_ras_ta_check_status(struct psp_context *psp) 1408 { 1409 struct ta_ras_shared_memory *ras_cmd = 1410 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1411 1412 switch (ras_cmd->ras_status) { 1413 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1414 dev_warn(psp->adev->dev, 1415 "RAS WARNING: cmd failed due to unsupported ip\n"); 1416 break; 1417 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1418 dev_warn(psp->adev->dev, 1419 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1420 break; 1421 case TA_RAS_STATUS__SUCCESS: 1422 break; 1423 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1424 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1425 dev_warn(psp->adev->dev, 1426 "RAS WARNING: Inject error to critical region is not allowed\n"); 1427 break; 1428 default: 1429 dev_warn(psp->adev->dev, 1430 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1431 break; 1432 } 1433 } 1434 1435 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1436 { 1437 struct ta_ras_shared_memory *ras_cmd; 1438 int ret; 1439 1440 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1441 1442 /* 1443 * TODO: bypass the loading in sriov for now 1444 */ 1445 if (amdgpu_sriov_vf(psp->adev)) 1446 return 0; 1447 1448 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1449 1450 if (amdgpu_ras_intr_triggered()) 1451 return ret; 1452 1453 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1454 { 1455 DRM_WARN("RAS: Unsupported Interface"); 1456 return -EINVAL; 1457 } 1458 1459 if (!ret) { 1460 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1461 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1462 1463 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1464 } 1465 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1466 dev_warn(psp->adev->dev, 1467 "RAS internal register access blocked\n"); 1468 1469 psp_ras_ta_check_status(psp); 1470 } 1471 1472 return ret; 1473 } 1474 1475 int psp_ras_enable_features(struct psp_context *psp, 1476 union ta_ras_cmd_input *info, bool enable) 1477 { 1478 struct ta_ras_shared_memory *ras_cmd; 1479 int ret; 1480 1481 if (!psp->ras_context.context.initialized) 1482 return -EINVAL; 1483 1484 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1485 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1486 1487 if (enable) 1488 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1489 else 1490 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1491 1492 ras_cmd->ras_in_message = *info; 1493 1494 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1495 if (ret) 1496 return -EINVAL; 1497 1498 return 0; 1499 } 1500 1501 int psp_ras_terminate(struct psp_context *psp) 1502 { 1503 int ret; 1504 1505 /* 1506 * TODO: bypass the terminate in sriov for now 1507 */ 1508 if (amdgpu_sriov_vf(psp->adev)) 1509 return 0; 1510 1511 if (!psp->ras_context.context.initialized) 1512 return 0; 1513 1514 ret = psp_ta_unload(psp, &psp->ras_context.context); 1515 1516 psp->ras_context.context.initialized = false; 1517 1518 return ret; 1519 } 1520 1521 static int psp_ras_initialize(struct psp_context *psp) 1522 { 1523 int ret; 1524 uint32_t boot_cfg = 0xFF; 1525 struct amdgpu_device *adev = psp->adev; 1526 struct ta_ras_shared_memory *ras_cmd; 1527 1528 /* 1529 * TODO: bypass the initialize in sriov for now 1530 */ 1531 if (amdgpu_sriov_vf(adev)) 1532 return 0; 1533 1534 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1535 !adev->psp.ras_context.context.bin_desc.start_addr) { 1536 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1537 return 0; 1538 } 1539 1540 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1541 /* query GECC enablement status from boot config 1542 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1543 */ 1544 ret = psp_boot_config_get(adev, &boot_cfg); 1545 if (ret) 1546 dev_warn(adev->dev, "PSP get boot config failed\n"); 1547 1548 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1549 if (!boot_cfg) { 1550 dev_info(adev->dev, "GECC is disabled\n"); 1551 } else { 1552 /* disable GECC in next boot cycle if ras is 1553 * disabled by module parameter amdgpu_ras_enable 1554 * and/or amdgpu_ras_mask, or boot_config_get call 1555 * is failed 1556 */ 1557 ret = psp_boot_config_set(adev, 0); 1558 if (ret) 1559 dev_warn(adev->dev, "PSP set boot config failed\n"); 1560 else 1561 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1562 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1563 } 1564 } else { 1565 if (1 == boot_cfg) { 1566 dev_info(adev->dev, "GECC is enabled\n"); 1567 } else { 1568 /* enable GECC in next boot cycle if it is disabled 1569 * in boot config, or force enable GECC if failed to 1570 * get boot configuration 1571 */ 1572 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1573 if (ret) 1574 dev_warn(adev->dev, "PSP set boot config failed\n"); 1575 else 1576 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1577 } 1578 } 1579 } 1580 1581 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1582 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1583 1584 if (!psp->ras_context.context.initialized) { 1585 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1586 if (ret) 1587 return ret; 1588 } 1589 1590 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1591 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1592 1593 if (amdgpu_ras_is_poison_mode_supported(adev)) 1594 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1595 if (!adev->gmc.xgmi.connected_to_cpu) 1596 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1597 1598 ret = psp_ta_load(psp, &psp->ras_context.context); 1599 1600 if (!ret && !ras_cmd->ras_status) 1601 psp->ras_context.context.initialized = true; 1602 else { 1603 if (ras_cmd->ras_status) 1604 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1605 amdgpu_ras_fini(psp->adev); 1606 } 1607 1608 return ret; 1609 } 1610 1611 int psp_ras_trigger_error(struct psp_context *psp, 1612 struct ta_ras_trigger_error_input *info) 1613 { 1614 struct ta_ras_shared_memory *ras_cmd; 1615 int ret; 1616 1617 if (!psp->ras_context.context.initialized) 1618 return -EINVAL; 1619 1620 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1621 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1622 1623 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1624 ras_cmd->ras_in_message.trigger_error = *info; 1625 1626 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1627 if (ret) 1628 return -EINVAL; 1629 1630 /* If err_event_athub occurs error inject was successful, however 1631 return status from TA is no long reliable */ 1632 if (amdgpu_ras_intr_triggered()) 1633 return 0; 1634 1635 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1636 return -EACCES; 1637 else if (ras_cmd->ras_status) 1638 return -EINVAL; 1639 1640 return 0; 1641 } 1642 // ras end 1643 1644 // HDCP start 1645 static int psp_hdcp_initialize(struct psp_context *psp) 1646 { 1647 int ret; 1648 1649 /* 1650 * TODO: bypass the initialize in sriov for now 1651 */ 1652 if (amdgpu_sriov_vf(psp->adev)) 1653 return 0; 1654 1655 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1656 !psp->hdcp_context.context.bin_desc.start_addr) { 1657 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1658 return 0; 1659 } 1660 1661 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1662 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1663 1664 if (!psp->hdcp_context.context.initialized) { 1665 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1666 if (ret) 1667 return ret; 1668 } 1669 1670 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1671 if (!ret) { 1672 psp->hdcp_context.context.initialized = true; 1673 mutex_init(&psp->hdcp_context.mutex); 1674 } 1675 1676 return ret; 1677 } 1678 1679 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1680 { 1681 /* 1682 * TODO: bypass the loading in sriov for now 1683 */ 1684 if (amdgpu_sriov_vf(psp->adev)) 1685 return 0; 1686 1687 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1688 } 1689 1690 static int psp_hdcp_terminate(struct psp_context *psp) 1691 { 1692 int ret; 1693 1694 /* 1695 * TODO: bypass the terminate in sriov for now 1696 */ 1697 if (amdgpu_sriov_vf(psp->adev)) 1698 return 0; 1699 1700 if (!psp->hdcp_context.context.initialized) 1701 return 0; 1702 1703 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1704 1705 psp->hdcp_context.context.initialized = false; 1706 1707 return ret; 1708 } 1709 // HDCP end 1710 1711 // DTM start 1712 static int psp_dtm_initialize(struct psp_context *psp) 1713 { 1714 int ret; 1715 1716 /* 1717 * TODO: bypass the initialize in sriov for now 1718 */ 1719 if (amdgpu_sriov_vf(psp->adev)) 1720 return 0; 1721 1722 if (!psp->dtm_context.context.bin_desc.size_bytes || 1723 !psp->dtm_context.context.bin_desc.start_addr) { 1724 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1725 return 0; 1726 } 1727 1728 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1729 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1730 1731 if (!psp->dtm_context.context.initialized) { 1732 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1733 if (ret) 1734 return ret; 1735 } 1736 1737 ret = psp_ta_load(psp, &psp->dtm_context.context); 1738 if (!ret) { 1739 psp->dtm_context.context.initialized = true; 1740 mutex_init(&psp->dtm_context.mutex); 1741 } 1742 1743 return ret; 1744 } 1745 1746 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1747 { 1748 /* 1749 * TODO: bypass the loading in sriov for now 1750 */ 1751 if (amdgpu_sriov_vf(psp->adev)) 1752 return 0; 1753 1754 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1755 } 1756 1757 static int psp_dtm_terminate(struct psp_context *psp) 1758 { 1759 int ret; 1760 1761 /* 1762 * TODO: bypass the terminate in sriov for now 1763 */ 1764 if (amdgpu_sriov_vf(psp->adev)) 1765 return 0; 1766 1767 if (!psp->dtm_context.context.initialized) 1768 return 0; 1769 1770 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1771 1772 psp->dtm_context.context.initialized = false; 1773 1774 return ret; 1775 } 1776 // DTM end 1777 1778 // RAP start 1779 static int psp_rap_initialize(struct psp_context *psp) 1780 { 1781 int ret; 1782 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1783 1784 /* 1785 * TODO: bypass the initialize in sriov for now 1786 */ 1787 if (amdgpu_sriov_vf(psp->adev)) 1788 return 0; 1789 1790 if (!psp->rap_context.context.bin_desc.size_bytes || 1791 !psp->rap_context.context.bin_desc.start_addr) { 1792 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1793 return 0; 1794 } 1795 1796 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1797 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1798 1799 if (!psp->rap_context.context.initialized) { 1800 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1801 if (ret) 1802 return ret; 1803 } 1804 1805 ret = psp_ta_load(psp, &psp->rap_context.context); 1806 if (!ret) { 1807 psp->rap_context.context.initialized = true; 1808 mutex_init(&psp->rap_context.mutex); 1809 } else 1810 return ret; 1811 1812 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1813 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1814 psp_rap_terminate(psp); 1815 /* free rap shared memory */ 1816 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1817 1818 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1819 ret, status); 1820 1821 return ret; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static int psp_rap_terminate(struct psp_context *psp) 1828 { 1829 int ret; 1830 1831 if (!psp->rap_context.context.initialized) 1832 return 0; 1833 1834 ret = psp_ta_unload(psp, &psp->rap_context.context); 1835 1836 psp->rap_context.context.initialized = false; 1837 1838 return ret; 1839 } 1840 1841 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1842 { 1843 struct ta_rap_shared_memory *rap_cmd; 1844 int ret = 0; 1845 1846 if (!psp->rap_context.context.initialized) 1847 return 0; 1848 1849 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1850 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1851 return -EINVAL; 1852 1853 mutex_lock(&psp->rap_context.mutex); 1854 1855 rap_cmd = (struct ta_rap_shared_memory *) 1856 psp->rap_context.context.mem_context.shared_buf; 1857 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1858 1859 rap_cmd->cmd_id = ta_cmd_id; 1860 rap_cmd->validation_method_id = METHOD_A; 1861 1862 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1863 if (ret) 1864 goto out_unlock; 1865 1866 if (status) 1867 *status = rap_cmd->rap_status; 1868 1869 out_unlock: 1870 mutex_unlock(&psp->rap_context.mutex); 1871 1872 return ret; 1873 } 1874 // RAP end 1875 1876 /* securedisplay start */ 1877 static int psp_securedisplay_initialize(struct psp_context *psp) 1878 { 1879 int ret; 1880 struct securedisplay_cmd *securedisplay_cmd; 1881 1882 /* 1883 * TODO: bypass the initialize in sriov for now 1884 */ 1885 if (amdgpu_sriov_vf(psp->adev)) 1886 return 0; 1887 1888 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1889 !psp->securedisplay_context.context.bin_desc.start_addr) { 1890 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1891 return 0; 1892 } 1893 1894 psp->securedisplay_context.context.mem_context.shared_mem_size = 1895 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1896 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1897 1898 if (!psp->securedisplay_context.context.initialized) { 1899 ret = psp_ta_init_shared_buf(psp, 1900 &psp->securedisplay_context.context.mem_context); 1901 if (ret) 1902 return ret; 1903 } 1904 1905 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1906 if (!ret) { 1907 psp->securedisplay_context.context.initialized = true; 1908 mutex_init(&psp->securedisplay_context.mutex); 1909 } else 1910 return ret; 1911 1912 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1913 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1914 1915 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1916 if (ret) { 1917 psp_securedisplay_terminate(psp); 1918 /* free securedisplay shared memory */ 1919 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1920 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1921 return -EINVAL; 1922 } 1923 1924 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1925 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1926 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1927 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1928 } 1929 1930 return 0; 1931 } 1932 1933 static int psp_securedisplay_terminate(struct psp_context *psp) 1934 { 1935 int ret; 1936 1937 /* 1938 * TODO:bypass the terminate in sriov for now 1939 */ 1940 if (amdgpu_sriov_vf(psp->adev)) 1941 return 0; 1942 1943 if (!psp->securedisplay_context.context.initialized) 1944 return 0; 1945 1946 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1947 1948 psp->securedisplay_context.context.initialized = false; 1949 1950 return ret; 1951 } 1952 1953 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1954 { 1955 int ret; 1956 1957 if (!psp->securedisplay_context.context.initialized) 1958 return -EINVAL; 1959 1960 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1961 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1962 return -EINVAL; 1963 1964 mutex_lock(&psp->securedisplay_context.mutex); 1965 1966 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1967 1968 mutex_unlock(&psp->securedisplay_context.mutex); 1969 1970 return ret; 1971 } 1972 /* SECUREDISPLAY end */ 1973 1974 static int psp_hw_start(struct psp_context *psp) 1975 { 1976 struct amdgpu_device *adev = psp->adev; 1977 int ret; 1978 1979 if (!amdgpu_sriov_vf(adev)) { 1980 if ((is_psp_fw_valid(psp->kdb)) && 1981 (psp->funcs->bootloader_load_kdb != NULL)) { 1982 ret = psp_bootloader_load_kdb(psp); 1983 if (ret) { 1984 DRM_ERROR("PSP load kdb failed!\n"); 1985 return ret; 1986 } 1987 } 1988 1989 if ((is_psp_fw_valid(psp->spl)) && 1990 (psp->funcs->bootloader_load_spl != NULL)) { 1991 ret = psp_bootloader_load_spl(psp); 1992 if (ret) { 1993 DRM_ERROR("PSP load spl failed!\n"); 1994 return ret; 1995 } 1996 } 1997 1998 if ((is_psp_fw_valid(psp->sys)) && 1999 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2000 ret = psp_bootloader_load_sysdrv(psp); 2001 if (ret) { 2002 DRM_ERROR("PSP load sys drv failed!\n"); 2003 return ret; 2004 } 2005 } 2006 2007 if ((is_psp_fw_valid(psp->soc_drv)) && 2008 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2009 ret = psp_bootloader_load_soc_drv(psp); 2010 if (ret) { 2011 DRM_ERROR("PSP load soc drv failed!\n"); 2012 return ret; 2013 } 2014 } 2015 2016 if ((is_psp_fw_valid(psp->intf_drv)) && 2017 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2018 ret = psp_bootloader_load_intf_drv(psp); 2019 if (ret) { 2020 DRM_ERROR("PSP load intf drv failed!\n"); 2021 return ret; 2022 } 2023 } 2024 2025 if ((is_psp_fw_valid(psp->dbg_drv)) && 2026 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2027 ret = psp_bootloader_load_dbg_drv(psp); 2028 if (ret) { 2029 DRM_ERROR("PSP load dbg drv failed!\n"); 2030 return ret; 2031 } 2032 } 2033 2034 if ((is_psp_fw_valid(psp->sos)) && 2035 (psp->funcs->bootloader_load_sos != NULL)) { 2036 ret = psp_bootloader_load_sos(psp); 2037 if (ret) { 2038 DRM_ERROR("PSP load sos failed!\n"); 2039 return ret; 2040 } 2041 } 2042 } 2043 2044 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2045 if (ret) { 2046 DRM_ERROR("PSP create ring failed!\n"); 2047 return ret; 2048 } 2049 2050 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2051 goto skip_pin_bo; 2052 2053 ret = psp_tmr_init(psp); 2054 if (ret) { 2055 DRM_ERROR("PSP tmr init failed!\n"); 2056 return ret; 2057 } 2058 2059 skip_pin_bo: 2060 /* 2061 * For ASICs with DF Cstate management centralized 2062 * to PMFW, TMR setup should be performed after PMFW 2063 * loaded and before other non-psp firmware loaded. 2064 */ 2065 if (psp->pmfw_centralized_cstate_management) { 2066 ret = psp_load_smu_fw(psp); 2067 if (ret) 2068 return ret; 2069 } 2070 2071 ret = psp_tmr_load(psp); 2072 if (ret) { 2073 DRM_ERROR("PSP load tmr failed!\n"); 2074 return ret; 2075 } 2076 2077 return 0; 2078 } 2079 2080 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2081 enum psp_gfx_fw_type *type) 2082 { 2083 switch (ucode->ucode_id) { 2084 case AMDGPU_UCODE_ID_CAP: 2085 *type = GFX_FW_TYPE_CAP; 2086 break; 2087 case AMDGPU_UCODE_ID_SDMA0: 2088 *type = GFX_FW_TYPE_SDMA0; 2089 break; 2090 case AMDGPU_UCODE_ID_SDMA1: 2091 *type = GFX_FW_TYPE_SDMA1; 2092 break; 2093 case AMDGPU_UCODE_ID_SDMA2: 2094 *type = GFX_FW_TYPE_SDMA2; 2095 break; 2096 case AMDGPU_UCODE_ID_SDMA3: 2097 *type = GFX_FW_TYPE_SDMA3; 2098 break; 2099 case AMDGPU_UCODE_ID_SDMA4: 2100 *type = GFX_FW_TYPE_SDMA4; 2101 break; 2102 case AMDGPU_UCODE_ID_SDMA5: 2103 *type = GFX_FW_TYPE_SDMA5; 2104 break; 2105 case AMDGPU_UCODE_ID_SDMA6: 2106 *type = GFX_FW_TYPE_SDMA6; 2107 break; 2108 case AMDGPU_UCODE_ID_SDMA7: 2109 *type = GFX_FW_TYPE_SDMA7; 2110 break; 2111 case AMDGPU_UCODE_ID_CP_MES: 2112 *type = GFX_FW_TYPE_CP_MES; 2113 break; 2114 case AMDGPU_UCODE_ID_CP_MES_DATA: 2115 *type = GFX_FW_TYPE_MES_STACK; 2116 break; 2117 case AMDGPU_UCODE_ID_CP_MES1: 2118 *type = GFX_FW_TYPE_CP_MES_KIQ; 2119 break; 2120 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2121 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2122 break; 2123 case AMDGPU_UCODE_ID_CP_CE: 2124 *type = GFX_FW_TYPE_CP_CE; 2125 break; 2126 case AMDGPU_UCODE_ID_CP_PFP: 2127 *type = GFX_FW_TYPE_CP_PFP; 2128 break; 2129 case AMDGPU_UCODE_ID_CP_ME: 2130 *type = GFX_FW_TYPE_CP_ME; 2131 break; 2132 case AMDGPU_UCODE_ID_CP_MEC1: 2133 *type = GFX_FW_TYPE_CP_MEC; 2134 break; 2135 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2136 *type = GFX_FW_TYPE_CP_MEC_ME1; 2137 break; 2138 case AMDGPU_UCODE_ID_CP_MEC2: 2139 *type = GFX_FW_TYPE_CP_MEC; 2140 break; 2141 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2142 *type = GFX_FW_TYPE_CP_MEC_ME2; 2143 break; 2144 case AMDGPU_UCODE_ID_RLC_P: 2145 *type = GFX_FW_TYPE_RLC_P; 2146 break; 2147 case AMDGPU_UCODE_ID_RLC_V: 2148 *type = GFX_FW_TYPE_RLC_V; 2149 break; 2150 case AMDGPU_UCODE_ID_RLC_G: 2151 *type = GFX_FW_TYPE_RLC_G; 2152 break; 2153 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2154 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2155 break; 2156 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2157 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2158 break; 2159 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2160 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2161 break; 2162 case AMDGPU_UCODE_ID_RLC_IRAM: 2163 *type = GFX_FW_TYPE_RLC_IRAM; 2164 break; 2165 case AMDGPU_UCODE_ID_RLC_DRAM: 2166 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2167 break; 2168 case AMDGPU_UCODE_ID_SMC: 2169 *type = GFX_FW_TYPE_SMU; 2170 break; 2171 case AMDGPU_UCODE_ID_PPTABLE: 2172 *type = GFX_FW_TYPE_PPTABLE; 2173 break; 2174 case AMDGPU_UCODE_ID_UVD: 2175 *type = GFX_FW_TYPE_UVD; 2176 break; 2177 case AMDGPU_UCODE_ID_UVD1: 2178 *type = GFX_FW_TYPE_UVD1; 2179 break; 2180 case AMDGPU_UCODE_ID_VCE: 2181 *type = GFX_FW_TYPE_VCE; 2182 break; 2183 case AMDGPU_UCODE_ID_VCN: 2184 *type = GFX_FW_TYPE_VCN; 2185 break; 2186 case AMDGPU_UCODE_ID_VCN1: 2187 *type = GFX_FW_TYPE_VCN1; 2188 break; 2189 case AMDGPU_UCODE_ID_DMCU_ERAM: 2190 *type = GFX_FW_TYPE_DMCU_ERAM; 2191 break; 2192 case AMDGPU_UCODE_ID_DMCU_INTV: 2193 *type = GFX_FW_TYPE_DMCU_ISR; 2194 break; 2195 case AMDGPU_UCODE_ID_VCN0_RAM: 2196 *type = GFX_FW_TYPE_VCN0_RAM; 2197 break; 2198 case AMDGPU_UCODE_ID_VCN1_RAM: 2199 *type = GFX_FW_TYPE_VCN1_RAM; 2200 break; 2201 case AMDGPU_UCODE_ID_DMCUB: 2202 *type = GFX_FW_TYPE_DMUB; 2203 break; 2204 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2205 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2206 break; 2207 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2208 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2209 break; 2210 case AMDGPU_UCODE_ID_IMU_I: 2211 *type = GFX_FW_TYPE_IMU_I; 2212 break; 2213 case AMDGPU_UCODE_ID_IMU_D: 2214 *type = GFX_FW_TYPE_IMU_D; 2215 break; 2216 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2217 *type = GFX_FW_TYPE_RS64_PFP; 2218 break; 2219 case AMDGPU_UCODE_ID_CP_RS64_ME: 2220 *type = GFX_FW_TYPE_RS64_ME; 2221 break; 2222 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2223 *type = GFX_FW_TYPE_RS64_MEC; 2224 break; 2225 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2226 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2227 break; 2228 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2229 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2230 break; 2231 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2232 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2233 break; 2234 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2235 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2236 break; 2237 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2238 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2239 break; 2240 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2241 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2242 break; 2243 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2244 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2245 break; 2246 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2247 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2248 break; 2249 case AMDGPU_UCODE_ID_MAXIMUM: 2250 default: 2251 return -EINVAL; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static void psp_print_fw_hdr(struct psp_context *psp, 2258 struct amdgpu_firmware_info *ucode) 2259 { 2260 struct amdgpu_device *adev = psp->adev; 2261 struct common_firmware_header *hdr; 2262 2263 switch (ucode->ucode_id) { 2264 case AMDGPU_UCODE_ID_SDMA0: 2265 case AMDGPU_UCODE_ID_SDMA1: 2266 case AMDGPU_UCODE_ID_SDMA2: 2267 case AMDGPU_UCODE_ID_SDMA3: 2268 case AMDGPU_UCODE_ID_SDMA4: 2269 case AMDGPU_UCODE_ID_SDMA5: 2270 case AMDGPU_UCODE_ID_SDMA6: 2271 case AMDGPU_UCODE_ID_SDMA7: 2272 hdr = (struct common_firmware_header *) 2273 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2274 amdgpu_ucode_print_sdma_hdr(hdr); 2275 break; 2276 case AMDGPU_UCODE_ID_CP_CE: 2277 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2278 amdgpu_ucode_print_gfx_hdr(hdr); 2279 break; 2280 case AMDGPU_UCODE_ID_CP_PFP: 2281 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2282 amdgpu_ucode_print_gfx_hdr(hdr); 2283 break; 2284 case AMDGPU_UCODE_ID_CP_ME: 2285 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2286 amdgpu_ucode_print_gfx_hdr(hdr); 2287 break; 2288 case AMDGPU_UCODE_ID_CP_MEC1: 2289 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2290 amdgpu_ucode_print_gfx_hdr(hdr); 2291 break; 2292 case AMDGPU_UCODE_ID_RLC_G: 2293 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2294 amdgpu_ucode_print_rlc_hdr(hdr); 2295 break; 2296 case AMDGPU_UCODE_ID_SMC: 2297 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2298 amdgpu_ucode_print_smc_hdr(hdr); 2299 break; 2300 default: 2301 break; 2302 } 2303 } 2304 2305 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2306 struct psp_gfx_cmd_resp *cmd) 2307 { 2308 int ret; 2309 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2310 2311 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2312 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2313 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2314 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2315 2316 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2317 if (ret) 2318 DRM_ERROR("Unknown firmware type\n"); 2319 2320 return ret; 2321 } 2322 2323 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2324 struct amdgpu_firmware_info *ucode) 2325 { 2326 int ret = 0; 2327 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2328 2329 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2330 if (!ret) { 2331 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2332 psp->fence_buf_mc_addr); 2333 } 2334 2335 release_psp_cmd_buf(psp); 2336 2337 return ret; 2338 } 2339 2340 static int psp_load_smu_fw(struct psp_context *psp) 2341 { 2342 int ret; 2343 struct amdgpu_device *adev = psp->adev; 2344 struct amdgpu_firmware_info *ucode = 2345 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2346 struct amdgpu_ras *ras = psp->ras_context.ras; 2347 2348 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2349 return 0; 2350 2351 if ((amdgpu_in_reset(adev) && 2352 ras && adev->ras_enabled && 2353 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2354 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2355 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2356 if (ret) { 2357 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2358 } 2359 } 2360 2361 ret = psp_execute_non_psp_fw_load(psp, ucode); 2362 2363 if (ret) 2364 DRM_ERROR("PSP load smu failed!\n"); 2365 2366 return ret; 2367 } 2368 2369 static bool fw_load_skip_check(struct psp_context *psp, 2370 struct amdgpu_firmware_info *ucode) 2371 { 2372 if (!ucode->fw) 2373 return true; 2374 2375 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2376 (psp_smu_reload_quirk(psp) || 2377 psp->autoload_supported || 2378 psp->pmfw_centralized_cstate_management)) 2379 return true; 2380 2381 if (amdgpu_sriov_vf(psp->adev) && 2382 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2383 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2384 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2385 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2386 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2387 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2388 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2389 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2390 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2391 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2392 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2393 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2394 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2395 /*skip ucode loading in SRIOV VF */ 2396 return true; 2397 2398 if (psp->autoload_supported && 2399 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2400 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2401 /* skip mec JT when autoload is enabled */ 2402 return true; 2403 2404 return false; 2405 } 2406 2407 int psp_load_fw_list(struct psp_context *psp, 2408 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2409 { 2410 int ret = 0, i; 2411 struct amdgpu_firmware_info *ucode; 2412 2413 for (i = 0; i < ucode_count; ++i) { 2414 ucode = ucode_list[i]; 2415 psp_print_fw_hdr(psp, ucode); 2416 ret = psp_execute_non_psp_fw_load(psp, ucode); 2417 if (ret) 2418 return ret; 2419 } 2420 return ret; 2421 } 2422 2423 static int psp_load_non_psp_fw(struct psp_context *psp) 2424 { 2425 int i, ret; 2426 struct amdgpu_firmware_info *ucode; 2427 struct amdgpu_device *adev = psp->adev; 2428 2429 if (psp->autoload_supported && 2430 !psp->pmfw_centralized_cstate_management) { 2431 ret = psp_load_smu_fw(psp); 2432 if (ret) 2433 return ret; 2434 } 2435 2436 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2437 ucode = &adev->firmware.ucode[i]; 2438 2439 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2440 !fw_load_skip_check(psp, ucode)) { 2441 ret = psp_load_smu_fw(psp); 2442 if (ret) 2443 return ret; 2444 continue; 2445 } 2446 2447 if (fw_load_skip_check(psp, ucode)) 2448 continue; 2449 2450 if (psp->autoload_supported && 2451 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2452 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2453 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2454 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2455 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2456 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2457 /* PSP only receive one SDMA fw for sienna_cichlid, 2458 * as all four sdma fw are same */ 2459 continue; 2460 2461 psp_print_fw_hdr(psp, ucode); 2462 2463 ret = psp_execute_non_psp_fw_load(psp, ucode); 2464 if (ret) 2465 return ret; 2466 2467 /* Start rlc autoload after psp recieved all the gfx firmware */ 2468 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2469 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2470 ret = psp_rlc_autoload_start(psp); 2471 if (ret) { 2472 DRM_ERROR("Failed to start rlc autoload\n"); 2473 return ret; 2474 } 2475 } 2476 } 2477 2478 return 0; 2479 } 2480 2481 static int psp_load_fw(struct amdgpu_device *adev) 2482 { 2483 int ret; 2484 struct psp_context *psp = &adev->psp; 2485 2486 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2487 /* should not destroy ring, only stop */ 2488 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2489 } else { 2490 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2491 2492 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2493 if (ret) { 2494 DRM_ERROR("PSP ring init failed!\n"); 2495 goto failed; 2496 } 2497 } 2498 2499 ret = psp_hw_start(psp); 2500 if (ret) 2501 goto failed; 2502 2503 ret = psp_load_non_psp_fw(psp); 2504 if (ret) 2505 goto failed1; 2506 2507 ret = psp_asd_initialize(psp); 2508 if (ret) { 2509 DRM_ERROR("PSP load asd failed!\n"); 2510 goto failed1; 2511 } 2512 2513 ret = psp_rl_load(adev); 2514 if (ret) { 2515 DRM_ERROR("PSP load RL failed!\n"); 2516 goto failed1; 2517 } 2518 2519 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2520 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2521 ret = psp_xgmi_initialize(psp, false, true); 2522 /* Warning the XGMI seesion initialize failure 2523 * Instead of stop driver initialization 2524 */ 2525 if (ret) 2526 dev_err(psp->adev->dev, 2527 "XGMI: Failed to initialize XGMI session\n"); 2528 } 2529 } 2530 2531 if (psp->ta_fw) { 2532 ret = psp_ras_initialize(psp); 2533 if (ret) 2534 dev_err(psp->adev->dev, 2535 "RAS: Failed to initialize RAS\n"); 2536 2537 ret = psp_hdcp_initialize(psp); 2538 if (ret) 2539 dev_err(psp->adev->dev, 2540 "HDCP: Failed to initialize HDCP\n"); 2541 2542 ret = psp_dtm_initialize(psp); 2543 if (ret) 2544 dev_err(psp->adev->dev, 2545 "DTM: Failed to initialize DTM\n"); 2546 2547 ret = psp_rap_initialize(psp); 2548 if (ret) 2549 dev_err(psp->adev->dev, 2550 "RAP: Failed to initialize RAP\n"); 2551 2552 ret = psp_securedisplay_initialize(psp); 2553 if (ret) 2554 dev_err(psp->adev->dev, 2555 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2556 } 2557 2558 return 0; 2559 2560 failed1: 2561 psp_free_shared_bufs(psp); 2562 failed: 2563 /* 2564 * all cleanup jobs (xgmi terminate, ras terminate, 2565 * ring destroy, cmd/fence/fw buffers destory, 2566 * psp->cmd destory) are delayed to psp_hw_fini 2567 */ 2568 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2569 return ret; 2570 } 2571 2572 static int psp_hw_init(void *handle) 2573 { 2574 int ret; 2575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2576 2577 mutex_lock(&adev->firmware.mutex); 2578 /* 2579 * This sequence is just used on hw_init only once, no need on 2580 * resume. 2581 */ 2582 ret = amdgpu_ucode_init_bo(adev); 2583 if (ret) 2584 goto failed; 2585 2586 ret = psp_load_fw(adev); 2587 if (ret) { 2588 DRM_ERROR("PSP firmware loading failed\n"); 2589 goto failed; 2590 } 2591 2592 mutex_unlock(&adev->firmware.mutex); 2593 return 0; 2594 2595 failed: 2596 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2597 mutex_unlock(&adev->firmware.mutex); 2598 return -EINVAL; 2599 } 2600 2601 static int psp_hw_fini(void *handle) 2602 { 2603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2604 struct psp_context *psp = &adev->psp; 2605 2606 if (psp->ta_fw) { 2607 psp_ras_terminate(psp); 2608 psp_securedisplay_terminate(psp); 2609 psp_rap_terminate(psp); 2610 psp_dtm_terminate(psp); 2611 psp_hdcp_terminate(psp); 2612 } 2613 2614 psp_asd_terminate(psp); 2615 psp_tmr_terminate(psp); 2616 2617 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2618 2619 psp_free_shared_bufs(psp); 2620 2621 return 0; 2622 } 2623 2624 static int psp_suspend(void *handle) 2625 { 2626 int ret = 0; 2627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2628 struct psp_context *psp = &adev->psp; 2629 2630 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2631 psp->xgmi_context.context.initialized) { 2632 ret = psp_xgmi_terminate(psp); 2633 if (ret) { 2634 DRM_ERROR("Failed to terminate xgmi ta\n"); 2635 goto out; 2636 } 2637 } 2638 2639 if (psp->ta_fw) { 2640 ret = psp_ras_terminate(psp); 2641 if (ret) { 2642 DRM_ERROR("Failed to terminate ras ta\n"); 2643 goto out; 2644 } 2645 ret = psp_hdcp_terminate(psp); 2646 if (ret) { 2647 DRM_ERROR("Failed to terminate hdcp ta\n"); 2648 goto out; 2649 } 2650 ret = psp_dtm_terminate(psp); 2651 if (ret) { 2652 DRM_ERROR("Failed to terminate dtm ta\n"); 2653 goto out; 2654 } 2655 ret = psp_rap_terminate(psp); 2656 if (ret) { 2657 DRM_ERROR("Failed to terminate rap ta\n"); 2658 goto out; 2659 } 2660 ret = psp_securedisplay_terminate(psp); 2661 if (ret) { 2662 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2663 goto out; 2664 } 2665 } 2666 2667 ret = psp_asd_terminate(psp); 2668 if (ret) { 2669 DRM_ERROR("Failed to terminate asd\n"); 2670 goto out; 2671 } 2672 2673 ret = psp_tmr_terminate(psp); 2674 if (ret) { 2675 DRM_ERROR("Failed to terminate tmr\n"); 2676 goto out; 2677 } 2678 2679 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2680 if (ret) { 2681 DRM_ERROR("PSP ring stop failed\n"); 2682 } 2683 2684 out: 2685 psp_free_shared_bufs(psp); 2686 2687 return ret; 2688 } 2689 2690 static int psp_resume(void *handle) 2691 { 2692 int ret; 2693 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2694 struct psp_context *psp = &adev->psp; 2695 2696 DRM_INFO("PSP is resuming...\n"); 2697 2698 if (psp->mem_train_ctx.enable_mem_training) { 2699 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2700 if (ret) { 2701 DRM_ERROR("Failed to process memory training!\n"); 2702 return ret; 2703 } 2704 } 2705 2706 mutex_lock(&adev->firmware.mutex); 2707 2708 ret = psp_hw_start(psp); 2709 if (ret) 2710 goto failed; 2711 2712 ret = psp_load_non_psp_fw(psp); 2713 if (ret) 2714 goto failed; 2715 2716 ret = psp_asd_initialize(psp); 2717 if (ret) { 2718 DRM_ERROR("PSP load asd failed!\n"); 2719 goto failed; 2720 } 2721 2722 ret = psp_rl_load(adev); 2723 if (ret) { 2724 dev_err(adev->dev, "PSP load RL failed!\n"); 2725 goto failed; 2726 } 2727 2728 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2729 ret = psp_xgmi_initialize(psp, false, true); 2730 /* Warning the XGMI seesion initialize failure 2731 * Instead of stop driver initialization 2732 */ 2733 if (ret) 2734 dev_err(psp->adev->dev, 2735 "XGMI: Failed to initialize XGMI session\n"); 2736 } 2737 2738 if (psp->ta_fw) { 2739 ret = psp_ras_initialize(psp); 2740 if (ret) 2741 dev_err(psp->adev->dev, 2742 "RAS: Failed to initialize RAS\n"); 2743 2744 ret = psp_hdcp_initialize(psp); 2745 if (ret) 2746 dev_err(psp->adev->dev, 2747 "HDCP: Failed to initialize HDCP\n"); 2748 2749 ret = psp_dtm_initialize(psp); 2750 if (ret) 2751 dev_err(psp->adev->dev, 2752 "DTM: Failed to initialize DTM\n"); 2753 2754 ret = psp_rap_initialize(psp); 2755 if (ret) 2756 dev_err(psp->adev->dev, 2757 "RAP: Failed to initialize RAP\n"); 2758 2759 ret = psp_securedisplay_initialize(psp); 2760 if (ret) 2761 dev_err(psp->adev->dev, 2762 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2763 } 2764 2765 mutex_unlock(&adev->firmware.mutex); 2766 2767 return 0; 2768 2769 failed: 2770 DRM_ERROR("PSP resume failed\n"); 2771 mutex_unlock(&adev->firmware.mutex); 2772 return ret; 2773 } 2774 2775 int psp_gpu_reset(struct amdgpu_device *adev) 2776 { 2777 int ret; 2778 2779 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2780 return 0; 2781 2782 mutex_lock(&adev->psp.mutex); 2783 ret = psp_mode1_reset(&adev->psp); 2784 mutex_unlock(&adev->psp.mutex); 2785 2786 return ret; 2787 } 2788 2789 int psp_rlc_autoload_start(struct psp_context *psp) 2790 { 2791 int ret; 2792 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2793 2794 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2795 2796 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2797 psp->fence_buf_mc_addr); 2798 2799 release_psp_cmd_buf(psp); 2800 2801 return ret; 2802 } 2803 2804 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2805 uint64_t cmd_gpu_addr, int cmd_size) 2806 { 2807 struct amdgpu_firmware_info ucode = {0}; 2808 2809 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2810 AMDGPU_UCODE_ID_VCN0_RAM; 2811 ucode.mc_addr = cmd_gpu_addr; 2812 ucode.ucode_size = cmd_size; 2813 2814 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2815 } 2816 2817 int psp_ring_cmd_submit(struct psp_context *psp, 2818 uint64_t cmd_buf_mc_addr, 2819 uint64_t fence_mc_addr, 2820 int index) 2821 { 2822 unsigned int psp_write_ptr_reg = 0; 2823 struct psp_gfx_rb_frame *write_frame; 2824 struct psp_ring *ring = &psp->km_ring; 2825 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2826 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2827 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2828 struct amdgpu_device *adev = psp->adev; 2829 uint32_t ring_size_dw = ring->ring_size / 4; 2830 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2831 2832 /* KM (GPCOM) prepare write pointer */ 2833 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2834 2835 /* Update KM RB frame pointer to new frame */ 2836 /* write_frame ptr increments by size of rb_frame in bytes */ 2837 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2838 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2839 write_frame = ring_buffer_start; 2840 else 2841 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2842 /* Check invalid write_frame ptr address */ 2843 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2844 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2845 ring_buffer_start, ring_buffer_end, write_frame); 2846 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2847 return -EINVAL; 2848 } 2849 2850 /* Initialize KM RB frame */ 2851 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2852 2853 /* Update KM RB frame */ 2854 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2855 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2856 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2857 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2858 write_frame->fence_value = index; 2859 amdgpu_device_flush_hdp(adev, NULL); 2860 2861 /* Update the write Pointer in DWORDs */ 2862 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2863 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2864 return 0; 2865 } 2866 2867 int psp_init_asd_microcode(struct psp_context *psp, 2868 const char *chip_name) 2869 { 2870 struct amdgpu_device *adev = psp->adev; 2871 char fw_name[PSP_FW_NAME_LEN]; 2872 const struct psp_firmware_header_v1_0 *asd_hdr; 2873 int err = 0; 2874 2875 if (!chip_name) { 2876 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2877 return -EINVAL; 2878 } 2879 2880 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2881 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2882 if (err) 2883 goto out; 2884 2885 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2886 if (err) 2887 goto out; 2888 2889 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2890 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2891 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2892 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2893 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2894 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2895 return 0; 2896 out: 2897 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2898 release_firmware(adev->psp.asd_fw); 2899 adev->psp.asd_fw = NULL; 2900 return err; 2901 } 2902 2903 int psp_init_toc_microcode(struct psp_context *psp, 2904 const char *chip_name) 2905 { 2906 struct amdgpu_device *adev = psp->adev; 2907 char fw_name[PSP_FW_NAME_LEN]; 2908 const struct psp_firmware_header_v1_0 *toc_hdr; 2909 int err = 0; 2910 2911 if (!chip_name) { 2912 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2913 return -EINVAL; 2914 } 2915 2916 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2917 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2918 if (err) 2919 goto out; 2920 2921 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2922 if (err) 2923 goto out; 2924 2925 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2926 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2927 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2928 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2929 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2930 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2931 return 0; 2932 out: 2933 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2934 release_firmware(adev->psp.toc_fw); 2935 adev->psp.toc_fw = NULL; 2936 return err; 2937 } 2938 2939 static int parse_sos_bin_descriptor(struct psp_context *psp, 2940 const struct psp_fw_bin_desc *desc, 2941 const struct psp_firmware_header_v2_0 *sos_hdr) 2942 { 2943 uint8_t *ucode_start_addr = NULL; 2944 2945 if (!psp || !desc || !sos_hdr) 2946 return -EINVAL; 2947 2948 ucode_start_addr = (uint8_t *)sos_hdr + 2949 le32_to_cpu(desc->offset_bytes) + 2950 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2951 2952 switch (desc->fw_type) { 2953 case PSP_FW_TYPE_PSP_SOS: 2954 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2955 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2956 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2957 psp->sos.start_addr = ucode_start_addr; 2958 break; 2959 case PSP_FW_TYPE_PSP_SYS_DRV: 2960 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2961 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2962 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2963 psp->sys.start_addr = ucode_start_addr; 2964 break; 2965 case PSP_FW_TYPE_PSP_KDB: 2966 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2967 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2968 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2969 psp->kdb.start_addr = ucode_start_addr; 2970 break; 2971 case PSP_FW_TYPE_PSP_TOC: 2972 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2973 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2974 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2975 psp->toc.start_addr = ucode_start_addr; 2976 break; 2977 case PSP_FW_TYPE_PSP_SPL: 2978 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2979 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2980 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2981 psp->spl.start_addr = ucode_start_addr; 2982 break; 2983 case PSP_FW_TYPE_PSP_RL: 2984 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2985 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2986 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2987 psp->rl.start_addr = ucode_start_addr; 2988 break; 2989 case PSP_FW_TYPE_PSP_SOC_DRV: 2990 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2991 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2992 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2993 psp->soc_drv.start_addr = ucode_start_addr; 2994 break; 2995 case PSP_FW_TYPE_PSP_INTF_DRV: 2996 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2997 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2998 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2999 psp->intf_drv.start_addr = ucode_start_addr; 3000 break; 3001 case PSP_FW_TYPE_PSP_DBG_DRV: 3002 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3003 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3004 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3005 psp->dbg_drv.start_addr = ucode_start_addr; 3006 break; 3007 default: 3008 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3009 break; 3010 } 3011 3012 return 0; 3013 } 3014 3015 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3016 { 3017 const struct psp_firmware_header_v1_0 *sos_hdr; 3018 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3019 uint8_t *ucode_array_start_addr; 3020 3021 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3022 ucode_array_start_addr = (uint8_t *)sos_hdr + 3023 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3024 3025 if (adev->gmc.xgmi.connected_to_cpu || 3026 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3027 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3028 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3029 3030 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3031 adev->psp.sys.start_addr = ucode_array_start_addr; 3032 3033 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3034 adev->psp.sos.start_addr = ucode_array_start_addr + 3035 le32_to_cpu(sos_hdr->sos.offset_bytes); 3036 } else { 3037 /* Load alternate PSP SOS FW */ 3038 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3039 3040 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3041 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3042 3043 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3044 adev->psp.sys.start_addr = ucode_array_start_addr + 3045 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3046 3047 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3048 adev->psp.sos.start_addr = ucode_array_start_addr + 3049 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3050 } 3051 3052 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3053 dev_warn(adev->dev, "PSP SOS FW not available"); 3054 return -EINVAL; 3055 } 3056 3057 return 0; 3058 } 3059 3060 int psp_init_sos_microcode(struct psp_context *psp, 3061 const char *chip_name) 3062 { 3063 struct amdgpu_device *adev = psp->adev; 3064 char fw_name[PSP_FW_NAME_LEN]; 3065 const struct psp_firmware_header_v1_0 *sos_hdr; 3066 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3067 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3068 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3069 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3070 int err = 0; 3071 uint8_t *ucode_array_start_addr; 3072 int fw_index = 0; 3073 3074 if (!chip_name) { 3075 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3076 return -EINVAL; 3077 } 3078 3079 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3080 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3081 if (err) 3082 goto out; 3083 3084 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3085 if (err) 3086 goto out; 3087 3088 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3089 ucode_array_start_addr = (uint8_t *)sos_hdr + 3090 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3091 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3092 3093 switch (sos_hdr->header.header_version_major) { 3094 case 1: 3095 err = psp_init_sos_base_fw(adev); 3096 if (err) 3097 goto out; 3098 3099 if (sos_hdr->header.header_version_minor == 1) { 3100 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3101 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3102 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3103 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3104 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3105 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3106 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3107 } 3108 if (sos_hdr->header.header_version_minor == 2) { 3109 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3110 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3111 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3112 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3113 } 3114 if (sos_hdr->header.header_version_minor == 3) { 3115 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3116 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3117 adev->psp.toc.start_addr = ucode_array_start_addr + 3118 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3119 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3120 adev->psp.kdb.start_addr = ucode_array_start_addr + 3121 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3122 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3123 adev->psp.spl.start_addr = ucode_array_start_addr + 3124 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3125 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3126 adev->psp.rl.start_addr = ucode_array_start_addr + 3127 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3128 } 3129 break; 3130 case 2: 3131 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3132 3133 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3134 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3135 err = -EINVAL; 3136 goto out; 3137 } 3138 3139 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3140 err = parse_sos_bin_descriptor(psp, 3141 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3142 sos_hdr_v2_0); 3143 if (err) 3144 goto out; 3145 } 3146 break; 3147 default: 3148 dev_err(adev->dev, 3149 "unsupported psp sos firmware\n"); 3150 err = -EINVAL; 3151 goto out; 3152 } 3153 3154 return 0; 3155 out: 3156 dev_err(adev->dev, 3157 "failed to init sos firmware\n"); 3158 release_firmware(adev->psp.sos_fw); 3159 adev->psp.sos_fw = NULL; 3160 3161 return err; 3162 } 3163 3164 static int parse_ta_bin_descriptor(struct psp_context *psp, 3165 const struct psp_fw_bin_desc *desc, 3166 const struct ta_firmware_header_v2_0 *ta_hdr) 3167 { 3168 uint8_t *ucode_start_addr = NULL; 3169 3170 if (!psp || !desc || !ta_hdr) 3171 return -EINVAL; 3172 3173 ucode_start_addr = (uint8_t *)ta_hdr + 3174 le32_to_cpu(desc->offset_bytes) + 3175 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3176 3177 switch (desc->fw_type) { 3178 case TA_FW_TYPE_PSP_ASD: 3179 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3180 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3181 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3182 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3183 break; 3184 case TA_FW_TYPE_PSP_XGMI: 3185 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3186 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3187 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3188 break; 3189 case TA_FW_TYPE_PSP_RAS: 3190 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3191 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3192 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3193 break; 3194 case TA_FW_TYPE_PSP_HDCP: 3195 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3196 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3197 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3198 break; 3199 case TA_FW_TYPE_PSP_DTM: 3200 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3201 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3202 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3203 break; 3204 case TA_FW_TYPE_PSP_RAP: 3205 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3206 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3207 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3208 break; 3209 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3210 psp->securedisplay_context.context.bin_desc.fw_version = 3211 le32_to_cpu(desc->fw_version); 3212 psp->securedisplay_context.context.bin_desc.size_bytes = 3213 le32_to_cpu(desc->size_bytes); 3214 psp->securedisplay_context.context.bin_desc.start_addr = 3215 ucode_start_addr; 3216 break; 3217 default: 3218 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3219 break; 3220 } 3221 3222 return 0; 3223 } 3224 3225 int psp_init_ta_microcode(struct psp_context *psp, 3226 const char *chip_name) 3227 { 3228 struct amdgpu_device *adev = psp->adev; 3229 char fw_name[PSP_FW_NAME_LEN]; 3230 const struct ta_firmware_header_v2_0 *ta_hdr; 3231 int err = 0; 3232 int ta_index = 0; 3233 3234 if (!chip_name) { 3235 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3236 return -EINVAL; 3237 } 3238 3239 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3240 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3241 if (err) 3242 goto out; 3243 3244 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3245 if (err) 3246 goto out; 3247 3248 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3249 3250 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3251 dev_err(adev->dev, "unsupported TA header version\n"); 3252 err = -EINVAL; 3253 goto out; 3254 } 3255 3256 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3257 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3258 err = -EINVAL; 3259 goto out; 3260 } 3261 3262 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3263 err = parse_ta_bin_descriptor(psp, 3264 &ta_hdr->ta_fw_bin[ta_index], 3265 ta_hdr); 3266 if (err) 3267 goto out; 3268 } 3269 3270 return 0; 3271 out: 3272 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3273 release_firmware(adev->psp.ta_fw); 3274 adev->psp.ta_fw = NULL; 3275 return err; 3276 } 3277 3278 int psp_init_cap_microcode(struct psp_context *psp, 3279 const char *chip_name) 3280 { 3281 struct amdgpu_device *adev = psp->adev; 3282 char fw_name[PSP_FW_NAME_LEN]; 3283 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3284 struct amdgpu_firmware_info *info = NULL; 3285 int err = 0; 3286 3287 if (!chip_name) { 3288 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3289 return -EINVAL; 3290 } 3291 3292 if (!amdgpu_sriov_vf(adev)) { 3293 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3294 return -EINVAL; 3295 } 3296 3297 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3298 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3299 if (err) { 3300 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3301 err = 0; 3302 goto out; 3303 } 3304 3305 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3306 if (err) { 3307 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3308 goto out; 3309 } 3310 3311 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3312 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3313 info->fw = adev->psp.cap_fw; 3314 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3315 adev->psp.cap_fw->data; 3316 adev->firmware.fw_size += ALIGN( 3317 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3318 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3319 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3320 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3321 3322 return 0; 3323 3324 out: 3325 release_firmware(adev->psp.cap_fw); 3326 adev->psp.cap_fw = NULL; 3327 return err; 3328 } 3329 3330 static int psp_set_clockgating_state(void *handle, 3331 enum amd_clockgating_state state) 3332 { 3333 return 0; 3334 } 3335 3336 static int psp_set_powergating_state(void *handle, 3337 enum amd_powergating_state state) 3338 { 3339 return 0; 3340 } 3341 3342 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3343 struct device_attribute *attr, 3344 char *buf) 3345 { 3346 struct drm_device *ddev = dev_get_drvdata(dev); 3347 struct amdgpu_device *adev = drm_to_adev(ddev); 3348 uint32_t fw_ver; 3349 int ret; 3350 3351 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3352 DRM_INFO("PSP block is not ready yet."); 3353 return -EBUSY; 3354 } 3355 3356 mutex_lock(&adev->psp.mutex); 3357 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3358 mutex_unlock(&adev->psp.mutex); 3359 3360 if (ret) { 3361 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3362 return ret; 3363 } 3364 3365 return sysfs_emit(buf, "%x\n", fw_ver); 3366 } 3367 3368 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3369 struct device_attribute *attr, 3370 const char *buf, 3371 size_t count) 3372 { 3373 struct drm_device *ddev = dev_get_drvdata(dev); 3374 struct amdgpu_device *adev = drm_to_adev(ddev); 3375 int ret, idx; 3376 char fw_name[100]; 3377 const struct firmware *usbc_pd_fw; 3378 struct amdgpu_bo *fw_buf_bo = NULL; 3379 uint64_t fw_pri_mc_addr; 3380 void *fw_pri_cpu_addr; 3381 3382 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3383 DRM_INFO("PSP block is not ready yet."); 3384 return -EBUSY; 3385 } 3386 3387 if (!drm_dev_enter(ddev, &idx)) 3388 return -ENODEV; 3389 3390 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3391 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3392 if (ret) 3393 goto fail; 3394 3395 /* LFB address which is aligned to 1MB boundary per PSP request */ 3396 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3397 AMDGPU_GEM_DOMAIN_VRAM, 3398 &fw_buf_bo, 3399 &fw_pri_mc_addr, 3400 &fw_pri_cpu_addr); 3401 if (ret) 3402 goto rel_buf; 3403 3404 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3405 3406 mutex_lock(&adev->psp.mutex); 3407 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3408 mutex_unlock(&adev->psp.mutex); 3409 3410 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3411 3412 rel_buf: 3413 release_firmware(usbc_pd_fw); 3414 fail: 3415 if (ret) { 3416 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3417 count = ret; 3418 } 3419 3420 drm_dev_exit(idx); 3421 return count; 3422 } 3423 3424 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3425 { 3426 int idx; 3427 3428 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3429 return; 3430 3431 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3432 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3433 3434 drm_dev_exit(idx); 3435 } 3436 3437 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3438 psp_usbc_pd_fw_sysfs_read, 3439 psp_usbc_pd_fw_sysfs_write); 3440 3441 int is_psp_fw_valid(struct psp_bin_desc bin) 3442 { 3443 return bin.size_bytes; 3444 } 3445 3446 const struct amd_ip_funcs psp_ip_funcs = { 3447 .name = "psp", 3448 .early_init = psp_early_init, 3449 .late_init = NULL, 3450 .sw_init = psp_sw_init, 3451 .sw_fini = psp_sw_fini, 3452 .hw_init = psp_hw_init, 3453 .hw_fini = psp_hw_fini, 3454 .suspend = psp_suspend, 3455 .resume = psp_resume, 3456 .is_idle = NULL, 3457 .check_soft_reset = NULL, 3458 .wait_for_idle = NULL, 3459 .soft_reset = NULL, 3460 .set_clockgating_state = psp_set_clockgating_state, 3461 .set_powergating_state = psp_set_powergating_state, 3462 }; 3463 3464 static int psp_sysfs_init(struct amdgpu_device *adev) 3465 { 3466 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3467 3468 if (ret) 3469 DRM_ERROR("Failed to create USBC PD FW control file!"); 3470 3471 return ret; 3472 } 3473 3474 static void psp_sysfs_fini(struct amdgpu_device *adev) 3475 { 3476 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3477 } 3478 3479 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3480 { 3481 .type = AMD_IP_BLOCK_TYPE_PSP, 3482 .major = 3, 3483 .minor = 1, 3484 .rev = 0, 3485 .funcs = &psp_ip_funcs, 3486 }; 3487 3488 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3489 { 3490 .type = AMD_IP_BLOCK_TYPE_PSP, 3491 .major = 10, 3492 .minor = 0, 3493 .rev = 0, 3494 .funcs = &psp_ip_funcs, 3495 }; 3496 3497 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3498 { 3499 .type = AMD_IP_BLOCK_TYPE_PSP, 3500 .major = 11, 3501 .minor = 0, 3502 .rev = 0, 3503 .funcs = &psp_ip_funcs, 3504 }; 3505 3506 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3507 .type = AMD_IP_BLOCK_TYPE_PSP, 3508 .major = 11, 3509 .minor = 0, 3510 .rev = 8, 3511 .funcs = &psp_ip_funcs, 3512 }; 3513 3514 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3515 { 3516 .type = AMD_IP_BLOCK_TYPE_PSP, 3517 .major = 12, 3518 .minor = 0, 3519 .rev = 0, 3520 .funcs = &psp_ip_funcs, 3521 }; 3522 3523 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3524 .type = AMD_IP_BLOCK_TYPE_PSP, 3525 .major = 13, 3526 .minor = 0, 3527 .rev = 0, 3528 .funcs = &psp_ip_funcs, 3529 }; 3530