1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 42 static int psp_sysfs_init(struct amdgpu_device *adev); 43 static void psp_sysfs_fini(struct amdgpu_device *adev); 44 45 static int psp_load_smu_fw(struct psp_context *psp); 46 47 /* 48 * Due to DF Cstate management centralized to PMFW, the firmware 49 * loading sequence will be updated as below: 50 * - Load KDB 51 * - Load SYS_DRV 52 * - Load tOS 53 * - Load PMFW 54 * - Setup TMR 55 * - Load other non-psp fw 56 * - Load ASD 57 * - Load XGMI/RAS/HDCP/DTM TA if any 58 * 59 * This new sequence is required for 60 * - Arcturus and onwards 61 * - Navi12 and onwards 62 */ 63 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 64 { 65 struct amdgpu_device *adev = psp->adev; 66 67 psp->pmfw_centralized_cstate_management = false; 68 69 if (amdgpu_sriov_vf(adev)) 70 return; 71 72 if (adev->flags & AMD_IS_APU) 73 return; 74 75 if ((adev->asic_type >= CHIP_ARCTURUS) || 76 (adev->asic_type >= CHIP_NAVI12)) 77 psp->pmfw_centralized_cstate_management = true; 78 } 79 80 static int psp_early_init(void *handle) 81 { 82 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 83 struct psp_context *psp = &adev->psp; 84 85 switch (adev->asic_type) { 86 case CHIP_VEGA10: 87 case CHIP_VEGA12: 88 psp_v3_1_set_psp_funcs(psp); 89 psp->autoload_supported = false; 90 break; 91 case CHIP_RAVEN: 92 psp_v10_0_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_VEGA20: 96 case CHIP_ARCTURUS: 97 psp_v11_0_set_psp_funcs(psp); 98 psp->autoload_supported = false; 99 break; 100 case CHIP_NAVI10: 101 case CHIP_NAVI14: 102 case CHIP_NAVI12: 103 case CHIP_SIENNA_CICHLID: 104 case CHIP_NAVY_FLOUNDER: 105 case CHIP_VANGOGH: 106 case CHIP_DIMGREY_CAVEFISH: 107 psp_v11_0_set_psp_funcs(psp); 108 psp->autoload_supported = true; 109 break; 110 case CHIP_RENOIR: 111 psp_v12_0_set_psp_funcs(psp); 112 break; 113 case CHIP_ALDEBARAN: 114 psp_v13_0_set_psp_funcs(psp); 115 break; 116 default: 117 return -EINVAL; 118 } 119 120 psp->adev = adev; 121 122 psp_check_pmfw_centralized_cstate_management(psp); 123 124 return 0; 125 } 126 127 static void psp_memory_training_fini(struct psp_context *psp) 128 { 129 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 130 131 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 132 kfree(ctx->sys_cache); 133 ctx->sys_cache = NULL; 134 } 135 136 static int psp_memory_training_init(struct psp_context *psp) 137 { 138 int ret; 139 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 140 141 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 142 DRM_DEBUG("memory training is not supported!\n"); 143 return 0; 144 } 145 146 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 147 if (ctx->sys_cache == NULL) { 148 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 149 ret = -ENOMEM; 150 goto Err_out; 151 } 152 153 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 154 ctx->train_data_size, 155 ctx->p2c_train_data_offset, 156 ctx->c2p_train_data_offset); 157 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 158 return 0; 159 160 Err_out: 161 psp_memory_training_fini(psp); 162 return ret; 163 } 164 165 static int psp_sw_init(void *handle) 166 { 167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 168 struct psp_context *psp = &adev->psp; 169 int ret; 170 171 if (!amdgpu_sriov_vf(adev)) { 172 ret = psp_init_microcode(psp); 173 if (ret) { 174 DRM_ERROR("Failed to load psp firmware!\n"); 175 return ret; 176 } 177 } 178 179 ret = psp_memory_training_init(psp); 180 if (ret) { 181 DRM_ERROR("Failed to initialize memory training!\n"); 182 return ret; 183 } 184 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 185 if (ret) { 186 DRM_ERROR("Failed to process memory training!\n"); 187 return ret; 188 } 189 190 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 191 ret= psp_sysfs_init(adev); 192 if (ret) { 193 return ret; 194 } 195 } 196 197 return 0; 198 } 199 200 static int psp_sw_fini(void *handle) 201 { 202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 203 204 psp_memory_training_fini(&adev->psp); 205 if (adev->psp.sos_fw) { 206 release_firmware(adev->psp.sos_fw); 207 adev->psp.sos_fw = NULL; 208 } 209 if (adev->psp.asd_fw) { 210 release_firmware(adev->psp.asd_fw); 211 adev->psp.asd_fw = NULL; 212 } 213 if (adev->psp.ta_fw) { 214 release_firmware(adev->psp.ta_fw); 215 adev->psp.ta_fw = NULL; 216 } 217 218 if (adev->asic_type == CHIP_NAVI10 || 219 adev->asic_type == CHIP_SIENNA_CICHLID) 220 psp_sysfs_fini(adev); 221 222 return 0; 223 } 224 225 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 226 uint32_t reg_val, uint32_t mask, bool check_changed) 227 { 228 uint32_t val; 229 int i; 230 struct amdgpu_device *adev = psp->adev; 231 232 if (psp->adev->in_pci_err_recovery) 233 return 0; 234 235 for (i = 0; i < adev->usec_timeout; i++) { 236 val = RREG32(reg_index); 237 if (check_changed) { 238 if (val != reg_val) 239 return 0; 240 } else { 241 if ((val & mask) == reg_val) 242 return 0; 243 } 244 udelay(1); 245 } 246 247 return -ETIME; 248 } 249 250 static int 251 psp_cmd_submit_buf(struct psp_context *psp, 252 struct amdgpu_firmware_info *ucode, 253 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 254 { 255 int ret; 256 int index; 257 int timeout = 20000; 258 bool ras_intr = false; 259 bool skip_unsupport = false; 260 261 if (psp->adev->in_pci_err_recovery) 262 return 0; 263 264 mutex_lock(&psp->mutex); 265 266 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 267 268 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 269 270 index = atomic_inc_return(&psp->fence_value); 271 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 272 if (ret) { 273 atomic_dec(&psp->fence_value); 274 mutex_unlock(&psp->mutex); 275 return ret; 276 } 277 278 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 279 while (*((unsigned int *)psp->fence_buf) != index) { 280 if (--timeout == 0) 281 break; 282 /* 283 * Shouldn't wait for timeout when err_event_athub occurs, 284 * because gpu reset thread triggered and lock resource should 285 * be released for psp resume sequence. 286 */ 287 ras_intr = amdgpu_ras_intr_triggered(); 288 if (ras_intr) 289 break; 290 usleep_range(10, 100); 291 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 292 } 293 294 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 295 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 296 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 297 298 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 299 300 /* In some cases, psp response status is not 0 even there is no 301 * problem while the command is submitted. Some version of PSP FW 302 * doesn't write 0 to that field. 303 * So here we would like to only print a warning instead of an error 304 * during psp initialization to avoid breaking hw_init and it doesn't 305 * return -EINVAL. 306 */ 307 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 308 if (ucode) 309 DRM_WARN("failed to load ucode id (%d) ", 310 ucode->ucode_id); 311 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 312 psp->cmd_buf_mem->cmd_id, 313 psp->cmd_buf_mem->resp.status); 314 if (!timeout) { 315 mutex_unlock(&psp->mutex); 316 return -EINVAL; 317 } 318 } 319 320 if (ucode) { 321 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 322 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 323 } 324 mutex_unlock(&psp->mutex); 325 326 return ret; 327 } 328 329 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 330 struct psp_gfx_cmd_resp *cmd, 331 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 332 { 333 struct amdgpu_device *adev = psp->adev; 334 uint32_t size = amdgpu_bo_size(tmr_bo); 335 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 336 337 if (amdgpu_sriov_vf(psp->adev)) 338 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 339 else 340 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 341 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 342 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 343 cmd->cmd.cmd_setup_tmr.buf_size = size; 344 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 345 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 346 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 347 } 348 349 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 350 uint64_t pri_buf_mc, uint32_t size) 351 { 352 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 353 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 354 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 355 cmd->cmd.cmd_load_toc.toc_size = size; 356 } 357 358 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 359 static int psp_load_toc(struct psp_context *psp, 360 uint32_t *tmr_size) 361 { 362 int ret; 363 struct psp_gfx_cmd_resp *cmd; 364 365 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 366 if (!cmd) 367 return -ENOMEM; 368 /* Copy toc to psp firmware private buffer */ 369 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 370 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 371 372 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 373 374 ret = psp_cmd_submit_buf(psp, NULL, cmd, 375 psp->fence_buf_mc_addr); 376 if (!ret) 377 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 378 kfree(cmd); 379 return ret; 380 } 381 382 /* Set up Trusted Memory Region */ 383 static int psp_tmr_init(struct psp_context *psp) 384 { 385 int ret; 386 int tmr_size; 387 void *tmr_buf; 388 void **pptr; 389 390 /* 391 * According to HW engineer, they prefer the TMR address be "naturally 392 * aligned" , e.g. the start address be an integer divide of TMR size. 393 * 394 * Note: this memory need be reserved till the driver 395 * uninitializes. 396 */ 397 tmr_size = PSP_TMR_SIZE(psp->adev); 398 399 /* For ASICs support RLC autoload, psp will parse the toc 400 * and calculate the total size of TMR needed */ 401 if (!amdgpu_sriov_vf(psp->adev) && 402 psp->toc_start_addr && 403 psp->toc_bin_size && 404 psp->fw_pri_buf) { 405 ret = psp_load_toc(psp, &tmr_size); 406 if (ret) { 407 DRM_ERROR("Failed to load toc\n"); 408 return ret; 409 } 410 } 411 412 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 413 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 414 AMDGPU_GEM_DOMAIN_VRAM, 415 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 416 417 return ret; 418 } 419 420 static int psp_clear_vf_fw(struct psp_context *psp) 421 { 422 int ret; 423 struct psp_gfx_cmd_resp *cmd; 424 425 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 426 return 0; 427 428 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 429 if (!cmd) 430 return -ENOMEM; 431 432 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 433 434 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 435 kfree(cmd); 436 437 return ret; 438 } 439 440 static bool psp_skip_tmr(struct psp_context *psp) 441 { 442 switch (psp->adev->asic_type) { 443 case CHIP_NAVI12: 444 case CHIP_SIENNA_CICHLID: 445 return true; 446 default: 447 return false; 448 } 449 } 450 451 static int psp_tmr_load(struct psp_context *psp) 452 { 453 int ret; 454 struct psp_gfx_cmd_resp *cmd; 455 456 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 457 * Already set up by host driver. 458 */ 459 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 460 return 0; 461 462 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 463 if (!cmd) 464 return -ENOMEM; 465 466 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 467 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 468 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 469 470 ret = psp_cmd_submit_buf(psp, NULL, cmd, 471 psp->fence_buf_mc_addr); 472 473 kfree(cmd); 474 475 return ret; 476 } 477 478 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 479 struct psp_gfx_cmd_resp *cmd) 480 { 481 if (amdgpu_sriov_vf(psp->adev)) 482 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 483 else 484 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 485 } 486 487 static int psp_tmr_unload(struct psp_context *psp) 488 { 489 int ret; 490 struct psp_gfx_cmd_resp *cmd; 491 492 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 493 if (!cmd) 494 return -ENOMEM; 495 496 psp_prep_tmr_unload_cmd_buf(psp, cmd); 497 DRM_INFO("free PSP TMR buffer\n"); 498 499 ret = psp_cmd_submit_buf(psp, NULL, cmd, 500 psp->fence_buf_mc_addr); 501 502 kfree(cmd); 503 504 return ret; 505 } 506 507 static int psp_tmr_terminate(struct psp_context *psp) 508 { 509 int ret; 510 void *tmr_buf; 511 void **pptr; 512 513 ret = psp_tmr_unload(psp); 514 if (ret) 515 return ret; 516 517 /* free TMR memory buffer */ 518 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 519 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 520 521 return 0; 522 } 523 524 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 525 uint64_t *output_ptr) 526 { 527 int ret; 528 struct psp_gfx_cmd_resp *cmd; 529 530 if (!output_ptr) 531 return -EINVAL; 532 533 if (amdgpu_sriov_vf(psp->adev)) 534 return 0; 535 536 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 537 if (!cmd) 538 return -ENOMEM; 539 540 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 541 542 ret = psp_cmd_submit_buf(psp, NULL, cmd, 543 psp->fence_buf_mc_addr); 544 545 if (!ret) { 546 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 547 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 548 } 549 550 kfree(cmd); 551 552 return ret; 553 } 554 555 static int psp_boot_config_set(struct amdgpu_device *adev) 556 { 557 struct psp_context *psp = &adev->psp; 558 struct psp_gfx_cmd_resp *cmd = psp->cmd; 559 560 if (adev->asic_type != CHIP_SIENNA_CICHLID || amdgpu_sriov_vf(adev)) 561 return 0; 562 563 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 564 565 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 566 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 567 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 568 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 569 570 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 571 } 572 573 static int psp_rl_load(struct amdgpu_device *adev) 574 { 575 struct psp_context *psp = &adev->psp; 576 struct psp_gfx_cmd_resp *cmd = psp->cmd; 577 578 if (psp->rl_bin_size == 0) 579 return 0; 580 581 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 582 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 583 584 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 585 586 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 587 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 588 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 589 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 590 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 591 592 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 593 } 594 595 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 596 uint64_t asd_mc, uint32_t size) 597 { 598 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 599 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 600 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 601 cmd->cmd.cmd_load_ta.app_len = size; 602 603 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 604 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 605 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 606 } 607 608 static int psp_asd_load(struct psp_context *psp) 609 { 610 int ret; 611 struct psp_gfx_cmd_resp *cmd; 612 613 /* If PSP version doesn't match ASD version, asd loading will be failed. 614 * add workaround to bypass it for sriov now. 615 * TODO: add version check to make it common 616 */ 617 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 618 return 0; 619 620 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 621 if (!cmd) 622 return -ENOMEM; 623 624 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 625 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 626 627 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 628 psp->asd_ucode_size); 629 630 ret = psp_cmd_submit_buf(psp, NULL, cmd, 631 psp->fence_buf_mc_addr); 632 if (!ret) { 633 psp->asd_context.asd_initialized = true; 634 psp->asd_context.session_id = cmd->resp.session_id; 635 } 636 637 kfree(cmd); 638 639 return ret; 640 } 641 642 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 643 uint32_t session_id) 644 { 645 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 646 cmd->cmd.cmd_unload_ta.session_id = session_id; 647 } 648 649 static int psp_asd_unload(struct psp_context *psp) 650 { 651 int ret; 652 struct psp_gfx_cmd_resp *cmd; 653 654 if (amdgpu_sriov_vf(psp->adev)) 655 return 0; 656 657 if (!psp->asd_context.asd_initialized) 658 return 0; 659 660 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 661 if (!cmd) 662 return -ENOMEM; 663 664 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 665 666 ret = psp_cmd_submit_buf(psp, NULL, cmd, 667 psp->fence_buf_mc_addr); 668 if (!ret) 669 psp->asd_context.asd_initialized = false; 670 671 kfree(cmd); 672 673 return ret; 674 } 675 676 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 677 uint32_t id, uint32_t value) 678 { 679 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 680 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 681 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 682 } 683 684 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 685 uint32_t value) 686 { 687 struct psp_gfx_cmd_resp *cmd = NULL; 688 int ret = 0; 689 690 if (reg >= PSP_REG_LAST) 691 return -EINVAL; 692 693 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 694 if (!cmd) 695 return -ENOMEM; 696 697 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 698 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 699 700 kfree(cmd); 701 return ret; 702 } 703 704 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 705 uint64_t ta_bin_mc, 706 uint32_t ta_bin_size, 707 uint64_t ta_shared_mc, 708 uint32_t ta_shared_size) 709 { 710 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 711 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 712 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 713 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 714 715 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 716 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 717 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 718 } 719 720 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 721 { 722 int ret; 723 724 /* 725 * Allocate 16k memory aligned to 4k from Frame Buffer (local 726 * physical) for xgmi ta <-> Driver 727 */ 728 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 729 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 730 &psp->xgmi_context.xgmi_shared_bo, 731 &psp->xgmi_context.xgmi_shared_mc_addr, 732 &psp->xgmi_context.xgmi_shared_buf); 733 734 return ret; 735 } 736 737 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 738 uint32_t ta_cmd_id, 739 uint32_t session_id) 740 { 741 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 742 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 743 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 744 } 745 746 static int psp_ta_invoke(struct psp_context *psp, 747 uint32_t ta_cmd_id, 748 uint32_t session_id) 749 { 750 int ret; 751 struct psp_gfx_cmd_resp *cmd; 752 753 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 754 if (!cmd) 755 return -ENOMEM; 756 757 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 758 759 ret = psp_cmd_submit_buf(psp, NULL, cmd, 760 psp->fence_buf_mc_addr); 761 762 kfree(cmd); 763 764 return ret; 765 } 766 767 static int psp_xgmi_load(struct psp_context *psp) 768 { 769 int ret; 770 struct psp_gfx_cmd_resp *cmd; 771 772 /* 773 * TODO: bypass the loading in sriov for now 774 */ 775 776 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 777 if (!cmd) 778 return -ENOMEM; 779 780 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 781 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 782 783 psp_prep_ta_load_cmd_buf(cmd, 784 psp->fw_pri_mc_addr, 785 psp->ta_xgmi_ucode_size, 786 psp->xgmi_context.xgmi_shared_mc_addr, 787 PSP_XGMI_SHARED_MEM_SIZE); 788 789 ret = psp_cmd_submit_buf(psp, NULL, cmd, 790 psp->fence_buf_mc_addr); 791 792 if (!ret) { 793 psp->xgmi_context.initialized = 1; 794 psp->xgmi_context.session_id = cmd->resp.session_id; 795 } 796 797 kfree(cmd); 798 799 return ret; 800 } 801 802 static int psp_xgmi_unload(struct psp_context *psp) 803 { 804 int ret; 805 struct psp_gfx_cmd_resp *cmd; 806 struct amdgpu_device *adev = psp->adev; 807 808 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 809 if (adev->asic_type == CHIP_ARCTURUS || 810 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 811 return 0; 812 813 /* 814 * TODO: bypass the unloading in sriov for now 815 */ 816 817 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 818 if (!cmd) 819 return -ENOMEM; 820 821 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 822 823 ret = psp_cmd_submit_buf(psp, NULL, cmd, 824 psp->fence_buf_mc_addr); 825 826 kfree(cmd); 827 828 return ret; 829 } 830 831 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 832 { 833 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 834 } 835 836 int psp_xgmi_terminate(struct psp_context *psp) 837 { 838 int ret; 839 840 if (!psp->xgmi_context.initialized) 841 return 0; 842 843 ret = psp_xgmi_unload(psp); 844 if (ret) 845 return ret; 846 847 psp->xgmi_context.initialized = 0; 848 849 /* free xgmi shared memory */ 850 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 851 &psp->xgmi_context.xgmi_shared_mc_addr, 852 &psp->xgmi_context.xgmi_shared_buf); 853 854 return 0; 855 } 856 857 int psp_xgmi_initialize(struct psp_context *psp) 858 { 859 struct ta_xgmi_shared_memory *xgmi_cmd; 860 int ret; 861 862 if (!psp->adev->psp.ta_fw || 863 !psp->adev->psp.ta_xgmi_ucode_size || 864 !psp->adev->psp.ta_xgmi_start_addr) 865 return -ENOENT; 866 867 if (!psp->xgmi_context.initialized) { 868 ret = psp_xgmi_init_shared_buf(psp); 869 if (ret) 870 return ret; 871 } 872 873 /* Load XGMI TA */ 874 ret = psp_xgmi_load(psp); 875 if (ret) 876 return ret; 877 878 /* Initialize XGMI session */ 879 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 880 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 881 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 882 883 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 884 885 return ret; 886 } 887 888 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 889 { 890 struct ta_xgmi_shared_memory *xgmi_cmd; 891 int ret; 892 893 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 894 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 895 896 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 897 898 /* Invoke xgmi ta to get hive id */ 899 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 900 if (ret) 901 return ret; 902 903 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 904 905 return 0; 906 } 907 908 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 909 { 910 struct ta_xgmi_shared_memory *xgmi_cmd; 911 int ret; 912 913 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 914 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 915 916 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 917 918 /* Invoke xgmi ta to get the node id */ 919 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 920 if (ret) 921 return ret; 922 923 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 924 925 return 0; 926 } 927 928 int psp_xgmi_get_topology_info(struct psp_context *psp, 929 int number_devices, 930 struct psp_xgmi_topology_info *topology) 931 { 932 struct ta_xgmi_shared_memory *xgmi_cmd; 933 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 934 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 935 int i; 936 int ret; 937 938 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 939 return -EINVAL; 940 941 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 942 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 943 944 /* Fill in the shared memory with topology information as input */ 945 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 946 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 947 topology_info_input->num_nodes = number_devices; 948 949 for (i = 0; i < topology_info_input->num_nodes; i++) { 950 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 951 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 952 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 953 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 954 } 955 956 /* Invoke xgmi ta to get the topology information */ 957 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 958 if (ret) 959 return ret; 960 961 /* Read the output topology information from the shared memory */ 962 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 963 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 964 for (i = 0; i < topology->num_nodes; i++) { 965 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 966 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 967 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 968 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 969 } 970 971 return 0; 972 } 973 974 int psp_xgmi_set_topology_info(struct psp_context *psp, 975 int number_devices, 976 struct psp_xgmi_topology_info *topology) 977 { 978 struct ta_xgmi_shared_memory *xgmi_cmd; 979 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 980 int i; 981 982 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 983 return -EINVAL; 984 985 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 986 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 987 988 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 989 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 990 topology_info_input->num_nodes = number_devices; 991 992 for (i = 0; i < topology_info_input->num_nodes; i++) { 993 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 994 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 995 topology_info_input->nodes[i].is_sharing_enabled = 1; 996 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 997 } 998 999 /* Invoke xgmi ta to set topology information */ 1000 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1001 } 1002 1003 // ras begin 1004 static int psp_ras_init_shared_buf(struct psp_context *psp) 1005 { 1006 int ret; 1007 1008 /* 1009 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1010 * physical) for ras ta <-> Driver 1011 */ 1012 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1013 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1014 &psp->ras.ras_shared_bo, 1015 &psp->ras.ras_shared_mc_addr, 1016 &psp->ras.ras_shared_buf); 1017 1018 return ret; 1019 } 1020 1021 static int psp_ras_load(struct psp_context *psp) 1022 { 1023 int ret; 1024 struct psp_gfx_cmd_resp *cmd; 1025 struct ta_ras_shared_memory *ras_cmd; 1026 1027 /* 1028 * TODO: bypass the loading in sriov for now 1029 */ 1030 if (amdgpu_sriov_vf(psp->adev)) 1031 return 0; 1032 1033 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1034 if (!cmd) 1035 return -ENOMEM; 1036 1037 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1038 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1039 1040 psp_prep_ta_load_cmd_buf(cmd, 1041 psp->fw_pri_mc_addr, 1042 psp->ta_ras_ucode_size, 1043 psp->ras.ras_shared_mc_addr, 1044 PSP_RAS_SHARED_MEM_SIZE); 1045 1046 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1047 psp->fence_buf_mc_addr); 1048 1049 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1050 1051 if (!ret) { 1052 psp->ras.session_id = cmd->resp.session_id; 1053 1054 if (!ras_cmd->ras_status) 1055 psp->ras.ras_initialized = true; 1056 else 1057 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1058 } 1059 1060 if (ret || ras_cmd->ras_status) 1061 amdgpu_ras_fini(psp->adev); 1062 1063 kfree(cmd); 1064 1065 return ret; 1066 } 1067 1068 static int psp_ras_unload(struct psp_context *psp) 1069 { 1070 int ret; 1071 struct psp_gfx_cmd_resp *cmd; 1072 1073 /* 1074 * TODO: bypass the unloading in sriov for now 1075 */ 1076 if (amdgpu_sriov_vf(psp->adev)) 1077 return 0; 1078 1079 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1080 if (!cmd) 1081 return -ENOMEM; 1082 1083 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1084 1085 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1086 psp->fence_buf_mc_addr); 1087 1088 kfree(cmd); 1089 1090 return ret; 1091 } 1092 1093 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1094 { 1095 struct ta_ras_shared_memory *ras_cmd; 1096 int ret; 1097 1098 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1099 1100 /* 1101 * TODO: bypass the loading in sriov for now 1102 */ 1103 if (amdgpu_sriov_vf(psp->adev)) 1104 return 0; 1105 1106 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1107 1108 if (amdgpu_ras_intr_triggered()) 1109 return ret; 1110 1111 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1112 { 1113 DRM_WARN("RAS: Unsupported Interface"); 1114 return -EINVAL; 1115 } 1116 1117 if (!ret) { 1118 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1119 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1120 1121 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1122 } 1123 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1124 dev_warn(psp->adev->dev, 1125 "RAS internal register access blocked\n"); 1126 } 1127 1128 return ret; 1129 } 1130 1131 int psp_ras_enable_features(struct psp_context *psp, 1132 union ta_ras_cmd_input *info, bool enable) 1133 { 1134 struct ta_ras_shared_memory *ras_cmd; 1135 int ret; 1136 1137 if (!psp->ras.ras_initialized) 1138 return -EINVAL; 1139 1140 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1141 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1142 1143 if (enable) 1144 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1145 else 1146 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1147 1148 ras_cmd->ras_in_message = *info; 1149 1150 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1151 if (ret) 1152 return -EINVAL; 1153 1154 return ras_cmd->ras_status; 1155 } 1156 1157 static int psp_ras_terminate(struct psp_context *psp) 1158 { 1159 int ret; 1160 1161 /* 1162 * TODO: bypass the terminate in sriov for now 1163 */ 1164 if (amdgpu_sriov_vf(psp->adev)) 1165 return 0; 1166 1167 if (!psp->ras.ras_initialized) 1168 return 0; 1169 1170 ret = psp_ras_unload(psp); 1171 if (ret) 1172 return ret; 1173 1174 psp->ras.ras_initialized = false; 1175 1176 /* free ras shared memory */ 1177 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1178 &psp->ras.ras_shared_mc_addr, 1179 &psp->ras.ras_shared_buf); 1180 1181 return 0; 1182 } 1183 1184 static int psp_ras_initialize(struct psp_context *psp) 1185 { 1186 int ret; 1187 1188 /* 1189 * TODO: bypass the initialize in sriov for now 1190 */ 1191 if (amdgpu_sriov_vf(psp->adev)) 1192 return 0; 1193 1194 if (!psp->adev->psp.ta_ras_ucode_size || 1195 !psp->adev->psp.ta_ras_start_addr) { 1196 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1197 return 0; 1198 } 1199 1200 if (!psp->ras.ras_initialized) { 1201 ret = psp_ras_init_shared_buf(psp); 1202 if (ret) 1203 return ret; 1204 } 1205 1206 ret = psp_ras_load(psp); 1207 if (ret) 1208 return ret; 1209 1210 return 0; 1211 } 1212 1213 int psp_ras_trigger_error(struct psp_context *psp, 1214 struct ta_ras_trigger_error_input *info) 1215 { 1216 struct ta_ras_shared_memory *ras_cmd; 1217 int ret; 1218 1219 if (!psp->ras.ras_initialized) 1220 return -EINVAL; 1221 1222 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1223 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1224 1225 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1226 ras_cmd->ras_in_message.trigger_error = *info; 1227 1228 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1229 if (ret) 1230 return -EINVAL; 1231 1232 /* If err_event_athub occurs error inject was successful, however 1233 return status from TA is no long reliable */ 1234 if (amdgpu_ras_intr_triggered()) 1235 return 0; 1236 1237 return ras_cmd->ras_status; 1238 } 1239 // ras end 1240 1241 // HDCP start 1242 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1243 { 1244 int ret; 1245 1246 /* 1247 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1248 * physical) for hdcp ta <-> Driver 1249 */ 1250 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1251 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1252 &psp->hdcp_context.hdcp_shared_bo, 1253 &psp->hdcp_context.hdcp_shared_mc_addr, 1254 &psp->hdcp_context.hdcp_shared_buf); 1255 1256 return ret; 1257 } 1258 1259 static int psp_hdcp_load(struct psp_context *psp) 1260 { 1261 int ret; 1262 struct psp_gfx_cmd_resp *cmd; 1263 1264 /* 1265 * TODO: bypass the loading in sriov for now 1266 */ 1267 if (amdgpu_sriov_vf(psp->adev)) 1268 return 0; 1269 1270 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1271 if (!cmd) 1272 return -ENOMEM; 1273 1274 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1275 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1276 psp->ta_hdcp_ucode_size); 1277 1278 psp_prep_ta_load_cmd_buf(cmd, 1279 psp->fw_pri_mc_addr, 1280 psp->ta_hdcp_ucode_size, 1281 psp->hdcp_context.hdcp_shared_mc_addr, 1282 PSP_HDCP_SHARED_MEM_SIZE); 1283 1284 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1285 1286 if (!ret) { 1287 psp->hdcp_context.hdcp_initialized = true; 1288 psp->hdcp_context.session_id = cmd->resp.session_id; 1289 mutex_init(&psp->hdcp_context.mutex); 1290 } 1291 1292 kfree(cmd); 1293 1294 return ret; 1295 } 1296 static int psp_hdcp_initialize(struct psp_context *psp) 1297 { 1298 int ret; 1299 1300 /* 1301 * TODO: bypass the initialize in sriov for now 1302 */ 1303 if (amdgpu_sriov_vf(psp->adev)) 1304 return 0; 1305 1306 if (!psp->adev->psp.ta_hdcp_ucode_size || 1307 !psp->adev->psp.ta_hdcp_start_addr) { 1308 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1309 return 0; 1310 } 1311 1312 if (!psp->hdcp_context.hdcp_initialized) { 1313 ret = psp_hdcp_init_shared_buf(psp); 1314 if (ret) 1315 return ret; 1316 } 1317 1318 ret = psp_hdcp_load(psp); 1319 if (ret) 1320 return ret; 1321 1322 return 0; 1323 } 1324 1325 static int psp_hdcp_unload(struct psp_context *psp) 1326 { 1327 int ret; 1328 struct psp_gfx_cmd_resp *cmd; 1329 1330 /* 1331 * TODO: bypass the unloading in sriov for now 1332 */ 1333 if (amdgpu_sriov_vf(psp->adev)) 1334 return 0; 1335 1336 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1337 if (!cmd) 1338 return -ENOMEM; 1339 1340 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1341 1342 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1343 1344 kfree(cmd); 1345 1346 return ret; 1347 } 1348 1349 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1350 { 1351 /* 1352 * TODO: bypass the loading in sriov for now 1353 */ 1354 if (amdgpu_sriov_vf(psp->adev)) 1355 return 0; 1356 1357 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1358 } 1359 1360 static int psp_hdcp_terminate(struct psp_context *psp) 1361 { 1362 int ret; 1363 1364 /* 1365 * TODO: bypass the terminate in sriov for now 1366 */ 1367 if (amdgpu_sriov_vf(psp->adev)) 1368 return 0; 1369 1370 if (!psp->hdcp_context.hdcp_initialized) { 1371 if (psp->hdcp_context.hdcp_shared_buf) 1372 goto out; 1373 else 1374 return 0; 1375 } 1376 1377 ret = psp_hdcp_unload(psp); 1378 if (ret) 1379 return ret; 1380 1381 psp->hdcp_context.hdcp_initialized = false; 1382 1383 out: 1384 /* free hdcp shared memory */ 1385 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1386 &psp->hdcp_context.hdcp_shared_mc_addr, 1387 &psp->hdcp_context.hdcp_shared_buf); 1388 1389 return 0; 1390 } 1391 // HDCP end 1392 1393 // DTM start 1394 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1395 { 1396 int ret; 1397 1398 /* 1399 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1400 * physical) for dtm ta <-> Driver 1401 */ 1402 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1403 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1404 &psp->dtm_context.dtm_shared_bo, 1405 &psp->dtm_context.dtm_shared_mc_addr, 1406 &psp->dtm_context.dtm_shared_buf); 1407 1408 return ret; 1409 } 1410 1411 static int psp_dtm_load(struct psp_context *psp) 1412 { 1413 int ret; 1414 struct psp_gfx_cmd_resp *cmd; 1415 1416 /* 1417 * TODO: bypass the loading in sriov for now 1418 */ 1419 if (amdgpu_sriov_vf(psp->adev)) 1420 return 0; 1421 1422 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1423 if (!cmd) 1424 return -ENOMEM; 1425 1426 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1427 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1428 1429 psp_prep_ta_load_cmd_buf(cmd, 1430 psp->fw_pri_mc_addr, 1431 psp->ta_dtm_ucode_size, 1432 psp->dtm_context.dtm_shared_mc_addr, 1433 PSP_DTM_SHARED_MEM_SIZE); 1434 1435 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1436 1437 if (!ret) { 1438 psp->dtm_context.dtm_initialized = true; 1439 psp->dtm_context.session_id = cmd->resp.session_id; 1440 mutex_init(&psp->dtm_context.mutex); 1441 } 1442 1443 kfree(cmd); 1444 1445 return ret; 1446 } 1447 1448 static int psp_dtm_initialize(struct psp_context *psp) 1449 { 1450 int ret; 1451 1452 /* 1453 * TODO: bypass the initialize in sriov for now 1454 */ 1455 if (amdgpu_sriov_vf(psp->adev)) 1456 return 0; 1457 1458 if (!psp->adev->psp.ta_dtm_ucode_size || 1459 !psp->adev->psp.ta_dtm_start_addr) { 1460 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1461 return 0; 1462 } 1463 1464 if (!psp->dtm_context.dtm_initialized) { 1465 ret = psp_dtm_init_shared_buf(psp); 1466 if (ret) 1467 return ret; 1468 } 1469 1470 ret = psp_dtm_load(psp); 1471 if (ret) 1472 return ret; 1473 1474 return 0; 1475 } 1476 1477 static int psp_dtm_unload(struct psp_context *psp) 1478 { 1479 int ret; 1480 struct psp_gfx_cmd_resp *cmd; 1481 1482 /* 1483 * TODO: bypass the unloading in sriov for now 1484 */ 1485 if (amdgpu_sriov_vf(psp->adev)) 1486 return 0; 1487 1488 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1489 if (!cmd) 1490 return -ENOMEM; 1491 1492 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1493 1494 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1495 1496 kfree(cmd); 1497 1498 return ret; 1499 } 1500 1501 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1502 { 1503 /* 1504 * TODO: bypass the loading in sriov for now 1505 */ 1506 if (amdgpu_sriov_vf(psp->adev)) 1507 return 0; 1508 1509 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1510 } 1511 1512 static int psp_dtm_terminate(struct psp_context *psp) 1513 { 1514 int ret; 1515 1516 /* 1517 * TODO: bypass the terminate in sriov for now 1518 */ 1519 if (amdgpu_sriov_vf(psp->adev)) 1520 return 0; 1521 1522 if (!psp->dtm_context.dtm_initialized) { 1523 if (psp->dtm_context.dtm_shared_buf) 1524 goto out; 1525 else 1526 return 0; 1527 } 1528 1529 ret = psp_dtm_unload(psp); 1530 if (ret) 1531 return ret; 1532 1533 psp->dtm_context.dtm_initialized = false; 1534 1535 out: 1536 /* free hdcp shared memory */ 1537 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1538 &psp->dtm_context.dtm_shared_mc_addr, 1539 &psp->dtm_context.dtm_shared_buf); 1540 1541 return 0; 1542 } 1543 // DTM end 1544 1545 // RAP start 1546 static int psp_rap_init_shared_buf(struct psp_context *psp) 1547 { 1548 int ret; 1549 1550 /* 1551 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1552 * physical) for rap ta <-> Driver 1553 */ 1554 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1555 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1556 &psp->rap_context.rap_shared_bo, 1557 &psp->rap_context.rap_shared_mc_addr, 1558 &psp->rap_context.rap_shared_buf); 1559 1560 return ret; 1561 } 1562 1563 static int psp_rap_load(struct psp_context *psp) 1564 { 1565 int ret; 1566 struct psp_gfx_cmd_resp *cmd; 1567 1568 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1569 if (!cmd) 1570 return -ENOMEM; 1571 1572 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1573 memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1574 1575 psp_prep_ta_load_cmd_buf(cmd, 1576 psp->fw_pri_mc_addr, 1577 psp->ta_rap_ucode_size, 1578 psp->rap_context.rap_shared_mc_addr, 1579 PSP_RAP_SHARED_MEM_SIZE); 1580 1581 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1582 1583 if (!ret) { 1584 psp->rap_context.rap_initialized = true; 1585 psp->rap_context.session_id = cmd->resp.session_id; 1586 mutex_init(&psp->rap_context.mutex); 1587 } 1588 1589 kfree(cmd); 1590 1591 return ret; 1592 } 1593 1594 static int psp_rap_unload(struct psp_context *psp) 1595 { 1596 int ret; 1597 struct psp_gfx_cmd_resp *cmd; 1598 1599 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1600 if (!cmd) 1601 return -ENOMEM; 1602 1603 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1604 1605 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1606 1607 kfree(cmd); 1608 1609 return ret; 1610 } 1611 1612 static int psp_rap_initialize(struct psp_context *psp) 1613 { 1614 int ret; 1615 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1616 1617 /* 1618 * TODO: bypass the initialize in sriov for now 1619 */ 1620 if (amdgpu_sriov_vf(psp->adev)) 1621 return 0; 1622 1623 if (!psp->adev->psp.ta_rap_ucode_size || 1624 !psp->adev->psp.ta_rap_start_addr) { 1625 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1626 return 0; 1627 } 1628 1629 if (!psp->rap_context.rap_initialized) { 1630 ret = psp_rap_init_shared_buf(psp); 1631 if (ret) 1632 return ret; 1633 } 1634 1635 ret = psp_rap_load(psp); 1636 if (ret) 1637 return ret; 1638 1639 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1640 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1641 psp_rap_unload(psp); 1642 1643 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1644 &psp->rap_context.rap_shared_mc_addr, 1645 &psp->rap_context.rap_shared_buf); 1646 1647 psp->rap_context.rap_initialized = false; 1648 1649 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1650 ret, status); 1651 1652 return ret; 1653 } 1654 1655 return 0; 1656 } 1657 1658 static int psp_rap_terminate(struct psp_context *psp) 1659 { 1660 int ret; 1661 1662 if (!psp->rap_context.rap_initialized) 1663 return 0; 1664 1665 ret = psp_rap_unload(psp); 1666 1667 psp->rap_context.rap_initialized = false; 1668 1669 /* free rap shared memory */ 1670 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1671 &psp->rap_context.rap_shared_mc_addr, 1672 &psp->rap_context.rap_shared_buf); 1673 1674 return ret; 1675 } 1676 1677 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1678 { 1679 struct ta_rap_shared_memory *rap_cmd; 1680 int ret = 0; 1681 1682 if (!psp->rap_context.rap_initialized) 1683 return 0; 1684 1685 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1686 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1687 return -EINVAL; 1688 1689 mutex_lock(&psp->rap_context.mutex); 1690 1691 rap_cmd = (struct ta_rap_shared_memory *) 1692 psp->rap_context.rap_shared_buf; 1693 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1694 1695 rap_cmd->cmd_id = ta_cmd_id; 1696 rap_cmd->validation_method_id = METHOD_A; 1697 1698 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1699 if (ret) 1700 goto out_unlock; 1701 1702 if (status) 1703 *status = rap_cmd->rap_status; 1704 1705 out_unlock: 1706 mutex_unlock(&psp->rap_context.mutex); 1707 1708 return ret; 1709 } 1710 // RAP end 1711 1712 /* securedisplay start */ 1713 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1714 { 1715 int ret; 1716 1717 /* 1718 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1719 * physical) for sa ta <-> Driver 1720 */ 1721 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1722 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1723 &psp->securedisplay_context.securedisplay_shared_bo, 1724 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1725 &psp->securedisplay_context.securedisplay_shared_buf); 1726 1727 return ret; 1728 } 1729 1730 static int psp_securedisplay_load(struct psp_context *psp) 1731 { 1732 int ret; 1733 struct psp_gfx_cmd_resp *cmd; 1734 1735 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1736 if (!cmd) 1737 return -ENOMEM; 1738 1739 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1740 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1741 1742 psp_prep_ta_load_cmd_buf(cmd, 1743 psp->fw_pri_mc_addr, 1744 psp->ta_securedisplay_ucode_size, 1745 psp->securedisplay_context.securedisplay_shared_mc_addr, 1746 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1747 1748 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1749 1750 if (ret) 1751 goto failed; 1752 1753 psp->securedisplay_context.securedisplay_initialized = true; 1754 psp->securedisplay_context.session_id = cmd->resp.session_id; 1755 mutex_init(&psp->securedisplay_context.mutex); 1756 1757 failed: 1758 kfree(cmd); 1759 return ret; 1760 } 1761 1762 static int psp_securedisplay_unload(struct psp_context *psp) 1763 { 1764 int ret; 1765 struct psp_gfx_cmd_resp *cmd; 1766 1767 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1768 if (!cmd) 1769 return -ENOMEM; 1770 1771 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1772 1773 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1774 1775 kfree(cmd); 1776 1777 return ret; 1778 } 1779 1780 static int psp_securedisplay_initialize(struct psp_context *psp) 1781 { 1782 int ret; 1783 struct securedisplay_cmd *securedisplay_cmd; 1784 1785 /* 1786 * TODO: bypass the initialize in sriov for now 1787 */ 1788 if (amdgpu_sriov_vf(psp->adev)) 1789 return 0; 1790 1791 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1792 !psp->adev->psp.ta_securedisplay_start_addr) { 1793 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1794 return 0; 1795 } 1796 1797 if (!psp->securedisplay_context.securedisplay_initialized) { 1798 ret = psp_securedisplay_init_shared_buf(psp); 1799 if (ret) 1800 return ret; 1801 } 1802 1803 ret = psp_securedisplay_load(psp); 1804 if (ret) 1805 return ret; 1806 1807 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1808 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1809 1810 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1811 if (ret) { 1812 psp_securedisplay_unload(psp); 1813 1814 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1815 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1816 &psp->securedisplay_context.securedisplay_shared_buf); 1817 1818 psp->securedisplay_context.securedisplay_initialized = false; 1819 1820 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1821 return -EINVAL; 1822 } 1823 1824 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1825 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1826 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1827 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int psp_securedisplay_terminate(struct psp_context *psp) 1834 { 1835 int ret; 1836 1837 /* 1838 * TODO:bypass the terminate in sriov for now 1839 */ 1840 if (amdgpu_sriov_vf(psp->adev)) 1841 return 0; 1842 1843 if (!psp->securedisplay_context.securedisplay_initialized) 1844 return 0; 1845 1846 ret = psp_securedisplay_unload(psp); 1847 if (ret) 1848 return ret; 1849 1850 psp->securedisplay_context.securedisplay_initialized = false; 1851 1852 /* free securedisplay shared memory */ 1853 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1854 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1855 &psp->securedisplay_context.securedisplay_shared_buf); 1856 1857 return ret; 1858 } 1859 1860 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1861 { 1862 int ret; 1863 1864 if (!psp->securedisplay_context.securedisplay_initialized) 1865 return -EINVAL; 1866 1867 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1868 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1869 return -EINVAL; 1870 1871 mutex_lock(&psp->securedisplay_context.mutex); 1872 1873 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1874 1875 mutex_unlock(&psp->securedisplay_context.mutex); 1876 1877 return ret; 1878 } 1879 /* SECUREDISPLAY end */ 1880 1881 static int psp_hw_start(struct psp_context *psp) 1882 { 1883 struct amdgpu_device *adev = psp->adev; 1884 int ret; 1885 1886 if (!amdgpu_sriov_vf(adev)) { 1887 if (psp->kdb_bin_size && 1888 (psp->funcs->bootloader_load_kdb != NULL)) { 1889 ret = psp_bootloader_load_kdb(psp); 1890 if (ret) { 1891 DRM_ERROR("PSP load kdb failed!\n"); 1892 return ret; 1893 } 1894 } 1895 1896 if (psp->spl_bin_size) { 1897 ret = psp_bootloader_load_spl(psp); 1898 if (ret) { 1899 DRM_ERROR("PSP load spl failed!\n"); 1900 return ret; 1901 } 1902 } 1903 1904 ret = psp_bootloader_load_sysdrv(psp); 1905 if (ret) { 1906 DRM_ERROR("PSP load sysdrv failed!\n"); 1907 return ret; 1908 } 1909 1910 ret = psp_bootloader_load_sos(psp); 1911 if (ret) { 1912 DRM_ERROR("PSP load sos failed!\n"); 1913 return ret; 1914 } 1915 } 1916 1917 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1918 if (ret) { 1919 DRM_ERROR("PSP create ring failed!\n"); 1920 return ret; 1921 } 1922 1923 ret = psp_clear_vf_fw(psp); 1924 if (ret) { 1925 DRM_ERROR("PSP clear vf fw!\n"); 1926 return ret; 1927 } 1928 1929 ret = psp_boot_config_set(adev); 1930 if (ret) { 1931 DRM_WARN("PSP set boot config@\n"); 1932 } 1933 1934 ret = psp_tmr_init(psp); 1935 if (ret) { 1936 DRM_ERROR("PSP tmr init failed!\n"); 1937 return ret; 1938 } 1939 1940 /* 1941 * For ASICs with DF Cstate management centralized 1942 * to PMFW, TMR setup should be performed after PMFW 1943 * loaded and before other non-psp firmware loaded. 1944 */ 1945 if (psp->pmfw_centralized_cstate_management) { 1946 ret = psp_load_smu_fw(psp); 1947 if (ret) 1948 return ret; 1949 } 1950 1951 ret = psp_tmr_load(psp); 1952 if (ret) { 1953 DRM_ERROR("PSP load tmr failed!\n"); 1954 return ret; 1955 } 1956 1957 return 0; 1958 } 1959 1960 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1961 enum psp_gfx_fw_type *type) 1962 { 1963 switch (ucode->ucode_id) { 1964 case AMDGPU_UCODE_ID_SDMA0: 1965 *type = GFX_FW_TYPE_SDMA0; 1966 break; 1967 case AMDGPU_UCODE_ID_SDMA1: 1968 *type = GFX_FW_TYPE_SDMA1; 1969 break; 1970 case AMDGPU_UCODE_ID_SDMA2: 1971 *type = GFX_FW_TYPE_SDMA2; 1972 break; 1973 case AMDGPU_UCODE_ID_SDMA3: 1974 *type = GFX_FW_TYPE_SDMA3; 1975 break; 1976 case AMDGPU_UCODE_ID_SDMA4: 1977 *type = GFX_FW_TYPE_SDMA4; 1978 break; 1979 case AMDGPU_UCODE_ID_SDMA5: 1980 *type = GFX_FW_TYPE_SDMA5; 1981 break; 1982 case AMDGPU_UCODE_ID_SDMA6: 1983 *type = GFX_FW_TYPE_SDMA6; 1984 break; 1985 case AMDGPU_UCODE_ID_SDMA7: 1986 *type = GFX_FW_TYPE_SDMA7; 1987 break; 1988 case AMDGPU_UCODE_ID_CP_MES: 1989 *type = GFX_FW_TYPE_CP_MES; 1990 break; 1991 case AMDGPU_UCODE_ID_CP_MES_DATA: 1992 *type = GFX_FW_TYPE_MES_STACK; 1993 break; 1994 case AMDGPU_UCODE_ID_CP_CE: 1995 *type = GFX_FW_TYPE_CP_CE; 1996 break; 1997 case AMDGPU_UCODE_ID_CP_PFP: 1998 *type = GFX_FW_TYPE_CP_PFP; 1999 break; 2000 case AMDGPU_UCODE_ID_CP_ME: 2001 *type = GFX_FW_TYPE_CP_ME; 2002 break; 2003 case AMDGPU_UCODE_ID_CP_MEC1: 2004 *type = GFX_FW_TYPE_CP_MEC; 2005 break; 2006 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2007 *type = GFX_FW_TYPE_CP_MEC_ME1; 2008 break; 2009 case AMDGPU_UCODE_ID_CP_MEC2: 2010 *type = GFX_FW_TYPE_CP_MEC; 2011 break; 2012 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2013 *type = GFX_FW_TYPE_CP_MEC_ME2; 2014 break; 2015 case AMDGPU_UCODE_ID_RLC_G: 2016 *type = GFX_FW_TYPE_RLC_G; 2017 break; 2018 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2019 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2020 break; 2021 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2022 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2023 break; 2024 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2025 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2026 break; 2027 case AMDGPU_UCODE_ID_RLC_IRAM: 2028 *type = GFX_FW_TYPE_RLC_IRAM; 2029 break; 2030 case AMDGPU_UCODE_ID_RLC_DRAM: 2031 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2032 break; 2033 case AMDGPU_UCODE_ID_SMC: 2034 *type = GFX_FW_TYPE_SMU; 2035 break; 2036 case AMDGPU_UCODE_ID_UVD: 2037 *type = GFX_FW_TYPE_UVD; 2038 break; 2039 case AMDGPU_UCODE_ID_UVD1: 2040 *type = GFX_FW_TYPE_UVD1; 2041 break; 2042 case AMDGPU_UCODE_ID_VCE: 2043 *type = GFX_FW_TYPE_VCE; 2044 break; 2045 case AMDGPU_UCODE_ID_VCN: 2046 *type = GFX_FW_TYPE_VCN; 2047 break; 2048 case AMDGPU_UCODE_ID_VCN1: 2049 *type = GFX_FW_TYPE_VCN1; 2050 break; 2051 case AMDGPU_UCODE_ID_DMCU_ERAM: 2052 *type = GFX_FW_TYPE_DMCU_ERAM; 2053 break; 2054 case AMDGPU_UCODE_ID_DMCU_INTV: 2055 *type = GFX_FW_TYPE_DMCU_ISR; 2056 break; 2057 case AMDGPU_UCODE_ID_VCN0_RAM: 2058 *type = GFX_FW_TYPE_VCN0_RAM; 2059 break; 2060 case AMDGPU_UCODE_ID_VCN1_RAM: 2061 *type = GFX_FW_TYPE_VCN1_RAM; 2062 break; 2063 case AMDGPU_UCODE_ID_DMCUB: 2064 *type = GFX_FW_TYPE_DMUB; 2065 break; 2066 case AMDGPU_UCODE_ID_MAXIMUM: 2067 default: 2068 return -EINVAL; 2069 } 2070 2071 return 0; 2072 } 2073 2074 static void psp_print_fw_hdr(struct psp_context *psp, 2075 struct amdgpu_firmware_info *ucode) 2076 { 2077 struct amdgpu_device *adev = psp->adev; 2078 struct common_firmware_header *hdr; 2079 2080 switch (ucode->ucode_id) { 2081 case AMDGPU_UCODE_ID_SDMA0: 2082 case AMDGPU_UCODE_ID_SDMA1: 2083 case AMDGPU_UCODE_ID_SDMA2: 2084 case AMDGPU_UCODE_ID_SDMA3: 2085 case AMDGPU_UCODE_ID_SDMA4: 2086 case AMDGPU_UCODE_ID_SDMA5: 2087 case AMDGPU_UCODE_ID_SDMA6: 2088 case AMDGPU_UCODE_ID_SDMA7: 2089 hdr = (struct common_firmware_header *) 2090 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2091 amdgpu_ucode_print_sdma_hdr(hdr); 2092 break; 2093 case AMDGPU_UCODE_ID_CP_CE: 2094 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2095 amdgpu_ucode_print_gfx_hdr(hdr); 2096 break; 2097 case AMDGPU_UCODE_ID_CP_PFP: 2098 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2099 amdgpu_ucode_print_gfx_hdr(hdr); 2100 break; 2101 case AMDGPU_UCODE_ID_CP_ME: 2102 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2103 amdgpu_ucode_print_gfx_hdr(hdr); 2104 break; 2105 case AMDGPU_UCODE_ID_CP_MEC1: 2106 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2107 amdgpu_ucode_print_gfx_hdr(hdr); 2108 break; 2109 case AMDGPU_UCODE_ID_RLC_G: 2110 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2111 amdgpu_ucode_print_rlc_hdr(hdr); 2112 break; 2113 case AMDGPU_UCODE_ID_SMC: 2114 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2115 amdgpu_ucode_print_smc_hdr(hdr); 2116 break; 2117 default: 2118 break; 2119 } 2120 } 2121 2122 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2123 struct psp_gfx_cmd_resp *cmd) 2124 { 2125 int ret; 2126 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2127 2128 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2129 2130 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2131 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2132 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2133 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2134 2135 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2136 if (ret) 2137 DRM_ERROR("Unknown firmware type\n"); 2138 2139 return ret; 2140 } 2141 2142 static int psp_execute_np_fw_load(struct psp_context *psp, 2143 struct amdgpu_firmware_info *ucode) 2144 { 2145 int ret = 0; 2146 2147 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2148 if (ret) 2149 return ret; 2150 2151 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2152 psp->fence_buf_mc_addr); 2153 2154 return ret; 2155 } 2156 2157 static int psp_load_smu_fw(struct psp_context *psp) 2158 { 2159 int ret; 2160 struct amdgpu_device *adev = psp->adev; 2161 struct amdgpu_firmware_info *ucode = 2162 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2163 struct amdgpu_ras *ras = psp->ras.ras; 2164 2165 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2166 return 0; 2167 2168 if ((amdgpu_in_reset(adev) && 2169 ras && ras->supported && 2170 (adev->asic_type == CHIP_ARCTURUS || 2171 adev->asic_type == CHIP_VEGA20)) || 2172 (adev->in_runpm && 2173 adev->asic_type >= CHIP_NAVI10 && 2174 adev->asic_type <= CHIP_NAVI12)) { 2175 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2176 if (ret) { 2177 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2178 } 2179 } 2180 2181 ret = psp_execute_np_fw_load(psp, ucode); 2182 2183 if (ret) 2184 DRM_ERROR("PSP load smu failed!\n"); 2185 2186 return ret; 2187 } 2188 2189 static bool fw_load_skip_check(struct psp_context *psp, 2190 struct amdgpu_firmware_info *ucode) 2191 { 2192 if (!ucode->fw) 2193 return true; 2194 2195 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2196 (psp_smu_reload_quirk(psp) || 2197 psp->autoload_supported || 2198 psp->pmfw_centralized_cstate_management)) 2199 return true; 2200 2201 if (amdgpu_sriov_vf(psp->adev) && 2202 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2203 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2204 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2205 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2206 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2207 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2208 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2209 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2210 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2211 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2212 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2213 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2214 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2215 /*skip ucode loading in SRIOV VF */ 2216 return true; 2217 2218 if (psp->autoload_supported && 2219 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2220 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2221 /* skip mec JT when autoload is enabled */ 2222 return true; 2223 2224 return false; 2225 } 2226 2227 int psp_load_fw_list(struct psp_context *psp, 2228 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2229 { 2230 int ret = 0, i; 2231 struct amdgpu_firmware_info *ucode; 2232 2233 for (i = 0; i < ucode_count; ++i) { 2234 ucode = ucode_list[i]; 2235 psp_print_fw_hdr(psp, ucode); 2236 ret = psp_execute_np_fw_load(psp, ucode); 2237 if (ret) 2238 return ret; 2239 } 2240 return ret; 2241 } 2242 2243 static int psp_np_fw_load(struct psp_context *psp) 2244 { 2245 int i, ret; 2246 struct amdgpu_firmware_info *ucode; 2247 struct amdgpu_device *adev = psp->adev; 2248 2249 if (psp->autoload_supported && 2250 !psp->pmfw_centralized_cstate_management) { 2251 ret = psp_load_smu_fw(psp); 2252 if (ret) 2253 return ret; 2254 } 2255 2256 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2257 ucode = &adev->firmware.ucode[i]; 2258 2259 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2260 !fw_load_skip_check(psp, ucode)) { 2261 ret = psp_load_smu_fw(psp); 2262 if (ret) 2263 return ret; 2264 continue; 2265 } 2266 2267 if (fw_load_skip_check(psp, ucode)) 2268 continue; 2269 2270 if (psp->autoload_supported && 2271 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2272 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2273 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2274 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2275 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2276 /* PSP only receive one SDMA fw for sienna_cichlid, 2277 * as all four sdma fw are same */ 2278 continue; 2279 2280 psp_print_fw_hdr(psp, ucode); 2281 2282 ret = psp_execute_np_fw_load(psp, ucode); 2283 if (ret) 2284 return ret; 2285 2286 /* Start rlc autoload after psp recieved all the gfx firmware */ 2287 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2288 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2289 ret = psp_rlc_autoload_start(psp); 2290 if (ret) { 2291 DRM_ERROR("Failed to start rlc autoload\n"); 2292 return ret; 2293 } 2294 } 2295 } 2296 2297 return 0; 2298 } 2299 2300 static int psp_load_fw(struct amdgpu_device *adev) 2301 { 2302 int ret; 2303 struct psp_context *psp = &adev->psp; 2304 2305 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2306 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2307 goto skip_memalloc; 2308 } 2309 2310 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2311 if (!psp->cmd) 2312 return -ENOMEM; 2313 2314 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2315 AMDGPU_GEM_DOMAIN_GTT, 2316 &psp->fw_pri_bo, 2317 &psp->fw_pri_mc_addr, 2318 &psp->fw_pri_buf); 2319 if (ret) 2320 goto failed; 2321 2322 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2323 AMDGPU_GEM_DOMAIN_VRAM, 2324 &psp->fence_buf_bo, 2325 &psp->fence_buf_mc_addr, 2326 &psp->fence_buf); 2327 if (ret) 2328 goto failed; 2329 2330 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2331 AMDGPU_GEM_DOMAIN_VRAM, 2332 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2333 (void **)&psp->cmd_buf_mem); 2334 if (ret) 2335 goto failed; 2336 2337 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2338 2339 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2340 if (ret) { 2341 DRM_ERROR("PSP ring init failed!\n"); 2342 goto failed; 2343 } 2344 2345 skip_memalloc: 2346 ret = psp_hw_start(psp); 2347 if (ret) 2348 goto failed; 2349 2350 ret = psp_np_fw_load(psp); 2351 if (ret) 2352 goto failed; 2353 2354 ret = psp_asd_load(psp); 2355 if (ret) { 2356 DRM_ERROR("PSP load asd failed!\n"); 2357 return ret; 2358 } 2359 2360 ret = psp_rl_load(adev); 2361 if (ret) { 2362 DRM_ERROR("PSP load RL failed!\n"); 2363 return ret; 2364 } 2365 2366 if (psp->adev->psp.ta_fw) { 2367 ret = psp_ras_initialize(psp); 2368 if (ret) 2369 dev_err(psp->adev->dev, 2370 "RAS: Failed to initialize RAS\n"); 2371 2372 ret = psp_hdcp_initialize(psp); 2373 if (ret) 2374 dev_err(psp->adev->dev, 2375 "HDCP: Failed to initialize HDCP\n"); 2376 2377 ret = psp_dtm_initialize(psp); 2378 if (ret) 2379 dev_err(psp->adev->dev, 2380 "DTM: Failed to initialize DTM\n"); 2381 2382 ret = psp_rap_initialize(psp); 2383 if (ret) 2384 dev_err(psp->adev->dev, 2385 "RAP: Failed to initialize RAP\n"); 2386 2387 ret = psp_securedisplay_initialize(psp); 2388 if (ret) 2389 dev_err(psp->adev->dev, 2390 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2391 } 2392 2393 return 0; 2394 2395 failed: 2396 /* 2397 * all cleanup jobs (xgmi terminate, ras terminate, 2398 * ring destroy, cmd/fence/fw buffers destory, 2399 * psp->cmd destory) are delayed to psp_hw_fini 2400 */ 2401 return ret; 2402 } 2403 2404 static int psp_hw_init(void *handle) 2405 { 2406 int ret; 2407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2408 2409 mutex_lock(&adev->firmware.mutex); 2410 /* 2411 * This sequence is just used on hw_init only once, no need on 2412 * resume. 2413 */ 2414 ret = amdgpu_ucode_init_bo(adev); 2415 if (ret) 2416 goto failed; 2417 2418 ret = psp_load_fw(adev); 2419 if (ret) { 2420 DRM_ERROR("PSP firmware loading failed\n"); 2421 goto failed; 2422 } 2423 2424 mutex_unlock(&adev->firmware.mutex); 2425 return 0; 2426 2427 failed: 2428 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2429 mutex_unlock(&adev->firmware.mutex); 2430 return -EINVAL; 2431 } 2432 2433 static int psp_hw_fini(void *handle) 2434 { 2435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2436 struct psp_context *psp = &adev->psp; 2437 int ret; 2438 2439 if (psp->adev->psp.ta_fw) { 2440 psp_ras_terminate(psp); 2441 psp_securedisplay_terminate(psp); 2442 psp_rap_terminate(psp); 2443 psp_dtm_terminate(psp); 2444 psp_hdcp_terminate(psp); 2445 } 2446 2447 psp_asd_unload(psp); 2448 ret = psp_clear_vf_fw(psp); 2449 if (ret) { 2450 DRM_ERROR("PSP clear vf fw!\n"); 2451 return ret; 2452 } 2453 2454 psp_tmr_terminate(psp); 2455 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2456 2457 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2458 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2459 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2460 &psp->fence_buf_mc_addr, &psp->fence_buf); 2461 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2462 (void **)&psp->cmd_buf_mem); 2463 2464 kfree(psp->cmd); 2465 psp->cmd = NULL; 2466 2467 return 0; 2468 } 2469 2470 static int psp_suspend(void *handle) 2471 { 2472 int ret; 2473 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2474 struct psp_context *psp = &adev->psp; 2475 2476 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2477 psp->xgmi_context.initialized == 1) { 2478 ret = psp_xgmi_terminate(psp); 2479 if (ret) { 2480 DRM_ERROR("Failed to terminate xgmi ta\n"); 2481 return ret; 2482 } 2483 } 2484 2485 if (psp->adev->psp.ta_fw) { 2486 ret = psp_ras_terminate(psp); 2487 if (ret) { 2488 DRM_ERROR("Failed to terminate ras ta\n"); 2489 return ret; 2490 } 2491 ret = psp_hdcp_terminate(psp); 2492 if (ret) { 2493 DRM_ERROR("Failed to terminate hdcp ta\n"); 2494 return ret; 2495 } 2496 ret = psp_dtm_terminate(psp); 2497 if (ret) { 2498 DRM_ERROR("Failed to terminate dtm ta\n"); 2499 return ret; 2500 } 2501 ret = psp_rap_terminate(psp); 2502 if (ret) { 2503 DRM_ERROR("Failed to terminate rap ta\n"); 2504 return ret; 2505 } 2506 ret = psp_securedisplay_terminate(psp); 2507 if (ret) { 2508 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2509 return ret; 2510 } 2511 } 2512 2513 ret = psp_asd_unload(psp); 2514 if (ret) { 2515 DRM_ERROR("Failed to unload asd\n"); 2516 return ret; 2517 } 2518 2519 ret = psp_tmr_terminate(psp); 2520 if (ret) { 2521 DRM_ERROR("Failed to terminate tmr\n"); 2522 return ret; 2523 } 2524 2525 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2526 if (ret) { 2527 DRM_ERROR("PSP ring stop failed\n"); 2528 return ret; 2529 } 2530 2531 return 0; 2532 } 2533 2534 static int psp_resume(void *handle) 2535 { 2536 int ret; 2537 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2538 struct psp_context *psp = &adev->psp; 2539 2540 DRM_INFO("PSP is resuming...\n"); 2541 2542 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2543 if (ret) { 2544 DRM_ERROR("Failed to process memory training!\n"); 2545 return ret; 2546 } 2547 2548 mutex_lock(&adev->firmware.mutex); 2549 2550 ret = psp_hw_start(psp); 2551 if (ret) 2552 goto failed; 2553 2554 ret = psp_np_fw_load(psp); 2555 if (ret) 2556 goto failed; 2557 2558 ret = psp_asd_load(psp); 2559 if (ret) { 2560 DRM_ERROR("PSP load asd failed!\n"); 2561 goto failed; 2562 } 2563 2564 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2565 ret = psp_xgmi_initialize(psp); 2566 /* Warning the XGMI seesion initialize failure 2567 * Instead of stop driver initialization 2568 */ 2569 if (ret) 2570 dev_err(psp->adev->dev, 2571 "XGMI: Failed to initialize XGMI session\n"); 2572 } 2573 2574 if (psp->adev->psp.ta_fw) { 2575 ret = psp_ras_initialize(psp); 2576 if (ret) 2577 dev_err(psp->adev->dev, 2578 "RAS: Failed to initialize RAS\n"); 2579 2580 ret = psp_hdcp_initialize(psp); 2581 if (ret) 2582 dev_err(psp->adev->dev, 2583 "HDCP: Failed to initialize HDCP\n"); 2584 2585 ret = psp_dtm_initialize(psp); 2586 if (ret) 2587 dev_err(psp->adev->dev, 2588 "DTM: Failed to initialize DTM\n"); 2589 2590 ret = psp_rap_initialize(psp); 2591 if (ret) 2592 dev_err(psp->adev->dev, 2593 "RAP: Failed to initialize RAP\n"); 2594 2595 ret = psp_securedisplay_initialize(psp); 2596 if (ret) 2597 dev_err(psp->adev->dev, 2598 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2599 } 2600 2601 mutex_unlock(&adev->firmware.mutex); 2602 2603 return 0; 2604 2605 failed: 2606 DRM_ERROR("PSP resume failed\n"); 2607 mutex_unlock(&adev->firmware.mutex); 2608 return ret; 2609 } 2610 2611 int psp_gpu_reset(struct amdgpu_device *adev) 2612 { 2613 int ret; 2614 2615 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2616 return 0; 2617 2618 mutex_lock(&adev->psp.mutex); 2619 ret = psp_mode1_reset(&adev->psp); 2620 mutex_unlock(&adev->psp.mutex); 2621 2622 return ret; 2623 } 2624 2625 int psp_rlc_autoload_start(struct psp_context *psp) 2626 { 2627 int ret; 2628 struct psp_gfx_cmd_resp *cmd; 2629 2630 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2631 if (!cmd) 2632 return -ENOMEM; 2633 2634 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2635 2636 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2637 psp->fence_buf_mc_addr); 2638 kfree(cmd); 2639 return ret; 2640 } 2641 2642 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2643 uint64_t cmd_gpu_addr, int cmd_size) 2644 { 2645 struct amdgpu_firmware_info ucode = {0}; 2646 2647 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2648 AMDGPU_UCODE_ID_VCN0_RAM; 2649 ucode.mc_addr = cmd_gpu_addr; 2650 ucode.ucode_size = cmd_size; 2651 2652 return psp_execute_np_fw_load(&adev->psp, &ucode); 2653 } 2654 2655 int psp_ring_cmd_submit(struct psp_context *psp, 2656 uint64_t cmd_buf_mc_addr, 2657 uint64_t fence_mc_addr, 2658 int index) 2659 { 2660 unsigned int psp_write_ptr_reg = 0; 2661 struct psp_gfx_rb_frame *write_frame; 2662 struct psp_ring *ring = &psp->km_ring; 2663 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2664 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2665 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2666 struct amdgpu_device *adev = psp->adev; 2667 uint32_t ring_size_dw = ring->ring_size / 4; 2668 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2669 2670 /* KM (GPCOM) prepare write pointer */ 2671 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2672 2673 /* Update KM RB frame pointer to new frame */ 2674 /* write_frame ptr increments by size of rb_frame in bytes */ 2675 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2676 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2677 write_frame = ring_buffer_start; 2678 else 2679 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2680 /* Check invalid write_frame ptr address */ 2681 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2682 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2683 ring_buffer_start, ring_buffer_end, write_frame); 2684 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2685 return -EINVAL; 2686 } 2687 2688 /* Initialize KM RB frame */ 2689 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2690 2691 /* Update KM RB frame */ 2692 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2693 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2694 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2695 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2696 write_frame->fence_value = index; 2697 amdgpu_asic_flush_hdp(adev, NULL); 2698 2699 /* Update the write Pointer in DWORDs */ 2700 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2701 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2702 return 0; 2703 } 2704 2705 int psp_init_asd_microcode(struct psp_context *psp, 2706 const char *chip_name) 2707 { 2708 struct amdgpu_device *adev = psp->adev; 2709 char fw_name[PSP_FW_NAME_LEN]; 2710 const struct psp_firmware_header_v1_0 *asd_hdr; 2711 int err = 0; 2712 2713 if (!chip_name) { 2714 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2715 return -EINVAL; 2716 } 2717 2718 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2719 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2720 if (err) 2721 goto out; 2722 2723 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2724 if (err) 2725 goto out; 2726 2727 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2728 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2729 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2730 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2731 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2732 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2733 return 0; 2734 out: 2735 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2736 release_firmware(adev->psp.asd_fw); 2737 adev->psp.asd_fw = NULL; 2738 return err; 2739 } 2740 2741 int psp_init_toc_microcode(struct psp_context *psp, 2742 const char *chip_name) 2743 { 2744 struct amdgpu_device *adev = psp->adev; 2745 char fw_name[30]; 2746 const struct psp_firmware_header_v1_0 *toc_hdr; 2747 int err = 0; 2748 2749 if (!chip_name) { 2750 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2751 return -EINVAL; 2752 } 2753 2754 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2755 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2756 if (err) 2757 goto out; 2758 2759 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2760 if (err) 2761 goto out; 2762 2763 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2764 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2765 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2766 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2767 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2768 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2769 return 0; 2770 out: 2771 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2772 release_firmware(adev->psp.toc_fw); 2773 adev->psp.toc_fw = NULL; 2774 return err; 2775 } 2776 2777 int psp_init_sos_microcode(struct psp_context *psp, 2778 const char *chip_name) 2779 { 2780 struct amdgpu_device *adev = psp->adev; 2781 char fw_name[PSP_FW_NAME_LEN]; 2782 const struct psp_firmware_header_v1_0 *sos_hdr; 2783 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2784 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2785 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2786 int err = 0; 2787 2788 if (!chip_name) { 2789 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2790 return -EINVAL; 2791 } 2792 2793 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2794 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2795 if (err) 2796 goto out; 2797 2798 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2799 if (err) 2800 goto out; 2801 2802 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2803 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2804 2805 switch (sos_hdr->header.header_version_major) { 2806 case 1: 2807 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2808 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2809 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2810 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2811 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2812 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2813 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2814 le32_to_cpu(sos_hdr->sos_offset_bytes); 2815 if (sos_hdr->header.header_version_minor == 1) { 2816 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2817 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2818 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2819 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2820 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2821 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2822 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2823 } 2824 if (sos_hdr->header.header_version_minor == 2) { 2825 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2826 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2827 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2828 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2829 } 2830 if (sos_hdr->header.header_version_minor == 3) { 2831 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2832 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2833 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2834 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2835 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2836 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2837 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2838 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2839 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2840 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2841 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2842 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2843 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2844 } 2845 break; 2846 default: 2847 dev_err(adev->dev, 2848 "unsupported psp sos firmware\n"); 2849 err = -EINVAL; 2850 goto out; 2851 } 2852 2853 return 0; 2854 out: 2855 dev_err(adev->dev, 2856 "failed to init sos firmware\n"); 2857 release_firmware(adev->psp.sos_fw); 2858 adev->psp.sos_fw = NULL; 2859 2860 return err; 2861 } 2862 2863 static int parse_ta_bin_descriptor(struct psp_context *psp, 2864 const struct ta_fw_bin_desc *desc, 2865 const struct ta_firmware_header_v2_0 *ta_hdr) 2866 { 2867 uint8_t *ucode_start_addr = NULL; 2868 2869 if (!psp || !desc || !ta_hdr) 2870 return -EINVAL; 2871 2872 ucode_start_addr = (uint8_t *)ta_hdr + 2873 le32_to_cpu(desc->offset_bytes) + 2874 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2875 2876 switch (desc->fw_type) { 2877 case TA_FW_TYPE_PSP_ASD: 2878 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2879 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2880 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2881 psp->asd_start_addr = ucode_start_addr; 2882 break; 2883 case TA_FW_TYPE_PSP_XGMI: 2884 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2885 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2886 psp->ta_xgmi_start_addr = ucode_start_addr; 2887 break; 2888 case TA_FW_TYPE_PSP_RAS: 2889 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2890 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2891 psp->ta_ras_start_addr = ucode_start_addr; 2892 break; 2893 case TA_FW_TYPE_PSP_HDCP: 2894 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2895 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2896 psp->ta_hdcp_start_addr = ucode_start_addr; 2897 break; 2898 case TA_FW_TYPE_PSP_DTM: 2899 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2900 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2901 psp->ta_dtm_start_addr = ucode_start_addr; 2902 break; 2903 case TA_FW_TYPE_PSP_RAP: 2904 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2905 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2906 psp->ta_rap_start_addr = ucode_start_addr; 2907 break; 2908 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2909 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2910 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2911 psp->ta_securedisplay_start_addr = ucode_start_addr; 2912 break; 2913 default: 2914 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2915 break; 2916 } 2917 2918 return 0; 2919 } 2920 2921 int psp_init_ta_microcode(struct psp_context *psp, 2922 const char *chip_name) 2923 { 2924 struct amdgpu_device *adev = psp->adev; 2925 char fw_name[PSP_FW_NAME_LEN]; 2926 const struct ta_firmware_header_v2_0 *ta_hdr; 2927 int err = 0; 2928 int ta_index = 0; 2929 2930 if (!chip_name) { 2931 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2932 return -EINVAL; 2933 } 2934 2935 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2936 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2937 if (err) 2938 goto out; 2939 2940 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2941 if (err) 2942 goto out; 2943 2944 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2945 2946 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2947 dev_err(adev->dev, "unsupported TA header version\n"); 2948 err = -EINVAL; 2949 goto out; 2950 } 2951 2952 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2953 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2954 err = -EINVAL; 2955 goto out; 2956 } 2957 2958 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2959 err = parse_ta_bin_descriptor(psp, 2960 &ta_hdr->ta_fw_bin[ta_index], 2961 ta_hdr); 2962 if (err) 2963 goto out; 2964 } 2965 2966 return 0; 2967 out: 2968 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2969 release_firmware(adev->psp.ta_fw); 2970 adev->psp.ta_fw = NULL; 2971 return err; 2972 } 2973 2974 static int psp_set_clockgating_state(void *handle, 2975 enum amd_clockgating_state state) 2976 { 2977 return 0; 2978 } 2979 2980 static int psp_set_powergating_state(void *handle, 2981 enum amd_powergating_state state) 2982 { 2983 return 0; 2984 } 2985 2986 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2987 struct device_attribute *attr, 2988 char *buf) 2989 { 2990 struct drm_device *ddev = dev_get_drvdata(dev); 2991 struct amdgpu_device *adev = drm_to_adev(ddev); 2992 uint32_t fw_ver; 2993 int ret; 2994 2995 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2996 DRM_INFO("PSP block is not ready yet."); 2997 return -EBUSY; 2998 } 2999 3000 mutex_lock(&adev->psp.mutex); 3001 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3002 mutex_unlock(&adev->psp.mutex); 3003 3004 if (ret) { 3005 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3006 return ret; 3007 } 3008 3009 return sysfs_emit(buf, "%x\n", fw_ver); 3010 } 3011 3012 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3013 struct device_attribute *attr, 3014 const char *buf, 3015 size_t count) 3016 { 3017 struct drm_device *ddev = dev_get_drvdata(dev); 3018 struct amdgpu_device *adev = drm_to_adev(ddev); 3019 void *cpu_addr; 3020 dma_addr_t dma_addr; 3021 int ret; 3022 char fw_name[100]; 3023 const struct firmware *usbc_pd_fw; 3024 3025 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3026 DRM_INFO("PSP block is not ready yet."); 3027 return -EBUSY; 3028 } 3029 3030 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3031 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3032 if (ret) 3033 goto fail; 3034 3035 /* We need contiguous physical mem to place the FW for psp to access */ 3036 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3037 3038 ret = dma_mapping_error(adev->dev, dma_addr); 3039 if (ret) 3040 goto rel_buf; 3041 3042 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3043 3044 /* 3045 * x86 specific workaround. 3046 * Without it the buffer is invisible in PSP. 3047 * 3048 * TODO Remove once PSP starts snooping CPU cache 3049 */ 3050 #ifdef CONFIG_X86 3051 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3052 #endif 3053 3054 mutex_lock(&adev->psp.mutex); 3055 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3056 mutex_unlock(&adev->psp.mutex); 3057 3058 rel_buf: 3059 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3060 release_firmware(usbc_pd_fw); 3061 3062 fail: 3063 if (ret) { 3064 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3065 return ret; 3066 } 3067 3068 return count; 3069 } 3070 3071 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3072 psp_usbc_pd_fw_sysfs_read, 3073 psp_usbc_pd_fw_sysfs_write); 3074 3075 3076 3077 const struct amd_ip_funcs psp_ip_funcs = { 3078 .name = "psp", 3079 .early_init = psp_early_init, 3080 .late_init = NULL, 3081 .sw_init = psp_sw_init, 3082 .sw_fini = psp_sw_fini, 3083 .hw_init = psp_hw_init, 3084 .hw_fini = psp_hw_fini, 3085 .suspend = psp_suspend, 3086 .resume = psp_resume, 3087 .is_idle = NULL, 3088 .check_soft_reset = NULL, 3089 .wait_for_idle = NULL, 3090 .soft_reset = NULL, 3091 .set_clockgating_state = psp_set_clockgating_state, 3092 .set_powergating_state = psp_set_powergating_state, 3093 }; 3094 3095 static int psp_sysfs_init(struct amdgpu_device *adev) 3096 { 3097 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3098 3099 if (ret) 3100 DRM_ERROR("Failed to create USBC PD FW control file!"); 3101 3102 return ret; 3103 } 3104 3105 static void psp_sysfs_fini(struct amdgpu_device *adev) 3106 { 3107 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3108 } 3109 3110 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3111 { 3112 .type = AMD_IP_BLOCK_TYPE_PSP, 3113 .major = 3, 3114 .minor = 1, 3115 .rev = 0, 3116 .funcs = &psp_ip_funcs, 3117 }; 3118 3119 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3120 { 3121 .type = AMD_IP_BLOCK_TYPE_PSP, 3122 .major = 10, 3123 .minor = 0, 3124 .rev = 0, 3125 .funcs = &psp_ip_funcs, 3126 }; 3127 3128 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3129 { 3130 .type = AMD_IP_BLOCK_TYPE_PSP, 3131 .major = 11, 3132 .minor = 0, 3133 .rev = 0, 3134 .funcs = &psp_ip_funcs, 3135 }; 3136 3137 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3138 { 3139 .type = AMD_IP_BLOCK_TYPE_PSP, 3140 .major = 12, 3141 .minor = 0, 3142 .rev = 0, 3143 .funcs = &psp_ip_funcs, 3144 }; 3145 3146 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3147 .type = AMD_IP_BLOCK_TYPE_PSP, 3148 .major = 13, 3149 .minor = 0, 3150 .rev = 0, 3151 .funcs = &psp_ip_funcs, 3152 }; 3153