1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 38 #include "amdgpu_ras.h" 39 40 static int psp_sysfs_init(struct amdgpu_device *adev); 41 static void psp_sysfs_fini(struct amdgpu_device *adev); 42 43 static int psp_load_smu_fw(struct psp_context *psp); 44 45 /* 46 * Due to DF Cstate management centralized to PMFW, the firmware 47 * loading sequence will be updated as below: 48 * - Load KDB 49 * - Load SYS_DRV 50 * - Load tOS 51 * - Load PMFW 52 * - Setup TMR 53 * - Load other non-psp fw 54 * - Load ASD 55 * - Load XGMI/RAS/HDCP/DTM TA if any 56 * 57 * This new sequence is required for 58 * - Arcturus 59 * - Navi12 and onwards 60 */ 61 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 62 { 63 struct amdgpu_device *adev = psp->adev; 64 65 psp->pmfw_centralized_cstate_management = false; 66 67 if (amdgpu_sriov_vf(adev)) 68 return; 69 70 if (adev->flags & AMD_IS_APU) 71 return; 72 73 if ((adev->asic_type == CHIP_ARCTURUS) || 74 (adev->asic_type >= CHIP_NAVI12)) 75 psp->pmfw_centralized_cstate_management = true; 76 } 77 78 static int psp_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 struct psp_context *psp = &adev->psp; 82 83 switch (adev->asic_type) { 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 psp_v3_1_set_psp_funcs(psp); 87 psp->autoload_supported = false; 88 break; 89 case CHIP_RAVEN: 90 psp_v10_0_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_VEGA20: 94 case CHIP_ARCTURUS: 95 psp_v11_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_NAVI10: 99 case CHIP_NAVI14: 100 case CHIP_NAVI12: 101 case CHIP_SIENNA_CICHLID: 102 case CHIP_NAVY_FLOUNDER: 103 psp_v11_0_set_psp_funcs(psp); 104 psp->autoload_supported = true; 105 break; 106 case CHIP_RENOIR: 107 psp_v12_0_set_psp_funcs(psp); 108 break; 109 default: 110 return -EINVAL; 111 } 112 113 psp->adev = adev; 114 115 psp_check_pmfw_centralized_cstate_management(psp); 116 117 return 0; 118 } 119 120 static void psp_memory_training_fini(struct psp_context *psp) 121 { 122 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 123 124 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 125 kfree(ctx->sys_cache); 126 ctx->sys_cache = NULL; 127 } 128 129 static int psp_memory_training_init(struct psp_context *psp) 130 { 131 int ret; 132 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 133 134 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 135 DRM_DEBUG("memory training is not supported!\n"); 136 return 0; 137 } 138 139 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 140 if (ctx->sys_cache == NULL) { 141 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 142 ret = -ENOMEM; 143 goto Err_out; 144 } 145 146 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 147 ctx->train_data_size, 148 ctx->p2c_train_data_offset, 149 ctx->c2p_train_data_offset); 150 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 151 return 0; 152 153 Err_out: 154 psp_memory_training_fini(psp); 155 return ret; 156 } 157 158 static int psp_sw_init(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 struct psp_context *psp = &adev->psp; 162 int ret; 163 164 ret = psp_init_microcode(psp); 165 if (ret) { 166 DRM_ERROR("Failed to load psp firmware!\n"); 167 return ret; 168 } 169 170 ret = psp_memory_training_init(psp); 171 if (ret) { 172 DRM_ERROR("Failed to initialize memory training!\n"); 173 return ret; 174 } 175 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 176 if (ret) { 177 DRM_ERROR("Failed to process memory training!\n"); 178 return ret; 179 } 180 181 if (adev->asic_type == CHIP_NAVI10) { 182 ret= psp_sysfs_init(adev); 183 if (ret) { 184 return ret; 185 } 186 } 187 188 return 0; 189 } 190 191 static int psp_sw_fini(void *handle) 192 { 193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 194 195 psp_memory_training_fini(&adev->psp); 196 release_firmware(adev->psp.sos_fw); 197 adev->psp.sos_fw = NULL; 198 release_firmware(adev->psp.asd_fw); 199 adev->psp.asd_fw = NULL; 200 release_firmware(adev->psp.ta_fw); 201 adev->psp.ta_fw = NULL; 202 203 if (adev->asic_type == CHIP_NAVI10) 204 psp_sysfs_fini(adev); 205 206 return 0; 207 } 208 209 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 210 uint32_t reg_val, uint32_t mask, bool check_changed) 211 { 212 uint32_t val; 213 int i; 214 struct amdgpu_device *adev = psp->adev; 215 216 for (i = 0; i < adev->usec_timeout; i++) { 217 val = RREG32(reg_index); 218 if (check_changed) { 219 if (val != reg_val) 220 return 0; 221 } else { 222 if ((val & mask) == reg_val) 223 return 0; 224 } 225 udelay(1); 226 } 227 228 return -ETIME; 229 } 230 231 static int 232 psp_cmd_submit_buf(struct psp_context *psp, 233 struct amdgpu_firmware_info *ucode, 234 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 235 { 236 int ret; 237 int index; 238 int timeout = 2000; 239 bool ras_intr = false; 240 bool skip_unsupport = false; 241 242 mutex_lock(&psp->mutex); 243 244 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 245 246 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 247 248 index = atomic_inc_return(&psp->fence_value); 249 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 250 if (ret) { 251 atomic_dec(&psp->fence_value); 252 mutex_unlock(&psp->mutex); 253 return ret; 254 } 255 256 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 257 while (*((unsigned int *)psp->fence_buf) != index) { 258 if (--timeout == 0) 259 break; 260 /* 261 * Shouldn't wait for timeout when err_event_athub occurs, 262 * because gpu reset thread triggered and lock resource should 263 * be released for psp resume sequence. 264 */ 265 ras_intr = amdgpu_ras_intr_triggered(); 266 if (ras_intr) 267 break; 268 msleep(1); 269 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 270 } 271 272 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 273 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 274 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 275 276 /* In some cases, psp response status is not 0 even there is no 277 * problem while the command is submitted. Some version of PSP FW 278 * doesn't write 0 to that field. 279 * So here we would like to only print a warning instead of an error 280 * during psp initialization to avoid breaking hw_init and it doesn't 281 * return -EINVAL. 282 */ 283 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 284 if (ucode) 285 DRM_WARN("failed to load ucode id (%d) ", 286 ucode->ucode_id); 287 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 288 psp->cmd_buf_mem->cmd_id, 289 psp->cmd_buf_mem->resp.status); 290 if (!timeout) { 291 mutex_unlock(&psp->mutex); 292 return -EINVAL; 293 } 294 } 295 296 /* get xGMI session id from response buffer */ 297 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 298 299 if (ucode) { 300 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 301 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 302 } 303 mutex_unlock(&psp->mutex); 304 305 return ret; 306 } 307 308 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 309 struct psp_gfx_cmd_resp *cmd, 310 uint64_t tmr_mc, uint32_t size) 311 { 312 if (amdgpu_sriov_vf(psp->adev)) 313 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 314 else 315 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 316 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 317 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 318 cmd->cmd.cmd_setup_tmr.buf_size = size; 319 } 320 321 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 322 uint64_t pri_buf_mc, uint32_t size) 323 { 324 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 325 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 326 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 327 cmd->cmd.cmd_load_toc.toc_size = size; 328 } 329 330 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 331 static int psp_load_toc(struct psp_context *psp, 332 uint32_t *tmr_size) 333 { 334 int ret; 335 struct psp_gfx_cmd_resp *cmd; 336 337 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 338 if (!cmd) 339 return -ENOMEM; 340 /* Copy toc to psp firmware private buffer */ 341 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 342 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 343 344 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 345 346 ret = psp_cmd_submit_buf(psp, NULL, cmd, 347 psp->fence_buf_mc_addr); 348 if (!ret) 349 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 350 kfree(cmd); 351 return ret; 352 } 353 354 /* Set up Trusted Memory Region */ 355 static int psp_tmr_init(struct psp_context *psp) 356 { 357 int ret; 358 int tmr_size; 359 void *tmr_buf; 360 void **pptr; 361 362 /* 363 * According to HW engineer, they prefer the TMR address be "naturally 364 * aligned" , e.g. the start address be an integer divide of TMR size. 365 * 366 * Note: this memory need be reserved till the driver 367 * uninitializes. 368 */ 369 tmr_size = PSP_TMR_SIZE; 370 371 /* For ASICs support RLC autoload, psp will parse the toc 372 * and calculate the total size of TMR needed */ 373 if (!amdgpu_sriov_vf(psp->adev) && 374 psp->toc_start_addr && 375 psp->toc_bin_size && 376 psp->fw_pri_buf) { 377 ret = psp_load_toc(psp, &tmr_size); 378 if (ret) { 379 DRM_ERROR("Failed to load toc\n"); 380 return ret; 381 } 382 } 383 384 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 385 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 386 AMDGPU_GEM_DOMAIN_VRAM, 387 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 388 389 return ret; 390 } 391 392 static int psp_clear_vf_fw(struct psp_context *psp) 393 { 394 int ret; 395 struct psp_gfx_cmd_resp *cmd; 396 397 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) 398 return 0; 399 400 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 401 if (!cmd) 402 return -ENOMEM; 403 404 cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW; 405 406 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 407 kfree(cmd); 408 409 return ret; 410 } 411 412 static int psp_tmr_load(struct psp_context *psp) 413 { 414 int ret; 415 struct psp_gfx_cmd_resp *cmd; 416 417 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 418 if (!cmd) 419 return -ENOMEM; 420 421 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 422 amdgpu_bo_size(psp->tmr_bo)); 423 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 424 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 425 426 ret = psp_cmd_submit_buf(psp, NULL, cmd, 427 psp->fence_buf_mc_addr); 428 429 kfree(cmd); 430 431 return ret; 432 } 433 434 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 435 struct psp_gfx_cmd_resp *cmd) 436 { 437 if (amdgpu_sriov_vf(psp->adev)) 438 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 439 else 440 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 441 } 442 443 static int psp_tmr_unload(struct psp_context *psp) 444 { 445 int ret; 446 struct psp_gfx_cmd_resp *cmd; 447 448 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 449 if (!cmd) 450 return -ENOMEM; 451 452 psp_prep_tmr_unload_cmd_buf(psp, cmd); 453 DRM_INFO("free PSP TMR buffer\n"); 454 455 ret = psp_cmd_submit_buf(psp, NULL, cmd, 456 psp->fence_buf_mc_addr); 457 458 kfree(cmd); 459 460 return ret; 461 } 462 463 static int psp_tmr_terminate(struct psp_context *psp) 464 { 465 int ret; 466 void *tmr_buf; 467 void **pptr; 468 469 ret = psp_tmr_unload(psp); 470 if (ret) 471 return ret; 472 473 /* free TMR memory buffer */ 474 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 475 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 476 477 return 0; 478 } 479 480 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 481 uint64_t asd_mc, uint32_t size) 482 { 483 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 484 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 485 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 486 cmd->cmd.cmd_load_ta.app_len = size; 487 488 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 489 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 490 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 491 } 492 493 static int psp_asd_load(struct psp_context *psp) 494 { 495 int ret; 496 struct psp_gfx_cmd_resp *cmd; 497 498 /* If PSP version doesn't match ASD version, asd loading will be failed. 499 * add workaround to bypass it for sriov now. 500 * TODO: add version check to make it common 501 */ 502 if (amdgpu_sriov_vf(psp->adev) || 503 (psp->adev->asic_type == CHIP_SIENNA_CICHLID) || 504 (psp->adev->asic_type == CHIP_NAVY_FLOUNDER)) 505 return 0; 506 507 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 508 if (!cmd) 509 return -ENOMEM; 510 511 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 512 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 513 514 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 515 psp->asd_ucode_size); 516 517 ret = psp_cmd_submit_buf(psp, NULL, cmd, 518 psp->fence_buf_mc_addr); 519 if (!ret) { 520 psp->asd_context.asd_initialized = true; 521 psp->asd_context.session_id = cmd->resp.session_id; 522 } 523 524 kfree(cmd); 525 526 return ret; 527 } 528 529 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 530 uint32_t session_id) 531 { 532 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 533 cmd->cmd.cmd_unload_ta.session_id = session_id; 534 } 535 536 static int psp_asd_unload(struct psp_context *psp) 537 { 538 int ret; 539 struct psp_gfx_cmd_resp *cmd; 540 541 if (amdgpu_sriov_vf(psp->adev)) 542 return 0; 543 544 if (!psp->asd_context.asd_initialized) 545 return 0; 546 547 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 548 if (!cmd) 549 return -ENOMEM; 550 551 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 552 553 ret = psp_cmd_submit_buf(psp, NULL, cmd, 554 psp->fence_buf_mc_addr); 555 if (!ret) 556 psp->asd_context.asd_initialized = false; 557 558 kfree(cmd); 559 560 return ret; 561 } 562 563 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 564 uint32_t id, uint32_t value) 565 { 566 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 567 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 568 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 569 } 570 571 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 572 uint32_t value) 573 { 574 struct psp_gfx_cmd_resp *cmd = NULL; 575 int ret = 0; 576 577 if (reg >= PSP_REG_LAST) 578 return -EINVAL; 579 580 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 581 if (!cmd) 582 return -ENOMEM; 583 584 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 585 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 586 587 kfree(cmd); 588 return ret; 589 } 590 591 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 592 uint64_t ta_bin_mc, 593 uint32_t ta_bin_size, 594 uint64_t ta_shared_mc, 595 uint32_t ta_shared_size) 596 { 597 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 598 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 599 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 600 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 601 602 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 603 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 604 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 605 } 606 607 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 608 { 609 int ret; 610 611 /* 612 * Allocate 16k memory aligned to 4k from Frame Buffer (local 613 * physical) for xgmi ta <-> Driver 614 */ 615 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 616 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 617 &psp->xgmi_context.xgmi_shared_bo, 618 &psp->xgmi_context.xgmi_shared_mc_addr, 619 &psp->xgmi_context.xgmi_shared_buf); 620 621 return ret; 622 } 623 624 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 625 uint32_t ta_cmd_id, 626 uint32_t session_id) 627 { 628 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 629 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 630 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 631 } 632 633 static int psp_ta_invoke(struct psp_context *psp, 634 uint32_t ta_cmd_id, 635 uint32_t session_id) 636 { 637 int ret; 638 struct psp_gfx_cmd_resp *cmd; 639 640 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 641 if (!cmd) 642 return -ENOMEM; 643 644 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 645 646 ret = psp_cmd_submit_buf(psp, NULL, cmd, 647 psp->fence_buf_mc_addr); 648 649 kfree(cmd); 650 651 return ret; 652 } 653 654 static int psp_xgmi_load(struct psp_context *psp) 655 { 656 int ret; 657 struct psp_gfx_cmd_resp *cmd; 658 659 /* 660 * TODO: bypass the loading in sriov for now 661 */ 662 663 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 664 if (!cmd) 665 return -ENOMEM; 666 667 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 668 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 669 670 psp_prep_ta_load_cmd_buf(cmd, 671 psp->fw_pri_mc_addr, 672 psp->ta_xgmi_ucode_size, 673 psp->xgmi_context.xgmi_shared_mc_addr, 674 PSP_XGMI_SHARED_MEM_SIZE); 675 676 ret = psp_cmd_submit_buf(psp, NULL, cmd, 677 psp->fence_buf_mc_addr); 678 679 if (!ret) { 680 psp->xgmi_context.initialized = 1; 681 psp->xgmi_context.session_id = cmd->resp.session_id; 682 } 683 684 kfree(cmd); 685 686 return ret; 687 } 688 689 static int psp_xgmi_unload(struct psp_context *psp) 690 { 691 int ret; 692 struct psp_gfx_cmd_resp *cmd; 693 struct amdgpu_device *adev = psp->adev; 694 695 /* XGMI TA unload currently is not supported on Arcturus */ 696 if (adev->asic_type == CHIP_ARCTURUS) 697 return 0; 698 699 /* 700 * TODO: bypass the unloading in sriov for now 701 */ 702 703 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 704 if (!cmd) 705 return -ENOMEM; 706 707 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 708 709 ret = psp_cmd_submit_buf(psp, NULL, cmd, 710 psp->fence_buf_mc_addr); 711 712 kfree(cmd); 713 714 return ret; 715 } 716 717 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 718 { 719 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 720 } 721 722 int psp_xgmi_terminate(struct psp_context *psp) 723 { 724 int ret; 725 726 if (!psp->xgmi_context.initialized) 727 return 0; 728 729 ret = psp_xgmi_unload(psp); 730 if (ret) 731 return ret; 732 733 psp->xgmi_context.initialized = 0; 734 735 /* free xgmi shared memory */ 736 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 737 &psp->xgmi_context.xgmi_shared_mc_addr, 738 &psp->xgmi_context.xgmi_shared_buf); 739 740 return 0; 741 } 742 743 int psp_xgmi_initialize(struct psp_context *psp) 744 { 745 struct ta_xgmi_shared_memory *xgmi_cmd; 746 int ret; 747 748 if (!psp->adev->psp.ta_fw || 749 !psp->adev->psp.ta_xgmi_ucode_size || 750 !psp->adev->psp.ta_xgmi_start_addr) 751 return -ENOENT; 752 753 if (!psp->xgmi_context.initialized) { 754 ret = psp_xgmi_init_shared_buf(psp); 755 if (ret) 756 return ret; 757 } 758 759 /* Load XGMI TA */ 760 ret = psp_xgmi_load(psp); 761 if (ret) 762 return ret; 763 764 /* Initialize XGMI session */ 765 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 766 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 767 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 768 769 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 770 771 return ret; 772 } 773 774 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 775 { 776 struct ta_xgmi_shared_memory *xgmi_cmd; 777 int ret; 778 779 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 780 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 781 782 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 783 784 /* Invoke xgmi ta to get hive id */ 785 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 786 if (ret) 787 return ret; 788 789 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 790 791 return 0; 792 } 793 794 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 795 { 796 struct ta_xgmi_shared_memory *xgmi_cmd; 797 int ret; 798 799 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 800 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 801 802 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 803 804 /* Invoke xgmi ta to get the node id */ 805 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 806 if (ret) 807 return ret; 808 809 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 810 811 return 0; 812 } 813 814 int psp_xgmi_get_topology_info(struct psp_context *psp, 815 int number_devices, 816 struct psp_xgmi_topology_info *topology) 817 { 818 struct ta_xgmi_shared_memory *xgmi_cmd; 819 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 820 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 821 int i; 822 int ret; 823 824 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 825 return -EINVAL; 826 827 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 828 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 829 830 /* Fill in the shared memory with topology information as input */ 831 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 832 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 833 topology_info_input->num_nodes = number_devices; 834 835 for (i = 0; i < topology_info_input->num_nodes; i++) { 836 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 837 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 838 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 839 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 840 } 841 842 /* Invoke xgmi ta to get the topology information */ 843 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 844 if (ret) 845 return ret; 846 847 /* Read the output topology information from the shared memory */ 848 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 849 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 850 for (i = 0; i < topology->num_nodes; i++) { 851 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 852 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 853 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 854 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 855 } 856 857 return 0; 858 } 859 860 int psp_xgmi_set_topology_info(struct psp_context *psp, 861 int number_devices, 862 struct psp_xgmi_topology_info *topology) 863 { 864 struct ta_xgmi_shared_memory *xgmi_cmd; 865 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 866 int i; 867 868 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 869 return -EINVAL; 870 871 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 872 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 873 874 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 875 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 876 topology_info_input->num_nodes = number_devices; 877 878 for (i = 0; i < topology_info_input->num_nodes; i++) { 879 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 880 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 881 topology_info_input->nodes[i].is_sharing_enabled = 1; 882 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 883 } 884 885 /* Invoke xgmi ta to set topology information */ 886 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 887 } 888 889 // ras begin 890 static int psp_ras_init_shared_buf(struct psp_context *psp) 891 { 892 int ret; 893 894 /* 895 * Allocate 16k memory aligned to 4k from Frame Buffer (local 896 * physical) for ras ta <-> Driver 897 */ 898 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 899 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 900 &psp->ras.ras_shared_bo, 901 &psp->ras.ras_shared_mc_addr, 902 &psp->ras.ras_shared_buf); 903 904 return ret; 905 } 906 907 static int psp_ras_load(struct psp_context *psp) 908 { 909 int ret; 910 struct psp_gfx_cmd_resp *cmd; 911 912 /* 913 * TODO: bypass the loading in sriov for now 914 */ 915 if (amdgpu_sriov_vf(psp->adev)) 916 return 0; 917 918 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 919 if (!cmd) 920 return -ENOMEM; 921 922 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 923 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 924 925 psp_prep_ta_load_cmd_buf(cmd, 926 psp->fw_pri_mc_addr, 927 psp->ta_ras_ucode_size, 928 psp->ras.ras_shared_mc_addr, 929 PSP_RAS_SHARED_MEM_SIZE); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, 932 psp->fence_buf_mc_addr); 933 934 if (!ret) { 935 psp->ras.ras_initialized = true; 936 psp->ras.session_id = cmd->resp.session_id; 937 } 938 939 kfree(cmd); 940 941 return ret; 942 } 943 944 static int psp_ras_unload(struct psp_context *psp) 945 { 946 int ret; 947 struct psp_gfx_cmd_resp *cmd; 948 949 /* 950 * TODO: bypass the unloading in sriov for now 951 */ 952 if (amdgpu_sriov_vf(psp->adev)) 953 return 0; 954 955 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 956 if (!cmd) 957 return -ENOMEM; 958 959 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 960 961 ret = psp_cmd_submit_buf(psp, NULL, cmd, 962 psp->fence_buf_mc_addr); 963 964 kfree(cmd); 965 966 return ret; 967 } 968 969 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 970 { 971 struct ta_ras_shared_memory *ras_cmd; 972 int ret; 973 974 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 975 976 /* 977 * TODO: bypass the loading in sriov for now 978 */ 979 if (amdgpu_sriov_vf(psp->adev)) 980 return 0; 981 982 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 983 984 if (amdgpu_ras_intr_triggered()) 985 return ret; 986 987 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 988 { 989 DRM_WARN("RAS: Unsupported Interface"); 990 return -EINVAL; 991 } 992 993 if (!ret) { 994 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 995 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 996 997 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 998 } 999 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1000 dev_warn(psp->adev->dev, 1001 "RAS internal register access blocked\n"); 1002 } 1003 1004 return ret; 1005 } 1006 1007 int psp_ras_enable_features(struct psp_context *psp, 1008 union ta_ras_cmd_input *info, bool enable) 1009 { 1010 struct ta_ras_shared_memory *ras_cmd; 1011 int ret; 1012 1013 if (!psp->ras.ras_initialized) 1014 return -EINVAL; 1015 1016 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1017 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1018 1019 if (enable) 1020 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1021 else 1022 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1023 1024 ras_cmd->ras_in_message = *info; 1025 1026 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1027 if (ret) 1028 return -EINVAL; 1029 1030 return ras_cmd->ras_status; 1031 } 1032 1033 static int psp_ras_terminate(struct psp_context *psp) 1034 { 1035 int ret; 1036 1037 /* 1038 * TODO: bypass the terminate in sriov for now 1039 */ 1040 if (amdgpu_sriov_vf(psp->adev)) 1041 return 0; 1042 1043 if (!psp->ras.ras_initialized) 1044 return 0; 1045 1046 ret = psp_ras_unload(psp); 1047 if (ret) 1048 return ret; 1049 1050 psp->ras.ras_initialized = false; 1051 1052 /* free ras shared memory */ 1053 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1054 &psp->ras.ras_shared_mc_addr, 1055 &psp->ras.ras_shared_buf); 1056 1057 return 0; 1058 } 1059 1060 static int psp_ras_initialize(struct psp_context *psp) 1061 { 1062 int ret; 1063 1064 /* 1065 * TODO: bypass the initialize in sriov for now 1066 */ 1067 if (amdgpu_sriov_vf(psp->adev)) 1068 return 0; 1069 1070 if (!psp->adev->psp.ta_ras_ucode_size || 1071 !psp->adev->psp.ta_ras_start_addr) { 1072 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1073 return 0; 1074 } 1075 1076 if (!psp->ras.ras_initialized) { 1077 ret = psp_ras_init_shared_buf(psp); 1078 if (ret) 1079 return ret; 1080 } 1081 1082 ret = psp_ras_load(psp); 1083 if (ret) 1084 return ret; 1085 1086 return 0; 1087 } 1088 1089 int psp_ras_trigger_error(struct psp_context *psp, 1090 struct ta_ras_trigger_error_input *info) 1091 { 1092 struct ta_ras_shared_memory *ras_cmd; 1093 int ret; 1094 1095 if (!psp->ras.ras_initialized) 1096 return -EINVAL; 1097 1098 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1099 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1100 1101 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1102 ras_cmd->ras_in_message.trigger_error = *info; 1103 1104 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1105 if (ret) 1106 return -EINVAL; 1107 1108 /* If err_event_athub occurs error inject was successful, however 1109 return status from TA is no long reliable */ 1110 if (amdgpu_ras_intr_triggered()) 1111 return 0; 1112 1113 return ras_cmd->ras_status; 1114 } 1115 // ras end 1116 1117 // HDCP start 1118 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1119 { 1120 int ret; 1121 1122 /* 1123 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1124 * physical) for hdcp ta <-> Driver 1125 */ 1126 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1127 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1128 &psp->hdcp_context.hdcp_shared_bo, 1129 &psp->hdcp_context.hdcp_shared_mc_addr, 1130 &psp->hdcp_context.hdcp_shared_buf); 1131 1132 return ret; 1133 } 1134 1135 static int psp_hdcp_load(struct psp_context *psp) 1136 { 1137 int ret; 1138 struct psp_gfx_cmd_resp *cmd; 1139 1140 /* 1141 * TODO: bypass the loading in sriov for now 1142 */ 1143 if (amdgpu_sriov_vf(psp->adev)) 1144 return 0; 1145 1146 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1147 if (!cmd) 1148 return -ENOMEM; 1149 1150 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1151 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 1152 psp->ta_hdcp_ucode_size); 1153 1154 psp_prep_ta_load_cmd_buf(cmd, 1155 psp->fw_pri_mc_addr, 1156 psp->ta_hdcp_ucode_size, 1157 psp->hdcp_context.hdcp_shared_mc_addr, 1158 PSP_HDCP_SHARED_MEM_SIZE); 1159 1160 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1161 1162 if (!ret) { 1163 psp->hdcp_context.hdcp_initialized = true; 1164 psp->hdcp_context.session_id = cmd->resp.session_id; 1165 mutex_init(&psp->hdcp_context.mutex); 1166 } 1167 1168 kfree(cmd); 1169 1170 return ret; 1171 } 1172 static int psp_hdcp_initialize(struct psp_context *psp) 1173 { 1174 int ret; 1175 1176 /* 1177 * TODO: bypass the initialize in sriov for now 1178 */ 1179 if (amdgpu_sriov_vf(psp->adev)) 1180 return 0; 1181 1182 if (!psp->adev->psp.ta_hdcp_ucode_size || 1183 !psp->adev->psp.ta_hdcp_start_addr) { 1184 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1185 return 0; 1186 } 1187 1188 if (!psp->hdcp_context.hdcp_initialized) { 1189 ret = psp_hdcp_init_shared_buf(psp); 1190 if (ret) 1191 return ret; 1192 } 1193 1194 ret = psp_hdcp_load(psp); 1195 if (ret) 1196 return ret; 1197 1198 return 0; 1199 } 1200 1201 static int psp_hdcp_unload(struct psp_context *psp) 1202 { 1203 int ret; 1204 struct psp_gfx_cmd_resp *cmd; 1205 1206 /* 1207 * TODO: bypass the unloading in sriov for now 1208 */ 1209 if (amdgpu_sriov_vf(psp->adev)) 1210 return 0; 1211 1212 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1213 if (!cmd) 1214 return -ENOMEM; 1215 1216 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1217 1218 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1219 1220 kfree(cmd); 1221 1222 return ret; 1223 } 1224 1225 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1226 { 1227 /* 1228 * TODO: bypass the loading in sriov for now 1229 */ 1230 if (amdgpu_sriov_vf(psp->adev)) 1231 return 0; 1232 1233 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1234 } 1235 1236 static int psp_hdcp_terminate(struct psp_context *psp) 1237 { 1238 int ret; 1239 1240 /* 1241 * TODO: bypass the terminate in sriov for now 1242 */ 1243 if (amdgpu_sriov_vf(psp->adev)) 1244 return 0; 1245 1246 if (!psp->hdcp_context.hdcp_initialized) 1247 return 0; 1248 1249 ret = psp_hdcp_unload(psp); 1250 if (ret) 1251 return ret; 1252 1253 psp->hdcp_context.hdcp_initialized = false; 1254 1255 /* free hdcp shared memory */ 1256 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1257 &psp->hdcp_context.hdcp_shared_mc_addr, 1258 &psp->hdcp_context.hdcp_shared_buf); 1259 1260 return 0; 1261 } 1262 // HDCP end 1263 1264 // DTM start 1265 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1266 { 1267 int ret; 1268 1269 /* 1270 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1271 * physical) for dtm ta <-> Driver 1272 */ 1273 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1274 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1275 &psp->dtm_context.dtm_shared_bo, 1276 &psp->dtm_context.dtm_shared_mc_addr, 1277 &psp->dtm_context.dtm_shared_buf); 1278 1279 return ret; 1280 } 1281 1282 static int psp_dtm_load(struct psp_context *psp) 1283 { 1284 int ret; 1285 struct psp_gfx_cmd_resp *cmd; 1286 1287 /* 1288 * TODO: bypass the loading in sriov for now 1289 */ 1290 if (amdgpu_sriov_vf(psp->adev)) 1291 return 0; 1292 1293 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1294 if (!cmd) 1295 return -ENOMEM; 1296 1297 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1298 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1299 1300 psp_prep_ta_load_cmd_buf(cmd, 1301 psp->fw_pri_mc_addr, 1302 psp->ta_dtm_ucode_size, 1303 psp->dtm_context.dtm_shared_mc_addr, 1304 PSP_DTM_SHARED_MEM_SIZE); 1305 1306 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1307 1308 if (!ret) { 1309 psp->dtm_context.dtm_initialized = true; 1310 psp->dtm_context.session_id = cmd->resp.session_id; 1311 mutex_init(&psp->dtm_context.mutex); 1312 } 1313 1314 kfree(cmd); 1315 1316 return ret; 1317 } 1318 1319 static int psp_dtm_initialize(struct psp_context *psp) 1320 { 1321 int ret; 1322 1323 /* 1324 * TODO: bypass the initialize in sriov for now 1325 */ 1326 if (amdgpu_sriov_vf(psp->adev)) 1327 return 0; 1328 1329 if (!psp->adev->psp.ta_dtm_ucode_size || 1330 !psp->adev->psp.ta_dtm_start_addr) { 1331 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1332 return 0; 1333 } 1334 1335 if (!psp->dtm_context.dtm_initialized) { 1336 ret = psp_dtm_init_shared_buf(psp); 1337 if (ret) 1338 return ret; 1339 } 1340 1341 ret = psp_dtm_load(psp); 1342 if (ret) 1343 return ret; 1344 1345 return 0; 1346 } 1347 1348 static int psp_dtm_unload(struct psp_context *psp) 1349 { 1350 int ret; 1351 struct psp_gfx_cmd_resp *cmd; 1352 1353 /* 1354 * TODO: bypass the unloading in sriov for now 1355 */ 1356 if (amdgpu_sriov_vf(psp->adev)) 1357 return 0; 1358 1359 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1360 if (!cmd) 1361 return -ENOMEM; 1362 1363 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1364 1365 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1366 1367 kfree(cmd); 1368 1369 return ret; 1370 } 1371 1372 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1373 { 1374 /* 1375 * TODO: bypass the loading in sriov for now 1376 */ 1377 if (amdgpu_sriov_vf(psp->adev)) 1378 return 0; 1379 1380 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1381 } 1382 1383 static int psp_dtm_terminate(struct psp_context *psp) 1384 { 1385 int ret; 1386 1387 /* 1388 * TODO: bypass the terminate in sriov for now 1389 */ 1390 if (amdgpu_sriov_vf(psp->adev)) 1391 return 0; 1392 1393 if (!psp->dtm_context.dtm_initialized) 1394 return 0; 1395 1396 ret = psp_dtm_unload(psp); 1397 if (ret) 1398 return ret; 1399 1400 psp->dtm_context.dtm_initialized = false; 1401 1402 /* free hdcp shared memory */ 1403 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1404 &psp->dtm_context.dtm_shared_mc_addr, 1405 &psp->dtm_context.dtm_shared_buf); 1406 1407 return 0; 1408 } 1409 // DTM end 1410 1411 static int psp_hw_start(struct psp_context *psp) 1412 { 1413 struct amdgpu_device *adev = psp->adev; 1414 int ret; 1415 1416 if (!amdgpu_sriov_vf(adev)) { 1417 if (psp->kdb_bin_size && 1418 (psp->funcs->bootloader_load_kdb != NULL)) { 1419 ret = psp_bootloader_load_kdb(psp); 1420 if (ret) { 1421 DRM_ERROR("PSP load kdb failed!\n"); 1422 return ret; 1423 } 1424 } 1425 1426 if (psp->spl_bin_size) { 1427 ret = psp_bootloader_load_spl(psp); 1428 if (ret) { 1429 DRM_ERROR("PSP load spl failed!\n"); 1430 return ret; 1431 } 1432 } 1433 1434 ret = psp_bootloader_load_sysdrv(psp); 1435 if (ret) { 1436 DRM_ERROR("PSP load sysdrv failed!\n"); 1437 return ret; 1438 } 1439 1440 ret = psp_bootloader_load_sos(psp); 1441 if (ret) { 1442 DRM_ERROR("PSP load sos failed!\n"); 1443 return ret; 1444 } 1445 } 1446 1447 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1448 if (ret) { 1449 DRM_ERROR("PSP create ring failed!\n"); 1450 return ret; 1451 } 1452 1453 ret = psp_clear_vf_fw(psp); 1454 if (ret) { 1455 DRM_ERROR("PSP clear vf fw!\n"); 1456 return ret; 1457 } 1458 1459 ret = psp_tmr_init(psp); 1460 if (ret) { 1461 DRM_ERROR("PSP tmr init failed!\n"); 1462 return ret; 1463 } 1464 1465 /* 1466 * For ASICs with DF Cstate management centralized 1467 * to PMFW, TMR setup should be performed after PMFW 1468 * loaded and before other non-psp firmware loaded. 1469 */ 1470 if (psp->pmfw_centralized_cstate_management) { 1471 ret = psp_load_smu_fw(psp); 1472 if (ret) 1473 return ret; 1474 } 1475 1476 ret = psp_tmr_load(psp); 1477 if (ret) { 1478 DRM_ERROR("PSP load tmr failed!\n"); 1479 return ret; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1486 enum psp_gfx_fw_type *type) 1487 { 1488 switch (ucode->ucode_id) { 1489 case AMDGPU_UCODE_ID_SDMA0: 1490 *type = GFX_FW_TYPE_SDMA0; 1491 break; 1492 case AMDGPU_UCODE_ID_SDMA1: 1493 *type = GFX_FW_TYPE_SDMA1; 1494 break; 1495 case AMDGPU_UCODE_ID_SDMA2: 1496 *type = GFX_FW_TYPE_SDMA2; 1497 break; 1498 case AMDGPU_UCODE_ID_SDMA3: 1499 *type = GFX_FW_TYPE_SDMA3; 1500 break; 1501 case AMDGPU_UCODE_ID_SDMA4: 1502 *type = GFX_FW_TYPE_SDMA4; 1503 break; 1504 case AMDGPU_UCODE_ID_SDMA5: 1505 *type = GFX_FW_TYPE_SDMA5; 1506 break; 1507 case AMDGPU_UCODE_ID_SDMA6: 1508 *type = GFX_FW_TYPE_SDMA6; 1509 break; 1510 case AMDGPU_UCODE_ID_SDMA7: 1511 *type = GFX_FW_TYPE_SDMA7; 1512 break; 1513 case AMDGPU_UCODE_ID_CP_MES: 1514 *type = GFX_FW_TYPE_CP_MES; 1515 break; 1516 case AMDGPU_UCODE_ID_CP_MES_DATA: 1517 *type = GFX_FW_TYPE_MES_STACK; 1518 break; 1519 case AMDGPU_UCODE_ID_CP_CE: 1520 *type = GFX_FW_TYPE_CP_CE; 1521 break; 1522 case AMDGPU_UCODE_ID_CP_PFP: 1523 *type = GFX_FW_TYPE_CP_PFP; 1524 break; 1525 case AMDGPU_UCODE_ID_CP_ME: 1526 *type = GFX_FW_TYPE_CP_ME; 1527 break; 1528 case AMDGPU_UCODE_ID_CP_MEC1: 1529 *type = GFX_FW_TYPE_CP_MEC; 1530 break; 1531 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1532 *type = GFX_FW_TYPE_CP_MEC_ME1; 1533 break; 1534 case AMDGPU_UCODE_ID_CP_MEC2: 1535 *type = GFX_FW_TYPE_CP_MEC; 1536 break; 1537 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1538 *type = GFX_FW_TYPE_CP_MEC_ME2; 1539 break; 1540 case AMDGPU_UCODE_ID_RLC_G: 1541 *type = GFX_FW_TYPE_RLC_G; 1542 break; 1543 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1544 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1545 break; 1546 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1547 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1548 break; 1549 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1550 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1551 break; 1552 case AMDGPU_UCODE_ID_SMC: 1553 *type = GFX_FW_TYPE_SMU; 1554 break; 1555 case AMDGPU_UCODE_ID_UVD: 1556 *type = GFX_FW_TYPE_UVD; 1557 break; 1558 case AMDGPU_UCODE_ID_UVD1: 1559 *type = GFX_FW_TYPE_UVD1; 1560 break; 1561 case AMDGPU_UCODE_ID_VCE: 1562 *type = GFX_FW_TYPE_VCE; 1563 break; 1564 case AMDGPU_UCODE_ID_VCN: 1565 *type = GFX_FW_TYPE_VCN; 1566 break; 1567 case AMDGPU_UCODE_ID_VCN1: 1568 *type = GFX_FW_TYPE_VCN1; 1569 break; 1570 case AMDGPU_UCODE_ID_DMCU_ERAM: 1571 *type = GFX_FW_TYPE_DMCU_ERAM; 1572 break; 1573 case AMDGPU_UCODE_ID_DMCU_INTV: 1574 *type = GFX_FW_TYPE_DMCU_ISR; 1575 break; 1576 case AMDGPU_UCODE_ID_VCN0_RAM: 1577 *type = GFX_FW_TYPE_VCN0_RAM; 1578 break; 1579 case AMDGPU_UCODE_ID_VCN1_RAM: 1580 *type = GFX_FW_TYPE_VCN1_RAM; 1581 break; 1582 case AMDGPU_UCODE_ID_DMCUB: 1583 *type = GFX_FW_TYPE_DMUB; 1584 break; 1585 case AMDGPU_UCODE_ID_MAXIMUM: 1586 default: 1587 return -EINVAL; 1588 } 1589 1590 return 0; 1591 } 1592 1593 static void psp_print_fw_hdr(struct psp_context *psp, 1594 struct amdgpu_firmware_info *ucode) 1595 { 1596 struct amdgpu_device *adev = psp->adev; 1597 struct common_firmware_header *hdr; 1598 1599 switch (ucode->ucode_id) { 1600 case AMDGPU_UCODE_ID_SDMA0: 1601 case AMDGPU_UCODE_ID_SDMA1: 1602 case AMDGPU_UCODE_ID_SDMA2: 1603 case AMDGPU_UCODE_ID_SDMA3: 1604 case AMDGPU_UCODE_ID_SDMA4: 1605 case AMDGPU_UCODE_ID_SDMA5: 1606 case AMDGPU_UCODE_ID_SDMA6: 1607 case AMDGPU_UCODE_ID_SDMA7: 1608 hdr = (struct common_firmware_header *) 1609 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1610 amdgpu_ucode_print_sdma_hdr(hdr); 1611 break; 1612 case AMDGPU_UCODE_ID_CP_CE: 1613 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1614 amdgpu_ucode_print_gfx_hdr(hdr); 1615 break; 1616 case AMDGPU_UCODE_ID_CP_PFP: 1617 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1618 amdgpu_ucode_print_gfx_hdr(hdr); 1619 break; 1620 case AMDGPU_UCODE_ID_CP_ME: 1621 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1622 amdgpu_ucode_print_gfx_hdr(hdr); 1623 break; 1624 case AMDGPU_UCODE_ID_CP_MEC1: 1625 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1626 amdgpu_ucode_print_gfx_hdr(hdr); 1627 break; 1628 case AMDGPU_UCODE_ID_RLC_G: 1629 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1630 amdgpu_ucode_print_rlc_hdr(hdr); 1631 break; 1632 case AMDGPU_UCODE_ID_SMC: 1633 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1634 amdgpu_ucode_print_smc_hdr(hdr); 1635 break; 1636 default: 1637 break; 1638 } 1639 } 1640 1641 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1642 struct psp_gfx_cmd_resp *cmd) 1643 { 1644 int ret; 1645 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1646 1647 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1648 1649 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1650 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1651 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1652 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1653 1654 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1655 if (ret) 1656 DRM_ERROR("Unknown firmware type\n"); 1657 1658 return ret; 1659 } 1660 1661 static int psp_execute_np_fw_load(struct psp_context *psp, 1662 struct amdgpu_firmware_info *ucode) 1663 { 1664 int ret = 0; 1665 1666 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1667 if (ret) 1668 return ret; 1669 1670 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1671 psp->fence_buf_mc_addr); 1672 1673 return ret; 1674 } 1675 1676 static int psp_load_smu_fw(struct psp_context *psp) 1677 { 1678 int ret; 1679 struct amdgpu_device* adev = psp->adev; 1680 struct amdgpu_firmware_info *ucode = 1681 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1682 struct amdgpu_ras *ras = psp->ras.ras; 1683 1684 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 1685 return 0; 1686 1687 1688 if (adev->in_gpu_reset && ras && ras->supported) { 1689 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 1690 if (ret) { 1691 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 1692 } 1693 } 1694 1695 ret = psp_execute_np_fw_load(psp, ucode); 1696 1697 if (ret) 1698 DRM_ERROR("PSP load smu failed!\n"); 1699 1700 return ret; 1701 } 1702 1703 static bool fw_load_skip_check(struct psp_context *psp, 1704 struct amdgpu_firmware_info *ucode) 1705 { 1706 if (!ucode->fw) 1707 return true; 1708 1709 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1710 (psp_smu_reload_quirk(psp) || 1711 psp->autoload_supported || 1712 psp->pmfw_centralized_cstate_management)) 1713 return true; 1714 1715 if (amdgpu_sriov_vf(psp->adev) && 1716 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1717 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1718 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1719 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1720 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1721 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1722 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1723 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1724 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 1725 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1726 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 1727 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 1728 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 1729 /*skip ucode loading in SRIOV VF */ 1730 return true; 1731 1732 if (psp->autoload_supported && 1733 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1734 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1735 /* skip mec JT when autoload is enabled */ 1736 return true; 1737 1738 return false; 1739 } 1740 1741 static int psp_np_fw_load(struct psp_context *psp) 1742 { 1743 int i, ret; 1744 struct amdgpu_firmware_info *ucode; 1745 struct amdgpu_device* adev = psp->adev; 1746 1747 if (psp->autoload_supported && 1748 !psp->pmfw_centralized_cstate_management) { 1749 ret = psp_load_smu_fw(psp); 1750 if (ret) 1751 return ret; 1752 } 1753 1754 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1755 ucode = &adev->firmware.ucode[i]; 1756 1757 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1758 !fw_load_skip_check(psp, ucode)) { 1759 ret = psp_load_smu_fw(psp); 1760 if (ret) 1761 return ret; 1762 continue; 1763 } 1764 1765 if (fw_load_skip_check(psp, ucode)) 1766 continue; 1767 1768 if (psp->autoload_supported && 1769 (adev->asic_type == CHIP_SIENNA_CICHLID || 1770 adev->asic_type == CHIP_NAVY_FLOUNDER) && 1771 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 1772 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 1773 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 1774 /* PSP only receive one SDMA fw for sienna_cichlid, 1775 * as all four sdma fw are same */ 1776 continue; 1777 1778 psp_print_fw_hdr(psp, ucode); 1779 1780 ret = psp_execute_np_fw_load(psp, ucode); 1781 if (ret) 1782 return ret; 1783 1784 /* Start rlc autoload after psp recieved all the gfx firmware */ 1785 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 1786 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 1787 ret = psp_rlc_autoload_start(psp); 1788 if (ret) { 1789 DRM_ERROR("Failed to start rlc autoload\n"); 1790 return ret; 1791 } 1792 } 1793 } 1794 1795 return 0; 1796 } 1797 1798 static int psp_load_fw(struct amdgpu_device *adev) 1799 { 1800 int ret; 1801 struct psp_context *psp = &adev->psp; 1802 1803 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1804 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1805 goto skip_memalloc; 1806 } 1807 1808 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1809 if (!psp->cmd) 1810 return -ENOMEM; 1811 1812 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1813 AMDGPU_GEM_DOMAIN_GTT, 1814 &psp->fw_pri_bo, 1815 &psp->fw_pri_mc_addr, 1816 &psp->fw_pri_buf); 1817 if (ret) 1818 goto failed; 1819 1820 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1821 AMDGPU_GEM_DOMAIN_VRAM, 1822 &psp->fence_buf_bo, 1823 &psp->fence_buf_mc_addr, 1824 &psp->fence_buf); 1825 if (ret) 1826 goto failed; 1827 1828 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1829 AMDGPU_GEM_DOMAIN_VRAM, 1830 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1831 (void **)&psp->cmd_buf_mem); 1832 if (ret) 1833 goto failed; 1834 1835 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1836 1837 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1838 if (ret) { 1839 DRM_ERROR("PSP ring init failed!\n"); 1840 goto failed; 1841 } 1842 1843 skip_memalloc: 1844 ret = psp_hw_start(psp); 1845 if (ret) 1846 goto failed; 1847 1848 ret = psp_np_fw_load(psp); 1849 if (ret) 1850 goto failed; 1851 1852 ret = psp_asd_load(psp); 1853 if (ret) { 1854 DRM_ERROR("PSP load asd failed!\n"); 1855 return ret; 1856 } 1857 1858 if (psp->adev->psp.ta_fw) { 1859 ret = psp_ras_initialize(psp); 1860 if (ret) 1861 dev_err(psp->adev->dev, 1862 "RAS: Failed to initialize RAS\n"); 1863 1864 ret = psp_hdcp_initialize(psp); 1865 if (ret) 1866 dev_err(psp->adev->dev, 1867 "HDCP: Failed to initialize HDCP\n"); 1868 1869 ret = psp_dtm_initialize(psp); 1870 if (ret) 1871 dev_err(psp->adev->dev, 1872 "DTM: Failed to initialize DTM\n"); 1873 } 1874 1875 return 0; 1876 1877 failed: 1878 /* 1879 * all cleanup jobs (xgmi terminate, ras terminate, 1880 * ring destroy, cmd/fence/fw buffers destory, 1881 * psp->cmd destory) are delayed to psp_hw_fini 1882 */ 1883 return ret; 1884 } 1885 1886 static int psp_hw_init(void *handle) 1887 { 1888 int ret; 1889 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1890 1891 mutex_lock(&adev->firmware.mutex); 1892 /* 1893 * This sequence is just used on hw_init only once, no need on 1894 * resume. 1895 */ 1896 ret = amdgpu_ucode_init_bo(adev); 1897 if (ret) 1898 goto failed; 1899 1900 ret = psp_load_fw(adev); 1901 if (ret) { 1902 DRM_ERROR("PSP firmware loading failed\n"); 1903 goto failed; 1904 } 1905 1906 mutex_unlock(&adev->firmware.mutex); 1907 return 0; 1908 1909 failed: 1910 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1911 mutex_unlock(&adev->firmware.mutex); 1912 return -EINVAL; 1913 } 1914 1915 static int psp_hw_fini(void *handle) 1916 { 1917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1918 struct psp_context *psp = &adev->psp; 1919 int ret; 1920 1921 if (psp->adev->psp.ta_fw) { 1922 psp_ras_terminate(psp); 1923 psp_dtm_terminate(psp); 1924 psp_hdcp_terminate(psp); 1925 } 1926 1927 psp_asd_unload(psp); 1928 ret = psp_clear_vf_fw(psp); 1929 if (ret) { 1930 DRM_ERROR("PSP clear vf fw!\n"); 1931 return ret; 1932 } 1933 1934 psp_tmr_terminate(psp); 1935 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1936 1937 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1938 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1939 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1940 &psp->fence_buf_mc_addr, &psp->fence_buf); 1941 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1942 (void **)&psp->cmd_buf_mem); 1943 1944 kfree(psp->cmd); 1945 psp->cmd = NULL; 1946 1947 return 0; 1948 } 1949 1950 static int psp_suspend(void *handle) 1951 { 1952 int ret; 1953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1954 struct psp_context *psp = &adev->psp; 1955 1956 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1957 psp->xgmi_context.initialized == 1) { 1958 ret = psp_xgmi_terminate(psp); 1959 if (ret) { 1960 DRM_ERROR("Failed to terminate xgmi ta\n"); 1961 return ret; 1962 } 1963 } 1964 1965 if (psp->adev->psp.ta_fw) { 1966 ret = psp_ras_terminate(psp); 1967 if (ret) { 1968 DRM_ERROR("Failed to terminate ras ta\n"); 1969 return ret; 1970 } 1971 ret = psp_hdcp_terminate(psp); 1972 if (ret) { 1973 DRM_ERROR("Failed to terminate hdcp ta\n"); 1974 return ret; 1975 } 1976 ret = psp_dtm_terminate(psp); 1977 if (ret) { 1978 DRM_ERROR("Failed to terminate dtm ta\n"); 1979 return ret; 1980 } 1981 } 1982 1983 ret = psp_asd_unload(psp); 1984 if (ret) { 1985 DRM_ERROR("Failed to unload asd\n"); 1986 return ret; 1987 } 1988 1989 ret = psp_tmr_terminate(psp); 1990 if (ret) { 1991 DRM_ERROR("Falied to terminate tmr\n"); 1992 return ret; 1993 } 1994 1995 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1996 if (ret) { 1997 DRM_ERROR("PSP ring stop failed\n"); 1998 return ret; 1999 } 2000 2001 return 0; 2002 } 2003 2004 static int psp_resume(void *handle) 2005 { 2006 int ret; 2007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2008 struct psp_context *psp = &adev->psp; 2009 2010 DRM_INFO("PSP is resuming...\n"); 2011 2012 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2013 if (ret) { 2014 DRM_ERROR("Failed to process memory training!\n"); 2015 return ret; 2016 } 2017 2018 mutex_lock(&adev->firmware.mutex); 2019 2020 ret = psp_hw_start(psp); 2021 if (ret) 2022 goto failed; 2023 2024 ret = psp_np_fw_load(psp); 2025 if (ret) 2026 goto failed; 2027 2028 ret = psp_asd_load(psp); 2029 if (ret) { 2030 DRM_ERROR("PSP load asd failed!\n"); 2031 goto failed; 2032 } 2033 2034 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2035 ret = psp_xgmi_initialize(psp); 2036 /* Warning the XGMI seesion initialize failure 2037 * Instead of stop driver initialization 2038 */ 2039 if (ret) 2040 dev_err(psp->adev->dev, 2041 "XGMI: Failed to initialize XGMI session\n"); 2042 } 2043 2044 if (psp->adev->psp.ta_fw) { 2045 ret = psp_ras_initialize(psp); 2046 if (ret) 2047 dev_err(psp->adev->dev, 2048 "RAS: Failed to initialize RAS\n"); 2049 2050 ret = psp_hdcp_initialize(psp); 2051 if (ret) 2052 dev_err(psp->adev->dev, 2053 "HDCP: Failed to initialize HDCP\n"); 2054 2055 ret = psp_dtm_initialize(psp); 2056 if (ret) 2057 dev_err(psp->adev->dev, 2058 "DTM: Failed to initialize DTM\n"); 2059 } 2060 2061 mutex_unlock(&adev->firmware.mutex); 2062 2063 return 0; 2064 2065 failed: 2066 DRM_ERROR("PSP resume failed\n"); 2067 mutex_unlock(&adev->firmware.mutex); 2068 return ret; 2069 } 2070 2071 int psp_gpu_reset(struct amdgpu_device *adev) 2072 { 2073 int ret; 2074 2075 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2076 return 0; 2077 2078 mutex_lock(&adev->psp.mutex); 2079 ret = psp_mode1_reset(&adev->psp); 2080 mutex_unlock(&adev->psp.mutex); 2081 2082 return ret; 2083 } 2084 2085 int psp_rlc_autoload_start(struct psp_context *psp) 2086 { 2087 int ret; 2088 struct psp_gfx_cmd_resp *cmd; 2089 2090 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2091 if (!cmd) 2092 return -ENOMEM; 2093 2094 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2095 2096 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2097 psp->fence_buf_mc_addr); 2098 kfree(cmd); 2099 return ret; 2100 } 2101 2102 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2103 uint64_t cmd_gpu_addr, int cmd_size) 2104 { 2105 struct amdgpu_firmware_info ucode = {0}; 2106 2107 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2108 AMDGPU_UCODE_ID_VCN0_RAM; 2109 ucode.mc_addr = cmd_gpu_addr; 2110 ucode.ucode_size = cmd_size; 2111 2112 return psp_execute_np_fw_load(&adev->psp, &ucode); 2113 } 2114 2115 int psp_ring_cmd_submit(struct psp_context *psp, 2116 uint64_t cmd_buf_mc_addr, 2117 uint64_t fence_mc_addr, 2118 int index) 2119 { 2120 unsigned int psp_write_ptr_reg = 0; 2121 struct psp_gfx_rb_frame *write_frame; 2122 struct psp_ring *ring = &psp->km_ring; 2123 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2124 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2125 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2126 struct amdgpu_device *adev = psp->adev; 2127 uint32_t ring_size_dw = ring->ring_size / 4; 2128 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2129 2130 /* KM (GPCOM) prepare write pointer */ 2131 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2132 2133 /* Update KM RB frame pointer to new frame */ 2134 /* write_frame ptr increments by size of rb_frame in bytes */ 2135 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2136 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2137 write_frame = ring_buffer_start; 2138 else 2139 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2140 /* Check invalid write_frame ptr address */ 2141 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2142 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2143 ring_buffer_start, ring_buffer_end, write_frame); 2144 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2145 return -EINVAL; 2146 } 2147 2148 /* Initialize KM RB frame */ 2149 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2150 2151 /* Update KM RB frame */ 2152 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2153 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2154 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2155 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2156 write_frame->fence_value = index; 2157 amdgpu_asic_flush_hdp(adev, NULL); 2158 2159 /* Update the write Pointer in DWORDs */ 2160 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2161 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2162 return 0; 2163 } 2164 2165 int psp_init_asd_microcode(struct psp_context *psp, 2166 const char *chip_name) 2167 { 2168 struct amdgpu_device *adev = psp->adev; 2169 char fw_name[30]; 2170 const struct psp_firmware_header_v1_0 *asd_hdr; 2171 int err = 0; 2172 2173 if (!chip_name) { 2174 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2175 return -EINVAL; 2176 } 2177 2178 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2179 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2180 if (err) 2181 goto out; 2182 2183 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2184 if (err) 2185 goto out; 2186 2187 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2188 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2189 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2190 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2191 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2192 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2193 return 0; 2194 out: 2195 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2196 release_firmware(adev->psp.asd_fw); 2197 adev->psp.asd_fw = NULL; 2198 return err; 2199 } 2200 2201 int psp_init_sos_microcode(struct psp_context *psp, 2202 const char *chip_name) 2203 { 2204 struct amdgpu_device *adev = psp->adev; 2205 char fw_name[30]; 2206 const struct psp_firmware_header_v1_0 *sos_hdr; 2207 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2208 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2209 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2210 int err = 0; 2211 2212 if (!chip_name) { 2213 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2214 return -EINVAL; 2215 } 2216 2217 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2218 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2219 if (err) 2220 goto out; 2221 2222 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2223 if (err) 2224 goto out; 2225 2226 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2227 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2228 2229 switch (sos_hdr->header.header_version_major) { 2230 case 1: 2231 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2232 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2233 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2234 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2235 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2236 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2237 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2238 le32_to_cpu(sos_hdr->sos_offset_bytes); 2239 if (sos_hdr->header.header_version_minor == 1) { 2240 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2241 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2242 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2243 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2244 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2245 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2246 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2247 } 2248 if (sos_hdr->header.header_version_minor == 2) { 2249 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2250 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2251 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2252 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2253 } 2254 if (sos_hdr->header.header_version_minor == 3) { 2255 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2256 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2257 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2258 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2259 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2260 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2261 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2262 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2263 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2264 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2265 } 2266 break; 2267 default: 2268 dev_err(adev->dev, 2269 "unsupported psp sos firmware\n"); 2270 err = -EINVAL; 2271 goto out; 2272 } 2273 2274 return 0; 2275 out: 2276 dev_err(adev->dev, 2277 "failed to init sos firmware\n"); 2278 release_firmware(adev->psp.sos_fw); 2279 adev->psp.sos_fw = NULL; 2280 2281 return err; 2282 } 2283 2284 int parse_ta_bin_descriptor(struct psp_context *psp, 2285 const struct ta_fw_bin_desc *desc, 2286 const struct ta_firmware_header_v2_0 *ta_hdr) 2287 { 2288 uint8_t *ucode_start_addr = NULL; 2289 2290 if (!psp || !desc || !ta_hdr) 2291 return -EINVAL; 2292 2293 ucode_start_addr = (uint8_t *)ta_hdr + 2294 le32_to_cpu(desc->offset_bytes) + 2295 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2296 2297 switch (desc->fw_type) { 2298 case TA_FW_TYPE_PSP_ASD: 2299 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2300 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2301 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2302 psp->asd_start_addr = ucode_start_addr; 2303 break; 2304 case TA_FW_TYPE_PSP_XGMI: 2305 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2306 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2307 psp->ta_xgmi_start_addr = ucode_start_addr; 2308 break; 2309 case TA_FW_TYPE_PSP_RAS: 2310 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2311 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2312 psp->ta_ras_start_addr = ucode_start_addr; 2313 break; 2314 case TA_FW_TYPE_PSP_HDCP: 2315 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2316 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2317 psp->ta_hdcp_start_addr = ucode_start_addr; 2318 break; 2319 case TA_FW_TYPE_PSP_DTM: 2320 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2321 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2322 psp->ta_dtm_start_addr = ucode_start_addr; 2323 break; 2324 default: 2325 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2326 break; 2327 } 2328 2329 return 0; 2330 } 2331 2332 int psp_init_ta_microcode(struct psp_context *psp, 2333 const char *chip_name) 2334 { 2335 struct amdgpu_device *adev = psp->adev; 2336 char fw_name[30]; 2337 const struct ta_firmware_header_v2_0 *ta_hdr; 2338 int err = 0; 2339 int ta_index = 0; 2340 2341 if (!chip_name) { 2342 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2343 return -EINVAL; 2344 } 2345 2346 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2347 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2348 if (err) 2349 goto out; 2350 2351 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2352 if (err) 2353 goto out; 2354 2355 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2356 2357 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2358 dev_err(adev->dev, "unsupported TA header version\n"); 2359 err = -EINVAL; 2360 goto out; 2361 } 2362 2363 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2364 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2365 err = -EINVAL; 2366 goto out; 2367 } 2368 2369 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2370 err = parse_ta_bin_descriptor(psp, 2371 &ta_hdr->ta_fw_bin[ta_index], 2372 ta_hdr); 2373 if (err) 2374 goto out; 2375 } 2376 2377 return 0; 2378 out: 2379 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2380 release_firmware(adev->psp.ta_fw); 2381 adev->psp.ta_fw = NULL; 2382 return err; 2383 } 2384 2385 static int psp_set_clockgating_state(void *handle, 2386 enum amd_clockgating_state state) 2387 { 2388 return 0; 2389 } 2390 2391 static int psp_set_powergating_state(void *handle, 2392 enum amd_powergating_state state) 2393 { 2394 return 0; 2395 } 2396 2397 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2398 struct device_attribute *attr, 2399 char *buf) 2400 { 2401 struct drm_device *ddev = dev_get_drvdata(dev); 2402 struct amdgpu_device *adev = ddev->dev_private; 2403 uint32_t fw_ver; 2404 int ret; 2405 2406 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2407 DRM_INFO("PSP block is not ready yet."); 2408 return -EBUSY; 2409 } 2410 2411 mutex_lock(&adev->psp.mutex); 2412 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 2413 mutex_unlock(&adev->psp.mutex); 2414 2415 if (ret) { 2416 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 2417 return ret; 2418 } 2419 2420 return snprintf(buf, PAGE_SIZE, "%x\n", fw_ver); 2421 } 2422 2423 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 2424 struct device_attribute *attr, 2425 const char *buf, 2426 size_t count) 2427 { 2428 struct drm_device *ddev = dev_get_drvdata(dev); 2429 struct amdgpu_device *adev = ddev->dev_private; 2430 void *cpu_addr; 2431 dma_addr_t dma_addr; 2432 int ret; 2433 char fw_name[100]; 2434 const struct firmware *usbc_pd_fw; 2435 2436 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2437 DRM_INFO("PSP block is not ready yet."); 2438 return -EBUSY; 2439 } 2440 2441 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 2442 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 2443 if (ret) 2444 goto fail; 2445 2446 /* We need contiguous physical mem to place the FW for psp to access */ 2447 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 2448 2449 ret = dma_mapping_error(adev->dev, dma_addr); 2450 if (ret) 2451 goto rel_buf; 2452 2453 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 2454 2455 /* 2456 * x86 specific workaround. 2457 * Without it the buffer is invisible in PSP. 2458 * 2459 * TODO Remove once PSP starts snooping CPU cache 2460 */ 2461 #ifdef CONFIG_X86 2462 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 2463 #endif 2464 2465 mutex_lock(&adev->psp.mutex); 2466 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 2467 mutex_unlock(&adev->psp.mutex); 2468 2469 rel_buf: 2470 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 2471 release_firmware(usbc_pd_fw); 2472 2473 fail: 2474 if (ret) { 2475 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 2476 return ret; 2477 } 2478 2479 return count; 2480 } 2481 2482 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 2483 psp_usbc_pd_fw_sysfs_read, 2484 psp_usbc_pd_fw_sysfs_write); 2485 2486 2487 2488 const struct amd_ip_funcs psp_ip_funcs = { 2489 .name = "psp", 2490 .early_init = psp_early_init, 2491 .late_init = NULL, 2492 .sw_init = psp_sw_init, 2493 .sw_fini = psp_sw_fini, 2494 .hw_init = psp_hw_init, 2495 .hw_fini = psp_hw_fini, 2496 .suspend = psp_suspend, 2497 .resume = psp_resume, 2498 .is_idle = NULL, 2499 .check_soft_reset = NULL, 2500 .wait_for_idle = NULL, 2501 .soft_reset = NULL, 2502 .set_clockgating_state = psp_set_clockgating_state, 2503 .set_powergating_state = psp_set_powergating_state, 2504 }; 2505 2506 static int psp_sysfs_init(struct amdgpu_device *adev) 2507 { 2508 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 2509 2510 if (ret) 2511 DRM_ERROR("Failed to create USBC PD FW control file!"); 2512 2513 return ret; 2514 } 2515 2516 static void psp_sysfs_fini(struct amdgpu_device *adev) 2517 { 2518 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 2519 } 2520 2521 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 2522 { 2523 .type = AMD_IP_BLOCK_TYPE_PSP, 2524 .major = 3, 2525 .minor = 1, 2526 .rev = 0, 2527 .funcs = &psp_ip_funcs, 2528 }; 2529 2530 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 2531 { 2532 .type = AMD_IP_BLOCK_TYPE_PSP, 2533 .major = 10, 2534 .minor = 0, 2535 .rev = 0, 2536 .funcs = &psp_ip_funcs, 2537 }; 2538 2539 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 2540 { 2541 .type = AMD_IP_BLOCK_TYPE_PSP, 2542 .major = 11, 2543 .minor = 0, 2544 .rev = 0, 2545 .funcs = &psp_ip_funcs, 2546 }; 2547 2548 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 2549 { 2550 .type = AMD_IP_BLOCK_TYPE_PSP, 2551 .major = 12, 2552 .minor = 0, 2553 .rev = 0, 2554 .funcs = &psp_ip_funcs, 2555 }; 2556