1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 case IP_VERSION(15, 0, 9): 279 psp_v15_0_0_set_psp_funcs(psp); 280 psp->boot_time_tmr = false; 281 break; 282 case IP_VERSION(15, 0, 8): 283 psp_v15_0_8_set_psp_funcs(psp); 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 psp->adev = adev; 290 291 adev->psp_timeout = 20000; 292 293 psp_check_pmfw_centralized_cstate_management(psp); 294 295 if (amdgpu_sriov_vf(adev)) 296 return psp_init_sriov_microcode(psp); 297 else 298 return psp_init_microcode(psp); 299 } 300 301 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 302 { 303 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 304 &mem_ctx->shared_buf); 305 mem_ctx->shared_bo = NULL; 306 } 307 308 static void psp_free_shared_bufs(struct psp_context *psp) 309 { 310 void *tmr_buf; 311 void **pptr; 312 313 /* free TMR memory buffer */ 314 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 315 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 316 psp->tmr_bo = NULL; 317 318 /* free xgmi shared memory */ 319 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 320 321 /* free ras shared memory */ 322 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 323 324 /* free hdcp shared memory */ 325 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 326 327 /* free dtm shared memory */ 328 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 329 330 /* free rap shared memory */ 331 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 332 333 /* free securedisplay shared memory */ 334 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 335 336 337 } 338 339 static void psp_memory_training_fini(struct psp_context *psp) 340 { 341 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 342 343 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 344 kfree(ctx->sys_cache); 345 ctx->sys_cache = NULL; 346 } 347 348 static int psp_memory_training_init(struct psp_context *psp) 349 { 350 int ret; 351 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 352 353 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 354 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 355 return 0; 356 } 357 358 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 359 if (ctx->sys_cache == NULL) { 360 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 361 ret = -ENOMEM; 362 goto Err_out; 363 } 364 365 dev_dbg(psp->adev->dev, 366 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 367 ctx->train_data_size, 368 ctx->p2c_train_data_offset, 369 ctx->c2p_train_data_offset); 370 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 371 return 0; 372 373 Err_out: 374 psp_memory_training_fini(psp); 375 return ret; 376 } 377 378 /* 379 * Helper funciton to query psp runtime database entry 380 * 381 * @adev: amdgpu_device pointer 382 * @entry_type: the type of psp runtime database entry 383 * @db_entry: runtime database entry pointer 384 * 385 * Return false if runtime database doesn't exit or entry is invalid 386 * or true if the specific database entry is found, and copy to @db_entry 387 */ 388 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 389 enum psp_runtime_entry_type entry_type, 390 void *db_entry) 391 { 392 uint64_t db_header_pos, db_dir_pos; 393 struct psp_runtime_data_header db_header = {0}; 394 struct psp_runtime_data_directory db_dir = {0}; 395 bool ret = false; 396 int i; 397 398 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 399 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 401 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 402 return false; 403 404 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 405 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 406 407 /* read runtime db header from vram */ 408 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 409 sizeof(struct psp_runtime_data_header), false); 410 411 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 412 /* runtime db doesn't exist, exit */ 413 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 414 return false; 415 } 416 417 /* read runtime database entry from vram */ 418 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 419 sizeof(struct psp_runtime_data_directory), false); 420 421 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 422 /* invalid db entry count, exit */ 423 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 424 return false; 425 } 426 427 /* look up for requested entry type */ 428 for (i = 0; i < db_dir.entry_count && !ret; i++) { 429 if (db_dir.entry_list[i].entry_type == entry_type) { 430 switch (entry_type) { 431 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 432 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 433 /* invalid db entry size */ 434 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 435 return false; 436 } 437 /* read runtime database entry */ 438 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 439 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 440 ret = true; 441 break; 442 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 443 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 444 /* invalid db entry size */ 445 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 446 return false; 447 } 448 /* read runtime database entry */ 449 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 450 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 451 ret = true; 452 break; 453 default: 454 ret = false; 455 break; 456 } 457 } 458 } 459 460 return ret; 461 } 462 463 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 464 { 465 struct amdgpu_device *adev = ip_block->adev; 466 struct psp_context *psp = &adev->psp; 467 int ret; 468 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 469 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 470 struct psp_runtime_scpm_entry scpm_entry; 471 472 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 473 if (!psp->cmd) { 474 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 475 return -ENOMEM; 476 } 477 478 adev->psp.xgmi_context.supports_extended_data = 479 !adev->gmc.xgmi.connected_to_cpu && 480 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 481 482 memset(&scpm_entry, 0, sizeof(scpm_entry)); 483 if ((psp_get_runtime_db_entry(adev, 484 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 485 &scpm_entry)) && 486 (scpm_entry.scpm_status != SCPM_DISABLE)) { 487 adev->scpm_enabled = true; 488 adev->scpm_status = scpm_entry.scpm_status; 489 } else { 490 adev->scpm_enabled = false; 491 adev->scpm_status = SCPM_DISABLE; 492 } 493 494 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 495 496 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 497 if (psp_get_runtime_db_entry(adev, 498 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 499 &boot_cfg_entry)) { 500 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 501 if ((psp->boot_cfg_bitmask) & 502 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 503 /* If psp runtime database exists, then 504 * only enable two stage memory training 505 * when TWO_STAGE_DRAM_TRAINING bit is set 506 * in runtime database 507 */ 508 mem_training_ctx->enable_mem_training = true; 509 } 510 511 } else { 512 /* If psp runtime database doesn't exist or is 513 * invalid, force enable two stage memory training 514 */ 515 mem_training_ctx->enable_mem_training = true; 516 } 517 518 if (mem_training_ctx->enable_mem_training) { 519 ret = psp_memory_training_init(psp); 520 if (ret) { 521 dev_err(adev->dev, "Failed to initialize memory training!\n"); 522 return ret; 523 } 524 525 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 526 if (ret) { 527 dev_err(adev->dev, "Failed to process memory training!\n"); 528 return ret; 529 } 530 } 531 532 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 533 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 534 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 535 &psp->fw_pri_bo, 536 &psp->fw_pri_mc_addr, 537 &psp->fw_pri_buf); 538 if (ret) 539 return ret; 540 541 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 542 AMDGPU_GEM_DOMAIN_VRAM | 543 AMDGPU_GEM_DOMAIN_GTT, 544 &psp->fence_buf_bo, 545 &psp->fence_buf_mc_addr, 546 &psp->fence_buf); 547 if (ret) 548 goto failed1; 549 550 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 551 AMDGPU_GEM_DOMAIN_VRAM | 552 AMDGPU_GEM_DOMAIN_GTT, 553 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 554 (void **)&psp->cmd_buf_mem); 555 if (ret) 556 goto failed2; 557 558 return 0; 559 560 failed2: 561 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 562 &psp->fence_buf_mc_addr, &psp->fence_buf); 563 failed1: 564 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 565 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 566 return ret; 567 } 568 569 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 570 { 571 struct amdgpu_device *adev = ip_block->adev; 572 struct psp_context *psp = &adev->psp; 573 574 psp_memory_training_fini(psp); 575 576 amdgpu_ucode_release(&psp->sos_fw); 577 amdgpu_ucode_release(&psp->asd_fw); 578 amdgpu_ucode_release(&psp->ta_fw); 579 amdgpu_ucode_release(&psp->cap_fw); 580 amdgpu_ucode_release(&psp->toc_fw); 581 582 kfree(psp->cmd); 583 psp->cmd = NULL; 584 585 psp_free_shared_bufs(psp); 586 587 if (psp->km_ring.ring_mem) 588 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 589 &psp->km_ring.ring_mem_mc_addr, 590 (void **)&psp->km_ring.ring_mem); 591 592 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 593 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 594 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 595 &psp->fence_buf_mc_addr, &psp->fence_buf); 596 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 597 (void **)&psp->cmd_buf_mem); 598 599 return 0; 600 } 601 602 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 603 uint32_t mask, uint32_t flags) 604 { 605 bool check_changed = flags & PSP_WAITREG_CHANGED; 606 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 607 uint32_t val; 608 int i; 609 struct amdgpu_device *adev = psp->adev; 610 611 if (psp->adev->no_hw_access) 612 return 0; 613 614 for (i = 0; i < adev->usec_timeout; i++) { 615 val = RREG32(reg_index); 616 if (check_changed) { 617 if (val != reg_val) 618 return 0; 619 } else { 620 if ((val & mask) == reg_val) 621 return 0; 622 } 623 udelay(1); 624 } 625 626 if (verbose) 627 dev_err(adev->dev, 628 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 629 reg_index, mask, val, reg_val); 630 631 return -ETIME; 632 } 633 634 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 635 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 636 { 637 uint32_t val; 638 int i; 639 struct amdgpu_device *adev = psp->adev; 640 641 if (psp->adev->no_hw_access) 642 return 0; 643 644 for (i = 0; i < msec_timeout; i++) { 645 val = RREG32(reg_index); 646 if ((val & mask) == reg_val) 647 return 0; 648 msleep(1); 649 } 650 651 return -ETIME; 652 } 653 654 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 655 { 656 switch (cmd_id) { 657 case GFX_CMD_ID_LOAD_TA: 658 return "LOAD_TA"; 659 case GFX_CMD_ID_UNLOAD_TA: 660 return "UNLOAD_TA"; 661 case GFX_CMD_ID_INVOKE_CMD: 662 return "INVOKE_CMD"; 663 case GFX_CMD_ID_LOAD_ASD: 664 return "LOAD_ASD"; 665 case GFX_CMD_ID_SETUP_TMR: 666 return "SETUP_TMR"; 667 case GFX_CMD_ID_LOAD_IP_FW: 668 return "LOAD_IP_FW"; 669 case GFX_CMD_ID_DESTROY_TMR: 670 return "DESTROY_TMR"; 671 case GFX_CMD_ID_SAVE_RESTORE: 672 return "SAVE_RESTORE_IP_FW"; 673 case GFX_CMD_ID_SETUP_VMR: 674 return "SETUP_VMR"; 675 case GFX_CMD_ID_DESTROY_VMR: 676 return "DESTROY_VMR"; 677 case GFX_CMD_ID_PROG_REG: 678 return "PROG_REG"; 679 case GFX_CMD_ID_GET_FW_ATTESTATION: 680 return "GET_FW_ATTESTATION"; 681 case GFX_CMD_ID_LOAD_TOC: 682 return "ID_LOAD_TOC"; 683 case GFX_CMD_ID_AUTOLOAD_RLC: 684 return "AUTOLOAD_RLC"; 685 case GFX_CMD_ID_BOOT_CFG: 686 return "BOOT_CFG"; 687 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 688 return "CONFIG_SQ_PERFMON"; 689 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 690 return "FB_FW_RESERV_ADDR"; 691 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 692 return "FB_FW_RESERV_EXT_ADDR"; 693 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 694 return "SPATIAL_PARTITION"; 695 case GFX_CMD_ID_FB_NPS_MODE: 696 return "NPS_MODE_CHANGE"; 697 case GFX_CMD_ID_PERF_HW: 698 return "PERF MONITORING HW"; 699 default: 700 return "UNKNOWN CMD"; 701 } 702 } 703 704 static bool psp_err_warn(struct psp_context *psp) 705 { 706 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 707 708 /* This response indicates reg list is already loaded */ 709 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 710 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 711 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 712 cmd->resp.status == TEE_ERROR_CANCEL) 713 return false; 714 715 return true; 716 } 717 718 static int 719 psp_cmd_submit_buf(struct psp_context *psp, 720 struct amdgpu_firmware_info *ucode, 721 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 722 { 723 int ret; 724 int index; 725 int timeout = psp->adev->psp_timeout; 726 bool ras_intr = false; 727 bool skip_unsupport = false; 728 729 if (psp->adev->no_hw_access) 730 return 0; 731 732 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 733 734 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 735 736 index = atomic_inc_return(&psp->fence_value); 737 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 738 if (ret) { 739 atomic_dec(&psp->fence_value); 740 goto exit; 741 } 742 743 amdgpu_device_invalidate_hdp(psp->adev, NULL); 744 while (*((unsigned int *)psp->fence_buf) != index) { 745 if (--timeout == 0) 746 break; 747 /* 748 * Shouldn't wait for timeout when err_event_athub occurs, 749 * because gpu reset thread triggered and lock resource should 750 * be released for psp resume sequence. 751 */ 752 ras_intr = amdgpu_ras_intr_triggered(); 753 if (ras_intr) 754 break; 755 usleep_range(60, 100); 756 amdgpu_device_invalidate_hdp(psp->adev, NULL); 757 } 758 759 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 760 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 761 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 762 763 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 764 765 /* In some cases, psp response status is not 0 even there is no 766 * problem while the command is submitted. Some version of PSP FW 767 * doesn't write 0 to that field. 768 * So here we would like to only print a warning instead of an error 769 * during psp initialization to avoid breaking hw_init and it doesn't 770 * return -EINVAL. 771 */ 772 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 773 if (ucode) 774 dev_warn(psp->adev->dev, 775 "failed to load ucode %s(0x%X) ", 776 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 777 if (psp_err_warn(psp)) 778 dev_warn( 779 psp->adev->dev, 780 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 781 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 782 psp->cmd_buf_mem->cmd_id, 783 psp->cmd_buf_mem->resp.status); 784 /* If any firmware (including CAP) load fails under SRIOV, it should 785 * return failure to stop the VF from initializing. 786 * Also return failure in case of timeout 787 */ 788 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 789 ret = -EINVAL; 790 goto exit; 791 } 792 } 793 794 if (ucode) { 795 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 796 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 797 } 798 799 exit: 800 return ret; 801 } 802 803 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 804 { 805 struct psp_gfx_cmd_resp *cmd = psp->cmd; 806 807 mutex_lock(&psp->mutex); 808 809 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 810 811 return cmd; 812 } 813 814 static void release_psp_cmd_buf(struct psp_context *psp) 815 { 816 mutex_unlock(&psp->mutex); 817 } 818 819 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 820 struct psp_gfx_cmd_resp *cmd, 821 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 822 { 823 struct amdgpu_device *adev = psp->adev; 824 uint32_t size = 0; 825 uint64_t tmr_pa = 0; 826 827 if (tmr_bo) { 828 size = amdgpu_bo_size(tmr_bo); 829 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 830 } 831 832 if (amdgpu_sriov_vf(psp->adev)) 833 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 834 else 835 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 836 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 837 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 838 cmd->cmd.cmd_setup_tmr.buf_size = size; 839 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 840 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 841 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 842 } 843 844 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 845 uint64_t pri_buf_mc, uint32_t size) 846 { 847 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 848 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 849 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 850 cmd->cmd.cmd_load_toc.toc_size = size; 851 } 852 853 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 854 static int psp_load_toc(struct psp_context *psp, 855 uint32_t *tmr_size) 856 { 857 int ret; 858 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 859 860 /* Copy toc to psp firmware private buffer */ 861 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 862 if (ret) { 863 release_psp_cmd_buf(psp); 864 return ret; 865 } 866 867 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 868 869 ret = psp_cmd_submit_buf(psp, NULL, cmd, 870 psp->fence_buf_mc_addr); 871 if (!ret) 872 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 873 874 release_psp_cmd_buf(psp); 875 876 return ret; 877 } 878 879 /* Set up Trusted Memory Region */ 880 static int psp_tmr_init(struct psp_context *psp) 881 { 882 int ret = 0; 883 int tmr_size; 884 void *tmr_buf; 885 void **pptr; 886 887 /* 888 * According to HW engineer, they prefer the TMR address be "naturally 889 * aligned" , e.g. the start address be an integer divide of TMR size. 890 * 891 * Note: this memory need be reserved till the driver 892 * uninitializes. 893 */ 894 tmr_size = PSP_TMR_SIZE(psp->adev); 895 896 /* For ASICs support RLC autoload, psp will parse the toc 897 * and calculate the total size of TMR needed 898 */ 899 if (!amdgpu_sriov_vf(psp->adev) && 900 psp->toc.start_addr && 901 psp->toc.size_bytes && 902 psp->fw_pri_buf) { 903 ret = psp_load_toc(psp, &tmr_size); 904 if (ret) { 905 dev_err(psp->adev->dev, "Failed to load toc\n"); 906 return ret; 907 } 908 } 909 910 if (!psp->tmr_bo && !psp->boot_time_tmr) { 911 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 912 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 913 PSP_TMR_ALIGNMENT, 914 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 915 &psp->tmr_bo, &psp->tmr_mc_addr, 916 pptr); 917 } 918 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 919 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 920 921 return ret; 922 } 923 924 static bool psp_skip_tmr(struct psp_context *psp) 925 { 926 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 927 928 if (amdgpu_sriov_vf(psp->adev)) 929 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 930 else 931 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 932 } 933 934 static int psp_tmr_load(struct psp_context *psp) 935 { 936 int ret; 937 struct psp_gfx_cmd_resp *cmd; 938 939 if (psp_skip_tmr(psp)) 940 return 0; 941 942 cmd = acquire_psp_cmd_buf(psp); 943 944 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 945 if (psp->tmr_bo) 946 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 947 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 948 949 ret = psp_cmd_submit_buf(psp, NULL, cmd, 950 psp->fence_buf_mc_addr); 951 952 release_psp_cmd_buf(psp); 953 954 return ret; 955 } 956 957 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 958 struct psp_gfx_cmd_resp *cmd) 959 { 960 if (amdgpu_sriov_vf(psp->adev)) 961 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 962 else 963 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 964 } 965 966 static int psp_tmr_unload(struct psp_context *psp) 967 { 968 int ret; 969 struct psp_gfx_cmd_resp *cmd; 970 971 if (psp_skip_tmr(psp)) 972 return 0; 973 974 cmd = acquire_psp_cmd_buf(psp); 975 976 psp_prep_tmr_unload_cmd_buf(psp, cmd); 977 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 978 979 ret = psp_cmd_submit_buf(psp, NULL, cmd, 980 psp->fence_buf_mc_addr); 981 982 release_psp_cmd_buf(psp); 983 984 return ret; 985 } 986 987 static int psp_tmr_terminate(struct psp_context *psp) 988 { 989 return psp_tmr_unload(psp); 990 } 991 992 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 993 uint64_t *output_ptr) 994 { 995 int ret; 996 struct psp_gfx_cmd_resp *cmd; 997 998 if (!output_ptr) 999 return -EINVAL; 1000 1001 if (amdgpu_sriov_vf(psp->adev)) 1002 return 0; 1003 1004 cmd = acquire_psp_cmd_buf(psp); 1005 1006 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1007 1008 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1009 psp->fence_buf_mc_addr); 1010 1011 if (!ret) { 1012 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1013 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1014 } 1015 1016 release_psp_cmd_buf(psp); 1017 1018 return ret; 1019 } 1020 1021 static int psp_get_fw_reservation_info(struct psp_context *psp, 1022 uint32_t cmd_id, 1023 uint64_t *addr, 1024 uint32_t *size) 1025 { 1026 int ret; 1027 uint32_t status; 1028 struct psp_gfx_cmd_resp *cmd; 1029 1030 cmd = acquire_psp_cmd_buf(psp); 1031 1032 cmd->cmd_id = cmd_id; 1033 1034 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1035 psp->fence_buf_mc_addr); 1036 if (ret) { 1037 release_psp_cmd_buf(psp); 1038 return ret; 1039 } 1040 1041 status = cmd->resp.status; 1042 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1043 release_psp_cmd_buf(psp); 1044 *addr = 0; 1045 *size = 0; 1046 return 0; 1047 } 1048 1049 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1050 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1051 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1052 1053 release_psp_cmd_buf(psp); 1054 1055 return 0; 1056 } 1057 1058 int psp_update_fw_reservation(struct psp_context *psp) 1059 { 1060 int ret; 1061 uint64_t reserv_addr, reserv_addr_ext; 1062 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1063 struct amdgpu_device *adev = psp->adev; 1064 1065 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1066 1067 if (amdgpu_sriov_vf(psp->adev)) 1068 return 0; 1069 1070 switch (mp0_ip_ver) { 1071 case IP_VERSION(14, 0, 2): 1072 if (adev->psp.sos.fw_version < 0x3b0e0d) 1073 return 0; 1074 break; 1075 1076 case IP_VERSION(14, 0, 3): 1077 if (adev->psp.sos.fw_version < 0x3a0e14) 1078 return 0; 1079 break; 1080 1081 default: 1082 return 0; 1083 } 1084 1085 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1086 if (ret) 1087 return ret; 1088 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1089 if (ret) 1090 return ret; 1091 1092 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1093 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1094 return 0; 1095 } 1096 1097 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1098 1099 reserv_size = roundup(reserv_size, SZ_1M); 1100 1101 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1102 reserv_addr, reserv_size, false); 1103 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1104 if (ret) { 1105 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1106 return ret; 1107 } 1108 1109 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1110 1111 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1112 reserv_addr_ext, reserv_size_ext, false); 1113 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1114 if (ret) { 1115 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1116 return ret; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1123 { 1124 struct psp_context *psp = &adev->psp; 1125 struct psp_gfx_cmd_resp *cmd; 1126 int ret; 1127 1128 if (amdgpu_sriov_vf(adev)) 1129 return 0; 1130 1131 cmd = acquire_psp_cmd_buf(psp); 1132 1133 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1134 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1135 1136 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1137 if (!ret) { 1138 *boot_cfg = 1139 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1140 } 1141 1142 release_psp_cmd_buf(psp); 1143 1144 return ret; 1145 } 1146 1147 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1148 { 1149 int ret; 1150 struct psp_context *psp = &adev->psp; 1151 struct psp_gfx_cmd_resp *cmd; 1152 1153 if (amdgpu_sriov_vf(adev)) 1154 return 0; 1155 1156 cmd = acquire_psp_cmd_buf(psp); 1157 1158 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1159 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1160 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1161 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1162 1163 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1164 1165 release_psp_cmd_buf(psp); 1166 1167 return ret; 1168 } 1169 1170 static int psp_rl_load(struct amdgpu_device *adev) 1171 { 1172 int ret; 1173 struct psp_context *psp = &adev->psp; 1174 struct psp_gfx_cmd_resp *cmd; 1175 1176 if (!is_psp_fw_valid(psp->rl)) 1177 return 0; 1178 1179 cmd = acquire_psp_cmd_buf(psp); 1180 1181 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1182 if (ret) { 1183 release_psp_cmd_buf(psp); 1184 return ret; 1185 } 1186 1187 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1188 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1189 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1190 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1191 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1192 1193 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1194 1195 release_psp_cmd_buf(psp); 1196 1197 return ret; 1198 } 1199 1200 int psp_memory_partition(struct psp_context *psp, int mode) 1201 { 1202 struct psp_gfx_cmd_resp *cmd; 1203 int ret; 1204 1205 if (amdgpu_sriov_vf(psp->adev)) 1206 return 0; 1207 1208 cmd = acquire_psp_cmd_buf(psp); 1209 1210 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1211 cmd->cmd.cmd_memory_part.mode = mode; 1212 1213 dev_info(psp->adev->dev, 1214 "Requesting %d memory partition change through PSP", mode); 1215 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1216 if (ret) 1217 dev_err(psp->adev->dev, 1218 "PSP request failed to change to NPS%d mode\n", mode); 1219 1220 release_psp_cmd_buf(psp); 1221 1222 return ret; 1223 } 1224 1225 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 1226 { 1227 int ret; 1228 struct psp_context *psp = &adev->psp; 1229 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1230 1231 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL; 1232 1233 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1234 if (ret) { 1235 dev_err(psp->adev->dev, 1236 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret); 1237 release_psp_cmd_buf(psp); 1238 return ret; 1239 } 1240 1241 if (cmd->resp.status) { 1242 dev_err(psp->adev->dev, 1243 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n", 1244 cmd->cmd_id, cmd->resp.status); 1245 ret = -EIO; 1246 } 1247 release_psp_cmd_buf(psp); 1248 1249 return ret; 1250 } 1251 1252 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1253 uint32_t *ptl_fmt) 1254 { 1255 struct amdgpu_device *adev = psp->adev; 1256 1257 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1258 return -EINVAL; 1259 1260 switch (fmt) { 1261 case AMDGPU_PTL_FMT_I8: 1262 *ptl_fmt = GFX_FTYPE_I8; 1263 break; 1264 case AMDGPU_PTL_FMT_F16: 1265 *ptl_fmt = GFX_FTYPE_F16; 1266 break; 1267 case AMDGPU_PTL_FMT_BF16: 1268 *ptl_fmt = GFX_FTYPE_BF16; 1269 break; 1270 case AMDGPU_PTL_FMT_F32: 1271 *ptl_fmt = GFX_FTYPE_F32; 1272 break; 1273 case AMDGPU_PTL_FMT_F64: 1274 *ptl_fmt = GFX_FTYPE_F64; 1275 break; 1276 case AMDGPU_PTL_FMT_F8: 1277 *ptl_fmt = GFX_FTYPE_F8; 1278 break; 1279 case AMDGPU_PTL_FMT_VECTOR: 1280 *ptl_fmt = GFX_FTYPE_VECTOR; 1281 break; 1282 default: 1283 return -EINVAL; 1284 } 1285 1286 return 0; 1287 } 1288 1289 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1290 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1291 { 1292 struct psp_gfx_cmd_resp *cmd; 1293 struct amdgpu_ptl *ptl = &psp->ptl; 1294 int ret; 1295 1296 cmd = acquire_psp_cmd_buf(psp); 1297 1298 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1299 cmd->cmd.cmd_req_perf_hw.req = req_code; 1300 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1301 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1302 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1303 1304 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1305 if (ret) 1306 goto out; 1307 1308 /* 1309 * Check response status explicitly to avoid 1310 * updating cached PTL state with invalid data. 1311 */ 1312 if (cmd->resp.status) { 1313 dev_err(psp->adev->dev, 1314 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1315 req_code, cmd->resp.status, 1316 cmd->resp.uresp.perf_hw_info.resp); 1317 ret = -EIO; 1318 goto out; 1319 } 1320 1321 /* Parse response */ 1322 switch (req_code) { 1323 case PSP_PTL_PERF_MON_QUERY: 1324 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1325 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1326 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1327 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1328 *ptl_state, *fmt1, *fmt2); 1329 break; 1330 case PSP_PTL_PERF_MON_SET: 1331 /* Update cached state only on success */ 1332 ptl->enabled = *ptl_state; 1333 ptl->fmt1 = *fmt1; 1334 ptl->fmt2 = *fmt2; 1335 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1336 *ptl_state, *fmt1, *fmt2); 1337 break; 1338 } 1339 1340 out: 1341 release_psp_cmd_buf(psp); 1342 return ret; 1343 } 1344 1345 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1346 uint32_t *ptl_state, 1347 enum amdgpu_ptl_fmt *fmt1, 1348 enum amdgpu_ptl_fmt *fmt2) 1349 { 1350 uint32_t ptl_fmt1, ptl_fmt2; 1351 struct psp_context *psp; 1352 struct amdgpu_ptl *ptl; 1353 int ret; 1354 1355 if (!adev || !ptl_state || !fmt1 || !fmt2) 1356 return -EINVAL; 1357 1358 if (amdgpu_sriov_vf(adev)) 1359 return 0; 1360 1361 psp = &adev->psp; 1362 ptl = &psp->ptl; 1363 1364 if (ptl->permanently_disabled && *ptl_state == 1) 1365 return 0; 1366 1367 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1368 psp->sos.fw_version < 0x0036081a) 1369 return -EOPNOTSUPP; 1370 1371 /* Verify formats */ 1372 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1373 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1374 return -EINVAL; 1375 1376 /* 1377 * Add check to skip if state and formats are identical to current ones 1378 */ 1379 if (req_code == PSP_PTL_PERF_MON_SET && 1380 ptl->enabled == *ptl_state && 1381 ptl->fmt1 == ptl_fmt1 && 1382 ptl->fmt2 == ptl_fmt2) 1383 return 0; 1384 1385 /* If enabling PTL, check disable bitmap */ 1386 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1387 if (!bitmap_empty(ptl->disable_bitmap, 1388 AMDGPU_PTL_DISABLE_MAX)) { 1389 dev_dbg(adev->dev, 1390 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1391 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1392 ptl->disable_bitmap), 1393 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1394 ptl->disable_bitmap), 1395 atomic_read(&ptl->disable_ref)); 1396 return 0; 1397 } 1398 } 1399 1400 if (req_code == PSP_PTL_PERF_MON_SET) { 1401 amdgpu_amdkfd_stop_sched_all(adev); 1402 /* Wait for GFX engine idle before PTL state transition */ 1403 ret = amdgpu_device_ip_wait_for_idle(adev, 1404 AMD_IP_BLOCK_TYPE_GFX); 1405 if (ret) { 1406 amdgpu_amdkfd_start_sched_all(adev); 1407 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1408 return ret; 1409 } 1410 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1411 amdgpu_amdkfd_start_sched_all(adev); 1412 } else { 1413 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1414 } 1415 1416 return ret; 1417 } 1418 1419 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1420 { 1421 int i; 1422 1423 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1424 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1425 return (enum amdgpu_ptl_fmt)i; 1426 } 1427 1428 return AMDGPU_PTL_FMT_INVALID; 1429 } 1430 1431 static ssize_t ptl_supported_formats_show(struct device *dev, 1432 struct device_attribute *attr, char *buf) 1433 { 1434 ssize_t len = 0; 1435 1436 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1437 const char *fmt = amdgpu_ptl_fmt_str[i]; 1438 1439 len += sysfs_emit_at(buf, len, "%s%s", 1440 fmt ? fmt : "UNKNOWN", 1441 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1442 } 1443 1444 return len; 1445 } 1446 1447 static ssize_t ptl_enable_store(struct device *dev, 1448 struct device_attribute *attr, 1449 const char *buf, size_t count) 1450 { 1451 struct drm_device *ddev = dev_get_drvdata(dev); 1452 struct amdgpu_device *adev = drm_to_adev(ddev); 1453 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1454 uint32_t ptl_state, fmt1, fmt2; 1455 int ret; 1456 bool enable; 1457 bool bit_changed = false; 1458 1459 mutex_lock(&ptl->mutex); 1460 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1461 enable = true; 1462 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1463 enable = false; 1464 } else { 1465 mutex_unlock(&ptl->mutex); 1466 return -EINVAL; 1467 } 1468 1469 /* Block enable when permanently disabled */ 1470 if (ptl->permanently_disabled) { 1471 mutex_unlock(&ptl->mutex); 1472 return -EPERM; 1473 } 1474 1475 fmt1 = ptl->fmt1; 1476 fmt2 = ptl->fmt2; 1477 ptl_state = enable ? 1 : 0; 1478 1479 if (enable) 1480 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1481 ptl->disable_bitmap); 1482 1483 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1484 if (ret) { 1485 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1486 if (enable && bit_changed) 1487 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1488 mutex_unlock(&ptl->mutex); 1489 return ret; 1490 } 1491 1492 if (!enable) 1493 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1494 1495 mutex_unlock(&ptl->mutex); 1496 1497 return count; 1498 } 1499 1500 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1501 { 1502 struct drm_device *ddev = dev_get_drvdata(dev); 1503 struct amdgpu_device *adev = drm_to_adev(ddev); 1504 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1505 1506 if (ptl->permanently_disabled) 1507 return sysfs_emit(buf, "permanently disabled\n"); 1508 1509 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1510 } 1511 1512 static ssize_t ptl_format_store(struct device *dev, 1513 struct device_attribute *attr, 1514 const char *buf, size_t count) 1515 { 1516 struct drm_device *ddev = dev_get_drvdata(dev); 1517 struct amdgpu_device *adev = drm_to_adev(ddev); 1518 char fmt1_str[8], fmt2_str[8]; 1519 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1520 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1521 uint32_t ptl_state, fmt1, fmt2; 1522 int ret; 1523 1524 /* Only allow format update when PTL is enabled */ 1525 if (!ptl->enabled) 1526 return -EPERM; 1527 1528 mutex_lock(&ptl->mutex); 1529 /* Parse input, expecting "FMT1,FMT2" */ 1530 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1531 mutex_unlock(&ptl->mutex); 1532 return -EINVAL; 1533 } 1534 1535 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1536 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1537 1538 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1539 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1540 fmt1_enum == fmt2_enum) { 1541 mutex_unlock(&ptl->mutex); 1542 return -EINVAL; 1543 } 1544 1545 ptl_state = ptl->enabled; 1546 fmt1 = fmt1_enum; 1547 fmt2 = fmt2_enum; 1548 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1549 if (ret) { 1550 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1551 mutex_unlock(&ptl->mutex); 1552 return ret; 1553 } 1554 mutex_unlock(&ptl->mutex); 1555 1556 return count; 1557 } 1558 1559 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1560 { 1561 struct drm_device *ddev = dev_get_drvdata(dev); 1562 struct amdgpu_device *adev = drm_to_adev(ddev); 1563 struct psp_context *psp = &adev->psp; 1564 1565 return sysfs_emit(buf, "%s,%s\n", 1566 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1567 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1568 } 1569 1570 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1571 { 1572 struct device *dev = kobj_to_dev(kobj); 1573 struct drm_device *ddev = dev_get_drvdata(dev); 1574 struct amdgpu_device *adev = drm_to_adev(ddev); 1575 1576 /* Only show PTL sysfs files if PTL hardware is supported */ 1577 if (!adev->psp.ptl.hw_supported) 1578 return 0; 1579 1580 return attr->mode; 1581 } 1582 1583 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1584 { 1585 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1586 int ret; 1587 1588 if (!ptl->hw_supported) 1589 return 0; 1590 1591 if (ptl->ptl_sysfs_created) 1592 return 0; 1593 1594 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1595 if (!ret) 1596 ptl->ptl_sysfs_created = true; 1597 1598 return ret; 1599 } 1600 1601 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1602 { 1603 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1604 1605 if (!ptl->hw_supported) 1606 return; 1607 1608 if (!ptl->ptl_sysfs_created) 1609 return; 1610 1611 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1612 ptl->ptl_sysfs_created = false; 1613 } 1614 1615 int psp_spatial_partition(struct psp_context *psp, int mode) 1616 { 1617 struct psp_gfx_cmd_resp *cmd; 1618 int ret; 1619 1620 if (amdgpu_sriov_vf(psp->adev)) 1621 return 0; 1622 1623 cmd = acquire_psp_cmd_buf(psp); 1624 1625 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1626 cmd->cmd.cmd_spatial_part.mode = mode; 1627 1628 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1629 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1630 1631 release_psp_cmd_buf(psp); 1632 1633 return ret; 1634 } 1635 1636 static int psp_asd_initialize(struct psp_context *psp) 1637 { 1638 int ret; 1639 1640 /* If PSP version doesn't match ASD version, asd loading will be failed. 1641 * add workaround to bypass it for sriov now. 1642 * TODO: add version check to make it common 1643 */ 1644 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1645 return 0; 1646 1647 /* bypass asd if display hardware is not available */ 1648 if (!amdgpu_device_has_display_hardware(psp->adev) && 1649 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1650 return 0; 1651 1652 psp->asd_context.mem_context.shared_mc_addr = 0; 1653 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1654 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1655 1656 ret = psp_ta_load(psp, &psp->asd_context); 1657 if (!ret) 1658 psp->asd_context.initialized = true; 1659 1660 return ret; 1661 } 1662 1663 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1664 uint32_t session_id) 1665 { 1666 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1667 cmd->cmd.cmd_unload_ta.session_id = session_id; 1668 } 1669 1670 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1671 { 1672 int ret; 1673 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1674 1675 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1676 1677 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1678 1679 context->resp_status = cmd->resp.status; 1680 1681 release_psp_cmd_buf(psp); 1682 1683 return ret; 1684 } 1685 1686 static int psp_asd_terminate(struct psp_context *psp) 1687 { 1688 int ret; 1689 1690 if (amdgpu_sriov_vf(psp->adev)) 1691 return 0; 1692 1693 if (!psp->asd_context.initialized) 1694 return 0; 1695 1696 ret = psp_ta_unload(psp, &psp->asd_context); 1697 if (!ret) 1698 psp->asd_context.initialized = false; 1699 1700 return ret; 1701 } 1702 1703 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1704 uint32_t id, uint32_t value) 1705 { 1706 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1707 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1708 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1709 } 1710 1711 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1712 uint32_t value) 1713 { 1714 struct psp_gfx_cmd_resp *cmd; 1715 int ret = 0; 1716 1717 if (reg >= PSP_REG_LAST) 1718 return -EINVAL; 1719 1720 cmd = acquire_psp_cmd_buf(psp); 1721 1722 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1723 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1724 if (ret) 1725 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1726 1727 release_psp_cmd_buf(psp); 1728 1729 return ret; 1730 } 1731 1732 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1733 uint64_t ta_bin_mc, 1734 struct ta_context *context) 1735 { 1736 cmd->cmd_id = context->ta_load_type; 1737 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1738 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1739 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1740 1741 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1742 lower_32_bits(context->mem_context.shared_mc_addr); 1743 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1744 upper_32_bits(context->mem_context.shared_mc_addr); 1745 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1746 } 1747 1748 int psp_ta_init_shared_buf(struct psp_context *psp, 1749 struct ta_mem_context *mem_ctx) 1750 { 1751 /* 1752 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1753 * physical) for ta to host memory 1754 */ 1755 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1756 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1757 AMDGPU_GEM_DOMAIN_GTT, 1758 &mem_ctx->shared_bo, 1759 &mem_ctx->shared_mc_addr, 1760 &mem_ctx->shared_buf); 1761 } 1762 1763 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1764 uint32_t ta_cmd_id, 1765 uint32_t session_id) 1766 { 1767 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1768 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1769 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1770 } 1771 1772 int psp_ta_invoke(struct psp_context *psp, 1773 uint32_t ta_cmd_id, 1774 struct ta_context *context) 1775 { 1776 int ret; 1777 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1778 1779 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1780 1781 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1782 psp->fence_buf_mc_addr); 1783 1784 context->resp_status = cmd->resp.status; 1785 1786 release_psp_cmd_buf(psp); 1787 1788 return ret; 1789 } 1790 1791 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1792 { 1793 int ret; 1794 struct psp_gfx_cmd_resp *cmd; 1795 1796 cmd = acquire_psp_cmd_buf(psp); 1797 1798 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1799 context->bin_desc.size_bytes); 1800 if (ret) { 1801 release_psp_cmd_buf(psp); 1802 return ret; 1803 } 1804 1805 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1806 context->mem_context.shared_bo) 1807 context->mem_context.shared_mc_addr = 1808 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1809 1810 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1811 1812 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1813 psp->fence_buf_mc_addr); 1814 1815 context->resp_status = cmd->resp.status; 1816 1817 if (!ret) 1818 context->session_id = cmd->resp.session_id; 1819 1820 release_psp_cmd_buf(psp); 1821 1822 return ret; 1823 } 1824 1825 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1826 { 1827 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1828 } 1829 1830 int psp_xgmi_terminate(struct psp_context *psp) 1831 { 1832 int ret; 1833 struct amdgpu_device *adev = psp->adev; 1834 1835 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1836 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1837 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1838 adev->gmc.xgmi.connected_to_cpu)) 1839 return 0; 1840 1841 if (!psp->xgmi_context.context.initialized) 1842 return 0; 1843 1844 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1845 1846 psp->xgmi_context.context.initialized = false; 1847 1848 return ret; 1849 } 1850 1851 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1852 { 1853 struct ta_xgmi_shared_memory *xgmi_cmd; 1854 int ret; 1855 1856 if (!psp->ta_fw || 1857 !psp->xgmi_context.context.bin_desc.size_bytes || 1858 !psp->xgmi_context.context.bin_desc.start_addr) 1859 return -ENOENT; 1860 1861 if (!load_ta) 1862 goto invoke; 1863 1864 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1865 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1866 1867 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1868 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1869 if (ret) 1870 return ret; 1871 } 1872 1873 /* Load XGMI TA */ 1874 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1875 if (!ret) 1876 psp->xgmi_context.context.initialized = true; 1877 else 1878 return ret; 1879 1880 invoke: 1881 /* Initialize XGMI session */ 1882 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1883 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1884 xgmi_cmd->flag_extend_link_record = set_extended_data; 1885 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1886 1887 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1888 /* note down the capbility flag for XGMI TA */ 1889 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1890 1891 if (!amdgpu_sriov_vf(psp->adev)) 1892 psp->xgmi_context.supports_ext_link_info = psp->xgmi_context.xgmi_ta_caps & 1893 EXTEND_PEER_LINK_INFO_CMD_FLAG; 1894 else 1895 psp->xgmi_context.supports_ext_link_info = amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 1896 1897 return ret; 1898 } 1899 1900 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1901 { 1902 struct ta_xgmi_shared_memory *xgmi_cmd; 1903 int ret; 1904 1905 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1906 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1907 1908 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1909 1910 /* Invoke xgmi ta to get hive id */ 1911 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1912 if (ret) 1913 return ret; 1914 1915 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1916 1917 return 0; 1918 } 1919 1920 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1921 { 1922 struct ta_xgmi_shared_memory *xgmi_cmd; 1923 int ret; 1924 1925 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1926 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1927 1928 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1929 1930 /* Invoke xgmi ta to get the node id */ 1931 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1932 if (ret) 1933 return ret; 1934 1935 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1936 1937 return 0; 1938 } 1939 1940 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1941 { 1942 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1943 IP_VERSION(13, 0, 2) && 1944 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1945 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1946 IP_VERSION(13, 0, 6); 1947 } 1948 1949 /* 1950 * Chips that support extended topology information require the driver to 1951 * reflect topology information in the opposite direction. This is 1952 * because the TA has already exceeded its link record limit and if the 1953 * TA holds bi-directional information, the driver would have to do 1954 * multiple fetches instead of just two. 1955 */ 1956 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1957 struct psp_xgmi_node_info node_info) 1958 { 1959 struct amdgpu_device *mirror_adev; 1960 struct amdgpu_hive_info *hive; 1961 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1962 uint64_t dst_node_id = node_info.node_id; 1963 uint8_t dst_num_hops = node_info.num_hops; 1964 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1965 uint8_t dst_num_links = node_info.num_links; 1966 1967 hive = amdgpu_get_xgmi_hive(psp->adev); 1968 if (WARN_ON(!hive)) 1969 return; 1970 1971 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1972 struct psp_xgmi_topology_info *mirror_top_info; 1973 int j; 1974 1975 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1976 continue; 1977 1978 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1979 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1980 if (mirror_top_info->nodes[j].node_id != src_node_id) 1981 continue; 1982 1983 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1984 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1985 /* prevent 0 num_links value re-reflection since reflection 1986 * criteria is based on num_hops (direct or indirect). 1987 */ 1988 if (dst_num_links) { 1989 mirror_top_info->nodes[j].num_links = dst_num_links; 1990 /* swap src and dst due to frame of reference */ 1991 for (int k = 0; k < dst_num_links; k++) { 1992 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1993 node_info.port_num[k].dst_xgmi_port_num; 1994 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1995 node_info.port_num[k].src_xgmi_port_num; 1996 } 1997 } 1998 1999 break; 2000 } 2001 2002 break; 2003 } 2004 2005 amdgpu_put_xgmi_hive(hive); 2006 } 2007 2008 int psp_xgmi_get_topology_info(struct psp_context *psp, 2009 int number_devices, 2010 struct psp_xgmi_topology_info *topology, 2011 bool get_extended_data) 2012 { 2013 struct ta_xgmi_shared_memory *xgmi_cmd; 2014 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2015 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 2016 int i; 2017 int ret; 2018 2019 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2020 return -EINVAL; 2021 2022 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2023 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2024 xgmi_cmd->flag_extend_link_record = get_extended_data; 2025 2026 /* Fill in the shared memory with topology information as input */ 2027 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2028 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 2029 topology_info_input->num_nodes = number_devices; 2030 2031 for (i = 0; i < topology_info_input->num_nodes; i++) { 2032 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2033 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2034 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2035 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2036 } 2037 2038 /* Invoke xgmi ta to get the topology information */ 2039 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2040 if (ret) 2041 return ret; 2042 2043 /* Read the output topology information from the shared memory */ 2044 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2045 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2046 for (i = 0; i < topology->num_nodes; i++) { 2047 /* extended data will either be 0 or equal to non-extended data */ 2048 if (topology_info_output->nodes[i].num_hops) 2049 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2050 2051 /* non-extended data gets everything here so no need to update */ 2052 if (!get_extended_data) { 2053 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2054 topology->nodes[i].is_sharing_enabled = 2055 topology_info_output->nodes[i].is_sharing_enabled; 2056 topology->nodes[i].sdma_engine = 2057 topology_info_output->nodes[i].sdma_engine; 2058 } 2059 2060 } 2061 2062 /* Invoke xgmi ta again to get the link information */ 2063 if (psp_xgmi_peer_link_info_supported(psp)) { 2064 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2065 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2066 bool requires_reflection = 2067 (psp->xgmi_context.supports_extended_data && 2068 get_extended_data) || 2069 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2070 IP_VERSION(13, 0, 6) || 2071 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2072 IP_VERSION(13, 0, 14) || 2073 amdgpu_sriov_vf(psp->adev); 2074 2075 /* popluate the shared output buffer rather than the cmd input buffer 2076 * with node_ids as the input for GET_PEER_LINKS command execution. 2077 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2078 * The same requirement for GET_EXTEND_PEER_LINKS command. 2079 */ 2080 if (psp->xgmi_context.supports_ext_link_info) { 2081 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2082 2083 for (i = 0; i < topology->num_nodes; i++) 2084 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2085 2086 link_extend_info_output->num_nodes = topology->num_nodes; 2087 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2088 } else { 2089 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2090 2091 for (i = 0; i < topology->num_nodes; i++) 2092 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2093 2094 link_info_output->num_nodes = topology->num_nodes; 2095 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2096 } 2097 2098 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2099 if (ret) 2100 return ret; 2101 2102 for (i = 0; i < topology->num_nodes; i++) { 2103 uint8_t node_num_links = psp->xgmi_context.supports_ext_link_info ? 2104 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2105 /* accumulate num_links on extended data */ 2106 if (get_extended_data) { 2107 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2108 } else { 2109 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2110 topology->nodes[i].num_links : node_num_links; 2111 } 2112 /* popluate the connected port num info if supported and available */ 2113 if (psp->xgmi_context.supports_ext_link_info && topology->nodes[i].num_links) { 2114 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2115 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2116 } 2117 2118 /* reflect the topology information for bi-directionality */ 2119 if (requires_reflection && topology->nodes[i].num_hops) 2120 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2121 } 2122 } 2123 2124 return 0; 2125 } 2126 2127 int psp_xgmi_set_topology_info(struct psp_context *psp, 2128 int number_devices, 2129 struct psp_xgmi_topology_info *topology) 2130 { 2131 struct ta_xgmi_shared_memory *xgmi_cmd; 2132 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2133 int i; 2134 2135 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2136 return -EINVAL; 2137 2138 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2139 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2140 2141 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2142 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2143 topology_info_input->num_nodes = number_devices; 2144 2145 for (i = 0; i < topology_info_input->num_nodes; i++) { 2146 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2147 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2148 topology_info_input->nodes[i].is_sharing_enabled = 1; 2149 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2150 } 2151 2152 /* Invoke xgmi ta to set topology information */ 2153 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2154 } 2155 2156 // ras begin 2157 static void psp_ras_ta_check_status(struct psp_context *psp) 2158 { 2159 struct ta_ras_shared_memory *ras_cmd = 2160 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2161 2162 switch (ras_cmd->ras_status) { 2163 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2164 dev_warn(psp->adev->dev, 2165 "RAS WARNING: cmd failed due to unsupported ip\n"); 2166 break; 2167 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2168 dev_warn(psp->adev->dev, 2169 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2170 break; 2171 case TA_RAS_STATUS__SUCCESS: 2172 break; 2173 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2174 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2175 dev_warn(psp->adev->dev, 2176 "RAS WARNING: Inject error to critical region is not allowed\n"); 2177 break; 2178 default: 2179 dev_warn(psp->adev->dev, 2180 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2181 break; 2182 } 2183 } 2184 2185 static int psp_ras_send_cmd(struct psp_context *psp, 2186 enum ras_command cmd_id, void *in, void *out) 2187 { 2188 struct ta_ras_shared_memory *ras_cmd; 2189 uint32_t cmd = cmd_id; 2190 int ret = 0; 2191 2192 if (!in) 2193 return -EINVAL; 2194 2195 mutex_lock(&psp->ras_context.mutex); 2196 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2197 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2198 2199 switch (cmd) { 2200 case TA_RAS_COMMAND__ENABLE_FEATURES: 2201 case TA_RAS_COMMAND__DISABLE_FEATURES: 2202 memcpy(&ras_cmd->ras_in_message, 2203 in, sizeof(ras_cmd->ras_in_message)); 2204 break; 2205 case TA_RAS_COMMAND__TRIGGER_ERROR: 2206 memcpy(&ras_cmd->ras_in_message.trigger_error, 2207 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2208 break; 2209 case TA_RAS_COMMAND__QUERY_ADDRESS: 2210 memcpy(&ras_cmd->ras_in_message.address, 2211 in, sizeof(ras_cmd->ras_in_message.address)); 2212 break; 2213 default: 2214 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2215 ret = -EINVAL; 2216 goto err_out; 2217 } 2218 2219 ras_cmd->cmd_id = cmd; 2220 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2221 2222 switch (cmd) { 2223 case TA_RAS_COMMAND__TRIGGER_ERROR: 2224 if (!ret && out) 2225 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2226 break; 2227 case TA_RAS_COMMAND__QUERY_ADDRESS: 2228 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2229 ret = -EINVAL; 2230 else if (out) 2231 memcpy(out, 2232 &ras_cmd->ras_out_message.address, 2233 sizeof(ras_cmd->ras_out_message.address)); 2234 break; 2235 default: 2236 break; 2237 } 2238 2239 err_out: 2240 mutex_unlock(&psp->ras_context.mutex); 2241 2242 return ret; 2243 } 2244 2245 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2246 { 2247 struct ta_ras_shared_memory *ras_cmd; 2248 int ret; 2249 2250 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2251 2252 /* 2253 * TODO: bypass the loading in sriov for now 2254 */ 2255 if (amdgpu_sriov_vf(psp->adev)) 2256 return 0; 2257 2258 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2259 2260 if (amdgpu_ras_intr_triggered()) 2261 return ret; 2262 2263 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2264 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2265 return -EINVAL; 2266 } 2267 2268 if (!ret) { 2269 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2270 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2271 2272 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2273 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2274 dev_warn(psp->adev->dev, 2275 "RAS internal register access blocked\n"); 2276 2277 psp_ras_ta_check_status(psp); 2278 } 2279 2280 return ret; 2281 } 2282 2283 int psp_ras_enable_features(struct psp_context *psp, 2284 union ta_ras_cmd_input *info, bool enable) 2285 { 2286 enum ras_command cmd_id; 2287 int ret; 2288 2289 if (!psp->ras_context.context.initialized || !info) 2290 return -EINVAL; 2291 2292 cmd_id = enable ? 2293 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2294 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2295 if (ret) 2296 return -EINVAL; 2297 2298 return 0; 2299 } 2300 2301 int psp_ras_terminate(struct psp_context *psp) 2302 { 2303 int ret; 2304 2305 /* 2306 * TODO: bypass the terminate in sriov for now 2307 */ 2308 if (amdgpu_sriov_vf(psp->adev)) 2309 return 0; 2310 2311 if (!psp->ras_context.context.initialized) 2312 return 0; 2313 2314 ret = psp_ta_unload(psp, &psp->ras_context.context); 2315 2316 psp->ras_context.context.initialized = false; 2317 2318 mutex_destroy(&psp->ras_context.mutex); 2319 2320 return ret; 2321 } 2322 2323 int psp_ras_initialize(struct psp_context *psp) 2324 { 2325 int ret; 2326 uint32_t boot_cfg = 0xFF; 2327 struct amdgpu_device *adev = psp->adev; 2328 struct ta_ras_shared_memory *ras_cmd; 2329 2330 /* 2331 * TODO: bypass the initialize in sriov for now 2332 */ 2333 if (amdgpu_sriov_vf(adev)) 2334 return 0; 2335 2336 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2337 !adev->psp.ras_context.context.bin_desc.start_addr) { 2338 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2339 return 0; 2340 } 2341 2342 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2343 /* query GECC enablement status from boot config 2344 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2345 */ 2346 ret = psp_boot_config_get(adev, &boot_cfg); 2347 if (ret) 2348 dev_warn(adev->dev, "PSP get boot config failed\n"); 2349 2350 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2351 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2352 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2353 dev_warn(adev->dev, 2354 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2355 } else { 2356 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2357 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2358 if (boot_cfg == 1) { 2359 dev_info(adev->dev, "GECC is enabled\n"); 2360 } else { 2361 /* enable GECC in next boot cycle if it is disabled 2362 * in boot config, or force enable GECC if failed to 2363 * get boot configuration 2364 */ 2365 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2366 if (ret) 2367 dev_warn(adev->dev, "PSP set boot config failed\n"); 2368 else 2369 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2370 } 2371 } else { 2372 if (!boot_cfg) { 2373 if (!adev->ras_default_ecc_enabled && 2374 amdgpu_ras_enable != 1 && 2375 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2376 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2377 else 2378 dev_info(adev->dev, "GECC is disabled\n"); 2379 } else { 2380 /* disable GECC in next boot cycle if ras is 2381 * disabled by module parameter amdgpu_ras_enable 2382 * and/or amdgpu_ras_mask, or boot_config_get call 2383 * is failed 2384 */ 2385 ret = psp_boot_config_set(adev, 0); 2386 if (ret) 2387 dev_warn(adev->dev, "PSP set boot config failed\n"); 2388 else 2389 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2390 } 2391 } 2392 } 2393 } 2394 2395 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2396 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2397 2398 if (!psp->ras_context.context.mem_context.shared_buf) { 2399 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2400 if (ret) 2401 return ret; 2402 } 2403 2404 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2405 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2406 2407 if (amdgpu_ras_is_poison_mode_supported(adev)) 2408 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2409 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2410 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2411 ras_cmd->ras_in_message.init_flags.xcc_mask = 2412 adev->gfx.xcc_mask; 2413 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2414 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2415 ras_cmd->ras_in_message.init_flags.nps_mode = 2416 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2417 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2418 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2419 2420 ret = psp_ta_load(psp, &psp->ras_context.context); 2421 2422 if (!ret && !ras_cmd->ras_status) { 2423 psp->ras_context.context.initialized = true; 2424 mutex_init(&psp->ras_context.mutex); 2425 } else { 2426 if (ras_cmd->ras_status) 2427 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2428 2429 /* fail to load RAS TA */ 2430 psp->ras_context.context.initialized = false; 2431 } 2432 2433 return ret; 2434 } 2435 2436 int psp_ras_trigger_error(struct psp_context *psp, 2437 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2438 { 2439 struct amdgpu_device *adev = psp->adev; 2440 int ret; 2441 uint32_t dev_mask; 2442 uint32_t ras_status = 0; 2443 2444 if (!psp->ras_context.context.initialized || !info) 2445 return -EINVAL; 2446 2447 switch (info->block_id) { 2448 case TA_RAS_BLOCK__GFX: 2449 dev_mask = GET_MASK(GC, instance_mask); 2450 break; 2451 case TA_RAS_BLOCK__SDMA: 2452 dev_mask = GET_MASK(SDMA0, instance_mask); 2453 break; 2454 case TA_RAS_BLOCK__VCN: 2455 case TA_RAS_BLOCK__JPEG: 2456 dev_mask = GET_MASK(VCN, instance_mask); 2457 break; 2458 default: 2459 dev_mask = instance_mask; 2460 break; 2461 } 2462 2463 /* reuse sub_block_index for backward compatibility */ 2464 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2465 dev_mask &= AMDGPU_RAS_INST_MASK; 2466 info->sub_block_index |= dev_mask; 2467 2468 ret = psp_ras_send_cmd(psp, 2469 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2470 if (ret) 2471 return -EINVAL; 2472 2473 /* If err_event_athub occurs error inject was successful, however 2474 * return status from TA is no long reliable 2475 */ 2476 if (amdgpu_ras_intr_triggered()) 2477 return 0; 2478 2479 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2480 return -EACCES; 2481 else if (ras_status) 2482 return -EINVAL; 2483 2484 return 0; 2485 } 2486 2487 int psp_ras_query_address(struct psp_context *psp, 2488 struct ta_ras_query_address_input *addr_in, 2489 struct ta_ras_query_address_output *addr_out) 2490 { 2491 int ret; 2492 2493 if (!psp->ras_context.context.initialized || 2494 !addr_in || !addr_out) 2495 return -EINVAL; 2496 2497 ret = psp_ras_send_cmd(psp, 2498 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2499 2500 return ret; 2501 } 2502 // ras end 2503 2504 // HDCP start 2505 static int psp_hdcp_initialize(struct psp_context *psp) 2506 { 2507 int ret; 2508 2509 /* 2510 * TODO: bypass the initialize in sriov for now 2511 */ 2512 if (amdgpu_sriov_vf(psp->adev)) 2513 return 0; 2514 2515 /* bypass hdcp initialization if dmu is harvested */ 2516 if (!amdgpu_device_has_display_hardware(psp->adev)) 2517 return 0; 2518 2519 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2520 !psp->hdcp_context.context.bin_desc.start_addr) { 2521 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2522 return 0; 2523 } 2524 2525 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2526 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2527 2528 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2529 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2530 if (ret) 2531 return ret; 2532 } 2533 2534 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2535 if (!ret) { 2536 psp->hdcp_context.context.initialized = true; 2537 mutex_init(&psp->hdcp_context.mutex); 2538 } 2539 2540 return ret; 2541 } 2542 2543 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2544 { 2545 /* 2546 * TODO: bypass the loading in sriov for now 2547 */ 2548 if (amdgpu_sriov_vf(psp->adev)) 2549 return 0; 2550 2551 if (!psp->hdcp_context.context.initialized) 2552 return 0; 2553 2554 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2555 } 2556 2557 static int psp_hdcp_terminate(struct psp_context *psp) 2558 { 2559 int ret; 2560 2561 /* 2562 * TODO: bypass the terminate in sriov for now 2563 */ 2564 if (amdgpu_sriov_vf(psp->adev)) 2565 return 0; 2566 2567 if (!psp->hdcp_context.context.initialized) 2568 return 0; 2569 2570 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2571 2572 psp->hdcp_context.context.initialized = false; 2573 2574 return ret; 2575 } 2576 // HDCP end 2577 2578 // DTM start 2579 static int psp_dtm_initialize(struct psp_context *psp) 2580 { 2581 int ret; 2582 2583 /* 2584 * TODO: bypass the initialize in sriov for now 2585 */ 2586 if (amdgpu_sriov_vf(psp->adev)) 2587 return 0; 2588 2589 /* bypass dtm initialization if dmu is harvested */ 2590 if (!amdgpu_device_has_display_hardware(psp->adev)) 2591 return 0; 2592 2593 if (!psp->dtm_context.context.bin_desc.size_bytes || 2594 !psp->dtm_context.context.bin_desc.start_addr) { 2595 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2596 return 0; 2597 } 2598 2599 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2600 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2601 2602 if (!psp->dtm_context.context.mem_context.shared_buf) { 2603 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2604 if (ret) 2605 return ret; 2606 } 2607 2608 ret = psp_ta_load(psp, &psp->dtm_context.context); 2609 if (!ret) { 2610 psp->dtm_context.context.initialized = true; 2611 mutex_init(&psp->dtm_context.mutex); 2612 } 2613 2614 return ret; 2615 } 2616 2617 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2618 { 2619 /* 2620 * TODO: bypass the loading in sriov for now 2621 */ 2622 if (amdgpu_sriov_vf(psp->adev)) 2623 return 0; 2624 2625 if (!psp->dtm_context.context.initialized) 2626 return 0; 2627 2628 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2629 } 2630 2631 static int psp_dtm_terminate(struct psp_context *psp) 2632 { 2633 int ret; 2634 2635 /* 2636 * TODO: bypass the terminate in sriov for now 2637 */ 2638 if (amdgpu_sriov_vf(psp->adev)) 2639 return 0; 2640 2641 if (!psp->dtm_context.context.initialized) 2642 return 0; 2643 2644 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2645 2646 psp->dtm_context.context.initialized = false; 2647 2648 return ret; 2649 } 2650 // DTM end 2651 2652 // RAP start 2653 static int psp_rap_initialize(struct psp_context *psp) 2654 { 2655 int ret; 2656 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2657 2658 /* 2659 * TODO: bypass the initialize in sriov for now 2660 */ 2661 if (amdgpu_sriov_vf(psp->adev)) 2662 return 0; 2663 2664 if (!psp->rap_context.context.bin_desc.size_bytes || 2665 !psp->rap_context.context.bin_desc.start_addr) { 2666 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2667 return 0; 2668 } 2669 2670 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2671 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2672 2673 if (!psp->rap_context.context.mem_context.shared_buf) { 2674 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2675 if (ret) 2676 return ret; 2677 } 2678 2679 ret = psp_ta_load(psp, &psp->rap_context.context); 2680 if (!ret) { 2681 psp->rap_context.context.initialized = true; 2682 mutex_init(&psp->rap_context.mutex); 2683 } else 2684 return ret; 2685 2686 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2687 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2688 psp_rap_terminate(psp); 2689 /* free rap shared memory */ 2690 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2691 2692 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2693 ret, status); 2694 2695 return ret; 2696 } 2697 2698 return 0; 2699 } 2700 2701 static int psp_rap_terminate(struct psp_context *psp) 2702 { 2703 int ret; 2704 2705 if (!psp->rap_context.context.initialized) 2706 return 0; 2707 2708 ret = psp_ta_unload(psp, &psp->rap_context.context); 2709 2710 psp->rap_context.context.initialized = false; 2711 2712 return ret; 2713 } 2714 2715 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2716 { 2717 struct ta_rap_shared_memory *rap_cmd; 2718 int ret = 0; 2719 2720 if (!psp->rap_context.context.initialized) 2721 return 0; 2722 2723 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2724 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2725 return -EINVAL; 2726 2727 mutex_lock(&psp->rap_context.mutex); 2728 2729 rap_cmd = (struct ta_rap_shared_memory *) 2730 psp->rap_context.context.mem_context.shared_buf; 2731 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2732 2733 rap_cmd->cmd_id = ta_cmd_id; 2734 rap_cmd->validation_method_id = METHOD_A; 2735 2736 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2737 if (ret) 2738 goto out_unlock; 2739 2740 if (status) 2741 *status = rap_cmd->rap_status; 2742 2743 out_unlock: 2744 mutex_unlock(&psp->rap_context.mutex); 2745 2746 return ret; 2747 } 2748 // RAP end 2749 2750 /* securedisplay start */ 2751 static int psp_securedisplay_initialize(struct psp_context *psp) 2752 { 2753 int ret; 2754 struct ta_securedisplay_cmd *securedisplay_cmd; 2755 2756 /* 2757 * TODO: bypass the initialize in sriov for now 2758 */ 2759 if (amdgpu_sriov_vf(psp->adev)) 2760 return 0; 2761 2762 /* bypass securedisplay initialization if dmu is harvested */ 2763 if (!amdgpu_device_has_display_hardware(psp->adev)) 2764 return 0; 2765 2766 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2767 !psp->securedisplay_context.context.bin_desc.start_addr) { 2768 dev_info(psp->adev->dev, 2769 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2770 return 0; 2771 } 2772 2773 psp->securedisplay_context.context.mem_context.shared_mem_size = 2774 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2775 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2776 2777 if (!psp->securedisplay_context.context.initialized) { 2778 ret = psp_ta_init_shared_buf(psp, 2779 &psp->securedisplay_context.context.mem_context); 2780 if (ret) 2781 return ret; 2782 } 2783 2784 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2785 if (!ret && !psp->securedisplay_context.context.resp_status) { 2786 psp->securedisplay_context.context.initialized = true; 2787 mutex_init(&psp->securedisplay_context.mutex); 2788 } else { 2789 /* don't try again */ 2790 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2791 return ret; 2792 } 2793 2794 mutex_lock(&psp->securedisplay_context.mutex); 2795 2796 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2797 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2798 2799 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2800 2801 mutex_unlock(&psp->securedisplay_context.mutex); 2802 2803 if (ret) { 2804 psp_securedisplay_terminate(psp); 2805 /* free securedisplay shared memory */ 2806 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2807 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2808 return -EINVAL; 2809 } 2810 2811 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2812 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2813 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2814 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2815 /* don't try again */ 2816 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static int psp_securedisplay_terminate(struct psp_context *psp) 2823 { 2824 int ret; 2825 2826 /* 2827 * TODO:bypass the terminate in sriov for now 2828 */ 2829 if (amdgpu_sriov_vf(psp->adev)) 2830 return 0; 2831 2832 if (!psp->securedisplay_context.context.initialized) 2833 return 0; 2834 2835 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2836 2837 psp->securedisplay_context.context.initialized = false; 2838 2839 return ret; 2840 } 2841 2842 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2843 { 2844 int ret; 2845 2846 if (!psp->securedisplay_context.context.initialized) 2847 return -EINVAL; 2848 2849 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2850 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2851 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2852 return -EINVAL; 2853 2854 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2855 2856 return ret; 2857 } 2858 /* SECUREDISPLAY end */ 2859 2860 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2861 { 2862 struct psp_context *psp = &adev->psp; 2863 int ret = 0; 2864 2865 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2866 ret = psp->funcs->wait_for_bootloader(psp); 2867 2868 return ret; 2869 } 2870 2871 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2872 { 2873 if (psp->funcs && 2874 psp->funcs->get_ras_capability) { 2875 return psp->funcs->get_ras_capability(psp); 2876 } else { 2877 return false; 2878 } 2879 } 2880 2881 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2882 { 2883 struct psp_context *psp = &adev->psp; 2884 2885 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2886 return false; 2887 2888 if (psp->funcs && psp->funcs->is_reload_needed) 2889 return psp->funcs->is_reload_needed(psp); 2890 2891 return false; 2892 } 2893 2894 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2895 { 2896 struct psp_context *psp = &adev->psp; 2897 2898 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2899 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2900 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2901 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2902 } 2903 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2904 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2905 } 2906 2907 static int psp_hw_start(struct psp_context *psp) 2908 { 2909 struct amdgpu_device *adev = psp->adev; 2910 int ret; 2911 2912 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2913 psp_update_gpu_addresses(adev); 2914 2915 if (!amdgpu_sriov_vf(adev)) { 2916 if ((is_psp_fw_valid(psp->kdb)) && 2917 (psp->funcs->bootloader_load_kdb != NULL)) { 2918 ret = psp_bootloader_load_kdb(psp); 2919 if (ret) { 2920 dev_err(adev->dev, "PSP load kdb failed!\n"); 2921 return ret; 2922 } 2923 } 2924 2925 if ((is_psp_fw_valid(psp->spl)) && 2926 (psp->funcs->bootloader_load_spl != NULL)) { 2927 ret = psp_bootloader_load_spl(psp); 2928 if (ret) { 2929 dev_err(adev->dev, "PSP load spl failed!\n"); 2930 return ret; 2931 } 2932 } 2933 2934 if ((is_psp_fw_valid(psp->sys)) && 2935 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2936 ret = psp_bootloader_load_sysdrv(psp); 2937 if (ret) { 2938 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2939 return ret; 2940 } 2941 } 2942 2943 if ((is_psp_fw_valid(psp->soc_drv)) && 2944 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2945 ret = psp_bootloader_load_soc_drv(psp); 2946 if (ret) { 2947 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2948 return ret; 2949 } 2950 } 2951 2952 if ((is_psp_fw_valid(psp->intf_drv)) && 2953 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2954 ret = psp_bootloader_load_intf_drv(psp); 2955 if (ret) { 2956 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2957 return ret; 2958 } 2959 } 2960 2961 if ((is_psp_fw_valid(psp->dbg_drv)) && 2962 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2963 ret = psp_bootloader_load_dbg_drv(psp); 2964 if (ret) { 2965 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2966 return ret; 2967 } 2968 } 2969 2970 if ((is_psp_fw_valid(psp->ras_drv)) && 2971 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2972 ret = psp_bootloader_load_ras_drv(psp); 2973 if (ret) { 2974 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2975 return ret; 2976 } 2977 } 2978 2979 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2980 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2981 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2982 if (ret) { 2983 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2984 return ret; 2985 } 2986 } 2987 2988 if ((is_psp_fw_valid(psp->spdm_drv)) && 2989 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2990 ret = psp_bootloader_load_spdm_drv(psp); 2991 if (ret) { 2992 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2993 return ret; 2994 } 2995 } 2996 2997 if ((is_psp_fw_valid(psp->sos)) && 2998 (psp->funcs->bootloader_load_sos != NULL)) { 2999 ret = psp_bootloader_load_sos(psp); 3000 if (ret) { 3001 dev_err(adev->dev, "PSP load sos failed!\n"); 3002 return ret; 3003 } 3004 } 3005 } 3006 3007 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 3008 if (ret) { 3009 dev_err(adev->dev, "PSP create ring failed!\n"); 3010 return ret; 3011 } 3012 3013 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3014 ret = psp_update_fw_reservation(psp); 3015 if (ret) { 3016 dev_err(adev->dev, "update fw reservation failed!\n"); 3017 return ret; 3018 } 3019 } 3020 3021 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 3022 goto skip_pin_bo; 3023 3024 if (!psp->boot_time_tmr || psp->autoload_supported) { 3025 ret = psp_tmr_init(psp); 3026 if (ret) { 3027 dev_err(adev->dev, "PSP tmr init failed!\n"); 3028 return ret; 3029 } 3030 } 3031 3032 skip_pin_bo: 3033 /* 3034 * For ASICs with DF Cstate management centralized 3035 * to PMFW, TMR setup should be performed after PMFW 3036 * loaded and before other non-psp firmware loaded. 3037 */ 3038 if (psp->pmfw_centralized_cstate_management) { 3039 ret = psp_load_smu_fw(psp); 3040 if (ret) 3041 return ret; 3042 } 3043 3044 ret = psp_tmr_load(psp); 3045 if (ret) { 3046 dev_err(adev->dev, "PSP load tmr failed!\n"); 3047 return ret; 3048 } 3049 3050 return 0; 3051 } 3052 3053 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3054 enum psp_gfx_fw_type *type) 3055 { 3056 switch (ucode->ucode_id) { 3057 case AMDGPU_UCODE_ID_CAP: 3058 *type = GFX_FW_TYPE_CAP; 3059 break; 3060 case AMDGPU_UCODE_ID_SDMA0: 3061 *type = GFX_FW_TYPE_SDMA0; 3062 break; 3063 case AMDGPU_UCODE_ID_SDMA1: 3064 *type = GFX_FW_TYPE_SDMA1; 3065 break; 3066 case AMDGPU_UCODE_ID_SDMA2: 3067 *type = GFX_FW_TYPE_SDMA2; 3068 break; 3069 case AMDGPU_UCODE_ID_SDMA3: 3070 *type = GFX_FW_TYPE_SDMA3; 3071 break; 3072 case AMDGPU_UCODE_ID_SDMA4: 3073 *type = GFX_FW_TYPE_SDMA4; 3074 break; 3075 case AMDGPU_UCODE_ID_SDMA5: 3076 *type = GFX_FW_TYPE_SDMA5; 3077 break; 3078 case AMDGPU_UCODE_ID_SDMA6: 3079 *type = GFX_FW_TYPE_SDMA6; 3080 break; 3081 case AMDGPU_UCODE_ID_SDMA7: 3082 *type = GFX_FW_TYPE_SDMA7; 3083 break; 3084 case AMDGPU_UCODE_ID_CP_MES: 3085 *type = GFX_FW_TYPE_CP_MES; 3086 break; 3087 case AMDGPU_UCODE_ID_CP_MES_DATA: 3088 *type = GFX_FW_TYPE_MES_STACK; 3089 break; 3090 case AMDGPU_UCODE_ID_CP_MES1: 3091 *type = GFX_FW_TYPE_CP_MES_KIQ; 3092 break; 3093 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3094 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3095 break; 3096 case AMDGPU_UCODE_ID_CP_CE: 3097 *type = GFX_FW_TYPE_CP_CE; 3098 break; 3099 case AMDGPU_UCODE_ID_CP_PFP: 3100 *type = GFX_FW_TYPE_CP_PFP; 3101 break; 3102 case AMDGPU_UCODE_ID_CP_ME: 3103 *type = GFX_FW_TYPE_CP_ME; 3104 break; 3105 case AMDGPU_UCODE_ID_CP_MEC1: 3106 *type = GFX_FW_TYPE_CP_MEC; 3107 break; 3108 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3109 *type = GFX_FW_TYPE_CP_MEC_ME1; 3110 break; 3111 case AMDGPU_UCODE_ID_CP_MEC2: 3112 *type = GFX_FW_TYPE_CP_MEC; 3113 break; 3114 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3115 *type = GFX_FW_TYPE_CP_MEC_ME2; 3116 break; 3117 case AMDGPU_UCODE_ID_RLC_P: 3118 *type = GFX_FW_TYPE_RLC_P; 3119 break; 3120 case AMDGPU_UCODE_ID_RLC_V: 3121 *type = GFX_FW_TYPE_RLC_V; 3122 break; 3123 case AMDGPU_UCODE_ID_RLC_G: 3124 *type = GFX_FW_TYPE_RLC_G; 3125 break; 3126 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3127 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3128 break; 3129 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3130 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3131 break; 3132 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3133 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3134 break; 3135 case AMDGPU_UCODE_ID_RLC_IRAM: 3136 *type = GFX_FW_TYPE_RLC_IRAM; 3137 break; 3138 case AMDGPU_UCODE_ID_RLC_DRAM: 3139 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3140 break; 3141 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3142 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3143 break; 3144 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3145 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3146 break; 3147 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3148 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3149 break; 3150 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3151 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3152 break; 3153 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3154 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3155 break; 3156 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3157 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3158 break; 3159 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3160 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3161 break; 3162 case AMDGPU_UCODE_ID_SMC: 3163 *type = GFX_FW_TYPE_SMU; 3164 break; 3165 case AMDGPU_UCODE_ID_PPTABLE: 3166 *type = GFX_FW_TYPE_PPTABLE; 3167 break; 3168 case AMDGPU_UCODE_ID_UVD: 3169 *type = GFX_FW_TYPE_UVD; 3170 break; 3171 case AMDGPU_UCODE_ID_UVD1: 3172 *type = GFX_FW_TYPE_UVD1; 3173 break; 3174 case AMDGPU_UCODE_ID_VCE: 3175 *type = GFX_FW_TYPE_VCE; 3176 break; 3177 case AMDGPU_UCODE_ID_VCN: 3178 *type = GFX_FW_TYPE_VCN; 3179 break; 3180 case AMDGPU_UCODE_ID_VCN1: 3181 *type = GFX_FW_TYPE_VCN1; 3182 break; 3183 case AMDGPU_UCODE_ID_DMCU_ERAM: 3184 *type = GFX_FW_TYPE_DMCU_ERAM; 3185 break; 3186 case AMDGPU_UCODE_ID_DMCU_INTV: 3187 *type = GFX_FW_TYPE_DMCU_ISR; 3188 break; 3189 case AMDGPU_UCODE_ID_VCN0_RAM: 3190 *type = GFX_FW_TYPE_VCN0_RAM; 3191 break; 3192 case AMDGPU_UCODE_ID_VCN1_RAM: 3193 *type = GFX_FW_TYPE_VCN1_RAM; 3194 break; 3195 case AMDGPU_UCODE_ID_DMCUB: 3196 *type = GFX_FW_TYPE_DMUB; 3197 break; 3198 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3199 case AMDGPU_UCODE_ID_SDMA_RS64: 3200 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3201 break; 3202 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3203 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3204 break; 3205 case AMDGPU_UCODE_ID_IMU_I: 3206 *type = GFX_FW_TYPE_IMU_I; 3207 break; 3208 case AMDGPU_UCODE_ID_IMU_D: 3209 *type = GFX_FW_TYPE_IMU_D; 3210 break; 3211 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3212 *type = GFX_FW_TYPE_RS64_PFP; 3213 break; 3214 case AMDGPU_UCODE_ID_CP_RS64_ME: 3215 *type = GFX_FW_TYPE_RS64_ME; 3216 break; 3217 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3218 *type = GFX_FW_TYPE_RS64_MEC; 3219 break; 3220 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3221 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3222 break; 3223 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3224 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3225 break; 3226 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3227 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3228 break; 3229 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3230 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3231 break; 3232 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3233 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3234 break; 3235 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3236 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3237 break; 3238 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3239 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3240 break; 3241 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3242 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3243 break; 3244 case AMDGPU_UCODE_ID_VPE_CTX: 3245 *type = GFX_FW_TYPE_VPEC_FW1; 3246 break; 3247 case AMDGPU_UCODE_ID_VPE_CTL: 3248 *type = GFX_FW_TYPE_VPEC_FW2; 3249 break; 3250 case AMDGPU_UCODE_ID_VPE: 3251 *type = GFX_FW_TYPE_VPE; 3252 break; 3253 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3254 *type = GFX_FW_TYPE_UMSCH_UCODE; 3255 break; 3256 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3257 *type = GFX_FW_TYPE_UMSCH_DATA; 3258 break; 3259 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3260 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3261 break; 3262 case AMDGPU_UCODE_ID_P2S_TABLE: 3263 *type = GFX_FW_TYPE_P2S_TABLE; 3264 break; 3265 case AMDGPU_UCODE_ID_JPEG_RAM: 3266 *type = GFX_FW_TYPE_JPEG_RAM; 3267 break; 3268 case AMDGPU_UCODE_ID_ISP: 3269 *type = GFX_FW_TYPE_ISP; 3270 break; 3271 case AMDGPU_UCODE_ID_MAXIMUM: 3272 default: 3273 return -EINVAL; 3274 } 3275 3276 return 0; 3277 } 3278 3279 static void psp_print_fw_hdr(struct psp_context *psp, 3280 struct amdgpu_firmware_info *ucode) 3281 { 3282 struct amdgpu_device *adev = psp->adev; 3283 struct common_firmware_header *hdr; 3284 3285 switch (ucode->ucode_id) { 3286 case AMDGPU_UCODE_ID_SDMA0: 3287 case AMDGPU_UCODE_ID_SDMA1: 3288 case AMDGPU_UCODE_ID_SDMA2: 3289 case AMDGPU_UCODE_ID_SDMA3: 3290 case AMDGPU_UCODE_ID_SDMA4: 3291 case AMDGPU_UCODE_ID_SDMA5: 3292 case AMDGPU_UCODE_ID_SDMA6: 3293 case AMDGPU_UCODE_ID_SDMA7: 3294 hdr = (struct common_firmware_header *) 3295 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3296 amdgpu_ucode_print_sdma_hdr(hdr); 3297 break; 3298 case AMDGPU_UCODE_ID_CP_CE: 3299 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3300 amdgpu_ucode_print_gfx_hdr(hdr); 3301 break; 3302 case AMDGPU_UCODE_ID_CP_PFP: 3303 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3304 amdgpu_ucode_print_gfx_hdr(hdr); 3305 break; 3306 case AMDGPU_UCODE_ID_CP_ME: 3307 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3308 amdgpu_ucode_print_gfx_hdr(hdr); 3309 break; 3310 case AMDGPU_UCODE_ID_CP_MEC1: 3311 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3312 amdgpu_ucode_print_gfx_hdr(hdr); 3313 break; 3314 case AMDGPU_UCODE_ID_RLC_G: 3315 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3316 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3317 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3318 amdgpu_ucode_print_rlc_hdr(hdr); 3319 break; 3320 case AMDGPU_UCODE_ID_SMC: 3321 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3322 amdgpu_ucode_print_smc_hdr(hdr); 3323 break; 3324 default: 3325 break; 3326 } 3327 } 3328 3329 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3330 struct amdgpu_firmware_info *ucode, 3331 struct psp_gfx_cmd_resp *cmd) 3332 { 3333 int ret; 3334 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3335 3336 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3337 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3338 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3339 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3340 3341 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3342 if (ret) 3343 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3344 return ret; 3345 } 3346 3347 int psp_execute_ip_fw_load(struct psp_context *psp, 3348 struct amdgpu_firmware_info *ucode) 3349 { 3350 int ret = 0; 3351 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3352 3353 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3354 if (!ret) { 3355 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3356 psp->fence_buf_mc_addr); 3357 } 3358 3359 release_psp_cmd_buf(psp); 3360 3361 return ret; 3362 } 3363 3364 static int psp_load_p2s_table(struct psp_context *psp) 3365 { 3366 int ret; 3367 struct amdgpu_device *adev = psp->adev; 3368 struct amdgpu_firmware_info *ucode = 3369 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3370 3371 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3372 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3373 return 0; 3374 3375 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3376 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3377 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3378 0x0036003C; 3379 if (psp->sos.fw_version < supp_vers) 3380 return 0; 3381 } 3382 3383 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3384 return 0; 3385 3386 ret = psp_execute_ip_fw_load(psp, ucode); 3387 3388 return ret; 3389 } 3390 3391 static int psp_load_smu_fw(struct psp_context *psp) 3392 { 3393 int ret; 3394 struct amdgpu_device *adev = psp->adev; 3395 struct amdgpu_firmware_info *ucode = 3396 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3397 struct amdgpu_ras *ras = psp->ras_context.ras; 3398 3399 /* 3400 * Skip SMU FW reloading in case of using BACO for runpm only, 3401 * as SMU is always alive. 3402 */ 3403 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3404 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3405 return 0; 3406 3407 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3408 return 0; 3409 3410 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3411 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3412 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3413 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3414 if (ret) 3415 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3416 } 3417 3418 ret = psp_execute_ip_fw_load(psp, ucode); 3419 3420 if (ret) 3421 dev_err(adev->dev, "PSP load smu failed!\n"); 3422 3423 return ret; 3424 } 3425 3426 static bool fw_load_skip_check(struct psp_context *psp, 3427 struct amdgpu_firmware_info *ucode) 3428 { 3429 if (!ucode->fw || !ucode->ucode_size) 3430 return true; 3431 3432 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3433 return true; 3434 3435 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3436 (psp_smu_reload_quirk(psp) || 3437 psp->autoload_supported || 3438 psp->pmfw_centralized_cstate_management)) 3439 return true; 3440 3441 if (amdgpu_sriov_vf(psp->adev) && 3442 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3443 return true; 3444 3445 if (psp->autoload_supported && 3446 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3447 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3448 /* skip mec JT when autoload is enabled */ 3449 return true; 3450 3451 return false; 3452 } 3453 3454 int psp_load_fw_list(struct psp_context *psp, 3455 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3456 { 3457 int ret = 0, i; 3458 struct amdgpu_firmware_info *ucode; 3459 3460 for (i = 0; i < ucode_count; ++i) { 3461 ucode = ucode_list[i]; 3462 psp_print_fw_hdr(psp, ucode); 3463 ret = psp_execute_ip_fw_load(psp, ucode); 3464 if (ret) 3465 return ret; 3466 } 3467 return ret; 3468 } 3469 3470 static int psp_load_non_psp_fw(struct psp_context *psp) 3471 { 3472 int i, ret; 3473 struct amdgpu_firmware_info *ucode; 3474 struct amdgpu_device *adev = psp->adev; 3475 3476 if (psp->autoload_supported && 3477 !psp->pmfw_centralized_cstate_management) { 3478 ret = psp_load_smu_fw(psp); 3479 if (ret) 3480 return ret; 3481 } 3482 3483 /* Load P2S table first if it's available */ 3484 psp_load_p2s_table(psp); 3485 3486 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3487 ucode = &adev->firmware.ucode[i]; 3488 3489 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3490 !fw_load_skip_check(psp, ucode)) { 3491 ret = psp_load_smu_fw(psp); 3492 if (ret) 3493 return ret; 3494 continue; 3495 } 3496 3497 if (fw_load_skip_check(psp, ucode)) 3498 continue; 3499 3500 if (psp->autoload_supported && 3501 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3502 IP_VERSION(11, 0, 7) || 3503 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3504 IP_VERSION(11, 0, 11) || 3505 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3506 IP_VERSION(11, 0, 12) || 3507 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3508 IP_VERSION(15, 0, 0) || 3509 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3510 IP_VERSION(15, 0, 8) || 3511 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3512 IP_VERSION(15, 0, 9)) && 3513 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3514 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3515 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3516 /* PSP only receive one SDMA fw for sienna_cichlid, 3517 * as all four sdma fw are same 3518 */ 3519 continue; 3520 3521 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3522 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3523 IP_VERSION(15, 0, 8) && 3524 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3525 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3526 continue; 3527 3528 psp_print_fw_hdr(psp, ucode); 3529 3530 ret = psp_execute_ip_fw_load(psp, ucode); 3531 if (ret) 3532 return ret; 3533 3534 /* Start rlc autoload after psp received all the gfx firmware */ 3535 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3536 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3537 ret = psp_rlc_autoload_start(psp); 3538 if (ret) { 3539 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3540 return ret; 3541 } 3542 } 3543 } 3544 3545 return 0; 3546 } 3547 3548 static int psp_load_fw(struct amdgpu_device *adev) 3549 { 3550 int ret; 3551 struct psp_context *psp = &adev->psp; 3552 3553 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3554 /* should not destroy ring, only stop */ 3555 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3556 } else { 3557 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3558 3559 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3560 if (ret) { 3561 dev_err(adev->dev, "PSP ring init failed!\n"); 3562 goto failed; 3563 } 3564 } 3565 3566 ret = psp_hw_start(psp); 3567 if (ret) 3568 goto failed; 3569 3570 ret = psp_load_non_psp_fw(psp); 3571 if (ret) 3572 goto failed1; 3573 3574 ret = psp_asd_initialize(psp); 3575 if (ret) { 3576 dev_err(adev->dev, "PSP load asd failed!\n"); 3577 goto failed1; 3578 } 3579 3580 ret = psp_rl_load(adev); 3581 if (ret) { 3582 dev_err(adev->dev, "PSP load RL failed!\n"); 3583 goto failed1; 3584 } 3585 3586 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3587 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3588 ret = psp_xgmi_initialize(psp, false, true); 3589 /* Warning the XGMI seesion initialize failure 3590 * Instead of stop driver initialization 3591 */ 3592 if (ret) 3593 dev_err(psp->adev->dev, 3594 "XGMI: Failed to initialize XGMI session\n"); 3595 } 3596 } 3597 3598 if (psp->ta_fw) { 3599 ret = psp_ras_initialize(psp); 3600 if (ret) 3601 dev_err(psp->adev->dev, 3602 "RAS: Failed to initialize RAS\n"); 3603 3604 ret = psp_hdcp_initialize(psp); 3605 if (ret) 3606 dev_err(psp->adev->dev, 3607 "HDCP: Failed to initialize HDCP\n"); 3608 3609 ret = psp_dtm_initialize(psp); 3610 if (ret) 3611 dev_err(psp->adev->dev, 3612 "DTM: Failed to initialize DTM\n"); 3613 3614 ret = psp_rap_initialize(psp); 3615 if (ret) 3616 dev_err(psp->adev->dev, 3617 "RAP: Failed to initialize RAP\n"); 3618 3619 ret = psp_securedisplay_initialize(psp); 3620 if (ret) 3621 dev_err(psp->adev->dev, 3622 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3623 } 3624 3625 return 0; 3626 3627 failed1: 3628 psp_free_shared_bufs(psp); 3629 failed: 3630 /* 3631 * all cleanup jobs (xgmi terminate, ras terminate, 3632 * ring destroy, cmd/fence/fw buffers destory, 3633 * psp->cmd destory) are delayed to psp_hw_fini 3634 */ 3635 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3636 return ret; 3637 } 3638 3639 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3640 { 3641 int ret; 3642 struct amdgpu_device *adev = ip_block->adev; 3643 3644 mutex_lock(&adev->firmware.mutex); 3645 3646 ret = amdgpu_ucode_init_bo(adev); 3647 if (ret) 3648 goto failed; 3649 3650 ret = psp_load_fw(adev); 3651 if (ret) { 3652 dev_err(adev->dev, "PSP firmware loading failed\n"); 3653 goto failed; 3654 } 3655 3656 mutex_unlock(&adev->firmware.mutex); 3657 return 0; 3658 3659 failed: 3660 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3661 mutex_unlock(&adev->firmware.mutex); 3662 return -EINVAL; 3663 } 3664 3665 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3666 { 3667 struct amdgpu_device *adev = ip_block->adev; 3668 struct psp_context *psp = &adev->psp; 3669 3670 if (psp->ta_fw) { 3671 psp_ras_terminate(psp); 3672 psp_securedisplay_terminate(psp); 3673 psp_rap_terminate(psp); 3674 psp_dtm_terminate(psp); 3675 psp_hdcp_terminate(psp); 3676 3677 if (adev->gmc.xgmi.num_physical_nodes > 1) 3678 psp_xgmi_terminate(psp); 3679 } 3680 3681 psp_asd_terminate(psp); 3682 psp_tmr_terminate(psp); 3683 3684 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3685 3686 return 0; 3687 } 3688 3689 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3690 { 3691 int ret = 0; 3692 struct amdgpu_device *adev = ip_block->adev; 3693 struct psp_context *psp = &adev->psp; 3694 3695 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3696 psp->xgmi_context.context.initialized) { 3697 ret = psp_xgmi_terminate(psp); 3698 if (ret) { 3699 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3700 goto out; 3701 } 3702 } 3703 3704 if (psp->ta_fw) { 3705 ret = psp_ras_terminate(psp); 3706 if (ret) { 3707 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3708 goto out; 3709 } 3710 ret = psp_hdcp_terminate(psp); 3711 if (ret) { 3712 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3713 goto out; 3714 } 3715 ret = psp_dtm_terminate(psp); 3716 if (ret) { 3717 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3718 goto out; 3719 } 3720 ret = psp_rap_terminate(psp); 3721 if (ret) { 3722 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3723 goto out; 3724 } 3725 ret = psp_securedisplay_terminate(psp); 3726 if (ret) { 3727 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3728 goto out; 3729 } 3730 } 3731 3732 ret = psp_asd_terminate(psp); 3733 if (ret) { 3734 dev_err(adev->dev, "Failed to terminate asd\n"); 3735 goto out; 3736 } 3737 3738 ret = psp_tmr_terminate(psp); 3739 if (ret) { 3740 dev_err(adev->dev, "Failed to terminate tmr\n"); 3741 goto out; 3742 } 3743 3744 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3745 if (ret) 3746 dev_err(adev->dev, "PSP ring stop failed\n"); 3747 3748 out: 3749 return ret; 3750 } 3751 3752 static int psp_resume(struct amdgpu_ip_block *ip_block) 3753 { 3754 int ret; 3755 struct amdgpu_device *adev = ip_block->adev; 3756 struct psp_context *psp = &adev->psp; 3757 3758 dev_info(adev->dev, "PSP is resuming...\n"); 3759 3760 if (psp->mem_train_ctx.enable_mem_training) { 3761 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3762 if (ret) { 3763 dev_err(adev->dev, "Failed to process memory training!\n"); 3764 return ret; 3765 } 3766 } 3767 3768 mutex_lock(&adev->firmware.mutex); 3769 3770 ret = amdgpu_ucode_init_bo(adev); 3771 if (ret) 3772 goto failed; 3773 3774 ret = psp_hw_start(psp); 3775 if (ret) 3776 goto failed; 3777 3778 ret = psp_load_non_psp_fw(psp); 3779 if (ret) 3780 goto failed; 3781 3782 ret = psp_asd_initialize(psp); 3783 if (ret) { 3784 dev_err(adev->dev, "PSP load asd failed!\n"); 3785 goto failed; 3786 } 3787 3788 ret = psp_rl_load(adev); 3789 if (ret) { 3790 dev_err(adev->dev, "PSP load RL failed!\n"); 3791 goto failed; 3792 } 3793 3794 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3795 ret = psp_xgmi_initialize(psp, false, true); 3796 /* Warning the XGMI seesion initialize failure 3797 * Instead of stop driver initialization 3798 */ 3799 if (ret) 3800 dev_err(psp->adev->dev, 3801 "XGMI: Failed to initialize XGMI session\n"); 3802 } 3803 3804 if (psp->ta_fw) { 3805 ret = psp_ras_initialize(psp); 3806 if (ret) 3807 dev_err(psp->adev->dev, 3808 "RAS: Failed to initialize RAS\n"); 3809 3810 ret = psp_hdcp_initialize(psp); 3811 if (ret) 3812 dev_err(psp->adev->dev, 3813 "HDCP: Failed to initialize HDCP\n"); 3814 3815 ret = psp_dtm_initialize(psp); 3816 if (ret) 3817 dev_err(psp->adev->dev, 3818 "DTM: Failed to initialize DTM\n"); 3819 3820 ret = psp_rap_initialize(psp); 3821 if (ret) 3822 dev_err(psp->adev->dev, 3823 "RAP: Failed to initialize RAP\n"); 3824 3825 ret = psp_securedisplay_initialize(psp); 3826 if (ret) 3827 dev_err(psp->adev->dev, 3828 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3829 } 3830 3831 mutex_unlock(&adev->firmware.mutex); 3832 3833 return 0; 3834 3835 failed: 3836 dev_err(adev->dev, "PSP resume failed\n"); 3837 mutex_unlock(&adev->firmware.mutex); 3838 return ret; 3839 } 3840 3841 int psp_gpu_reset(struct amdgpu_device *adev) 3842 { 3843 int ret; 3844 3845 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3846 return 0; 3847 3848 mutex_lock(&adev->psp.mutex); 3849 ret = psp_mode1_reset(&adev->psp); 3850 mutex_unlock(&adev->psp.mutex); 3851 3852 return ret; 3853 } 3854 3855 int psp_rlc_autoload_start(struct psp_context *psp) 3856 { 3857 int ret; 3858 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3859 3860 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3861 3862 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3863 psp->fence_buf_mc_addr); 3864 3865 release_psp_cmd_buf(psp); 3866 3867 return ret; 3868 } 3869 3870 int psp_ring_cmd_submit(struct psp_context *psp, 3871 uint64_t cmd_buf_mc_addr, 3872 uint64_t fence_mc_addr, 3873 int index) 3874 { 3875 unsigned int psp_write_ptr_reg = 0; 3876 struct psp_gfx_rb_frame *write_frame; 3877 struct psp_ring *ring = &psp->km_ring; 3878 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3879 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3880 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3881 struct amdgpu_device *adev = psp->adev; 3882 uint32_t ring_size_dw = ring->ring_size / 4; 3883 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3884 3885 /* KM (GPCOM) prepare write pointer */ 3886 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3887 3888 /* Update KM RB frame pointer to new frame */ 3889 /* write_frame ptr increments by size of rb_frame in bytes */ 3890 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3891 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3892 write_frame = ring_buffer_start; 3893 else 3894 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3895 /* Check invalid write_frame ptr address */ 3896 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3897 dev_err(adev->dev, 3898 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3899 ring_buffer_start, ring_buffer_end, write_frame); 3900 dev_err(adev->dev, 3901 "write_frame is pointing to address out of bounds\n"); 3902 return -EINVAL; 3903 } 3904 3905 /* Initialize KM RB frame */ 3906 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3907 3908 /* Update KM RB frame */ 3909 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3910 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3911 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3912 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3913 write_frame->fence_value = index; 3914 amdgpu_device_flush_hdp(adev, NULL); 3915 3916 /* Update the write Pointer in DWORDs */ 3917 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3918 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3919 return 0; 3920 } 3921 3922 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3923 { 3924 struct amdgpu_device *adev = psp->adev; 3925 const struct psp_firmware_header_v1_0 *asd_hdr; 3926 int err = 0; 3927 3928 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3929 "amdgpu/%s_asd.bin", chip_name); 3930 if (err) 3931 goto out; 3932 3933 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3934 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3935 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3936 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3937 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3938 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3939 return 0; 3940 out: 3941 amdgpu_ucode_release(&adev->psp.asd_fw); 3942 return err; 3943 } 3944 3945 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3946 { 3947 struct amdgpu_device *adev = psp->adev; 3948 const struct psp_firmware_header_v1_0 *toc_hdr; 3949 int err = 0; 3950 3951 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3952 adev->rev_id == 0) 3953 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3954 "amdgpu/%s_toc_1.bin", chip_name); 3955 else 3956 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3957 "amdgpu/%s_toc.bin", chip_name); 3958 if (err) 3959 goto out; 3960 3961 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3962 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3963 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3964 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3965 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3966 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3967 return 0; 3968 out: 3969 amdgpu_ucode_release(&adev->psp.toc_fw); 3970 return err; 3971 } 3972 3973 static int parse_sos_bin_descriptor(struct psp_context *psp, 3974 const struct psp_fw_bin_desc *desc, 3975 const struct psp_firmware_header_v2_0 *sos_hdr) 3976 { 3977 uint8_t *ucode_start_addr = NULL; 3978 3979 if (!psp || !desc || !sos_hdr) 3980 return -EINVAL; 3981 3982 ucode_start_addr = (uint8_t *)sos_hdr + 3983 le32_to_cpu(desc->offset_bytes) + 3984 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3985 3986 switch (desc->fw_type) { 3987 case PSP_FW_TYPE_PSP_SOS: 3988 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3989 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3990 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3991 psp->sos.start_addr = ucode_start_addr; 3992 break; 3993 case PSP_FW_TYPE_PSP_SYS_DRV: 3994 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3995 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3996 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3997 psp->sys.start_addr = ucode_start_addr; 3998 break; 3999 case PSP_FW_TYPE_PSP_KDB: 4000 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 4001 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 4002 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 4003 psp->kdb.start_addr = ucode_start_addr; 4004 break; 4005 case PSP_FW_TYPE_PSP_TOC: 4006 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 4007 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 4008 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 4009 psp->toc.start_addr = ucode_start_addr; 4010 break; 4011 case PSP_FW_TYPE_PSP_SPL: 4012 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 4013 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 4014 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 4015 psp->spl.start_addr = ucode_start_addr; 4016 break; 4017 case PSP_FW_TYPE_PSP_RL: 4018 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 4019 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 4020 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 4021 psp->rl.start_addr = ucode_start_addr; 4022 break; 4023 case PSP_FW_TYPE_PSP_SOC_DRV: 4024 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 4025 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 4026 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4027 psp->soc_drv.start_addr = ucode_start_addr; 4028 break; 4029 case PSP_FW_TYPE_PSP_INTF_DRV: 4030 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4031 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4032 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4033 psp->intf_drv.start_addr = ucode_start_addr; 4034 break; 4035 case PSP_FW_TYPE_PSP_DBG_DRV: 4036 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4037 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4038 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4039 psp->dbg_drv.start_addr = ucode_start_addr; 4040 break; 4041 case PSP_FW_TYPE_PSP_RAS_DRV: 4042 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4043 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4044 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4045 psp->ras_drv.start_addr = ucode_start_addr; 4046 break; 4047 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4048 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4049 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4050 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4051 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4052 break; 4053 case PSP_FW_TYPE_PSP_SPDM_DRV: 4054 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4055 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4056 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4057 psp->spdm_drv.start_addr = ucode_start_addr; 4058 break; 4059 default: 4060 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4061 break; 4062 } 4063 4064 return 0; 4065 } 4066 4067 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4068 { 4069 const struct psp_firmware_header_v1_0 *sos_hdr; 4070 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4071 uint8_t *ucode_array_start_addr; 4072 4073 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4074 ucode_array_start_addr = (uint8_t *)sos_hdr + 4075 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4076 4077 if (adev->gmc.xgmi.connected_to_cpu || 4078 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4079 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4080 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4081 4082 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4083 adev->psp.sys.start_addr = ucode_array_start_addr; 4084 4085 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4086 adev->psp.sos.start_addr = ucode_array_start_addr + 4087 le32_to_cpu(sos_hdr->sos.offset_bytes); 4088 } else { 4089 /* Load alternate PSP SOS FW */ 4090 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4091 4092 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4093 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4094 4095 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4096 adev->psp.sys.start_addr = ucode_array_start_addr + 4097 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4098 4099 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4100 adev->psp.sos.start_addr = ucode_array_start_addr + 4101 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4102 } 4103 4104 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4105 dev_warn(adev->dev, "PSP SOS FW not available"); 4106 return -EINVAL; 4107 } 4108 4109 return 0; 4110 } 4111 4112 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4113 { 4114 struct amdgpu_device *adev = psp->adev; 4115 const struct psp_firmware_header_v1_0 *sos_hdr; 4116 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4117 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4118 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4119 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4120 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4121 int fw_index, fw_bin_count, start_index = 0; 4122 const struct psp_fw_bin_desc *fw_bin; 4123 uint8_t *ucode_array_start_addr; 4124 int err = 0; 4125 4126 if (amdgpu_is_kicker_fw(adev)) 4127 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4128 "amdgpu/%s_sos_kicker.bin", chip_name); 4129 else 4130 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4131 "amdgpu/%s_sos.bin", chip_name); 4132 if (err) 4133 goto out; 4134 4135 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4136 ucode_array_start_addr = (uint8_t *)sos_hdr + 4137 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4138 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4139 4140 switch (sos_hdr->header.header_version_major) { 4141 case 1: 4142 err = psp_init_sos_base_fw(adev); 4143 if (err) 4144 goto out; 4145 4146 if (sos_hdr->header.header_version_minor == 1) { 4147 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4148 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4149 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4150 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4151 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4152 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4153 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4154 } 4155 if (sos_hdr->header.header_version_minor == 2) { 4156 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4157 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4158 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4159 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4160 } 4161 if (sos_hdr->header.header_version_minor == 3) { 4162 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4163 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4164 adev->psp.toc.start_addr = ucode_array_start_addr + 4165 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4166 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4167 adev->psp.kdb.start_addr = ucode_array_start_addr + 4168 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4169 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4170 adev->psp.spl.start_addr = ucode_array_start_addr + 4171 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4172 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4173 adev->psp.rl.start_addr = ucode_array_start_addr + 4174 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4175 } 4176 break; 4177 case 2: 4178 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4179 4180 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4181 4182 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4183 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4184 err = -EINVAL; 4185 goto out; 4186 } 4187 4188 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4189 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4190 4191 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4192 4193 if (psp_is_aux_sos_load_required(psp)) 4194 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4195 else 4196 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4197 4198 } else { 4199 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4200 } 4201 4202 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4203 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4204 sos_hdr_v2_0); 4205 if (err) 4206 goto out; 4207 } 4208 break; 4209 default: 4210 dev_err(adev->dev, 4211 "unsupported psp sos firmware\n"); 4212 err = -EINVAL; 4213 goto out; 4214 } 4215 4216 return 0; 4217 out: 4218 amdgpu_ucode_release(&adev->psp.sos_fw); 4219 4220 return err; 4221 } 4222 4223 static bool is_ta_fw_applicable(struct psp_context *psp, 4224 const struct psp_fw_bin_desc *desc) 4225 { 4226 struct amdgpu_device *adev = psp->adev; 4227 uint32_t fw_version; 4228 4229 switch (desc->fw_type) { 4230 case TA_FW_TYPE_PSP_XGMI: 4231 case TA_FW_TYPE_PSP_XGMI_AUX: 4232 /* for now, AUX TA only exists on 13.0.6 ta bin, 4233 * from v20.00.0x.14 4234 */ 4235 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4236 IP_VERSION(13, 0, 6)) { 4237 fw_version = le32_to_cpu(desc->fw_version); 4238 4239 if (adev->flags & AMD_IS_APU && 4240 (fw_version & 0xff) >= 0x14) 4241 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4242 else 4243 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4244 } 4245 break; 4246 default: 4247 break; 4248 } 4249 4250 return true; 4251 } 4252 4253 static int parse_ta_bin_descriptor(struct psp_context *psp, 4254 const struct psp_fw_bin_desc *desc, 4255 const struct ta_firmware_header_v2_0 *ta_hdr) 4256 { 4257 uint8_t *ucode_start_addr = NULL; 4258 4259 if (!psp || !desc || !ta_hdr) 4260 return -EINVAL; 4261 4262 if (!is_ta_fw_applicable(psp, desc)) 4263 return 0; 4264 4265 ucode_start_addr = (uint8_t *)ta_hdr + 4266 le32_to_cpu(desc->offset_bytes) + 4267 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4268 4269 switch (desc->fw_type) { 4270 case TA_FW_TYPE_PSP_ASD: 4271 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4272 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4273 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4274 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4275 break; 4276 case TA_FW_TYPE_PSP_XGMI: 4277 case TA_FW_TYPE_PSP_XGMI_AUX: 4278 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4279 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4280 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4281 break; 4282 case TA_FW_TYPE_PSP_RAS: 4283 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4284 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4285 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4286 break; 4287 case TA_FW_TYPE_PSP_HDCP: 4288 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4289 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4290 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4291 break; 4292 case TA_FW_TYPE_PSP_DTM: 4293 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4294 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4295 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4296 break; 4297 case TA_FW_TYPE_PSP_RAP: 4298 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4299 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4300 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4301 break; 4302 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4303 psp->securedisplay_context.context.bin_desc.fw_version = 4304 le32_to_cpu(desc->fw_version); 4305 psp->securedisplay_context.context.bin_desc.size_bytes = 4306 le32_to_cpu(desc->size_bytes); 4307 psp->securedisplay_context.context.bin_desc.start_addr = 4308 ucode_start_addr; 4309 break; 4310 default: 4311 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4312 break; 4313 } 4314 4315 return 0; 4316 } 4317 4318 static int parse_ta_v1_microcode(struct psp_context *psp) 4319 { 4320 const struct ta_firmware_header_v1_0 *ta_hdr; 4321 struct amdgpu_device *adev = psp->adev; 4322 4323 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4324 4325 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4326 return -EINVAL; 4327 4328 adev->psp.xgmi_context.context.bin_desc.fw_version = 4329 le32_to_cpu(ta_hdr->xgmi.fw_version); 4330 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4331 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4332 adev->psp.xgmi_context.context.bin_desc.start_addr = 4333 (uint8_t *)ta_hdr + 4334 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4335 4336 adev->psp.ras_context.context.bin_desc.fw_version = 4337 le32_to_cpu(ta_hdr->ras.fw_version); 4338 adev->psp.ras_context.context.bin_desc.size_bytes = 4339 le32_to_cpu(ta_hdr->ras.size_bytes); 4340 adev->psp.ras_context.context.bin_desc.start_addr = 4341 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4342 le32_to_cpu(ta_hdr->ras.offset_bytes); 4343 4344 adev->psp.hdcp_context.context.bin_desc.fw_version = 4345 le32_to_cpu(ta_hdr->hdcp.fw_version); 4346 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4347 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4348 adev->psp.hdcp_context.context.bin_desc.start_addr = 4349 (uint8_t *)ta_hdr + 4350 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4351 4352 adev->psp.dtm_context.context.bin_desc.fw_version = 4353 le32_to_cpu(ta_hdr->dtm.fw_version); 4354 adev->psp.dtm_context.context.bin_desc.size_bytes = 4355 le32_to_cpu(ta_hdr->dtm.size_bytes); 4356 adev->psp.dtm_context.context.bin_desc.start_addr = 4357 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4358 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4359 4360 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4361 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4362 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4363 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4364 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4365 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4366 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4367 4368 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4369 4370 return 0; 4371 } 4372 4373 static int parse_ta_v2_microcode(struct psp_context *psp) 4374 { 4375 const struct ta_firmware_header_v2_0 *ta_hdr; 4376 struct amdgpu_device *adev = psp->adev; 4377 int err = 0; 4378 int ta_index = 0; 4379 4380 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4381 4382 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4383 return -EINVAL; 4384 4385 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4386 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4387 return -EINVAL; 4388 } 4389 4390 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4391 err = parse_ta_bin_descriptor(psp, 4392 &ta_hdr->ta_fw_bin[ta_index], 4393 ta_hdr); 4394 if (err) 4395 return err; 4396 } 4397 4398 return 0; 4399 } 4400 4401 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4402 { 4403 const struct common_firmware_header *hdr; 4404 struct amdgpu_device *adev = psp->adev; 4405 int err; 4406 4407 if (amdgpu_is_kicker_fw(adev)) 4408 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4409 "amdgpu/%s_ta_kicker.bin", chip_name); 4410 else 4411 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4412 "amdgpu/%s_ta.bin", chip_name); 4413 if (err) 4414 return err; 4415 4416 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4417 switch (le16_to_cpu(hdr->header_version_major)) { 4418 case 1: 4419 err = parse_ta_v1_microcode(psp); 4420 break; 4421 case 2: 4422 err = parse_ta_v2_microcode(psp); 4423 break; 4424 default: 4425 dev_err(adev->dev, "unsupported TA header version\n"); 4426 err = -EINVAL; 4427 } 4428 4429 if (err) 4430 amdgpu_ucode_release(&adev->psp.ta_fw); 4431 4432 return err; 4433 } 4434 4435 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4436 { 4437 struct amdgpu_device *adev = psp->adev; 4438 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4439 struct amdgpu_firmware_info *info = NULL; 4440 int err = 0; 4441 4442 if (!amdgpu_sriov_vf(adev)) { 4443 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4444 return -EINVAL; 4445 } 4446 4447 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4448 "amdgpu/%s_cap.bin", chip_name); 4449 if (err) { 4450 if (err == -ENODEV) { 4451 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4452 err = 0; 4453 } else { 4454 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4455 } 4456 goto out; 4457 } 4458 4459 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4460 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4461 info->fw = adev->psp.cap_fw; 4462 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4463 adev->psp.cap_fw->data; 4464 adev->firmware.fw_size += ALIGN( 4465 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4466 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4467 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4468 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4469 4470 return 0; 4471 4472 out: 4473 amdgpu_ucode_release(&adev->psp.cap_fw); 4474 return err; 4475 } 4476 4477 int psp_config_sq_perfmon(struct psp_context *psp, 4478 uint32_t xcp_id, bool core_override_enable, 4479 bool reg_override_enable, bool perfmon_override_enable) 4480 { 4481 int ret; 4482 4483 if (amdgpu_sriov_vf(psp->adev)) 4484 return 0; 4485 4486 if (xcp_id > MAX_XCP) { 4487 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4488 return -EINVAL; 4489 } 4490 4491 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4492 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4493 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4494 return -EINVAL; 4495 } 4496 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4497 4498 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4499 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4500 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4501 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4502 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4503 4504 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4505 if (ret) 4506 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4507 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4508 4509 release_psp_cmd_buf(psp); 4510 return ret; 4511 } 4512 4513 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4514 enum amd_clockgating_state state) 4515 { 4516 return 0; 4517 } 4518 4519 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4520 enum amd_powergating_state state) 4521 { 4522 return 0; 4523 } 4524 4525 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4526 struct device_attribute *attr, 4527 char *buf) 4528 { 4529 struct drm_device *ddev = dev_get_drvdata(dev); 4530 struct amdgpu_device *adev = drm_to_adev(ddev); 4531 struct amdgpu_ip_block *ip_block; 4532 uint32_t fw_ver; 4533 int ret; 4534 4535 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4536 if (!ip_block || !ip_block->status.late_initialized) { 4537 dev_info(adev->dev, "PSP block is not ready yet\n."); 4538 return -EBUSY; 4539 } 4540 4541 mutex_lock(&adev->psp.mutex); 4542 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4543 mutex_unlock(&adev->psp.mutex); 4544 4545 if (ret) { 4546 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4547 return ret; 4548 } 4549 4550 return sysfs_emit(buf, "%x\n", fw_ver); 4551 } 4552 4553 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4554 struct device_attribute *attr, 4555 const char *buf, 4556 size_t count) 4557 { 4558 struct drm_device *ddev = dev_get_drvdata(dev); 4559 struct amdgpu_device *adev = drm_to_adev(ddev); 4560 int ret, idx; 4561 const struct firmware *usbc_pd_fw; 4562 struct amdgpu_bo *fw_buf_bo = NULL; 4563 uint64_t fw_pri_mc_addr; 4564 void *fw_pri_cpu_addr; 4565 struct amdgpu_ip_block *ip_block; 4566 4567 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4568 if (!ip_block || !ip_block->status.late_initialized) { 4569 dev_err(adev->dev, "PSP block is not ready yet."); 4570 return -EBUSY; 4571 } 4572 4573 if (!drm_dev_enter(ddev, &idx)) 4574 return -ENODEV; 4575 4576 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4577 "amdgpu/%s", buf); 4578 if (ret) 4579 goto fail; 4580 4581 /* LFB address which is aligned to 1MB boundary per PSP request */ 4582 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4583 AMDGPU_GEM_DOMAIN_VRAM | 4584 AMDGPU_GEM_DOMAIN_GTT, 4585 &fw_buf_bo, &fw_pri_mc_addr, 4586 &fw_pri_cpu_addr); 4587 if (ret) 4588 goto rel_buf; 4589 4590 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4591 4592 mutex_lock(&adev->psp.mutex); 4593 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4594 mutex_unlock(&adev->psp.mutex); 4595 4596 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4597 4598 rel_buf: 4599 amdgpu_ucode_release(&usbc_pd_fw); 4600 fail: 4601 if (ret) { 4602 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4603 count = ret; 4604 } 4605 4606 drm_dev_exit(idx); 4607 return count; 4608 } 4609 4610 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4611 { 4612 int idx; 4613 4614 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4615 return -ENODEV; 4616 4617 if (!bin_size || bin_size > PSP_1_MEG) { 4618 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4619 drm_dev_exit(idx); 4620 return -EINVAL; 4621 } 4622 4623 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4624 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4625 4626 drm_dev_exit(idx); 4627 return 0; 4628 } 4629 4630 /** 4631 * DOC: usbc_pd_fw 4632 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4633 * this file will trigger the update process. 4634 */ 4635 static DEVICE_ATTR(usbc_pd_fw, 0644, 4636 psp_usbc_pd_fw_sysfs_read, 4637 psp_usbc_pd_fw_sysfs_write); 4638 /** 4639 * DOC: PTL sysfs attributes 4640 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4641 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4642 * formats for each GPU. 4643 */ 4644 static DEVICE_ATTR(ptl_enable, 0644, 4645 ptl_enable_show, ptl_enable_store); 4646 static DEVICE_ATTR(ptl_format, 0644, 4647 ptl_format_show, ptl_format_store); 4648 static DEVICE_ATTR(ptl_supported_formats, 0444, 4649 ptl_supported_formats_show, NULL); 4650 4651 static struct attribute *ptl_attrs[] = { 4652 &dev_attr_ptl_enable.attr, 4653 &dev_attr_ptl_format.attr, 4654 &dev_attr_ptl_supported_formats.attr, 4655 NULL, 4656 }; 4657 4658 const struct attribute_group amdgpu_ptl_attr_group = { 4659 .name = "ptl", 4660 .attrs = ptl_attrs, 4661 .is_visible = amdgpu_ptl_is_visible, 4662 }; 4663 4664 int is_psp_fw_valid(struct psp_bin_desc bin) 4665 { 4666 return bin.size_bytes; 4667 } 4668 4669 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4670 const struct bin_attribute *bin_attr, 4671 char *buffer, loff_t pos, size_t count) 4672 { 4673 struct device *dev = kobj_to_dev(kobj); 4674 struct drm_device *ddev = dev_get_drvdata(dev); 4675 struct amdgpu_device *adev = drm_to_adev(ddev); 4676 4677 adev->psp.vbflash_done = false; 4678 4679 /* Safeguard against memory drain */ 4680 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4681 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4682 kvfree(adev->psp.vbflash_tmp_buf); 4683 adev->psp.vbflash_tmp_buf = NULL; 4684 adev->psp.vbflash_image_size = 0; 4685 return -ENOMEM; 4686 } 4687 4688 mutex_lock(&adev->psp.mutex); 4689 4690 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4691 if (!adev->psp.vbflash_tmp_buf) { 4692 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4693 if (!adev->psp.vbflash_tmp_buf) { 4694 mutex_unlock(&adev->psp.mutex); 4695 return -ENOMEM; 4696 } 4697 } 4698 4699 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4700 adev->psp.vbflash_image_size += count; 4701 mutex_unlock(&adev->psp.mutex); 4702 4703 dev_dbg(adev->dev, "IFWI staged for update\n"); 4704 4705 return count; 4706 } 4707 4708 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4709 const struct bin_attribute *bin_attr, char *buffer, 4710 loff_t pos, size_t count) 4711 { 4712 struct device *dev = kobj_to_dev(kobj); 4713 struct drm_device *ddev = dev_get_drvdata(dev); 4714 struct amdgpu_device *adev = drm_to_adev(ddev); 4715 struct amdgpu_bo *fw_buf_bo = NULL; 4716 uint64_t fw_pri_mc_addr; 4717 void *fw_pri_cpu_addr; 4718 int ret; 4719 4720 if (adev->psp.vbflash_image_size == 0) 4721 return -EINVAL; 4722 4723 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4724 4725 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4726 AMDGPU_GPU_PAGE_SIZE, 4727 AMDGPU_GEM_DOMAIN_VRAM, 4728 &fw_buf_bo, 4729 &fw_pri_mc_addr, 4730 &fw_pri_cpu_addr); 4731 if (ret) 4732 goto rel_buf; 4733 4734 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4735 4736 mutex_lock(&adev->psp.mutex); 4737 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4738 mutex_unlock(&adev->psp.mutex); 4739 4740 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4741 4742 rel_buf: 4743 kvfree(adev->psp.vbflash_tmp_buf); 4744 adev->psp.vbflash_tmp_buf = NULL; 4745 adev->psp.vbflash_image_size = 0; 4746 4747 if (ret) { 4748 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4749 return ret; 4750 } 4751 4752 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4753 return 0; 4754 } 4755 4756 /** 4757 * DOC: psp_vbflash 4758 * Writing to this file will stage an IFWI for update. Reading from this file 4759 * will trigger the update process. 4760 */ 4761 static const struct bin_attribute psp_vbflash_bin_attr = { 4762 .attr = {.name = "psp_vbflash", .mode = 0660}, 4763 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4764 .write = amdgpu_psp_vbflash_write, 4765 .read = amdgpu_psp_vbflash_read, 4766 }; 4767 4768 /** 4769 * DOC: psp_vbflash_status 4770 * The status of the flash process. 4771 * 0: IFWI flash not complete. 4772 * 1: IFWI flash complete. 4773 */ 4774 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4775 struct device_attribute *attr, 4776 char *buf) 4777 { 4778 struct drm_device *ddev = dev_get_drvdata(dev); 4779 struct amdgpu_device *adev = drm_to_adev(ddev); 4780 uint32_t vbflash_status; 4781 4782 vbflash_status = psp_vbflash_status(&adev->psp); 4783 if (!adev->psp.vbflash_done) 4784 vbflash_status = 0; 4785 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4786 vbflash_status = 1; 4787 4788 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4789 } 4790 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4791 4792 static const struct bin_attribute *const bin_flash_attrs[] = { 4793 &psp_vbflash_bin_attr, 4794 NULL 4795 }; 4796 4797 static struct attribute *flash_attrs[] = { 4798 &dev_attr_psp_vbflash_status.attr, 4799 &dev_attr_usbc_pd_fw.attr, 4800 NULL 4801 }; 4802 4803 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4804 { 4805 struct device *dev = kobj_to_dev(kobj); 4806 struct drm_device *ddev = dev_get_drvdata(dev); 4807 struct amdgpu_device *adev = drm_to_adev(ddev); 4808 4809 if (attr == &dev_attr_usbc_pd_fw.attr) 4810 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4811 4812 return adev->psp.sup_ifwi_up ? 0440 : 0; 4813 } 4814 4815 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4816 const struct bin_attribute *attr, 4817 int idx) 4818 { 4819 struct device *dev = kobj_to_dev(kobj); 4820 struct drm_device *ddev = dev_get_drvdata(dev); 4821 struct amdgpu_device *adev = drm_to_adev(ddev); 4822 4823 return adev->psp.sup_ifwi_up ? 0660 : 0; 4824 } 4825 4826 const struct attribute_group amdgpu_flash_attr_group = { 4827 .attrs = flash_attrs, 4828 .bin_attrs = bin_flash_attrs, 4829 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4830 .is_visible = amdgpu_flash_attr_is_visible, 4831 }; 4832 4833 #if defined(CONFIG_DEBUG_FS) 4834 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4835 { 4836 struct amdgpu_device *adev = filp->f_inode->i_private; 4837 struct spirom_bo *bo_triplet; 4838 int ret; 4839 4840 /* serialize the open() file calling */ 4841 if (!mutex_trylock(&adev->psp.mutex)) 4842 return -EBUSY; 4843 4844 /* 4845 * make sure only one userpace process is alive for dumping so that 4846 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4847 * let's say the case where one process try opening the file while 4848 * another one has proceeded to read or release. In this way, eliminate 4849 * the use of mutex for read() or release() callback as well. 4850 */ 4851 if (adev->psp.spirom_dump_trip) { 4852 mutex_unlock(&adev->psp.mutex); 4853 return -EBUSY; 4854 } 4855 4856 bo_triplet = kzalloc_obj(struct spirom_bo); 4857 if (!bo_triplet) { 4858 mutex_unlock(&adev->psp.mutex); 4859 return -ENOMEM; 4860 } 4861 4862 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4863 AMDGPU_GPU_PAGE_SIZE, 4864 AMDGPU_GEM_DOMAIN_GTT, 4865 &bo_triplet->bo, 4866 &bo_triplet->mc_addr, 4867 &bo_triplet->cpu_addr); 4868 if (ret) 4869 goto rel_trip; 4870 4871 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4872 if (ret) 4873 goto rel_bo; 4874 4875 adev->psp.spirom_dump_trip = bo_triplet; 4876 mutex_unlock(&adev->psp.mutex); 4877 return 0; 4878 rel_bo: 4879 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4880 &bo_triplet->cpu_addr); 4881 rel_trip: 4882 kfree(bo_triplet); 4883 mutex_unlock(&adev->psp.mutex); 4884 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4885 return ret; 4886 } 4887 4888 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4889 loff_t *pos) 4890 { 4891 struct amdgpu_device *adev = filp->f_inode->i_private; 4892 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4893 4894 if (!bo_triplet) 4895 return -EINVAL; 4896 4897 return simple_read_from_buffer(buf, 4898 size, 4899 pos, bo_triplet->cpu_addr, 4900 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4901 } 4902 4903 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4904 { 4905 struct amdgpu_device *adev = filp->f_inode->i_private; 4906 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4907 4908 if (bo_triplet) { 4909 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4910 &bo_triplet->cpu_addr); 4911 kfree(bo_triplet); 4912 } 4913 4914 adev->psp.spirom_dump_trip = NULL; 4915 return 0; 4916 } 4917 4918 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4919 .owner = THIS_MODULE, 4920 .open = psp_read_spirom_debugfs_open, 4921 .read = psp_read_spirom_debugfs_read, 4922 .release = psp_read_spirom_debugfs_release, 4923 .llseek = default_llseek, 4924 }; 4925 #endif 4926 4927 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4928 { 4929 #if defined(CONFIG_DEBUG_FS) 4930 struct drm_minor *minor = adev_to_drm(adev)->primary; 4931 4932 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4933 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4934 #endif 4935 } 4936 4937 const struct amd_ip_funcs psp_ip_funcs = { 4938 .name = "psp", 4939 .early_init = psp_early_init, 4940 .sw_init = psp_sw_init, 4941 .sw_fini = psp_sw_fini, 4942 .hw_init = psp_hw_init, 4943 .hw_fini = psp_hw_fini, 4944 .suspend = psp_suspend, 4945 .resume = psp_resume, 4946 .set_clockgating_state = psp_set_clockgating_state, 4947 .set_powergating_state = psp_set_powergating_state, 4948 }; 4949 4950 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4951 .type = AMD_IP_BLOCK_TYPE_PSP, 4952 .major = 3, 4953 .minor = 1, 4954 .rev = 0, 4955 .funcs = &psp_ip_funcs, 4956 }; 4957 4958 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4959 .type = AMD_IP_BLOCK_TYPE_PSP, 4960 .major = 10, 4961 .minor = 0, 4962 .rev = 0, 4963 .funcs = &psp_ip_funcs, 4964 }; 4965 4966 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4967 .type = AMD_IP_BLOCK_TYPE_PSP, 4968 .major = 11, 4969 .minor = 0, 4970 .rev = 0, 4971 .funcs = &psp_ip_funcs, 4972 }; 4973 4974 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4975 .type = AMD_IP_BLOCK_TYPE_PSP, 4976 .major = 11, 4977 .minor = 0, 4978 .rev = 8, 4979 .funcs = &psp_ip_funcs, 4980 }; 4981 4982 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4983 .type = AMD_IP_BLOCK_TYPE_PSP, 4984 .major = 12, 4985 .minor = 0, 4986 .rev = 0, 4987 .funcs = &psp_ip_funcs, 4988 }; 4989 4990 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4991 .type = AMD_IP_BLOCK_TYPE_PSP, 4992 .major = 13, 4993 .minor = 0, 4994 .rev = 0, 4995 .funcs = &psp_ip_funcs, 4996 }; 4997 4998 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4999 .type = AMD_IP_BLOCK_TYPE_PSP, 5000 .major = 13, 5001 .minor = 0, 5002 .rev = 4, 5003 .funcs = &psp_ip_funcs, 5004 }; 5005 5006 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 5007 .type = AMD_IP_BLOCK_TYPE_PSP, 5008 .major = 14, 5009 .minor = 0, 5010 .rev = 0, 5011 .funcs = &psp_ip_funcs, 5012 }; 5013 5014 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 5015 .type = AMD_IP_BLOCK_TYPE_PSP, 5016 .major = 15, 5017 .minor = 0, 5018 .rev = 0, 5019 .funcs = &psp_ip_funcs, 5020 }; 5021 5022 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 5023 .type = AMD_IP_BLOCK_TYPE_PSP, 5024 .major = 15, 5025 .minor = 0, 5026 .rev = 8, 5027 .funcs = &psp_ip_funcs, 5028 }; 5029