1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 #include <drm/drm_drv.h> 45 46 static int psp_sysfs_init(struct amdgpu_device *adev); 47 static void psp_sysfs_fini(struct amdgpu_device *adev); 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 51 /* 52 * Due to DF Cstate management centralized to PMFW, the firmware 53 * loading sequence will be updated as below: 54 * - Load KDB 55 * - Load SYS_DRV 56 * - Load tOS 57 * - Load PMFW 58 * - Setup TMR 59 * - Load other non-psp fw 60 * - Load ASD 61 * - Load XGMI/RAS/HDCP/DTM TA if any 62 * 63 * This new sequence is required for 64 * - Arcturus and onwards 65 * - Navi12 and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 psp->pmfw_centralized_cstate_management = false; 72 73 if (amdgpu_sriov_vf(adev)) 74 return; 75 76 if (adev->flags & AMD_IS_APU) 77 return; 78 79 if ((adev->asic_type >= CHIP_ARCTURUS) || 80 (adev->asic_type >= CHIP_NAVI12)) 81 psp->pmfw_centralized_cstate_management = true; 82 } 83 84 static int psp_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 struct psp_context *psp = &adev->psp; 88 89 switch (adev->asic_type) { 90 case CHIP_VEGA10: 91 case CHIP_VEGA12: 92 psp_v3_1_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_RAVEN: 96 psp_v10_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_VEGA20: 100 case CHIP_ARCTURUS: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case CHIP_NAVI10: 105 case CHIP_NAVI14: 106 case CHIP_NAVI12: 107 case CHIP_SIENNA_CICHLID: 108 case CHIP_NAVY_FLOUNDER: 109 case CHIP_VANGOGH: 110 case CHIP_DIMGREY_CAVEFISH: 111 case CHIP_BEIGE_GOBY: 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = true; 114 break; 115 case CHIP_RENOIR: 116 psp_v12_0_set_psp_funcs(psp); 117 break; 118 case CHIP_ALDEBARAN: 119 psp_v13_0_set_psp_funcs(psp); 120 break; 121 default: 122 return -EINVAL; 123 } 124 125 psp->adev = adev; 126 127 psp_check_pmfw_centralized_cstate_management(psp); 128 129 return 0; 130 } 131 132 static void psp_memory_training_fini(struct psp_context *psp) 133 { 134 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 135 136 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 137 kfree(ctx->sys_cache); 138 ctx->sys_cache = NULL; 139 } 140 141 static int psp_memory_training_init(struct psp_context *psp) 142 { 143 int ret; 144 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 145 146 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 147 DRM_DEBUG("memory training is not supported!\n"); 148 return 0; 149 } 150 151 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 152 if (ctx->sys_cache == NULL) { 153 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 154 ret = -ENOMEM; 155 goto Err_out; 156 } 157 158 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 159 ctx->train_data_size, 160 ctx->p2c_train_data_offset, 161 ctx->c2p_train_data_offset); 162 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 163 return 0; 164 165 Err_out: 166 psp_memory_training_fini(psp); 167 return ret; 168 } 169 170 static int psp_sw_init(void *handle) 171 { 172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 173 struct psp_context *psp = &adev->psp; 174 int ret; 175 176 if (!amdgpu_sriov_vf(adev)) { 177 ret = psp_init_microcode(psp); 178 if (ret) { 179 DRM_ERROR("Failed to load psp firmware!\n"); 180 return ret; 181 } 182 } 183 184 ret = psp_memory_training_init(psp); 185 if (ret) { 186 DRM_ERROR("Failed to initialize memory training!\n"); 187 return ret; 188 } 189 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 190 if (ret) { 191 DRM_ERROR("Failed to process memory training!\n"); 192 return ret; 193 } 194 195 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 196 ret= psp_sysfs_init(adev); 197 if (ret) { 198 return ret; 199 } 200 } 201 202 return 0; 203 } 204 205 static int psp_sw_fini(void *handle) 206 { 207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 208 209 psp_memory_training_fini(&adev->psp); 210 if (adev->psp.sos_fw) { 211 release_firmware(adev->psp.sos_fw); 212 adev->psp.sos_fw = NULL; 213 } 214 if (adev->psp.asd_fw) { 215 release_firmware(adev->psp.asd_fw); 216 adev->psp.asd_fw = NULL; 217 } 218 if (adev->psp.ta_fw) { 219 release_firmware(adev->psp.ta_fw); 220 adev->psp.ta_fw = NULL; 221 } 222 223 if (adev->asic_type == CHIP_NAVI10 || 224 adev->asic_type == CHIP_SIENNA_CICHLID) 225 psp_sysfs_fini(adev); 226 227 return 0; 228 } 229 230 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 231 uint32_t reg_val, uint32_t mask, bool check_changed) 232 { 233 uint32_t val; 234 int i; 235 struct amdgpu_device *adev = psp->adev; 236 237 if (psp->adev->no_hw_access) 238 return 0; 239 240 for (i = 0; i < adev->usec_timeout; i++) { 241 val = RREG32(reg_index); 242 if (check_changed) { 243 if (val != reg_val) 244 return 0; 245 } else { 246 if ((val & mask) == reg_val) 247 return 0; 248 } 249 udelay(1); 250 } 251 252 return -ETIME; 253 } 254 255 static int 256 psp_cmd_submit_buf(struct psp_context *psp, 257 struct amdgpu_firmware_info *ucode, 258 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 259 { 260 int ret; 261 int index, idx; 262 int timeout = 20000; 263 bool ras_intr = false; 264 bool skip_unsupport = false; 265 266 if (psp->adev->no_hw_access) 267 return 0; 268 269 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 270 return 0; 271 272 mutex_lock(&psp->mutex); 273 274 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 275 276 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 277 278 index = atomic_inc_return(&psp->fence_value); 279 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 280 if (ret) { 281 atomic_dec(&psp->fence_value); 282 goto exit; 283 } 284 285 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 286 while (*((unsigned int *)psp->fence_buf) != index) { 287 if (--timeout == 0) 288 break; 289 /* 290 * Shouldn't wait for timeout when err_event_athub occurs, 291 * because gpu reset thread triggered and lock resource should 292 * be released for psp resume sequence. 293 */ 294 ras_intr = amdgpu_ras_intr_triggered(); 295 if (ras_intr) 296 break; 297 usleep_range(10, 100); 298 amdgpu_asic_invalidate_hdp(psp->adev, NULL); 299 } 300 301 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 302 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 303 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 304 305 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 306 307 /* In some cases, psp response status is not 0 even there is no 308 * problem while the command is submitted. Some version of PSP FW 309 * doesn't write 0 to that field. 310 * So here we would like to only print a warning instead of an error 311 * during psp initialization to avoid breaking hw_init and it doesn't 312 * return -EINVAL. 313 */ 314 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 315 if (ucode) 316 DRM_WARN("failed to load ucode id (%d) ", 317 ucode->ucode_id); 318 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 319 psp->cmd_buf_mem->cmd_id, 320 psp->cmd_buf_mem->resp.status); 321 if (!timeout) { 322 ret = -EINVAL; 323 goto exit; 324 } 325 } 326 327 if (ucode) { 328 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 329 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 330 } 331 332 exit: 333 mutex_unlock(&psp->mutex); 334 drm_dev_exit(idx); 335 return ret; 336 } 337 338 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 339 struct psp_gfx_cmd_resp *cmd, 340 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 341 { 342 struct amdgpu_device *adev = psp->adev; 343 uint32_t size = amdgpu_bo_size(tmr_bo); 344 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 345 346 if (amdgpu_sriov_vf(psp->adev)) 347 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 348 else 349 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 350 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 351 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 352 cmd->cmd.cmd_setup_tmr.buf_size = size; 353 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 354 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 355 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 356 } 357 358 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 359 uint64_t pri_buf_mc, uint32_t size) 360 { 361 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 362 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 363 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 364 cmd->cmd.cmd_load_toc.toc_size = size; 365 } 366 367 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 368 static int psp_load_toc(struct psp_context *psp, 369 uint32_t *tmr_size) 370 { 371 int ret; 372 struct psp_gfx_cmd_resp *cmd; 373 374 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 375 if (!cmd) 376 return -ENOMEM; 377 /* Copy toc to psp firmware private buffer */ 378 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); 379 380 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 381 382 ret = psp_cmd_submit_buf(psp, NULL, cmd, 383 psp->fence_buf_mc_addr); 384 if (!ret) 385 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 386 kfree(cmd); 387 return ret; 388 } 389 390 /* Set up Trusted Memory Region */ 391 static int psp_tmr_init(struct psp_context *psp) 392 { 393 int ret; 394 int tmr_size; 395 void *tmr_buf; 396 void **pptr; 397 398 /* 399 * According to HW engineer, they prefer the TMR address be "naturally 400 * aligned" , e.g. the start address be an integer divide of TMR size. 401 * 402 * Note: this memory need be reserved till the driver 403 * uninitializes. 404 */ 405 tmr_size = PSP_TMR_SIZE(psp->adev); 406 407 /* For ASICs support RLC autoload, psp will parse the toc 408 * and calculate the total size of TMR needed */ 409 if (!amdgpu_sriov_vf(psp->adev) && 410 psp->toc_start_addr && 411 psp->toc_bin_size && 412 psp->fw_pri_buf) { 413 ret = psp_load_toc(psp, &tmr_size); 414 if (ret) { 415 DRM_ERROR("Failed to load toc\n"); 416 return ret; 417 } 418 } 419 420 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 421 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 422 AMDGPU_GEM_DOMAIN_VRAM, 423 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 424 425 return ret; 426 } 427 428 static bool psp_skip_tmr(struct psp_context *psp) 429 { 430 switch (psp->adev->asic_type) { 431 case CHIP_NAVI12: 432 case CHIP_SIENNA_CICHLID: 433 case CHIP_ALDEBARAN: 434 return true; 435 default: 436 return false; 437 } 438 } 439 440 static int psp_tmr_load(struct psp_context *psp) 441 { 442 int ret; 443 struct psp_gfx_cmd_resp *cmd; 444 445 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 446 * Already set up by host driver. 447 */ 448 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 449 return 0; 450 451 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 452 if (!cmd) 453 return -ENOMEM; 454 455 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 456 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 457 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 458 459 ret = psp_cmd_submit_buf(psp, NULL, cmd, 460 psp->fence_buf_mc_addr); 461 462 kfree(cmd); 463 464 return ret; 465 } 466 467 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 468 struct psp_gfx_cmd_resp *cmd) 469 { 470 if (amdgpu_sriov_vf(psp->adev)) 471 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 472 else 473 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 474 } 475 476 static int psp_tmr_unload(struct psp_context *psp) 477 { 478 int ret; 479 struct psp_gfx_cmd_resp *cmd; 480 481 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 482 if (!cmd) 483 return -ENOMEM; 484 485 psp_prep_tmr_unload_cmd_buf(psp, cmd); 486 DRM_INFO("free PSP TMR buffer\n"); 487 488 ret = psp_cmd_submit_buf(psp, NULL, cmd, 489 psp->fence_buf_mc_addr); 490 491 kfree(cmd); 492 493 return ret; 494 } 495 496 static int psp_tmr_terminate(struct psp_context *psp) 497 { 498 int ret; 499 void *tmr_buf; 500 void **pptr; 501 502 ret = psp_tmr_unload(psp); 503 if (ret) 504 return ret; 505 506 /* free TMR memory buffer */ 507 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 508 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 509 510 return 0; 511 } 512 513 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 514 uint64_t *output_ptr) 515 { 516 int ret; 517 struct psp_gfx_cmd_resp *cmd; 518 519 if (!output_ptr) 520 return -EINVAL; 521 522 if (amdgpu_sriov_vf(psp->adev)) 523 return 0; 524 525 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 526 if (!cmd) 527 return -ENOMEM; 528 529 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 530 531 ret = psp_cmd_submit_buf(psp, NULL, cmd, 532 psp->fence_buf_mc_addr); 533 534 if (!ret) { 535 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 536 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 537 } 538 539 kfree(cmd); 540 541 return ret; 542 } 543 544 static int psp_boot_config_set(struct amdgpu_device *adev) 545 { 546 struct psp_context *psp = &adev->psp; 547 struct psp_gfx_cmd_resp *cmd = psp->cmd; 548 549 if (amdgpu_sriov_vf(adev)) 550 return 0; 551 552 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 553 554 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 555 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 556 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 557 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 558 559 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 560 } 561 562 static int psp_rl_load(struct amdgpu_device *adev) 563 { 564 struct psp_context *psp = &adev->psp; 565 struct psp_gfx_cmd_resp *cmd = psp->cmd; 566 567 if (psp->rl_bin_size == 0) 568 return 0; 569 570 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 571 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 572 573 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 574 575 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 576 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 577 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 578 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 579 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 580 581 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 582 } 583 584 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 585 uint64_t asd_mc, uint32_t size) 586 { 587 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 588 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 589 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 590 cmd->cmd.cmd_load_ta.app_len = size; 591 592 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 593 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 594 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 595 } 596 597 static int psp_asd_load(struct psp_context *psp) 598 { 599 int ret; 600 struct psp_gfx_cmd_resp *cmd; 601 602 /* If PSP version doesn't match ASD version, asd loading will be failed. 603 * add workaround to bypass it for sriov now. 604 * TODO: add version check to make it common 605 */ 606 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 607 return 0; 608 609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 610 if (!cmd) 611 return -ENOMEM; 612 613 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 614 615 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 616 psp->asd_ucode_size); 617 618 ret = psp_cmd_submit_buf(psp, NULL, cmd, 619 psp->fence_buf_mc_addr); 620 if (!ret) { 621 psp->asd_context.asd_initialized = true; 622 psp->asd_context.session_id = cmd->resp.session_id; 623 } 624 625 kfree(cmd); 626 627 return ret; 628 } 629 630 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 631 uint32_t session_id) 632 { 633 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 634 cmd->cmd.cmd_unload_ta.session_id = session_id; 635 } 636 637 static int psp_asd_unload(struct psp_context *psp) 638 { 639 int ret; 640 struct psp_gfx_cmd_resp *cmd; 641 642 if (amdgpu_sriov_vf(psp->adev)) 643 return 0; 644 645 if (!psp->asd_context.asd_initialized) 646 return 0; 647 648 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 649 if (!cmd) 650 return -ENOMEM; 651 652 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 653 654 ret = psp_cmd_submit_buf(psp, NULL, cmd, 655 psp->fence_buf_mc_addr); 656 if (!ret) 657 psp->asd_context.asd_initialized = false; 658 659 kfree(cmd); 660 661 return ret; 662 } 663 664 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 665 uint32_t id, uint32_t value) 666 { 667 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 668 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 669 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 670 } 671 672 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 673 uint32_t value) 674 { 675 struct psp_gfx_cmd_resp *cmd = NULL; 676 int ret = 0; 677 678 if (reg >= PSP_REG_LAST) 679 return -EINVAL; 680 681 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 682 if (!cmd) 683 return -ENOMEM; 684 685 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 686 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 687 688 kfree(cmd); 689 return ret; 690 } 691 692 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 693 uint64_t ta_bin_mc, 694 uint32_t ta_bin_size, 695 uint64_t ta_shared_mc, 696 uint32_t ta_shared_size) 697 { 698 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 699 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 700 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 701 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 702 703 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 704 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 705 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 706 } 707 708 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 709 { 710 int ret; 711 712 /* 713 * Allocate 16k memory aligned to 4k from Frame Buffer (local 714 * physical) for xgmi ta <-> Driver 715 */ 716 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 717 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 718 &psp->xgmi_context.xgmi_shared_bo, 719 &psp->xgmi_context.xgmi_shared_mc_addr, 720 &psp->xgmi_context.xgmi_shared_buf); 721 722 return ret; 723 } 724 725 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 726 uint32_t ta_cmd_id, 727 uint32_t session_id) 728 { 729 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 730 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 731 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 732 } 733 734 static int psp_ta_invoke(struct psp_context *psp, 735 uint32_t ta_cmd_id, 736 uint32_t session_id) 737 { 738 int ret; 739 struct psp_gfx_cmd_resp *cmd; 740 741 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 742 if (!cmd) 743 return -ENOMEM; 744 745 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 746 747 ret = psp_cmd_submit_buf(psp, NULL, cmd, 748 psp->fence_buf_mc_addr); 749 750 kfree(cmd); 751 752 return ret; 753 } 754 755 static int psp_xgmi_load(struct psp_context *psp) 756 { 757 int ret; 758 struct psp_gfx_cmd_resp *cmd; 759 760 /* 761 * TODO: bypass the loading in sriov for now 762 */ 763 764 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 765 if (!cmd) 766 return -ENOMEM; 767 768 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 769 770 psp_prep_ta_load_cmd_buf(cmd, 771 psp->fw_pri_mc_addr, 772 psp->ta_xgmi_ucode_size, 773 psp->xgmi_context.xgmi_shared_mc_addr, 774 PSP_XGMI_SHARED_MEM_SIZE); 775 776 ret = psp_cmd_submit_buf(psp, NULL, cmd, 777 psp->fence_buf_mc_addr); 778 779 if (!ret) { 780 psp->xgmi_context.initialized = 1; 781 psp->xgmi_context.session_id = cmd->resp.session_id; 782 } 783 784 kfree(cmd); 785 786 return ret; 787 } 788 789 static int psp_xgmi_unload(struct psp_context *psp) 790 { 791 int ret; 792 struct psp_gfx_cmd_resp *cmd; 793 struct amdgpu_device *adev = psp->adev; 794 795 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 796 if (adev->asic_type == CHIP_ARCTURUS || 797 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 798 return 0; 799 800 /* 801 * TODO: bypass the unloading in sriov for now 802 */ 803 804 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 805 if (!cmd) 806 return -ENOMEM; 807 808 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 809 810 ret = psp_cmd_submit_buf(psp, NULL, cmd, 811 psp->fence_buf_mc_addr); 812 813 kfree(cmd); 814 815 return ret; 816 } 817 818 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 819 { 820 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 821 } 822 823 int psp_xgmi_terminate(struct psp_context *psp) 824 { 825 int ret; 826 827 if (!psp->xgmi_context.initialized) 828 return 0; 829 830 ret = psp_xgmi_unload(psp); 831 if (ret) 832 return ret; 833 834 psp->xgmi_context.initialized = 0; 835 836 /* free xgmi shared memory */ 837 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 838 &psp->xgmi_context.xgmi_shared_mc_addr, 839 &psp->xgmi_context.xgmi_shared_buf); 840 841 return 0; 842 } 843 844 int psp_xgmi_initialize(struct psp_context *psp) 845 { 846 struct ta_xgmi_shared_memory *xgmi_cmd; 847 int ret; 848 849 if (!psp->adev->psp.ta_fw || 850 !psp->adev->psp.ta_xgmi_ucode_size || 851 !psp->adev->psp.ta_xgmi_start_addr) 852 return -ENOENT; 853 854 if (!psp->xgmi_context.initialized) { 855 ret = psp_xgmi_init_shared_buf(psp); 856 if (ret) 857 return ret; 858 } 859 860 /* Load XGMI TA */ 861 ret = psp_xgmi_load(psp); 862 if (ret) 863 return ret; 864 865 /* Initialize XGMI session */ 866 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 867 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 868 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 869 870 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 871 872 return ret; 873 } 874 875 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 876 { 877 struct ta_xgmi_shared_memory *xgmi_cmd; 878 int ret; 879 880 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 881 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 882 883 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 884 885 /* Invoke xgmi ta to get hive id */ 886 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 887 if (ret) 888 return ret; 889 890 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 891 892 return 0; 893 } 894 895 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 896 { 897 struct ta_xgmi_shared_memory *xgmi_cmd; 898 int ret; 899 900 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 901 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 902 903 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 904 905 /* Invoke xgmi ta to get the node id */ 906 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 907 if (ret) 908 return ret; 909 910 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 911 912 return 0; 913 } 914 915 int psp_xgmi_get_topology_info(struct psp_context *psp, 916 int number_devices, 917 struct psp_xgmi_topology_info *topology) 918 { 919 struct ta_xgmi_shared_memory *xgmi_cmd; 920 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 921 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 922 int i; 923 int ret; 924 925 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 926 return -EINVAL; 927 928 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 929 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 930 931 /* Fill in the shared memory with topology information as input */ 932 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 933 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 934 topology_info_input->num_nodes = number_devices; 935 936 for (i = 0; i < topology_info_input->num_nodes; i++) { 937 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 938 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 939 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 940 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 941 } 942 943 /* Invoke xgmi ta to get the topology information */ 944 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 945 if (ret) 946 return ret; 947 948 /* Read the output topology information from the shared memory */ 949 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 950 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 951 for (i = 0; i < topology->num_nodes; i++) { 952 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 953 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 954 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 955 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 956 } 957 958 return 0; 959 } 960 961 int psp_xgmi_set_topology_info(struct psp_context *psp, 962 int number_devices, 963 struct psp_xgmi_topology_info *topology) 964 { 965 struct ta_xgmi_shared_memory *xgmi_cmd; 966 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 967 int i; 968 969 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 970 return -EINVAL; 971 972 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 973 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 974 975 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 976 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 977 topology_info_input->num_nodes = number_devices; 978 979 for (i = 0; i < topology_info_input->num_nodes; i++) { 980 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 981 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 982 topology_info_input->nodes[i].is_sharing_enabled = 1; 983 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 984 } 985 986 /* Invoke xgmi ta to set topology information */ 987 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 988 } 989 990 // ras begin 991 static int psp_ras_init_shared_buf(struct psp_context *psp) 992 { 993 int ret; 994 995 /* 996 * Allocate 16k memory aligned to 4k from Frame Buffer (local 997 * physical) for ras ta <-> Driver 998 */ 999 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1000 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1001 &psp->ras.ras_shared_bo, 1002 &psp->ras.ras_shared_mc_addr, 1003 &psp->ras.ras_shared_buf); 1004 1005 return ret; 1006 } 1007 1008 static int psp_ras_load(struct psp_context *psp) 1009 { 1010 int ret; 1011 struct psp_gfx_cmd_resp *cmd; 1012 struct ta_ras_shared_memory *ras_cmd; 1013 1014 /* 1015 * TODO: bypass the loading in sriov for now 1016 */ 1017 if (amdgpu_sriov_vf(psp->adev)) 1018 return 0; 1019 1020 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1021 if (!cmd) 1022 return -ENOMEM; 1023 1024 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1025 1026 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1027 1028 if (psp->adev->gmc.xgmi.connected_to_cpu) 1029 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1030 else 1031 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1032 1033 psp_prep_ta_load_cmd_buf(cmd, 1034 psp->fw_pri_mc_addr, 1035 psp->ta_ras_ucode_size, 1036 psp->ras.ras_shared_mc_addr, 1037 PSP_RAS_SHARED_MEM_SIZE); 1038 1039 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1040 psp->fence_buf_mc_addr); 1041 1042 if (!ret) { 1043 psp->ras.session_id = cmd->resp.session_id; 1044 1045 if (!ras_cmd->ras_status) 1046 psp->ras.ras_initialized = true; 1047 else 1048 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1049 } 1050 1051 if (ret || ras_cmd->ras_status) 1052 amdgpu_ras_fini(psp->adev); 1053 1054 kfree(cmd); 1055 1056 return ret; 1057 } 1058 1059 static int psp_ras_unload(struct psp_context *psp) 1060 { 1061 int ret; 1062 struct psp_gfx_cmd_resp *cmd; 1063 1064 /* 1065 * TODO: bypass the unloading in sriov for now 1066 */ 1067 if (amdgpu_sriov_vf(psp->adev)) 1068 return 0; 1069 1070 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1071 if (!cmd) 1072 return -ENOMEM; 1073 1074 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1075 1076 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1077 psp->fence_buf_mc_addr); 1078 1079 kfree(cmd); 1080 1081 return ret; 1082 } 1083 1084 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1085 { 1086 struct ta_ras_shared_memory *ras_cmd; 1087 int ret; 1088 1089 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1090 1091 /* 1092 * TODO: bypass the loading in sriov for now 1093 */ 1094 if (amdgpu_sriov_vf(psp->adev)) 1095 return 0; 1096 1097 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1098 1099 if (amdgpu_ras_intr_triggered()) 1100 return ret; 1101 1102 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1103 { 1104 DRM_WARN("RAS: Unsupported Interface"); 1105 return -EINVAL; 1106 } 1107 1108 if (!ret) { 1109 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1110 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1111 1112 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1113 } 1114 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1115 dev_warn(psp->adev->dev, 1116 "RAS internal register access blocked\n"); 1117 } 1118 1119 return ret; 1120 } 1121 1122 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1123 enum ta_ras_status ras_status) 1124 { 1125 int ret = -EINVAL; 1126 1127 switch (ras_status) { 1128 case TA_RAS_STATUS__SUCCESS: 1129 ret = 0; 1130 break; 1131 case TA_RAS_STATUS__RESET_NEEDED: 1132 ret = -EAGAIN; 1133 break; 1134 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1135 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1136 break; 1137 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1138 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1139 break; 1140 default: 1141 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1142 } 1143 1144 return ret; 1145 } 1146 1147 int psp_ras_enable_features(struct psp_context *psp, 1148 union ta_ras_cmd_input *info, bool enable) 1149 { 1150 struct ta_ras_shared_memory *ras_cmd; 1151 int ret; 1152 1153 if (!psp->ras.ras_initialized) 1154 return -EINVAL; 1155 1156 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1157 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1158 1159 if (enable) 1160 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1161 else 1162 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1163 1164 ras_cmd->ras_in_message = *info; 1165 1166 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1167 if (ret) 1168 return -EINVAL; 1169 1170 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1171 } 1172 1173 static int psp_ras_terminate(struct psp_context *psp) 1174 { 1175 int ret; 1176 1177 /* 1178 * TODO: bypass the terminate in sriov for now 1179 */ 1180 if (amdgpu_sriov_vf(psp->adev)) 1181 return 0; 1182 1183 if (!psp->ras.ras_initialized) 1184 return 0; 1185 1186 ret = psp_ras_unload(psp); 1187 if (ret) 1188 return ret; 1189 1190 psp->ras.ras_initialized = false; 1191 1192 /* free ras shared memory */ 1193 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1194 &psp->ras.ras_shared_mc_addr, 1195 &psp->ras.ras_shared_buf); 1196 1197 return 0; 1198 } 1199 1200 static int psp_ras_initialize(struct psp_context *psp) 1201 { 1202 int ret; 1203 1204 /* 1205 * TODO: bypass the initialize in sriov for now 1206 */ 1207 if (amdgpu_sriov_vf(psp->adev)) 1208 return 0; 1209 1210 if (!psp->adev->psp.ta_ras_ucode_size || 1211 !psp->adev->psp.ta_ras_start_addr) { 1212 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1213 return 0; 1214 } 1215 1216 if (!psp->ras.ras_initialized) { 1217 ret = psp_ras_init_shared_buf(psp); 1218 if (ret) 1219 return ret; 1220 } 1221 1222 ret = psp_ras_load(psp); 1223 if (ret) 1224 return ret; 1225 1226 return 0; 1227 } 1228 1229 int psp_ras_trigger_error(struct psp_context *psp, 1230 struct ta_ras_trigger_error_input *info) 1231 { 1232 struct ta_ras_shared_memory *ras_cmd; 1233 int ret; 1234 1235 if (!psp->ras.ras_initialized) 1236 return -EINVAL; 1237 1238 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1239 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1240 1241 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1242 ras_cmd->ras_in_message.trigger_error = *info; 1243 1244 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1245 if (ret) 1246 return -EINVAL; 1247 1248 /* If err_event_athub occurs error inject was successful, however 1249 return status from TA is no long reliable */ 1250 if (amdgpu_ras_intr_triggered()) 1251 return 0; 1252 1253 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1254 } 1255 // ras end 1256 1257 // HDCP start 1258 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1259 { 1260 int ret; 1261 1262 /* 1263 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1264 * physical) for hdcp ta <-> Driver 1265 */ 1266 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1267 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1268 &psp->hdcp_context.hdcp_shared_bo, 1269 &psp->hdcp_context.hdcp_shared_mc_addr, 1270 &psp->hdcp_context.hdcp_shared_buf); 1271 1272 return ret; 1273 } 1274 1275 static int psp_hdcp_load(struct psp_context *psp) 1276 { 1277 int ret; 1278 struct psp_gfx_cmd_resp *cmd; 1279 1280 /* 1281 * TODO: bypass the loading in sriov for now 1282 */ 1283 if (amdgpu_sriov_vf(psp->adev)) 1284 return 0; 1285 1286 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1287 if (!cmd) 1288 return -ENOMEM; 1289 1290 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1291 psp->ta_hdcp_ucode_size); 1292 1293 psp_prep_ta_load_cmd_buf(cmd, 1294 psp->fw_pri_mc_addr, 1295 psp->ta_hdcp_ucode_size, 1296 psp->hdcp_context.hdcp_shared_mc_addr, 1297 PSP_HDCP_SHARED_MEM_SIZE); 1298 1299 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1300 1301 if (!ret) { 1302 psp->hdcp_context.hdcp_initialized = true; 1303 psp->hdcp_context.session_id = cmd->resp.session_id; 1304 mutex_init(&psp->hdcp_context.mutex); 1305 } 1306 1307 kfree(cmd); 1308 1309 return ret; 1310 } 1311 static int psp_hdcp_initialize(struct psp_context *psp) 1312 { 1313 int ret; 1314 1315 /* 1316 * TODO: bypass the initialize in sriov for now 1317 */ 1318 if (amdgpu_sriov_vf(psp->adev)) 1319 return 0; 1320 1321 if (!psp->adev->psp.ta_hdcp_ucode_size || 1322 !psp->adev->psp.ta_hdcp_start_addr) { 1323 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1324 return 0; 1325 } 1326 1327 if (!psp->hdcp_context.hdcp_initialized) { 1328 ret = psp_hdcp_init_shared_buf(psp); 1329 if (ret) 1330 return ret; 1331 } 1332 1333 ret = psp_hdcp_load(psp); 1334 if (ret) 1335 return ret; 1336 1337 return 0; 1338 } 1339 1340 static int psp_hdcp_unload(struct psp_context *psp) 1341 { 1342 int ret; 1343 struct psp_gfx_cmd_resp *cmd; 1344 1345 /* 1346 * TODO: bypass the unloading in sriov for now 1347 */ 1348 if (amdgpu_sriov_vf(psp->adev)) 1349 return 0; 1350 1351 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1352 if (!cmd) 1353 return -ENOMEM; 1354 1355 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1356 1357 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1358 1359 kfree(cmd); 1360 1361 return ret; 1362 } 1363 1364 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1365 { 1366 /* 1367 * TODO: bypass the loading in sriov for now 1368 */ 1369 if (amdgpu_sriov_vf(psp->adev)) 1370 return 0; 1371 1372 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1373 } 1374 1375 static int psp_hdcp_terminate(struct psp_context *psp) 1376 { 1377 int ret; 1378 1379 /* 1380 * TODO: bypass the terminate in sriov for now 1381 */ 1382 if (amdgpu_sriov_vf(psp->adev)) 1383 return 0; 1384 1385 if (!psp->hdcp_context.hdcp_initialized) { 1386 if (psp->hdcp_context.hdcp_shared_buf) 1387 goto out; 1388 else 1389 return 0; 1390 } 1391 1392 ret = psp_hdcp_unload(psp); 1393 if (ret) 1394 return ret; 1395 1396 psp->hdcp_context.hdcp_initialized = false; 1397 1398 out: 1399 /* free hdcp shared memory */ 1400 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1401 &psp->hdcp_context.hdcp_shared_mc_addr, 1402 &psp->hdcp_context.hdcp_shared_buf); 1403 1404 return 0; 1405 } 1406 // HDCP end 1407 1408 // DTM start 1409 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1410 { 1411 int ret; 1412 1413 /* 1414 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1415 * physical) for dtm ta <-> Driver 1416 */ 1417 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1418 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1419 &psp->dtm_context.dtm_shared_bo, 1420 &psp->dtm_context.dtm_shared_mc_addr, 1421 &psp->dtm_context.dtm_shared_buf); 1422 1423 return ret; 1424 } 1425 1426 static int psp_dtm_load(struct psp_context *psp) 1427 { 1428 int ret; 1429 struct psp_gfx_cmd_resp *cmd; 1430 1431 /* 1432 * TODO: bypass the loading in sriov for now 1433 */ 1434 if (amdgpu_sriov_vf(psp->adev)) 1435 return 0; 1436 1437 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1438 if (!cmd) 1439 return -ENOMEM; 1440 1441 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1442 1443 psp_prep_ta_load_cmd_buf(cmd, 1444 psp->fw_pri_mc_addr, 1445 psp->ta_dtm_ucode_size, 1446 psp->dtm_context.dtm_shared_mc_addr, 1447 PSP_DTM_SHARED_MEM_SIZE); 1448 1449 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1450 1451 if (!ret) { 1452 psp->dtm_context.dtm_initialized = true; 1453 psp->dtm_context.session_id = cmd->resp.session_id; 1454 mutex_init(&psp->dtm_context.mutex); 1455 } 1456 1457 kfree(cmd); 1458 1459 return ret; 1460 } 1461 1462 static int psp_dtm_initialize(struct psp_context *psp) 1463 { 1464 int ret; 1465 1466 /* 1467 * TODO: bypass the initialize in sriov for now 1468 */ 1469 if (amdgpu_sriov_vf(psp->adev)) 1470 return 0; 1471 1472 if (!psp->adev->psp.ta_dtm_ucode_size || 1473 !psp->adev->psp.ta_dtm_start_addr) { 1474 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1475 return 0; 1476 } 1477 1478 if (!psp->dtm_context.dtm_initialized) { 1479 ret = psp_dtm_init_shared_buf(psp); 1480 if (ret) 1481 return ret; 1482 } 1483 1484 ret = psp_dtm_load(psp); 1485 if (ret) 1486 return ret; 1487 1488 return 0; 1489 } 1490 1491 static int psp_dtm_unload(struct psp_context *psp) 1492 { 1493 int ret; 1494 struct psp_gfx_cmd_resp *cmd; 1495 1496 /* 1497 * TODO: bypass the unloading in sriov for now 1498 */ 1499 if (amdgpu_sriov_vf(psp->adev)) 1500 return 0; 1501 1502 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1503 if (!cmd) 1504 return -ENOMEM; 1505 1506 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1507 1508 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1509 1510 kfree(cmd); 1511 1512 return ret; 1513 } 1514 1515 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1516 { 1517 /* 1518 * TODO: bypass the loading in sriov for now 1519 */ 1520 if (amdgpu_sriov_vf(psp->adev)) 1521 return 0; 1522 1523 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1524 } 1525 1526 static int psp_dtm_terminate(struct psp_context *psp) 1527 { 1528 int ret; 1529 1530 /* 1531 * TODO: bypass the terminate in sriov for now 1532 */ 1533 if (amdgpu_sriov_vf(psp->adev)) 1534 return 0; 1535 1536 if (!psp->dtm_context.dtm_initialized) { 1537 if (psp->dtm_context.dtm_shared_buf) 1538 goto out; 1539 else 1540 return 0; 1541 } 1542 1543 ret = psp_dtm_unload(psp); 1544 if (ret) 1545 return ret; 1546 1547 psp->dtm_context.dtm_initialized = false; 1548 1549 out: 1550 /* free hdcp shared memory */ 1551 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1552 &psp->dtm_context.dtm_shared_mc_addr, 1553 &psp->dtm_context.dtm_shared_buf); 1554 1555 return 0; 1556 } 1557 // DTM end 1558 1559 // RAP start 1560 static int psp_rap_init_shared_buf(struct psp_context *psp) 1561 { 1562 int ret; 1563 1564 /* 1565 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1566 * physical) for rap ta <-> Driver 1567 */ 1568 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1569 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1570 &psp->rap_context.rap_shared_bo, 1571 &psp->rap_context.rap_shared_mc_addr, 1572 &psp->rap_context.rap_shared_buf); 1573 1574 return ret; 1575 } 1576 1577 static int psp_rap_load(struct psp_context *psp) 1578 { 1579 int ret; 1580 struct psp_gfx_cmd_resp *cmd; 1581 1582 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1583 if (!cmd) 1584 return -ENOMEM; 1585 1586 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1587 1588 psp_prep_ta_load_cmd_buf(cmd, 1589 psp->fw_pri_mc_addr, 1590 psp->ta_rap_ucode_size, 1591 psp->rap_context.rap_shared_mc_addr, 1592 PSP_RAP_SHARED_MEM_SIZE); 1593 1594 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1595 1596 if (!ret) { 1597 psp->rap_context.rap_initialized = true; 1598 psp->rap_context.session_id = cmd->resp.session_id; 1599 mutex_init(&psp->rap_context.mutex); 1600 } 1601 1602 kfree(cmd); 1603 1604 return ret; 1605 } 1606 1607 static int psp_rap_unload(struct psp_context *psp) 1608 { 1609 int ret; 1610 struct psp_gfx_cmd_resp *cmd; 1611 1612 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1613 if (!cmd) 1614 return -ENOMEM; 1615 1616 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1617 1618 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1619 1620 kfree(cmd); 1621 1622 return ret; 1623 } 1624 1625 static int psp_rap_initialize(struct psp_context *psp) 1626 { 1627 int ret; 1628 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1629 1630 /* 1631 * TODO: bypass the initialize in sriov for now 1632 */ 1633 if (amdgpu_sriov_vf(psp->adev)) 1634 return 0; 1635 1636 if (!psp->adev->psp.ta_rap_ucode_size || 1637 !psp->adev->psp.ta_rap_start_addr) { 1638 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1639 return 0; 1640 } 1641 1642 if (!psp->rap_context.rap_initialized) { 1643 ret = psp_rap_init_shared_buf(psp); 1644 if (ret) 1645 return ret; 1646 } 1647 1648 ret = psp_rap_load(psp); 1649 if (ret) 1650 return ret; 1651 1652 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1653 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1654 psp_rap_unload(psp); 1655 1656 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1657 &psp->rap_context.rap_shared_mc_addr, 1658 &psp->rap_context.rap_shared_buf); 1659 1660 psp->rap_context.rap_initialized = false; 1661 1662 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1663 ret, status); 1664 1665 return ret; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int psp_rap_terminate(struct psp_context *psp) 1672 { 1673 int ret; 1674 1675 if (!psp->rap_context.rap_initialized) 1676 return 0; 1677 1678 ret = psp_rap_unload(psp); 1679 1680 psp->rap_context.rap_initialized = false; 1681 1682 /* free rap shared memory */ 1683 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1684 &psp->rap_context.rap_shared_mc_addr, 1685 &psp->rap_context.rap_shared_buf); 1686 1687 return ret; 1688 } 1689 1690 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1691 { 1692 struct ta_rap_shared_memory *rap_cmd; 1693 int ret = 0; 1694 1695 if (!psp->rap_context.rap_initialized) 1696 return 0; 1697 1698 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1699 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1700 return -EINVAL; 1701 1702 mutex_lock(&psp->rap_context.mutex); 1703 1704 rap_cmd = (struct ta_rap_shared_memory *) 1705 psp->rap_context.rap_shared_buf; 1706 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1707 1708 rap_cmd->cmd_id = ta_cmd_id; 1709 rap_cmd->validation_method_id = METHOD_A; 1710 1711 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1712 if (ret) 1713 goto out_unlock; 1714 1715 if (status) 1716 *status = rap_cmd->rap_status; 1717 1718 out_unlock: 1719 mutex_unlock(&psp->rap_context.mutex); 1720 1721 return ret; 1722 } 1723 // RAP end 1724 1725 /* securedisplay start */ 1726 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1727 { 1728 int ret; 1729 1730 /* 1731 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1732 * physical) for sa ta <-> Driver 1733 */ 1734 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1735 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1736 &psp->securedisplay_context.securedisplay_shared_bo, 1737 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1738 &psp->securedisplay_context.securedisplay_shared_buf); 1739 1740 return ret; 1741 } 1742 1743 static int psp_securedisplay_load(struct psp_context *psp) 1744 { 1745 int ret; 1746 struct psp_gfx_cmd_resp *cmd; 1747 1748 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1749 if (!cmd) 1750 return -ENOMEM; 1751 1752 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1753 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1754 1755 psp_prep_ta_load_cmd_buf(cmd, 1756 psp->fw_pri_mc_addr, 1757 psp->ta_securedisplay_ucode_size, 1758 psp->securedisplay_context.securedisplay_shared_mc_addr, 1759 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1760 1761 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1762 1763 if (ret) 1764 goto failed; 1765 1766 psp->securedisplay_context.securedisplay_initialized = true; 1767 psp->securedisplay_context.session_id = cmd->resp.session_id; 1768 mutex_init(&psp->securedisplay_context.mutex); 1769 1770 failed: 1771 kfree(cmd); 1772 return ret; 1773 } 1774 1775 static int psp_securedisplay_unload(struct psp_context *psp) 1776 { 1777 int ret; 1778 struct psp_gfx_cmd_resp *cmd; 1779 1780 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1781 if (!cmd) 1782 return -ENOMEM; 1783 1784 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1785 1786 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1787 1788 kfree(cmd); 1789 1790 return ret; 1791 } 1792 1793 static int psp_securedisplay_initialize(struct psp_context *psp) 1794 { 1795 int ret; 1796 struct securedisplay_cmd *securedisplay_cmd; 1797 1798 /* 1799 * TODO: bypass the initialize in sriov for now 1800 */ 1801 if (amdgpu_sriov_vf(psp->adev)) 1802 return 0; 1803 1804 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1805 !psp->adev->psp.ta_securedisplay_start_addr) { 1806 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1807 return 0; 1808 } 1809 1810 if (!psp->securedisplay_context.securedisplay_initialized) { 1811 ret = psp_securedisplay_init_shared_buf(psp); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 ret = psp_securedisplay_load(psp); 1817 if (ret) 1818 return ret; 1819 1820 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1821 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1822 1823 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1824 if (ret) { 1825 psp_securedisplay_unload(psp); 1826 1827 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1828 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1829 &psp->securedisplay_context.securedisplay_shared_buf); 1830 1831 psp->securedisplay_context.securedisplay_initialized = false; 1832 1833 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1834 return -EINVAL; 1835 } 1836 1837 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1838 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1839 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1840 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int psp_securedisplay_terminate(struct psp_context *psp) 1847 { 1848 int ret; 1849 1850 /* 1851 * TODO:bypass the terminate in sriov for now 1852 */ 1853 if (amdgpu_sriov_vf(psp->adev)) 1854 return 0; 1855 1856 if (!psp->securedisplay_context.securedisplay_initialized) 1857 return 0; 1858 1859 ret = psp_securedisplay_unload(psp); 1860 if (ret) 1861 return ret; 1862 1863 psp->securedisplay_context.securedisplay_initialized = false; 1864 1865 /* free securedisplay shared memory */ 1866 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1867 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1868 &psp->securedisplay_context.securedisplay_shared_buf); 1869 1870 return ret; 1871 } 1872 1873 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1874 { 1875 int ret; 1876 1877 if (!psp->securedisplay_context.securedisplay_initialized) 1878 return -EINVAL; 1879 1880 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1881 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1882 return -EINVAL; 1883 1884 mutex_lock(&psp->securedisplay_context.mutex); 1885 1886 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1887 1888 mutex_unlock(&psp->securedisplay_context.mutex); 1889 1890 return ret; 1891 } 1892 /* SECUREDISPLAY end */ 1893 1894 static int psp_hw_start(struct psp_context *psp) 1895 { 1896 struct amdgpu_device *adev = psp->adev; 1897 int ret; 1898 1899 if (!amdgpu_sriov_vf(adev)) { 1900 if (psp->kdb_bin_size && 1901 (psp->funcs->bootloader_load_kdb != NULL)) { 1902 ret = psp_bootloader_load_kdb(psp); 1903 if (ret) { 1904 DRM_ERROR("PSP load kdb failed!\n"); 1905 return ret; 1906 } 1907 } 1908 1909 if (psp->spl_bin_size) { 1910 ret = psp_bootloader_load_spl(psp); 1911 if (ret) { 1912 DRM_ERROR("PSP load spl failed!\n"); 1913 return ret; 1914 } 1915 } 1916 1917 ret = psp_bootloader_load_sysdrv(psp); 1918 if (ret) { 1919 DRM_ERROR("PSP load sysdrv failed!\n"); 1920 return ret; 1921 } 1922 1923 ret = psp_bootloader_load_sos(psp); 1924 if (ret) { 1925 DRM_ERROR("PSP load sos failed!\n"); 1926 return ret; 1927 } 1928 } 1929 1930 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1931 if (ret) { 1932 DRM_ERROR("PSP create ring failed!\n"); 1933 return ret; 1934 } 1935 1936 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1937 ret = psp_boot_config_set(adev); 1938 if (ret) 1939 dev_warn(adev->dev, "PSP set boot config failed\n"); 1940 } 1941 1942 ret = psp_tmr_init(psp); 1943 if (ret) { 1944 DRM_ERROR("PSP tmr init failed!\n"); 1945 return ret; 1946 } 1947 1948 /* 1949 * For ASICs with DF Cstate management centralized 1950 * to PMFW, TMR setup should be performed after PMFW 1951 * loaded and before other non-psp firmware loaded. 1952 */ 1953 if (psp->pmfw_centralized_cstate_management) { 1954 ret = psp_load_smu_fw(psp); 1955 if (ret) 1956 return ret; 1957 } 1958 1959 ret = psp_tmr_load(psp); 1960 if (ret) { 1961 DRM_ERROR("PSP load tmr failed!\n"); 1962 return ret; 1963 } 1964 1965 return 0; 1966 } 1967 1968 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1969 enum psp_gfx_fw_type *type) 1970 { 1971 switch (ucode->ucode_id) { 1972 case AMDGPU_UCODE_ID_SDMA0: 1973 *type = GFX_FW_TYPE_SDMA0; 1974 break; 1975 case AMDGPU_UCODE_ID_SDMA1: 1976 *type = GFX_FW_TYPE_SDMA1; 1977 break; 1978 case AMDGPU_UCODE_ID_SDMA2: 1979 *type = GFX_FW_TYPE_SDMA2; 1980 break; 1981 case AMDGPU_UCODE_ID_SDMA3: 1982 *type = GFX_FW_TYPE_SDMA3; 1983 break; 1984 case AMDGPU_UCODE_ID_SDMA4: 1985 *type = GFX_FW_TYPE_SDMA4; 1986 break; 1987 case AMDGPU_UCODE_ID_SDMA5: 1988 *type = GFX_FW_TYPE_SDMA5; 1989 break; 1990 case AMDGPU_UCODE_ID_SDMA6: 1991 *type = GFX_FW_TYPE_SDMA6; 1992 break; 1993 case AMDGPU_UCODE_ID_SDMA7: 1994 *type = GFX_FW_TYPE_SDMA7; 1995 break; 1996 case AMDGPU_UCODE_ID_CP_MES: 1997 *type = GFX_FW_TYPE_CP_MES; 1998 break; 1999 case AMDGPU_UCODE_ID_CP_MES_DATA: 2000 *type = GFX_FW_TYPE_MES_STACK; 2001 break; 2002 case AMDGPU_UCODE_ID_CP_CE: 2003 *type = GFX_FW_TYPE_CP_CE; 2004 break; 2005 case AMDGPU_UCODE_ID_CP_PFP: 2006 *type = GFX_FW_TYPE_CP_PFP; 2007 break; 2008 case AMDGPU_UCODE_ID_CP_ME: 2009 *type = GFX_FW_TYPE_CP_ME; 2010 break; 2011 case AMDGPU_UCODE_ID_CP_MEC1: 2012 *type = GFX_FW_TYPE_CP_MEC; 2013 break; 2014 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2015 *type = GFX_FW_TYPE_CP_MEC_ME1; 2016 break; 2017 case AMDGPU_UCODE_ID_CP_MEC2: 2018 *type = GFX_FW_TYPE_CP_MEC; 2019 break; 2020 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2021 *type = GFX_FW_TYPE_CP_MEC_ME2; 2022 break; 2023 case AMDGPU_UCODE_ID_RLC_G: 2024 *type = GFX_FW_TYPE_RLC_G; 2025 break; 2026 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2027 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2028 break; 2029 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2030 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2031 break; 2032 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2033 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2034 break; 2035 case AMDGPU_UCODE_ID_RLC_IRAM: 2036 *type = GFX_FW_TYPE_RLC_IRAM; 2037 break; 2038 case AMDGPU_UCODE_ID_RLC_DRAM: 2039 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2040 break; 2041 case AMDGPU_UCODE_ID_SMC: 2042 *type = GFX_FW_TYPE_SMU; 2043 break; 2044 case AMDGPU_UCODE_ID_UVD: 2045 *type = GFX_FW_TYPE_UVD; 2046 break; 2047 case AMDGPU_UCODE_ID_UVD1: 2048 *type = GFX_FW_TYPE_UVD1; 2049 break; 2050 case AMDGPU_UCODE_ID_VCE: 2051 *type = GFX_FW_TYPE_VCE; 2052 break; 2053 case AMDGPU_UCODE_ID_VCN: 2054 *type = GFX_FW_TYPE_VCN; 2055 break; 2056 case AMDGPU_UCODE_ID_VCN1: 2057 *type = GFX_FW_TYPE_VCN1; 2058 break; 2059 case AMDGPU_UCODE_ID_DMCU_ERAM: 2060 *type = GFX_FW_TYPE_DMCU_ERAM; 2061 break; 2062 case AMDGPU_UCODE_ID_DMCU_INTV: 2063 *type = GFX_FW_TYPE_DMCU_ISR; 2064 break; 2065 case AMDGPU_UCODE_ID_VCN0_RAM: 2066 *type = GFX_FW_TYPE_VCN0_RAM; 2067 break; 2068 case AMDGPU_UCODE_ID_VCN1_RAM: 2069 *type = GFX_FW_TYPE_VCN1_RAM; 2070 break; 2071 case AMDGPU_UCODE_ID_DMCUB: 2072 *type = GFX_FW_TYPE_DMUB; 2073 break; 2074 case AMDGPU_UCODE_ID_MAXIMUM: 2075 default: 2076 return -EINVAL; 2077 } 2078 2079 return 0; 2080 } 2081 2082 static void psp_print_fw_hdr(struct psp_context *psp, 2083 struct amdgpu_firmware_info *ucode) 2084 { 2085 struct amdgpu_device *adev = psp->adev; 2086 struct common_firmware_header *hdr; 2087 2088 switch (ucode->ucode_id) { 2089 case AMDGPU_UCODE_ID_SDMA0: 2090 case AMDGPU_UCODE_ID_SDMA1: 2091 case AMDGPU_UCODE_ID_SDMA2: 2092 case AMDGPU_UCODE_ID_SDMA3: 2093 case AMDGPU_UCODE_ID_SDMA4: 2094 case AMDGPU_UCODE_ID_SDMA5: 2095 case AMDGPU_UCODE_ID_SDMA6: 2096 case AMDGPU_UCODE_ID_SDMA7: 2097 hdr = (struct common_firmware_header *) 2098 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2099 amdgpu_ucode_print_sdma_hdr(hdr); 2100 break; 2101 case AMDGPU_UCODE_ID_CP_CE: 2102 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2103 amdgpu_ucode_print_gfx_hdr(hdr); 2104 break; 2105 case AMDGPU_UCODE_ID_CP_PFP: 2106 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2107 amdgpu_ucode_print_gfx_hdr(hdr); 2108 break; 2109 case AMDGPU_UCODE_ID_CP_ME: 2110 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2111 amdgpu_ucode_print_gfx_hdr(hdr); 2112 break; 2113 case AMDGPU_UCODE_ID_CP_MEC1: 2114 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2115 amdgpu_ucode_print_gfx_hdr(hdr); 2116 break; 2117 case AMDGPU_UCODE_ID_RLC_G: 2118 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2119 amdgpu_ucode_print_rlc_hdr(hdr); 2120 break; 2121 case AMDGPU_UCODE_ID_SMC: 2122 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2123 amdgpu_ucode_print_smc_hdr(hdr); 2124 break; 2125 default: 2126 break; 2127 } 2128 } 2129 2130 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2131 struct psp_gfx_cmd_resp *cmd) 2132 { 2133 int ret; 2134 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2135 2136 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2137 2138 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2139 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2140 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2141 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2142 2143 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2144 if (ret) 2145 DRM_ERROR("Unknown firmware type\n"); 2146 2147 return ret; 2148 } 2149 2150 static int psp_execute_np_fw_load(struct psp_context *psp, 2151 struct amdgpu_firmware_info *ucode) 2152 { 2153 int ret = 0; 2154 2155 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2156 if (ret) 2157 return ret; 2158 2159 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2160 psp->fence_buf_mc_addr); 2161 2162 return ret; 2163 } 2164 2165 static int psp_load_smu_fw(struct psp_context *psp) 2166 { 2167 int ret; 2168 struct amdgpu_device *adev = psp->adev; 2169 struct amdgpu_firmware_info *ucode = 2170 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2171 struct amdgpu_ras *ras = psp->ras.ras; 2172 2173 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2174 return 0; 2175 2176 if ((amdgpu_in_reset(adev) && 2177 ras && adev->ras_enabled && 2178 (adev->asic_type == CHIP_ARCTURUS || 2179 adev->asic_type == CHIP_VEGA20)) || 2180 (adev->in_runpm && 2181 adev->asic_type >= CHIP_NAVI10 && 2182 adev->asic_type <= CHIP_NAVI12)) { 2183 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2184 if (ret) { 2185 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2186 } 2187 } 2188 2189 ret = psp_execute_np_fw_load(psp, ucode); 2190 2191 if (ret) 2192 DRM_ERROR("PSP load smu failed!\n"); 2193 2194 return ret; 2195 } 2196 2197 static bool fw_load_skip_check(struct psp_context *psp, 2198 struct amdgpu_firmware_info *ucode) 2199 { 2200 if (!ucode->fw) 2201 return true; 2202 2203 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2204 (psp_smu_reload_quirk(psp) || 2205 psp->autoload_supported || 2206 psp->pmfw_centralized_cstate_management)) 2207 return true; 2208 2209 if (amdgpu_sriov_vf(psp->adev) && 2210 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2211 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2212 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2213 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2214 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2215 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2216 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2217 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2218 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2219 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2220 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2221 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2222 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2223 /*skip ucode loading in SRIOV VF */ 2224 return true; 2225 2226 if (psp->autoload_supported && 2227 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2228 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2229 /* skip mec JT when autoload is enabled */ 2230 return true; 2231 2232 return false; 2233 } 2234 2235 int psp_load_fw_list(struct psp_context *psp, 2236 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2237 { 2238 int ret = 0, i; 2239 struct amdgpu_firmware_info *ucode; 2240 2241 for (i = 0; i < ucode_count; ++i) { 2242 ucode = ucode_list[i]; 2243 psp_print_fw_hdr(psp, ucode); 2244 ret = psp_execute_np_fw_load(psp, ucode); 2245 if (ret) 2246 return ret; 2247 } 2248 return ret; 2249 } 2250 2251 static int psp_np_fw_load(struct psp_context *psp) 2252 { 2253 int i, ret; 2254 struct amdgpu_firmware_info *ucode; 2255 struct amdgpu_device *adev = psp->adev; 2256 2257 if (psp->autoload_supported && 2258 !psp->pmfw_centralized_cstate_management) { 2259 ret = psp_load_smu_fw(psp); 2260 if (ret) 2261 return ret; 2262 } 2263 2264 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2265 ucode = &adev->firmware.ucode[i]; 2266 2267 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2268 !fw_load_skip_check(psp, ucode)) { 2269 ret = psp_load_smu_fw(psp); 2270 if (ret) 2271 return ret; 2272 continue; 2273 } 2274 2275 if (fw_load_skip_check(psp, ucode)) 2276 continue; 2277 2278 if (psp->autoload_supported && 2279 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2280 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2281 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2282 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2283 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2284 /* PSP only receive one SDMA fw for sienna_cichlid, 2285 * as all four sdma fw are same */ 2286 continue; 2287 2288 psp_print_fw_hdr(psp, ucode); 2289 2290 ret = psp_execute_np_fw_load(psp, ucode); 2291 if (ret) 2292 return ret; 2293 2294 /* Start rlc autoload after psp recieved all the gfx firmware */ 2295 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2296 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2297 ret = psp_rlc_autoload_start(psp); 2298 if (ret) { 2299 DRM_ERROR("Failed to start rlc autoload\n"); 2300 return ret; 2301 } 2302 } 2303 } 2304 2305 return 0; 2306 } 2307 2308 static int psp_load_fw(struct amdgpu_device *adev) 2309 { 2310 int ret; 2311 struct psp_context *psp = &adev->psp; 2312 2313 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2314 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2315 goto skip_memalloc; 2316 } 2317 2318 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2319 if (!psp->cmd) 2320 return -ENOMEM; 2321 2322 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2323 AMDGPU_GEM_DOMAIN_GTT, 2324 &psp->fw_pri_bo, 2325 &psp->fw_pri_mc_addr, 2326 &psp->fw_pri_buf); 2327 if (ret) 2328 goto failed; 2329 2330 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2331 AMDGPU_GEM_DOMAIN_VRAM, 2332 &psp->fence_buf_bo, 2333 &psp->fence_buf_mc_addr, 2334 &psp->fence_buf); 2335 if (ret) 2336 goto failed; 2337 2338 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2339 AMDGPU_GEM_DOMAIN_VRAM, 2340 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2341 (void **)&psp->cmd_buf_mem); 2342 if (ret) 2343 goto failed; 2344 2345 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2346 2347 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2348 if (ret) { 2349 DRM_ERROR("PSP ring init failed!\n"); 2350 goto failed; 2351 } 2352 2353 skip_memalloc: 2354 ret = psp_hw_start(psp); 2355 if (ret) 2356 goto failed; 2357 2358 ret = psp_np_fw_load(psp); 2359 if (ret) 2360 goto failed; 2361 2362 ret = psp_asd_load(psp); 2363 if (ret) { 2364 DRM_ERROR("PSP load asd failed!\n"); 2365 return ret; 2366 } 2367 2368 ret = psp_rl_load(adev); 2369 if (ret) { 2370 DRM_ERROR("PSP load RL failed!\n"); 2371 return ret; 2372 } 2373 2374 if (psp->adev->psp.ta_fw) { 2375 ret = psp_ras_initialize(psp); 2376 if (ret) 2377 dev_err(psp->adev->dev, 2378 "RAS: Failed to initialize RAS\n"); 2379 2380 ret = psp_hdcp_initialize(psp); 2381 if (ret) 2382 dev_err(psp->adev->dev, 2383 "HDCP: Failed to initialize HDCP\n"); 2384 2385 ret = psp_dtm_initialize(psp); 2386 if (ret) 2387 dev_err(psp->adev->dev, 2388 "DTM: Failed to initialize DTM\n"); 2389 2390 ret = psp_rap_initialize(psp); 2391 if (ret) 2392 dev_err(psp->adev->dev, 2393 "RAP: Failed to initialize RAP\n"); 2394 2395 ret = psp_securedisplay_initialize(psp); 2396 if (ret) 2397 dev_err(psp->adev->dev, 2398 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2399 } 2400 2401 return 0; 2402 2403 failed: 2404 /* 2405 * all cleanup jobs (xgmi terminate, ras terminate, 2406 * ring destroy, cmd/fence/fw buffers destory, 2407 * psp->cmd destory) are delayed to psp_hw_fini 2408 */ 2409 return ret; 2410 } 2411 2412 static int psp_hw_init(void *handle) 2413 { 2414 int ret; 2415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2416 2417 mutex_lock(&adev->firmware.mutex); 2418 /* 2419 * This sequence is just used on hw_init only once, no need on 2420 * resume. 2421 */ 2422 ret = amdgpu_ucode_init_bo(adev); 2423 if (ret) 2424 goto failed; 2425 2426 ret = psp_load_fw(adev); 2427 if (ret) { 2428 DRM_ERROR("PSP firmware loading failed\n"); 2429 goto failed; 2430 } 2431 2432 mutex_unlock(&adev->firmware.mutex); 2433 return 0; 2434 2435 failed: 2436 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2437 mutex_unlock(&adev->firmware.mutex); 2438 return -EINVAL; 2439 } 2440 2441 static int psp_hw_fini(void *handle) 2442 { 2443 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2444 struct psp_context *psp = &adev->psp; 2445 2446 if (psp->adev->psp.ta_fw) { 2447 psp_ras_terminate(psp); 2448 psp_securedisplay_terminate(psp); 2449 psp_rap_terminate(psp); 2450 psp_dtm_terminate(psp); 2451 psp_hdcp_terminate(psp); 2452 } 2453 2454 psp_asd_unload(psp); 2455 2456 psp_tmr_terminate(psp); 2457 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2458 2459 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2460 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2461 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2462 &psp->fence_buf_mc_addr, &psp->fence_buf); 2463 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2464 (void **)&psp->cmd_buf_mem); 2465 2466 kfree(psp->cmd); 2467 psp->cmd = NULL; 2468 2469 return 0; 2470 } 2471 2472 static int psp_suspend(void *handle) 2473 { 2474 int ret; 2475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2476 struct psp_context *psp = &adev->psp; 2477 2478 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2479 psp->xgmi_context.initialized == 1) { 2480 ret = psp_xgmi_terminate(psp); 2481 if (ret) { 2482 DRM_ERROR("Failed to terminate xgmi ta\n"); 2483 return ret; 2484 } 2485 } 2486 2487 if (psp->adev->psp.ta_fw) { 2488 ret = psp_ras_terminate(psp); 2489 if (ret) { 2490 DRM_ERROR("Failed to terminate ras ta\n"); 2491 return ret; 2492 } 2493 ret = psp_hdcp_terminate(psp); 2494 if (ret) { 2495 DRM_ERROR("Failed to terminate hdcp ta\n"); 2496 return ret; 2497 } 2498 ret = psp_dtm_terminate(psp); 2499 if (ret) { 2500 DRM_ERROR("Failed to terminate dtm ta\n"); 2501 return ret; 2502 } 2503 ret = psp_rap_terminate(psp); 2504 if (ret) { 2505 DRM_ERROR("Failed to terminate rap ta\n"); 2506 return ret; 2507 } 2508 ret = psp_securedisplay_terminate(psp); 2509 if (ret) { 2510 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2511 return ret; 2512 } 2513 } 2514 2515 ret = psp_asd_unload(psp); 2516 if (ret) { 2517 DRM_ERROR("Failed to unload asd\n"); 2518 return ret; 2519 } 2520 2521 ret = psp_tmr_terminate(psp); 2522 if (ret) { 2523 DRM_ERROR("Failed to terminate tmr\n"); 2524 return ret; 2525 } 2526 2527 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2528 if (ret) { 2529 DRM_ERROR("PSP ring stop failed\n"); 2530 return ret; 2531 } 2532 2533 return 0; 2534 } 2535 2536 static int psp_resume(void *handle) 2537 { 2538 int ret; 2539 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2540 struct psp_context *psp = &adev->psp; 2541 2542 DRM_INFO("PSP is resuming...\n"); 2543 2544 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2545 if (ret) { 2546 DRM_ERROR("Failed to process memory training!\n"); 2547 return ret; 2548 } 2549 2550 mutex_lock(&adev->firmware.mutex); 2551 2552 ret = psp_hw_start(psp); 2553 if (ret) 2554 goto failed; 2555 2556 ret = psp_np_fw_load(psp); 2557 if (ret) 2558 goto failed; 2559 2560 ret = psp_asd_load(psp); 2561 if (ret) { 2562 DRM_ERROR("PSP load asd failed!\n"); 2563 goto failed; 2564 } 2565 2566 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2567 ret = psp_xgmi_initialize(psp); 2568 /* Warning the XGMI seesion initialize failure 2569 * Instead of stop driver initialization 2570 */ 2571 if (ret) 2572 dev_err(psp->adev->dev, 2573 "XGMI: Failed to initialize XGMI session\n"); 2574 } 2575 2576 if (psp->adev->psp.ta_fw) { 2577 ret = psp_ras_initialize(psp); 2578 if (ret) 2579 dev_err(psp->adev->dev, 2580 "RAS: Failed to initialize RAS\n"); 2581 2582 ret = psp_hdcp_initialize(psp); 2583 if (ret) 2584 dev_err(psp->adev->dev, 2585 "HDCP: Failed to initialize HDCP\n"); 2586 2587 ret = psp_dtm_initialize(psp); 2588 if (ret) 2589 dev_err(psp->adev->dev, 2590 "DTM: Failed to initialize DTM\n"); 2591 2592 ret = psp_rap_initialize(psp); 2593 if (ret) 2594 dev_err(psp->adev->dev, 2595 "RAP: Failed to initialize RAP\n"); 2596 2597 ret = psp_securedisplay_initialize(psp); 2598 if (ret) 2599 dev_err(psp->adev->dev, 2600 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2601 } 2602 2603 mutex_unlock(&adev->firmware.mutex); 2604 2605 return 0; 2606 2607 failed: 2608 DRM_ERROR("PSP resume failed\n"); 2609 mutex_unlock(&adev->firmware.mutex); 2610 return ret; 2611 } 2612 2613 int psp_gpu_reset(struct amdgpu_device *adev) 2614 { 2615 int ret; 2616 2617 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2618 return 0; 2619 2620 mutex_lock(&adev->psp.mutex); 2621 ret = psp_mode1_reset(&adev->psp); 2622 mutex_unlock(&adev->psp.mutex); 2623 2624 return ret; 2625 } 2626 2627 int psp_rlc_autoload_start(struct psp_context *psp) 2628 { 2629 int ret; 2630 struct psp_gfx_cmd_resp *cmd; 2631 2632 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2633 if (!cmd) 2634 return -ENOMEM; 2635 2636 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2637 2638 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2639 psp->fence_buf_mc_addr); 2640 kfree(cmd); 2641 return ret; 2642 } 2643 2644 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2645 uint64_t cmd_gpu_addr, int cmd_size) 2646 { 2647 struct amdgpu_firmware_info ucode = {0}; 2648 2649 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2650 AMDGPU_UCODE_ID_VCN0_RAM; 2651 ucode.mc_addr = cmd_gpu_addr; 2652 ucode.ucode_size = cmd_size; 2653 2654 return psp_execute_np_fw_load(&adev->psp, &ucode); 2655 } 2656 2657 int psp_ring_cmd_submit(struct psp_context *psp, 2658 uint64_t cmd_buf_mc_addr, 2659 uint64_t fence_mc_addr, 2660 int index) 2661 { 2662 unsigned int psp_write_ptr_reg = 0; 2663 struct psp_gfx_rb_frame *write_frame; 2664 struct psp_ring *ring = &psp->km_ring; 2665 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2666 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2667 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2668 struct amdgpu_device *adev = psp->adev; 2669 uint32_t ring_size_dw = ring->ring_size / 4; 2670 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2671 2672 /* KM (GPCOM) prepare write pointer */ 2673 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2674 2675 /* Update KM RB frame pointer to new frame */ 2676 /* write_frame ptr increments by size of rb_frame in bytes */ 2677 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2678 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2679 write_frame = ring_buffer_start; 2680 else 2681 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2682 /* Check invalid write_frame ptr address */ 2683 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2684 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2685 ring_buffer_start, ring_buffer_end, write_frame); 2686 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2687 return -EINVAL; 2688 } 2689 2690 /* Initialize KM RB frame */ 2691 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2692 2693 /* Update KM RB frame */ 2694 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2695 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2696 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2697 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2698 write_frame->fence_value = index; 2699 amdgpu_asic_flush_hdp(adev, NULL); 2700 2701 /* Update the write Pointer in DWORDs */ 2702 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2703 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2704 return 0; 2705 } 2706 2707 int psp_init_asd_microcode(struct psp_context *psp, 2708 const char *chip_name) 2709 { 2710 struct amdgpu_device *adev = psp->adev; 2711 char fw_name[PSP_FW_NAME_LEN]; 2712 const struct psp_firmware_header_v1_0 *asd_hdr; 2713 int err = 0; 2714 2715 if (!chip_name) { 2716 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2717 return -EINVAL; 2718 } 2719 2720 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2721 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2722 if (err) 2723 goto out; 2724 2725 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2726 if (err) 2727 goto out; 2728 2729 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2730 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2731 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2732 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2733 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2734 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2735 return 0; 2736 out: 2737 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2738 release_firmware(adev->psp.asd_fw); 2739 adev->psp.asd_fw = NULL; 2740 return err; 2741 } 2742 2743 int psp_init_toc_microcode(struct psp_context *psp, 2744 const char *chip_name) 2745 { 2746 struct amdgpu_device *adev = psp->adev; 2747 char fw_name[30]; 2748 const struct psp_firmware_header_v1_0 *toc_hdr; 2749 int err = 0; 2750 2751 if (!chip_name) { 2752 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2753 return -EINVAL; 2754 } 2755 2756 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2757 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2758 if (err) 2759 goto out; 2760 2761 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2762 if (err) 2763 goto out; 2764 2765 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2766 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2767 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2768 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2769 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2770 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2771 return 0; 2772 out: 2773 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2774 release_firmware(adev->psp.toc_fw); 2775 adev->psp.toc_fw = NULL; 2776 return err; 2777 } 2778 2779 int psp_init_sos_microcode(struct psp_context *psp, 2780 const char *chip_name) 2781 { 2782 struct amdgpu_device *adev = psp->adev; 2783 char fw_name[PSP_FW_NAME_LEN]; 2784 const struct psp_firmware_header_v1_0 *sos_hdr; 2785 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2786 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2787 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2788 int err = 0; 2789 2790 if (!chip_name) { 2791 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2792 return -EINVAL; 2793 } 2794 2795 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2796 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2797 if (err) 2798 goto out; 2799 2800 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2801 if (err) 2802 goto out; 2803 2804 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2805 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2806 2807 switch (sos_hdr->header.header_version_major) { 2808 case 1: 2809 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2810 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2811 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2812 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2813 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2814 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2815 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2816 le32_to_cpu(sos_hdr->sos_offset_bytes); 2817 if (sos_hdr->header.header_version_minor == 1) { 2818 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2819 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2820 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2821 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2822 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2823 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2824 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2825 } 2826 if (sos_hdr->header.header_version_minor == 2) { 2827 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2828 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2829 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2830 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2831 } 2832 if (sos_hdr->header.header_version_minor == 3) { 2833 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2834 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2835 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2836 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2837 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2838 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2839 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2840 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2841 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2842 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2843 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2844 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2845 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2846 } 2847 break; 2848 default: 2849 dev_err(adev->dev, 2850 "unsupported psp sos firmware\n"); 2851 err = -EINVAL; 2852 goto out; 2853 } 2854 2855 return 0; 2856 out: 2857 dev_err(adev->dev, 2858 "failed to init sos firmware\n"); 2859 release_firmware(adev->psp.sos_fw); 2860 adev->psp.sos_fw = NULL; 2861 2862 return err; 2863 } 2864 2865 static int parse_ta_bin_descriptor(struct psp_context *psp, 2866 const struct ta_fw_bin_desc *desc, 2867 const struct ta_firmware_header_v2_0 *ta_hdr) 2868 { 2869 uint8_t *ucode_start_addr = NULL; 2870 2871 if (!psp || !desc || !ta_hdr) 2872 return -EINVAL; 2873 2874 ucode_start_addr = (uint8_t *)ta_hdr + 2875 le32_to_cpu(desc->offset_bytes) + 2876 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2877 2878 switch (desc->fw_type) { 2879 case TA_FW_TYPE_PSP_ASD: 2880 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2881 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2882 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2883 psp->asd_start_addr = ucode_start_addr; 2884 break; 2885 case TA_FW_TYPE_PSP_XGMI: 2886 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2887 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2888 psp->ta_xgmi_start_addr = ucode_start_addr; 2889 break; 2890 case TA_FW_TYPE_PSP_RAS: 2891 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2892 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2893 psp->ta_ras_start_addr = ucode_start_addr; 2894 break; 2895 case TA_FW_TYPE_PSP_HDCP: 2896 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2897 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2898 psp->ta_hdcp_start_addr = ucode_start_addr; 2899 break; 2900 case TA_FW_TYPE_PSP_DTM: 2901 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2902 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2903 psp->ta_dtm_start_addr = ucode_start_addr; 2904 break; 2905 case TA_FW_TYPE_PSP_RAP: 2906 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2907 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2908 psp->ta_rap_start_addr = ucode_start_addr; 2909 break; 2910 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2911 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2912 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2913 psp->ta_securedisplay_start_addr = ucode_start_addr; 2914 break; 2915 default: 2916 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2917 break; 2918 } 2919 2920 return 0; 2921 } 2922 2923 int psp_init_ta_microcode(struct psp_context *psp, 2924 const char *chip_name) 2925 { 2926 struct amdgpu_device *adev = psp->adev; 2927 char fw_name[PSP_FW_NAME_LEN]; 2928 const struct ta_firmware_header_v2_0 *ta_hdr; 2929 int err = 0; 2930 int ta_index = 0; 2931 2932 if (!chip_name) { 2933 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2934 return -EINVAL; 2935 } 2936 2937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2938 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2939 if (err) 2940 goto out; 2941 2942 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2943 if (err) 2944 goto out; 2945 2946 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2947 2948 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2949 dev_err(adev->dev, "unsupported TA header version\n"); 2950 err = -EINVAL; 2951 goto out; 2952 } 2953 2954 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2955 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2956 err = -EINVAL; 2957 goto out; 2958 } 2959 2960 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2961 err = parse_ta_bin_descriptor(psp, 2962 &ta_hdr->ta_fw_bin[ta_index], 2963 ta_hdr); 2964 if (err) 2965 goto out; 2966 } 2967 2968 return 0; 2969 out: 2970 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2971 release_firmware(adev->psp.ta_fw); 2972 adev->psp.ta_fw = NULL; 2973 return err; 2974 } 2975 2976 static int psp_set_clockgating_state(void *handle, 2977 enum amd_clockgating_state state) 2978 { 2979 return 0; 2980 } 2981 2982 static int psp_set_powergating_state(void *handle, 2983 enum amd_powergating_state state) 2984 { 2985 return 0; 2986 } 2987 2988 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 2989 struct device_attribute *attr, 2990 char *buf) 2991 { 2992 struct drm_device *ddev = dev_get_drvdata(dev); 2993 struct amdgpu_device *adev = drm_to_adev(ddev); 2994 uint32_t fw_ver; 2995 int ret; 2996 2997 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 2998 DRM_INFO("PSP block is not ready yet."); 2999 return -EBUSY; 3000 } 3001 3002 mutex_lock(&adev->psp.mutex); 3003 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3004 mutex_unlock(&adev->psp.mutex); 3005 3006 if (ret) { 3007 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3008 return ret; 3009 } 3010 3011 return sysfs_emit(buf, "%x\n", fw_ver); 3012 } 3013 3014 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3015 struct device_attribute *attr, 3016 const char *buf, 3017 size_t count) 3018 { 3019 struct drm_device *ddev = dev_get_drvdata(dev); 3020 struct amdgpu_device *adev = drm_to_adev(ddev); 3021 void *cpu_addr; 3022 dma_addr_t dma_addr; 3023 int ret, idx; 3024 char fw_name[100]; 3025 const struct firmware *usbc_pd_fw; 3026 3027 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3028 DRM_INFO("PSP block is not ready yet."); 3029 return -EBUSY; 3030 } 3031 3032 if (!drm_dev_enter(ddev, &idx)) 3033 return -ENODEV; 3034 3035 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3036 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3037 if (ret) 3038 goto fail; 3039 3040 /* We need contiguous physical mem to place the FW for psp to access */ 3041 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3042 3043 ret = dma_mapping_error(adev->dev, dma_addr); 3044 if (ret) 3045 goto rel_buf; 3046 3047 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3048 3049 /* 3050 * x86 specific workaround. 3051 * Without it the buffer is invisible in PSP. 3052 * 3053 * TODO Remove once PSP starts snooping CPU cache 3054 */ 3055 #ifdef CONFIG_X86 3056 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3057 #endif 3058 3059 mutex_lock(&adev->psp.mutex); 3060 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3061 mutex_unlock(&adev->psp.mutex); 3062 3063 rel_buf: 3064 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3065 release_firmware(usbc_pd_fw); 3066 fail: 3067 if (ret) { 3068 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3069 count = ret; 3070 } 3071 3072 drm_dev_exit(idx); 3073 return count; 3074 } 3075 3076 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3077 { 3078 int idx; 3079 3080 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3081 return; 3082 3083 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3084 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3085 3086 drm_dev_exit(idx); 3087 } 3088 3089 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3090 psp_usbc_pd_fw_sysfs_read, 3091 psp_usbc_pd_fw_sysfs_write); 3092 3093 3094 3095 const struct amd_ip_funcs psp_ip_funcs = { 3096 .name = "psp", 3097 .early_init = psp_early_init, 3098 .late_init = NULL, 3099 .sw_init = psp_sw_init, 3100 .sw_fini = psp_sw_fini, 3101 .hw_init = psp_hw_init, 3102 .hw_fini = psp_hw_fini, 3103 .suspend = psp_suspend, 3104 .resume = psp_resume, 3105 .is_idle = NULL, 3106 .check_soft_reset = NULL, 3107 .wait_for_idle = NULL, 3108 .soft_reset = NULL, 3109 .set_clockgating_state = psp_set_clockgating_state, 3110 .set_powergating_state = psp_set_powergating_state, 3111 }; 3112 3113 static int psp_sysfs_init(struct amdgpu_device *adev) 3114 { 3115 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3116 3117 if (ret) 3118 DRM_ERROR("Failed to create USBC PD FW control file!"); 3119 3120 return ret; 3121 } 3122 3123 static void psp_sysfs_fini(struct amdgpu_device *adev) 3124 { 3125 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3126 } 3127 3128 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3129 { 3130 .type = AMD_IP_BLOCK_TYPE_PSP, 3131 .major = 3, 3132 .minor = 1, 3133 .rev = 0, 3134 .funcs = &psp_ip_funcs, 3135 }; 3136 3137 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3138 { 3139 .type = AMD_IP_BLOCK_TYPE_PSP, 3140 .major = 10, 3141 .minor = 0, 3142 .rev = 0, 3143 .funcs = &psp_ip_funcs, 3144 }; 3145 3146 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3147 { 3148 .type = AMD_IP_BLOCK_TYPE_PSP, 3149 .major = 11, 3150 .minor = 0, 3151 .rev = 0, 3152 .funcs = &psp_ip_funcs, 3153 }; 3154 3155 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3156 { 3157 .type = AMD_IP_BLOCK_TYPE_PSP, 3158 .major = 12, 3159 .minor = 0, 3160 .rev = 0, 3161 .funcs = &psp_ip_funcs, 3162 }; 3163 3164 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3165 .type = AMD_IP_BLOCK_TYPE_PSP, 3166 .major = 13, 3167 .minor = 0, 3168 .rev = 0, 3169 .funcs = &psp_ip_funcs, 3170 }; 3171