1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static int psp_ring_init(struct psp_context *psp, 56 enum psp_ring_type ring_type) 57 { 58 int ret = 0; 59 struct psp_ring *ring; 60 struct amdgpu_device *adev = psp->adev; 61 62 ring = &psp->km_ring; 63 64 ring->ring_type = ring_type; 65 66 /* allocate 4k Page of Local Frame Buffer memory for ring */ 67 ring->ring_size = 0x1000; 68 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 69 AMDGPU_GEM_DOMAIN_VRAM | 70 AMDGPU_GEM_DOMAIN_GTT, 71 &adev->firmware.rbuf, 72 &ring->ring_mem_mc_addr, 73 (void **)&ring->ring_mem); 74 if (ret) { 75 ring->ring_size = 0; 76 return ret; 77 } 78 79 return 0; 80 } 81 82 /* 83 * Due to DF Cstate management centralized to PMFW, the firmware 84 * loading sequence will be updated as below: 85 * - Load KDB 86 * - Load SYS_DRV 87 * - Load tOS 88 * - Load PMFW 89 * - Setup TMR 90 * - Load other non-psp fw 91 * - Load ASD 92 * - Load XGMI/RAS/HDCP/DTM TA if any 93 * 94 * This new sequence is required for 95 * - Arcturus and onwards 96 */ 97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 101 if (amdgpu_sriov_vf(adev)) { 102 psp->pmfw_centralized_cstate_management = false; 103 return; 104 } 105 106 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 107 case IP_VERSION(11, 0, 0): 108 case IP_VERSION(11, 0, 4): 109 case IP_VERSION(11, 0, 5): 110 case IP_VERSION(11, 0, 7): 111 case IP_VERSION(11, 0, 9): 112 case IP_VERSION(11, 0, 11): 113 case IP_VERSION(11, 0, 12): 114 case IP_VERSION(11, 0, 13): 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 2): 117 case IP_VERSION(13, 0, 7): 118 psp->pmfw_centralized_cstate_management = true; 119 break; 120 default: 121 psp->pmfw_centralized_cstate_management = false; 122 break; 123 } 124 } 125 126 static int psp_init_sriov_microcode(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 char ucode_prefix[30]; 130 int ret = 0; 131 132 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 133 134 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 135 case IP_VERSION(9, 0, 0): 136 case IP_VERSION(11, 0, 7): 137 case IP_VERSION(11, 0, 9): 138 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 139 ret = psp_init_cap_microcode(psp, ucode_prefix); 140 break; 141 case IP_VERSION(13, 0, 2): 142 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 143 ret = psp_init_cap_microcode(psp, ucode_prefix); 144 ret &= psp_init_ta_microcode(psp, ucode_prefix); 145 break; 146 case IP_VERSION(13, 0, 0): 147 adev->virt.autoload_ucode_id = 0; 148 break; 149 case IP_VERSION(13, 0, 6): 150 case IP_VERSION(13, 0, 14): 151 case IP_VERSION(13, 0, 15): 152 ret = psp_init_cap_microcode(psp, ucode_prefix); 153 ret &= psp_init_ta_microcode(psp, ucode_prefix); 154 break; 155 case IP_VERSION(13, 0, 10): 156 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 157 ret = psp_init_cap_microcode(psp, ucode_prefix); 158 break; 159 case IP_VERSION(13, 0, 12): 160 ret = psp_init_ta_microcode(psp, ucode_prefix); 161 break; 162 default: 163 return -EINVAL; 164 } 165 return ret; 166 } 167 168 static int psp_early_init(struct amdgpu_ip_block *ip_block) 169 { 170 struct amdgpu_device *adev = ip_block->adev; 171 struct psp_context *psp = &adev->psp; 172 173 psp->autoload_supported = true; 174 psp->boot_time_tmr = true; 175 176 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 177 case IP_VERSION(9, 0, 0): 178 psp_v3_1_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(10, 0, 0): 183 case IP_VERSION(10, 0, 1): 184 psp_v10_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 2): 189 case IP_VERSION(11, 0, 4): 190 psp_v11_0_set_psp_funcs(psp); 191 psp->autoload_supported = false; 192 psp->boot_time_tmr = false; 193 break; 194 case IP_VERSION(11, 0, 0): 195 case IP_VERSION(11, 0, 7): 196 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 197 fallthrough; 198 case IP_VERSION(11, 0, 5): 199 case IP_VERSION(11, 0, 9): 200 case IP_VERSION(11, 0, 11): 201 case IP_VERSION(11, 5, 0): 202 case IP_VERSION(11, 5, 2): 203 case IP_VERSION(11, 0, 12): 204 case IP_VERSION(11, 0, 13): 205 psp_v11_0_set_psp_funcs(psp); 206 psp->boot_time_tmr = false; 207 break; 208 case IP_VERSION(11, 0, 3): 209 case IP_VERSION(12, 0, 1): 210 psp_v12_0_set_psp_funcs(psp); 211 psp->autoload_supported = false; 212 psp->boot_time_tmr = false; 213 break; 214 case IP_VERSION(13, 0, 2): 215 psp->boot_time_tmr = false; 216 fallthrough; 217 case IP_VERSION(13, 0, 6): 218 case IP_VERSION(13, 0, 14): 219 psp_v13_0_set_psp_funcs(psp); 220 psp->autoload_supported = false; 221 break; 222 case IP_VERSION(13, 0, 12): 223 case IP_VERSION(13, 0, 15): 224 psp_v13_0_set_psp_funcs(psp); 225 psp->autoload_supported = false; 226 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 227 break; 228 case IP_VERSION(13, 0, 1): 229 case IP_VERSION(13, 0, 3): 230 case IP_VERSION(13, 0, 5): 231 case IP_VERSION(13, 0, 8): 232 case IP_VERSION(13, 0, 11): 233 case IP_VERSION(14, 0, 0): 234 case IP_VERSION(14, 0, 1): 235 case IP_VERSION(14, 0, 4): 236 psp_v13_0_set_psp_funcs(psp); 237 psp->boot_time_tmr = false; 238 break; 239 case IP_VERSION(11, 0, 8): 240 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 241 psp_v11_0_8_set_psp_funcs(psp); 242 } 243 psp->autoload_supported = false; 244 psp->boot_time_tmr = false; 245 break; 246 case IP_VERSION(13, 0, 0): 247 case IP_VERSION(13, 0, 7): 248 case IP_VERSION(13, 0, 10): 249 psp_v13_0_set_psp_funcs(psp); 250 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 251 psp->boot_time_tmr = false; 252 break; 253 case IP_VERSION(13, 0, 4): 254 psp_v13_0_4_set_psp_funcs(psp); 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(14, 0, 2): 258 case IP_VERSION(14, 0, 3): 259 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 260 psp_v14_0_set_psp_funcs(psp); 261 break; 262 case IP_VERSION(14, 0, 5): 263 psp_v14_0_set_psp_funcs(psp); 264 psp->boot_time_tmr = false; 265 break; 266 case IP_VERSION(15, 0, 0): 267 psp_v15_0_0_set_psp_funcs(psp); 268 psp->boot_time_tmr = false; 269 break; 270 case IP_VERSION(15, 0, 8): 271 psp_v15_0_8_set_psp_funcs(psp); 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 psp->adev = adev; 278 279 adev->psp_timeout = 20000; 280 281 psp_check_pmfw_centralized_cstate_management(psp); 282 283 if (amdgpu_sriov_vf(adev)) 284 return psp_init_sriov_microcode(psp); 285 else 286 return psp_init_microcode(psp); 287 } 288 289 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 290 { 291 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 292 &mem_ctx->shared_buf); 293 mem_ctx->shared_bo = NULL; 294 } 295 296 static void psp_free_shared_bufs(struct psp_context *psp) 297 { 298 void *tmr_buf; 299 void **pptr; 300 301 /* free TMR memory buffer */ 302 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 303 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 304 psp->tmr_bo = NULL; 305 306 /* free xgmi shared memory */ 307 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 308 309 /* free ras shared memory */ 310 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 311 312 /* free hdcp shared memory */ 313 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 314 315 /* free dtm shared memory */ 316 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 317 318 /* free rap shared memory */ 319 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 320 321 /* free securedisplay shared memory */ 322 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 323 324 325 } 326 327 static void psp_memory_training_fini(struct psp_context *psp) 328 { 329 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 330 331 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 332 kfree(ctx->sys_cache); 333 ctx->sys_cache = NULL; 334 } 335 336 static int psp_memory_training_init(struct psp_context *psp) 337 { 338 int ret; 339 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 340 341 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 342 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 343 return 0; 344 } 345 346 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 347 if (ctx->sys_cache == NULL) { 348 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 349 ret = -ENOMEM; 350 goto Err_out; 351 } 352 353 dev_dbg(psp->adev->dev, 354 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 355 ctx->train_data_size, 356 ctx->p2c_train_data_offset, 357 ctx->c2p_train_data_offset); 358 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 359 return 0; 360 361 Err_out: 362 psp_memory_training_fini(psp); 363 return ret; 364 } 365 366 /* 367 * Helper funciton to query psp runtime database entry 368 * 369 * @adev: amdgpu_device pointer 370 * @entry_type: the type of psp runtime database entry 371 * @db_entry: runtime database entry pointer 372 * 373 * Return false if runtime database doesn't exit or entry is invalid 374 * or true if the specific database entry is found, and copy to @db_entry 375 */ 376 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 377 enum psp_runtime_entry_type entry_type, 378 void *db_entry) 379 { 380 uint64_t db_header_pos, db_dir_pos; 381 struct psp_runtime_data_header db_header = {0}; 382 struct psp_runtime_data_directory db_dir = {0}; 383 bool ret = false; 384 int i; 385 386 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 387 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 388 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 389 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 390 return false; 391 392 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 393 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 394 395 /* read runtime db header from vram */ 396 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 397 sizeof(struct psp_runtime_data_header), false); 398 399 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 400 /* runtime db doesn't exist, exit */ 401 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 402 return false; 403 } 404 405 /* read runtime database entry from vram */ 406 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 407 sizeof(struct psp_runtime_data_directory), false); 408 409 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 410 /* invalid db entry count, exit */ 411 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 412 return false; 413 } 414 415 /* look up for requested entry type */ 416 for (i = 0; i < db_dir.entry_count && !ret; i++) { 417 if (db_dir.entry_list[i].entry_type == entry_type) { 418 switch (entry_type) { 419 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 420 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 421 /* invalid db entry size */ 422 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 423 return false; 424 } 425 /* read runtime database entry */ 426 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 427 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 428 ret = true; 429 break; 430 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 431 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 432 /* invalid db entry size */ 433 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 434 return false; 435 } 436 /* read runtime database entry */ 437 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 438 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 439 ret = true; 440 break; 441 default: 442 ret = false; 443 break; 444 } 445 } 446 } 447 448 return ret; 449 } 450 451 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 452 { 453 struct amdgpu_device *adev = ip_block->adev; 454 struct psp_context *psp = &adev->psp; 455 int ret; 456 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 457 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 458 struct psp_runtime_scpm_entry scpm_entry; 459 460 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 461 if (!psp->cmd) { 462 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 463 return -ENOMEM; 464 } 465 466 adev->psp.xgmi_context.supports_extended_data = 467 !adev->gmc.xgmi.connected_to_cpu && 468 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 469 470 memset(&scpm_entry, 0, sizeof(scpm_entry)); 471 if ((psp_get_runtime_db_entry(adev, 472 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 473 &scpm_entry)) && 474 (scpm_entry.scpm_status != SCPM_DISABLE)) { 475 adev->scpm_enabled = true; 476 adev->scpm_status = scpm_entry.scpm_status; 477 } else { 478 adev->scpm_enabled = false; 479 adev->scpm_status = SCPM_DISABLE; 480 } 481 482 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 483 484 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 485 if (psp_get_runtime_db_entry(adev, 486 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 487 &boot_cfg_entry)) { 488 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 489 if ((psp->boot_cfg_bitmask) & 490 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 491 /* If psp runtime database exists, then 492 * only enable two stage memory training 493 * when TWO_STAGE_DRAM_TRAINING bit is set 494 * in runtime database 495 */ 496 mem_training_ctx->enable_mem_training = true; 497 } 498 499 } else { 500 /* If psp runtime database doesn't exist or is 501 * invalid, force enable two stage memory training 502 */ 503 mem_training_ctx->enable_mem_training = true; 504 } 505 506 if (mem_training_ctx->enable_mem_training) { 507 ret = psp_memory_training_init(psp); 508 if (ret) { 509 dev_err(adev->dev, "Failed to initialize memory training!\n"); 510 return ret; 511 } 512 513 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 514 if (ret) { 515 dev_err(adev->dev, "Failed to process memory training!\n"); 516 return ret; 517 } 518 } 519 520 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 521 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 522 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 523 &psp->fw_pri_bo, 524 &psp->fw_pri_mc_addr, 525 &psp->fw_pri_buf); 526 if (ret) 527 return ret; 528 529 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 530 AMDGPU_GEM_DOMAIN_VRAM | 531 AMDGPU_GEM_DOMAIN_GTT, 532 &psp->fence_buf_bo, 533 &psp->fence_buf_mc_addr, 534 &psp->fence_buf); 535 if (ret) 536 goto failed1; 537 538 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 539 AMDGPU_GEM_DOMAIN_VRAM | 540 AMDGPU_GEM_DOMAIN_GTT, 541 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 542 (void **)&psp->cmd_buf_mem); 543 if (ret) 544 goto failed2; 545 546 return 0; 547 548 failed2: 549 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 550 &psp->fence_buf_mc_addr, &psp->fence_buf); 551 failed1: 552 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 553 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 554 return ret; 555 } 556 557 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 558 { 559 struct amdgpu_device *adev = ip_block->adev; 560 struct psp_context *psp = &adev->psp; 561 562 psp_memory_training_fini(psp); 563 564 amdgpu_ucode_release(&psp->sos_fw); 565 amdgpu_ucode_release(&psp->asd_fw); 566 amdgpu_ucode_release(&psp->ta_fw); 567 amdgpu_ucode_release(&psp->cap_fw); 568 amdgpu_ucode_release(&psp->toc_fw); 569 570 kfree(psp->cmd); 571 psp->cmd = NULL; 572 573 psp_free_shared_bufs(psp); 574 575 if (psp->km_ring.ring_mem) 576 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 577 &psp->km_ring.ring_mem_mc_addr, 578 (void **)&psp->km_ring.ring_mem); 579 580 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 581 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 582 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 583 &psp->fence_buf_mc_addr, &psp->fence_buf); 584 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 585 (void **)&psp->cmd_buf_mem); 586 587 return 0; 588 } 589 590 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 591 uint32_t mask, uint32_t flags) 592 { 593 bool check_changed = flags & PSP_WAITREG_CHANGED; 594 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 595 uint32_t val; 596 int i; 597 struct amdgpu_device *adev = psp->adev; 598 599 if (psp->adev->no_hw_access) 600 return 0; 601 602 for (i = 0; i < adev->usec_timeout; i++) { 603 val = RREG32(reg_index); 604 if (check_changed) { 605 if (val != reg_val) 606 return 0; 607 } else { 608 if ((val & mask) == reg_val) 609 return 0; 610 } 611 udelay(1); 612 } 613 614 if (verbose) 615 dev_err(adev->dev, 616 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 617 reg_index, mask, val, reg_val); 618 619 return -ETIME; 620 } 621 622 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 623 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 624 { 625 uint32_t val; 626 int i; 627 struct amdgpu_device *adev = psp->adev; 628 629 if (psp->adev->no_hw_access) 630 return 0; 631 632 for (i = 0; i < msec_timeout; i++) { 633 val = RREG32(reg_index); 634 if ((val & mask) == reg_val) 635 return 0; 636 msleep(1); 637 } 638 639 return -ETIME; 640 } 641 642 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 643 { 644 switch (cmd_id) { 645 case GFX_CMD_ID_LOAD_TA: 646 return "LOAD_TA"; 647 case GFX_CMD_ID_UNLOAD_TA: 648 return "UNLOAD_TA"; 649 case GFX_CMD_ID_INVOKE_CMD: 650 return "INVOKE_CMD"; 651 case GFX_CMD_ID_LOAD_ASD: 652 return "LOAD_ASD"; 653 case GFX_CMD_ID_SETUP_TMR: 654 return "SETUP_TMR"; 655 case GFX_CMD_ID_LOAD_IP_FW: 656 return "LOAD_IP_FW"; 657 case GFX_CMD_ID_DESTROY_TMR: 658 return "DESTROY_TMR"; 659 case GFX_CMD_ID_SAVE_RESTORE: 660 return "SAVE_RESTORE_IP_FW"; 661 case GFX_CMD_ID_SETUP_VMR: 662 return "SETUP_VMR"; 663 case GFX_CMD_ID_DESTROY_VMR: 664 return "DESTROY_VMR"; 665 case GFX_CMD_ID_PROG_REG: 666 return "PROG_REG"; 667 case GFX_CMD_ID_GET_FW_ATTESTATION: 668 return "GET_FW_ATTESTATION"; 669 case GFX_CMD_ID_LOAD_TOC: 670 return "ID_LOAD_TOC"; 671 case GFX_CMD_ID_AUTOLOAD_RLC: 672 return "AUTOLOAD_RLC"; 673 case GFX_CMD_ID_BOOT_CFG: 674 return "BOOT_CFG"; 675 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 676 return "CONFIG_SQ_PERFMON"; 677 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 678 return "FB_FW_RESERV_ADDR"; 679 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 680 return "FB_FW_RESERV_EXT_ADDR"; 681 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 682 return "SPATIAL_PARTITION"; 683 case GFX_CMD_ID_FB_NPS_MODE: 684 return "NPS_MODE_CHANGE"; 685 default: 686 return "UNKNOWN CMD"; 687 } 688 } 689 690 static bool psp_err_warn(struct psp_context *psp) 691 { 692 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 693 694 /* This response indicates reg list is already loaded */ 695 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 696 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 697 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 698 cmd->resp.status == TEE_ERROR_CANCEL) 699 return false; 700 701 return true; 702 } 703 704 static int 705 psp_cmd_submit_buf(struct psp_context *psp, 706 struct amdgpu_firmware_info *ucode, 707 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 708 { 709 int ret; 710 int index; 711 int timeout = psp->adev->psp_timeout; 712 bool ras_intr = false; 713 bool skip_unsupport = false; 714 715 if (psp->adev->no_hw_access) 716 return 0; 717 718 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 719 720 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 721 722 index = atomic_inc_return(&psp->fence_value); 723 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 724 if (ret) { 725 atomic_dec(&psp->fence_value); 726 goto exit; 727 } 728 729 amdgpu_device_invalidate_hdp(psp->adev, NULL); 730 while (*((unsigned int *)psp->fence_buf) != index) { 731 if (--timeout == 0) 732 break; 733 /* 734 * Shouldn't wait for timeout when err_event_athub occurs, 735 * because gpu reset thread triggered and lock resource should 736 * be released for psp resume sequence. 737 */ 738 ras_intr = amdgpu_ras_intr_triggered(); 739 if (ras_intr) 740 break; 741 usleep_range(60, 100); 742 amdgpu_device_invalidate_hdp(psp->adev, NULL); 743 } 744 745 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 746 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 747 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 748 749 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 750 751 /* In some cases, psp response status is not 0 even there is no 752 * problem while the command is submitted. Some version of PSP FW 753 * doesn't write 0 to that field. 754 * So here we would like to only print a warning instead of an error 755 * during psp initialization to avoid breaking hw_init and it doesn't 756 * return -EINVAL. 757 */ 758 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 759 if (ucode) 760 dev_warn(psp->adev->dev, 761 "failed to load ucode %s(0x%X) ", 762 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 763 if (psp_err_warn(psp)) 764 dev_warn( 765 psp->adev->dev, 766 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 767 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 768 psp->cmd_buf_mem->cmd_id, 769 psp->cmd_buf_mem->resp.status); 770 /* If any firmware (including CAP) load fails under SRIOV, it should 771 * return failure to stop the VF from initializing. 772 * Also return failure in case of timeout 773 */ 774 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 775 ret = -EINVAL; 776 goto exit; 777 } 778 } 779 780 if (ucode) { 781 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 782 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 783 } 784 785 exit: 786 return ret; 787 } 788 789 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 790 { 791 struct psp_gfx_cmd_resp *cmd = psp->cmd; 792 793 mutex_lock(&psp->mutex); 794 795 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 796 797 return cmd; 798 } 799 800 static void release_psp_cmd_buf(struct psp_context *psp) 801 { 802 mutex_unlock(&psp->mutex); 803 } 804 805 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 806 struct psp_gfx_cmd_resp *cmd, 807 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 808 { 809 struct amdgpu_device *adev = psp->adev; 810 uint32_t size = 0; 811 uint64_t tmr_pa = 0; 812 813 if (tmr_bo) { 814 size = amdgpu_bo_size(tmr_bo); 815 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 816 } 817 818 if (amdgpu_sriov_vf(psp->adev)) 819 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 820 else 821 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 822 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 823 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 824 cmd->cmd.cmd_setup_tmr.buf_size = size; 825 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 826 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 827 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 828 } 829 830 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 831 uint64_t pri_buf_mc, uint32_t size) 832 { 833 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 834 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 835 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 836 cmd->cmd.cmd_load_toc.toc_size = size; 837 } 838 839 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 840 static int psp_load_toc(struct psp_context *psp, 841 uint32_t *tmr_size) 842 { 843 int ret; 844 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 845 846 /* Copy toc to psp firmware private buffer */ 847 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 848 849 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 850 851 ret = psp_cmd_submit_buf(psp, NULL, cmd, 852 psp->fence_buf_mc_addr); 853 if (!ret) 854 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 855 856 release_psp_cmd_buf(psp); 857 858 return ret; 859 } 860 861 /* Set up Trusted Memory Region */ 862 static int psp_tmr_init(struct psp_context *psp) 863 { 864 int ret = 0; 865 int tmr_size; 866 void *tmr_buf; 867 void **pptr; 868 869 /* 870 * According to HW engineer, they prefer the TMR address be "naturally 871 * aligned" , e.g. the start address be an integer divide of TMR size. 872 * 873 * Note: this memory need be reserved till the driver 874 * uninitializes. 875 */ 876 tmr_size = PSP_TMR_SIZE(psp->adev); 877 878 /* For ASICs support RLC autoload, psp will parse the toc 879 * and calculate the total size of TMR needed 880 */ 881 if (!amdgpu_sriov_vf(psp->adev) && 882 psp->toc.start_addr && 883 psp->toc.size_bytes && 884 psp->fw_pri_buf) { 885 ret = psp_load_toc(psp, &tmr_size); 886 if (ret) { 887 dev_err(psp->adev->dev, "Failed to load toc\n"); 888 return ret; 889 } 890 } 891 892 if (!psp->tmr_bo && !psp->boot_time_tmr) { 893 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 894 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 895 PSP_TMR_ALIGNMENT, 896 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 897 &psp->tmr_bo, &psp->tmr_mc_addr, 898 pptr); 899 } 900 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 901 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 902 903 return ret; 904 } 905 906 static bool psp_skip_tmr(struct psp_context *psp) 907 { 908 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 909 910 if (amdgpu_sriov_vf(psp->adev)) 911 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 912 else 913 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 914 } 915 916 static int psp_tmr_load(struct psp_context *psp) 917 { 918 int ret; 919 struct psp_gfx_cmd_resp *cmd; 920 921 if (psp_skip_tmr(psp)) 922 return 0; 923 924 cmd = acquire_psp_cmd_buf(psp); 925 926 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 927 if (psp->tmr_bo) 928 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 929 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 930 931 ret = psp_cmd_submit_buf(psp, NULL, cmd, 932 psp->fence_buf_mc_addr); 933 934 release_psp_cmd_buf(psp); 935 936 return ret; 937 } 938 939 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 940 struct psp_gfx_cmd_resp *cmd) 941 { 942 if (amdgpu_sriov_vf(psp->adev)) 943 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 944 else 945 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 946 } 947 948 static int psp_tmr_unload(struct psp_context *psp) 949 { 950 int ret; 951 struct psp_gfx_cmd_resp *cmd; 952 953 if (psp_skip_tmr(psp)) 954 return 0; 955 956 cmd = acquire_psp_cmd_buf(psp); 957 958 psp_prep_tmr_unload_cmd_buf(psp, cmd); 959 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 960 961 ret = psp_cmd_submit_buf(psp, NULL, cmd, 962 psp->fence_buf_mc_addr); 963 964 release_psp_cmd_buf(psp); 965 966 return ret; 967 } 968 969 static int psp_tmr_terminate(struct psp_context *psp) 970 { 971 return psp_tmr_unload(psp); 972 } 973 974 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 975 uint64_t *output_ptr) 976 { 977 int ret; 978 struct psp_gfx_cmd_resp *cmd; 979 980 if (!output_ptr) 981 return -EINVAL; 982 983 if (amdgpu_sriov_vf(psp->adev)) 984 return 0; 985 986 cmd = acquire_psp_cmd_buf(psp); 987 988 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, 991 psp->fence_buf_mc_addr); 992 993 if (!ret) { 994 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 995 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 996 } 997 998 release_psp_cmd_buf(psp); 999 1000 return ret; 1001 } 1002 1003 static int psp_get_fw_reservation_info(struct psp_context *psp, 1004 uint32_t cmd_id, 1005 uint64_t *addr, 1006 uint32_t *size) 1007 { 1008 int ret; 1009 uint32_t status; 1010 struct psp_gfx_cmd_resp *cmd; 1011 1012 cmd = acquire_psp_cmd_buf(psp); 1013 1014 cmd->cmd_id = cmd_id; 1015 1016 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1017 psp->fence_buf_mc_addr); 1018 if (ret) { 1019 release_psp_cmd_buf(psp); 1020 return ret; 1021 } 1022 1023 status = cmd->resp.status; 1024 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1025 release_psp_cmd_buf(psp); 1026 *addr = 0; 1027 *size = 0; 1028 return 0; 1029 } 1030 1031 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1032 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1033 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1034 1035 release_psp_cmd_buf(psp); 1036 1037 return 0; 1038 } 1039 1040 int psp_update_fw_reservation(struct psp_context *psp) 1041 { 1042 int ret; 1043 uint64_t reserv_addr, reserv_addr_ext; 1044 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1045 struct amdgpu_device *adev = psp->adev; 1046 1047 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1048 1049 if (amdgpu_sriov_vf(psp->adev)) 1050 return 0; 1051 1052 switch (mp0_ip_ver) { 1053 case IP_VERSION(14, 0, 2): 1054 if (adev->psp.sos.fw_version < 0x3b0e0d) 1055 return 0; 1056 break; 1057 1058 case IP_VERSION(14, 0, 3): 1059 if (adev->psp.sos.fw_version < 0x3a0e14) 1060 return 0; 1061 break; 1062 1063 default: 1064 return 0; 1065 } 1066 1067 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1068 if (ret) 1069 return ret; 1070 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1071 if (ret) 1072 return ret; 1073 1074 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1075 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1076 return 0; 1077 } 1078 1079 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1080 1081 reserv_size = roundup(reserv_size, SZ_1M); 1082 1083 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1084 reserv_addr, reserv_size, false); 1085 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1086 if (ret) { 1087 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1088 return ret; 1089 } 1090 1091 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1092 1093 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1094 reserv_addr_ext, reserv_size_ext, false); 1095 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1096 if (ret) { 1097 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1098 return ret; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1105 { 1106 struct psp_context *psp = &adev->psp; 1107 struct psp_gfx_cmd_resp *cmd; 1108 int ret; 1109 1110 if (amdgpu_sriov_vf(adev)) 1111 return 0; 1112 1113 cmd = acquire_psp_cmd_buf(psp); 1114 1115 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1116 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1117 1118 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1119 if (!ret) { 1120 *boot_cfg = 1121 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1122 } 1123 1124 release_psp_cmd_buf(psp); 1125 1126 return ret; 1127 } 1128 1129 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1130 { 1131 int ret; 1132 struct psp_context *psp = &adev->psp; 1133 struct psp_gfx_cmd_resp *cmd; 1134 1135 if (amdgpu_sriov_vf(adev)) 1136 return 0; 1137 1138 cmd = acquire_psp_cmd_buf(psp); 1139 1140 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1141 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1142 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1143 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1144 1145 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1146 1147 release_psp_cmd_buf(psp); 1148 1149 return ret; 1150 } 1151 1152 static int psp_rl_load(struct amdgpu_device *adev) 1153 { 1154 int ret; 1155 struct psp_context *psp = &adev->psp; 1156 struct psp_gfx_cmd_resp *cmd; 1157 1158 if (!is_psp_fw_valid(psp->rl)) 1159 return 0; 1160 1161 cmd = acquire_psp_cmd_buf(psp); 1162 1163 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1164 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1165 1166 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1167 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1168 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1169 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1170 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1171 1172 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1173 1174 release_psp_cmd_buf(psp); 1175 1176 return ret; 1177 } 1178 1179 int psp_memory_partition(struct psp_context *psp, int mode) 1180 { 1181 struct psp_gfx_cmd_resp *cmd; 1182 int ret; 1183 1184 if (amdgpu_sriov_vf(psp->adev)) 1185 return 0; 1186 1187 cmd = acquire_psp_cmd_buf(psp); 1188 1189 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1190 cmd->cmd.cmd_memory_part.mode = mode; 1191 1192 dev_info(psp->adev->dev, 1193 "Requesting %d memory partition change through PSP", mode); 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1195 if (ret) 1196 dev_err(psp->adev->dev, 1197 "PSP request failed to change to NPS%d mode\n", mode); 1198 1199 release_psp_cmd_buf(psp); 1200 1201 return ret; 1202 } 1203 1204 int psp_spatial_partition(struct psp_context *psp, int mode) 1205 { 1206 struct psp_gfx_cmd_resp *cmd; 1207 int ret; 1208 1209 if (amdgpu_sriov_vf(psp->adev)) 1210 return 0; 1211 1212 cmd = acquire_psp_cmd_buf(psp); 1213 1214 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1215 cmd->cmd.cmd_spatial_part.mode = mode; 1216 1217 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1218 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1219 1220 release_psp_cmd_buf(psp); 1221 1222 return ret; 1223 } 1224 1225 static int psp_asd_initialize(struct psp_context *psp) 1226 { 1227 int ret; 1228 1229 /* If PSP version doesn't match ASD version, asd loading will be failed. 1230 * add workaround to bypass it for sriov now. 1231 * TODO: add version check to make it common 1232 */ 1233 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1234 return 0; 1235 1236 /* bypass asd if display hardware is not available */ 1237 if (!amdgpu_device_has_display_hardware(psp->adev) && 1238 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1239 return 0; 1240 1241 psp->asd_context.mem_context.shared_mc_addr = 0; 1242 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1243 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1244 1245 ret = psp_ta_load(psp, &psp->asd_context); 1246 if (!ret) 1247 psp->asd_context.initialized = true; 1248 1249 return ret; 1250 } 1251 1252 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1253 uint32_t session_id) 1254 { 1255 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1256 cmd->cmd.cmd_unload_ta.session_id = session_id; 1257 } 1258 1259 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1260 { 1261 int ret; 1262 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1263 1264 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1265 1266 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1267 1268 context->resp_status = cmd->resp.status; 1269 1270 release_psp_cmd_buf(psp); 1271 1272 return ret; 1273 } 1274 1275 static int psp_asd_terminate(struct psp_context *psp) 1276 { 1277 int ret; 1278 1279 if (amdgpu_sriov_vf(psp->adev)) 1280 return 0; 1281 1282 if (!psp->asd_context.initialized) 1283 return 0; 1284 1285 ret = psp_ta_unload(psp, &psp->asd_context); 1286 if (!ret) 1287 psp->asd_context.initialized = false; 1288 1289 return ret; 1290 } 1291 1292 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1293 uint32_t id, uint32_t value) 1294 { 1295 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1296 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1297 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1298 } 1299 1300 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1301 uint32_t value) 1302 { 1303 struct psp_gfx_cmd_resp *cmd; 1304 int ret = 0; 1305 1306 if (reg >= PSP_REG_LAST) 1307 return -EINVAL; 1308 1309 cmd = acquire_psp_cmd_buf(psp); 1310 1311 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1312 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1313 if (ret) 1314 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1315 1316 release_psp_cmd_buf(psp); 1317 1318 return ret; 1319 } 1320 1321 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1322 uint64_t ta_bin_mc, 1323 struct ta_context *context) 1324 { 1325 cmd->cmd_id = context->ta_load_type; 1326 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1327 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1328 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1329 1330 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1331 lower_32_bits(context->mem_context.shared_mc_addr); 1332 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1333 upper_32_bits(context->mem_context.shared_mc_addr); 1334 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1335 } 1336 1337 int psp_ta_init_shared_buf(struct psp_context *psp, 1338 struct ta_mem_context *mem_ctx) 1339 { 1340 /* 1341 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1342 * physical) for ta to host memory 1343 */ 1344 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1345 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1346 AMDGPU_GEM_DOMAIN_GTT, 1347 &mem_ctx->shared_bo, 1348 &mem_ctx->shared_mc_addr, 1349 &mem_ctx->shared_buf); 1350 } 1351 1352 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1353 uint32_t ta_cmd_id, 1354 uint32_t session_id) 1355 { 1356 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1357 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1358 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1359 } 1360 1361 int psp_ta_invoke(struct psp_context *psp, 1362 uint32_t ta_cmd_id, 1363 struct ta_context *context) 1364 { 1365 int ret; 1366 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1367 1368 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1369 1370 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1371 psp->fence_buf_mc_addr); 1372 1373 context->resp_status = cmd->resp.status; 1374 1375 release_psp_cmd_buf(psp); 1376 1377 return ret; 1378 } 1379 1380 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1381 { 1382 int ret; 1383 struct psp_gfx_cmd_resp *cmd; 1384 1385 cmd = acquire_psp_cmd_buf(psp); 1386 1387 psp_copy_fw(psp, context->bin_desc.start_addr, 1388 context->bin_desc.size_bytes); 1389 1390 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1391 context->mem_context.shared_bo) 1392 context->mem_context.shared_mc_addr = 1393 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1394 1395 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1396 1397 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1398 psp->fence_buf_mc_addr); 1399 1400 context->resp_status = cmd->resp.status; 1401 1402 if (!ret) 1403 context->session_id = cmd->resp.session_id; 1404 1405 release_psp_cmd_buf(psp); 1406 1407 return ret; 1408 } 1409 1410 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1411 { 1412 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1413 } 1414 1415 int psp_xgmi_terminate(struct psp_context *psp) 1416 { 1417 int ret; 1418 struct amdgpu_device *adev = psp->adev; 1419 1420 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1421 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1422 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1423 adev->gmc.xgmi.connected_to_cpu)) 1424 return 0; 1425 1426 if (!psp->xgmi_context.context.initialized) 1427 return 0; 1428 1429 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1430 1431 psp->xgmi_context.context.initialized = false; 1432 1433 return ret; 1434 } 1435 1436 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1437 { 1438 struct ta_xgmi_shared_memory *xgmi_cmd; 1439 int ret; 1440 1441 if (!psp->ta_fw || 1442 !psp->xgmi_context.context.bin_desc.size_bytes || 1443 !psp->xgmi_context.context.bin_desc.start_addr) 1444 return -ENOENT; 1445 1446 if (!load_ta) 1447 goto invoke; 1448 1449 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1450 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1451 1452 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1453 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1454 if (ret) 1455 return ret; 1456 } 1457 1458 /* Load XGMI TA */ 1459 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1460 if (!ret) 1461 psp->xgmi_context.context.initialized = true; 1462 else 1463 return ret; 1464 1465 invoke: 1466 /* Initialize XGMI session */ 1467 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1468 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1469 xgmi_cmd->flag_extend_link_record = set_extended_data; 1470 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1471 1472 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1473 /* note down the capbility flag for XGMI TA */ 1474 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1475 1476 return ret; 1477 } 1478 1479 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1480 { 1481 struct ta_xgmi_shared_memory *xgmi_cmd; 1482 int ret; 1483 1484 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1485 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1486 1487 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1488 1489 /* Invoke xgmi ta to get hive id */ 1490 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1491 if (ret) 1492 return ret; 1493 1494 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1495 1496 return 0; 1497 } 1498 1499 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1500 { 1501 struct ta_xgmi_shared_memory *xgmi_cmd; 1502 int ret; 1503 1504 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1505 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1506 1507 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1508 1509 /* Invoke xgmi ta to get the node id */ 1510 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1511 if (ret) 1512 return ret; 1513 1514 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1515 1516 return 0; 1517 } 1518 1519 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1520 { 1521 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1522 IP_VERSION(13, 0, 2) && 1523 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1524 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1525 IP_VERSION(13, 0, 6); 1526 } 1527 1528 /* 1529 * Chips that support extended topology information require the driver to 1530 * reflect topology information in the opposite direction. This is 1531 * because the TA has already exceeded its link record limit and if the 1532 * TA holds bi-directional information, the driver would have to do 1533 * multiple fetches instead of just two. 1534 */ 1535 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1536 struct psp_xgmi_node_info node_info) 1537 { 1538 struct amdgpu_device *mirror_adev; 1539 struct amdgpu_hive_info *hive; 1540 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1541 uint64_t dst_node_id = node_info.node_id; 1542 uint8_t dst_num_hops = node_info.num_hops; 1543 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1544 uint8_t dst_num_links = node_info.num_links; 1545 1546 hive = amdgpu_get_xgmi_hive(psp->adev); 1547 if (WARN_ON(!hive)) 1548 return; 1549 1550 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1551 struct psp_xgmi_topology_info *mirror_top_info; 1552 int j; 1553 1554 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1555 continue; 1556 1557 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1558 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1559 if (mirror_top_info->nodes[j].node_id != src_node_id) 1560 continue; 1561 1562 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1563 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1564 /* prevent 0 num_links value re-reflection since reflection 1565 * criteria is based on num_hops (direct or indirect). 1566 */ 1567 if (dst_num_links) { 1568 mirror_top_info->nodes[j].num_links = dst_num_links; 1569 /* swap src and dst due to frame of reference */ 1570 for (int k = 0; k < dst_num_links; k++) { 1571 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1572 node_info.port_num[k].dst_xgmi_port_num; 1573 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1574 node_info.port_num[k].src_xgmi_port_num; 1575 } 1576 } 1577 1578 break; 1579 } 1580 1581 break; 1582 } 1583 1584 amdgpu_put_xgmi_hive(hive); 1585 } 1586 1587 int psp_xgmi_get_topology_info(struct psp_context *psp, 1588 int number_devices, 1589 struct psp_xgmi_topology_info *topology, 1590 bool get_extended_data) 1591 { 1592 struct ta_xgmi_shared_memory *xgmi_cmd; 1593 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1594 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1595 int i; 1596 int ret; 1597 1598 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1599 return -EINVAL; 1600 1601 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1602 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1603 xgmi_cmd->flag_extend_link_record = get_extended_data; 1604 1605 /* Fill in the shared memory with topology information as input */ 1606 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1607 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1608 topology_info_input->num_nodes = number_devices; 1609 1610 for (i = 0; i < topology_info_input->num_nodes; i++) { 1611 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1612 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1613 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1614 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1615 } 1616 1617 /* Invoke xgmi ta to get the topology information */ 1618 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1619 if (ret) 1620 return ret; 1621 1622 /* Read the output topology information from the shared memory */ 1623 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1624 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1625 for (i = 0; i < topology->num_nodes; i++) { 1626 /* extended data will either be 0 or equal to non-extended data */ 1627 if (topology_info_output->nodes[i].num_hops) 1628 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1629 1630 /* non-extended data gets everything here so no need to update */ 1631 if (!get_extended_data) { 1632 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1633 topology->nodes[i].is_sharing_enabled = 1634 topology_info_output->nodes[i].is_sharing_enabled; 1635 topology->nodes[i].sdma_engine = 1636 topology_info_output->nodes[i].sdma_engine; 1637 } 1638 1639 } 1640 1641 /* Invoke xgmi ta again to get the link information */ 1642 if (psp_xgmi_peer_link_info_supported(psp)) { 1643 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1644 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1645 bool requires_reflection = 1646 (psp->xgmi_context.supports_extended_data && 1647 get_extended_data) || 1648 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1649 IP_VERSION(13, 0, 6) || 1650 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1651 IP_VERSION(13, 0, 14) || 1652 amdgpu_sriov_vf(psp->adev); 1653 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 1654 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 1655 1656 /* popluate the shared output buffer rather than the cmd input buffer 1657 * with node_ids as the input for GET_PEER_LINKS command execution. 1658 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1659 * The same requirement for GET_EXTEND_PEER_LINKS command. 1660 */ 1661 if (ta_port_num_support) { 1662 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1663 1664 for (i = 0; i < topology->num_nodes; i++) 1665 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1666 1667 link_extend_info_output->num_nodes = topology->num_nodes; 1668 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1669 } else { 1670 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1671 1672 for (i = 0; i < topology->num_nodes; i++) 1673 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1674 1675 link_info_output->num_nodes = topology->num_nodes; 1676 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1677 } 1678 1679 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1680 if (ret) 1681 return ret; 1682 1683 for (i = 0; i < topology->num_nodes; i++) { 1684 uint8_t node_num_links = ta_port_num_support ? 1685 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1686 /* accumulate num_links on extended data */ 1687 if (get_extended_data) { 1688 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1689 } else { 1690 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1691 topology->nodes[i].num_links : node_num_links; 1692 } 1693 /* popluate the connected port num info if supported and available */ 1694 if (ta_port_num_support && topology->nodes[i].num_links) { 1695 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1696 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1697 } 1698 1699 /* reflect the topology information for bi-directionality */ 1700 if (requires_reflection && topology->nodes[i].num_hops) 1701 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1702 } 1703 } 1704 1705 return 0; 1706 } 1707 1708 int psp_xgmi_set_topology_info(struct psp_context *psp, 1709 int number_devices, 1710 struct psp_xgmi_topology_info *topology) 1711 { 1712 struct ta_xgmi_shared_memory *xgmi_cmd; 1713 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1714 int i; 1715 1716 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1717 return -EINVAL; 1718 1719 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1720 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1721 1722 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1723 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1724 topology_info_input->num_nodes = number_devices; 1725 1726 for (i = 0; i < topology_info_input->num_nodes; i++) { 1727 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1728 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1729 topology_info_input->nodes[i].is_sharing_enabled = 1; 1730 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1731 } 1732 1733 /* Invoke xgmi ta to set topology information */ 1734 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1735 } 1736 1737 // ras begin 1738 static void psp_ras_ta_check_status(struct psp_context *psp) 1739 { 1740 struct ta_ras_shared_memory *ras_cmd = 1741 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1742 1743 switch (ras_cmd->ras_status) { 1744 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1745 dev_warn(psp->adev->dev, 1746 "RAS WARNING: cmd failed due to unsupported ip\n"); 1747 break; 1748 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1749 dev_warn(psp->adev->dev, 1750 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1751 break; 1752 case TA_RAS_STATUS__SUCCESS: 1753 break; 1754 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1755 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1756 dev_warn(psp->adev->dev, 1757 "RAS WARNING: Inject error to critical region is not allowed\n"); 1758 break; 1759 default: 1760 dev_warn(psp->adev->dev, 1761 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1762 break; 1763 } 1764 } 1765 1766 static int psp_ras_send_cmd(struct psp_context *psp, 1767 enum ras_command cmd_id, void *in, void *out) 1768 { 1769 struct ta_ras_shared_memory *ras_cmd; 1770 uint32_t cmd = cmd_id; 1771 int ret = 0; 1772 1773 if (!in) 1774 return -EINVAL; 1775 1776 mutex_lock(&psp->ras_context.mutex); 1777 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1778 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1779 1780 switch (cmd) { 1781 case TA_RAS_COMMAND__ENABLE_FEATURES: 1782 case TA_RAS_COMMAND__DISABLE_FEATURES: 1783 memcpy(&ras_cmd->ras_in_message, 1784 in, sizeof(ras_cmd->ras_in_message)); 1785 break; 1786 case TA_RAS_COMMAND__TRIGGER_ERROR: 1787 memcpy(&ras_cmd->ras_in_message.trigger_error, 1788 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 1789 break; 1790 case TA_RAS_COMMAND__QUERY_ADDRESS: 1791 memcpy(&ras_cmd->ras_in_message.address, 1792 in, sizeof(ras_cmd->ras_in_message.address)); 1793 break; 1794 default: 1795 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 1796 ret = -EINVAL; 1797 goto err_out; 1798 } 1799 1800 ras_cmd->cmd_id = cmd; 1801 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1802 1803 switch (cmd) { 1804 case TA_RAS_COMMAND__TRIGGER_ERROR: 1805 if (!ret && out) 1806 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 1807 break; 1808 case TA_RAS_COMMAND__QUERY_ADDRESS: 1809 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1810 ret = -EINVAL; 1811 else if (out) 1812 memcpy(out, 1813 &ras_cmd->ras_out_message.address, 1814 sizeof(ras_cmd->ras_out_message.address)); 1815 break; 1816 default: 1817 break; 1818 } 1819 1820 err_out: 1821 mutex_unlock(&psp->ras_context.mutex); 1822 1823 return ret; 1824 } 1825 1826 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1827 { 1828 struct ta_ras_shared_memory *ras_cmd; 1829 int ret; 1830 1831 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1832 1833 /* 1834 * TODO: bypass the loading in sriov for now 1835 */ 1836 if (amdgpu_sriov_vf(psp->adev)) 1837 return 0; 1838 1839 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1840 1841 if (amdgpu_ras_intr_triggered()) 1842 return ret; 1843 1844 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1845 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1846 return -EINVAL; 1847 } 1848 1849 if (!ret) { 1850 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1851 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1852 1853 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1854 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1855 dev_warn(psp->adev->dev, 1856 "RAS internal register access blocked\n"); 1857 1858 psp_ras_ta_check_status(psp); 1859 } 1860 1861 return ret; 1862 } 1863 1864 int psp_ras_enable_features(struct psp_context *psp, 1865 union ta_ras_cmd_input *info, bool enable) 1866 { 1867 enum ras_command cmd_id; 1868 int ret; 1869 1870 if (!psp->ras_context.context.initialized || !info) 1871 return -EINVAL; 1872 1873 cmd_id = enable ? 1874 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 1875 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 1876 if (ret) 1877 return -EINVAL; 1878 1879 return 0; 1880 } 1881 1882 int psp_ras_terminate(struct psp_context *psp) 1883 { 1884 int ret; 1885 1886 /* 1887 * TODO: bypass the terminate in sriov for now 1888 */ 1889 if (amdgpu_sriov_vf(psp->adev)) 1890 return 0; 1891 1892 if (!psp->ras_context.context.initialized) 1893 return 0; 1894 1895 ret = psp_ta_unload(psp, &psp->ras_context.context); 1896 1897 psp->ras_context.context.initialized = false; 1898 1899 mutex_destroy(&psp->ras_context.mutex); 1900 1901 return ret; 1902 } 1903 1904 int psp_ras_initialize(struct psp_context *psp) 1905 { 1906 int ret; 1907 uint32_t boot_cfg = 0xFF; 1908 struct amdgpu_device *adev = psp->adev; 1909 struct ta_ras_shared_memory *ras_cmd; 1910 1911 /* 1912 * TODO: bypass the initialize in sriov for now 1913 */ 1914 if (amdgpu_sriov_vf(adev)) 1915 return 0; 1916 1917 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1918 !adev->psp.ras_context.context.bin_desc.start_addr) { 1919 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1920 return 0; 1921 } 1922 1923 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1924 /* query GECC enablement status from boot config 1925 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1926 */ 1927 ret = psp_boot_config_get(adev, &boot_cfg); 1928 if (ret) 1929 dev_warn(adev->dev, "PSP get boot config failed\n"); 1930 1931 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 1932 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1933 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 1934 dev_warn(adev->dev, 1935 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 1936 } else { 1937 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 1938 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 1939 if (boot_cfg == 1) { 1940 dev_info(adev->dev, "GECC is enabled\n"); 1941 } else { 1942 /* enable GECC in next boot cycle if it is disabled 1943 * in boot config, or force enable GECC if failed to 1944 * get boot configuration 1945 */ 1946 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1947 if (ret) 1948 dev_warn(adev->dev, "PSP set boot config failed\n"); 1949 else 1950 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1951 } 1952 } else { 1953 if (!boot_cfg) { 1954 if (!adev->ras_default_ecc_enabled && 1955 amdgpu_ras_enable != 1 && 1956 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1957 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 1958 else 1959 dev_info(adev->dev, "GECC is disabled\n"); 1960 } else { 1961 /* disable GECC in next boot cycle if ras is 1962 * disabled by module parameter amdgpu_ras_enable 1963 * and/or amdgpu_ras_mask, or boot_config_get call 1964 * is failed 1965 */ 1966 ret = psp_boot_config_set(adev, 0); 1967 if (ret) 1968 dev_warn(adev->dev, "PSP set boot config failed\n"); 1969 else 1970 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1971 } 1972 } 1973 } 1974 } 1975 1976 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1977 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1978 1979 if (!psp->ras_context.context.mem_context.shared_buf) { 1980 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1981 if (ret) 1982 return ret; 1983 } 1984 1985 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1986 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1987 1988 if (amdgpu_ras_is_poison_mode_supported(adev)) 1989 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1990 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1991 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1992 ras_cmd->ras_in_message.init_flags.xcc_mask = 1993 adev->gfx.xcc_mask; 1994 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1995 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 1996 ras_cmd->ras_in_message.init_flags.nps_mode = 1997 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1998 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 1999 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2000 2001 ret = psp_ta_load(psp, &psp->ras_context.context); 2002 2003 if (!ret && !ras_cmd->ras_status) { 2004 psp->ras_context.context.initialized = true; 2005 mutex_init(&psp->ras_context.mutex); 2006 } else { 2007 if (ras_cmd->ras_status) 2008 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2009 2010 /* fail to load RAS TA */ 2011 psp->ras_context.context.initialized = false; 2012 } 2013 2014 return ret; 2015 } 2016 2017 int psp_ras_trigger_error(struct psp_context *psp, 2018 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2019 { 2020 struct amdgpu_device *adev = psp->adev; 2021 int ret; 2022 uint32_t dev_mask; 2023 uint32_t ras_status = 0; 2024 2025 if (!psp->ras_context.context.initialized || !info) 2026 return -EINVAL; 2027 2028 switch (info->block_id) { 2029 case TA_RAS_BLOCK__GFX: 2030 dev_mask = GET_MASK(GC, instance_mask); 2031 break; 2032 case TA_RAS_BLOCK__SDMA: 2033 dev_mask = GET_MASK(SDMA0, instance_mask); 2034 break; 2035 case TA_RAS_BLOCK__VCN: 2036 case TA_RAS_BLOCK__JPEG: 2037 dev_mask = GET_MASK(VCN, instance_mask); 2038 break; 2039 default: 2040 dev_mask = instance_mask; 2041 break; 2042 } 2043 2044 /* reuse sub_block_index for backward compatibility */ 2045 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2046 dev_mask &= AMDGPU_RAS_INST_MASK; 2047 info->sub_block_index |= dev_mask; 2048 2049 ret = psp_ras_send_cmd(psp, 2050 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2051 if (ret) 2052 return -EINVAL; 2053 2054 /* If err_event_athub occurs error inject was successful, however 2055 * return status from TA is no long reliable 2056 */ 2057 if (amdgpu_ras_intr_triggered()) 2058 return 0; 2059 2060 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2061 return -EACCES; 2062 else if (ras_status) 2063 return -EINVAL; 2064 2065 return 0; 2066 } 2067 2068 int psp_ras_query_address(struct psp_context *psp, 2069 struct ta_ras_query_address_input *addr_in, 2070 struct ta_ras_query_address_output *addr_out) 2071 { 2072 int ret; 2073 2074 if (!psp->ras_context.context.initialized || 2075 !addr_in || !addr_out) 2076 return -EINVAL; 2077 2078 ret = psp_ras_send_cmd(psp, 2079 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2080 2081 return ret; 2082 } 2083 // ras end 2084 2085 // HDCP start 2086 static int psp_hdcp_initialize(struct psp_context *psp) 2087 { 2088 int ret; 2089 2090 /* 2091 * TODO: bypass the initialize in sriov for now 2092 */ 2093 if (amdgpu_sriov_vf(psp->adev)) 2094 return 0; 2095 2096 /* bypass hdcp initialization if dmu is harvested */ 2097 if (!amdgpu_device_has_display_hardware(psp->adev)) 2098 return 0; 2099 2100 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2101 !psp->hdcp_context.context.bin_desc.start_addr) { 2102 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2103 return 0; 2104 } 2105 2106 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2107 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2108 2109 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2110 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2111 if (ret) 2112 return ret; 2113 } 2114 2115 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2116 if (!ret) { 2117 psp->hdcp_context.context.initialized = true; 2118 mutex_init(&psp->hdcp_context.mutex); 2119 } 2120 2121 return ret; 2122 } 2123 2124 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2125 { 2126 /* 2127 * TODO: bypass the loading in sriov for now 2128 */ 2129 if (amdgpu_sriov_vf(psp->adev)) 2130 return 0; 2131 2132 if (!psp->hdcp_context.context.initialized) 2133 return 0; 2134 2135 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2136 } 2137 2138 static int psp_hdcp_terminate(struct psp_context *psp) 2139 { 2140 int ret; 2141 2142 /* 2143 * TODO: bypass the terminate in sriov for now 2144 */ 2145 if (amdgpu_sriov_vf(psp->adev)) 2146 return 0; 2147 2148 if (!psp->hdcp_context.context.initialized) 2149 return 0; 2150 2151 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2152 2153 psp->hdcp_context.context.initialized = false; 2154 2155 return ret; 2156 } 2157 // HDCP end 2158 2159 // DTM start 2160 static int psp_dtm_initialize(struct psp_context *psp) 2161 { 2162 int ret; 2163 2164 /* 2165 * TODO: bypass the initialize in sriov for now 2166 */ 2167 if (amdgpu_sriov_vf(psp->adev)) 2168 return 0; 2169 2170 /* bypass dtm initialization if dmu is harvested */ 2171 if (!amdgpu_device_has_display_hardware(psp->adev)) 2172 return 0; 2173 2174 if (!psp->dtm_context.context.bin_desc.size_bytes || 2175 !psp->dtm_context.context.bin_desc.start_addr) { 2176 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2177 return 0; 2178 } 2179 2180 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2181 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2182 2183 if (!psp->dtm_context.context.mem_context.shared_buf) { 2184 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2185 if (ret) 2186 return ret; 2187 } 2188 2189 ret = psp_ta_load(psp, &psp->dtm_context.context); 2190 if (!ret) { 2191 psp->dtm_context.context.initialized = true; 2192 mutex_init(&psp->dtm_context.mutex); 2193 } 2194 2195 return ret; 2196 } 2197 2198 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2199 { 2200 /* 2201 * TODO: bypass the loading in sriov for now 2202 */ 2203 if (amdgpu_sriov_vf(psp->adev)) 2204 return 0; 2205 2206 if (!psp->dtm_context.context.initialized) 2207 return 0; 2208 2209 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2210 } 2211 2212 static int psp_dtm_terminate(struct psp_context *psp) 2213 { 2214 int ret; 2215 2216 /* 2217 * TODO: bypass the terminate in sriov for now 2218 */ 2219 if (amdgpu_sriov_vf(psp->adev)) 2220 return 0; 2221 2222 if (!psp->dtm_context.context.initialized) 2223 return 0; 2224 2225 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2226 2227 psp->dtm_context.context.initialized = false; 2228 2229 return ret; 2230 } 2231 // DTM end 2232 2233 // RAP start 2234 static int psp_rap_initialize(struct psp_context *psp) 2235 { 2236 int ret; 2237 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2238 2239 /* 2240 * TODO: bypass the initialize in sriov for now 2241 */ 2242 if (amdgpu_sriov_vf(psp->adev)) 2243 return 0; 2244 2245 if (!psp->rap_context.context.bin_desc.size_bytes || 2246 !psp->rap_context.context.bin_desc.start_addr) { 2247 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2248 return 0; 2249 } 2250 2251 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2252 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2253 2254 if (!psp->rap_context.context.mem_context.shared_buf) { 2255 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2256 if (ret) 2257 return ret; 2258 } 2259 2260 ret = psp_ta_load(psp, &psp->rap_context.context); 2261 if (!ret) { 2262 psp->rap_context.context.initialized = true; 2263 mutex_init(&psp->rap_context.mutex); 2264 } else 2265 return ret; 2266 2267 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2268 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2269 psp_rap_terminate(psp); 2270 /* free rap shared memory */ 2271 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2272 2273 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2274 ret, status); 2275 2276 return ret; 2277 } 2278 2279 return 0; 2280 } 2281 2282 static int psp_rap_terminate(struct psp_context *psp) 2283 { 2284 int ret; 2285 2286 if (!psp->rap_context.context.initialized) 2287 return 0; 2288 2289 ret = psp_ta_unload(psp, &psp->rap_context.context); 2290 2291 psp->rap_context.context.initialized = false; 2292 2293 return ret; 2294 } 2295 2296 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2297 { 2298 struct ta_rap_shared_memory *rap_cmd; 2299 int ret = 0; 2300 2301 if (!psp->rap_context.context.initialized) 2302 return 0; 2303 2304 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2305 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2306 return -EINVAL; 2307 2308 mutex_lock(&psp->rap_context.mutex); 2309 2310 rap_cmd = (struct ta_rap_shared_memory *) 2311 psp->rap_context.context.mem_context.shared_buf; 2312 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2313 2314 rap_cmd->cmd_id = ta_cmd_id; 2315 rap_cmd->validation_method_id = METHOD_A; 2316 2317 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2318 if (ret) 2319 goto out_unlock; 2320 2321 if (status) 2322 *status = rap_cmd->rap_status; 2323 2324 out_unlock: 2325 mutex_unlock(&psp->rap_context.mutex); 2326 2327 return ret; 2328 } 2329 // RAP end 2330 2331 /* securedisplay start */ 2332 static int psp_securedisplay_initialize(struct psp_context *psp) 2333 { 2334 int ret; 2335 struct ta_securedisplay_cmd *securedisplay_cmd; 2336 2337 /* 2338 * TODO: bypass the initialize in sriov for now 2339 */ 2340 if (amdgpu_sriov_vf(psp->adev)) 2341 return 0; 2342 2343 /* bypass securedisplay initialization if dmu is harvested */ 2344 if (!amdgpu_device_has_display_hardware(psp->adev)) 2345 return 0; 2346 2347 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2348 !psp->securedisplay_context.context.bin_desc.start_addr) { 2349 dev_info(psp->adev->dev, 2350 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2351 return 0; 2352 } 2353 2354 psp->securedisplay_context.context.mem_context.shared_mem_size = 2355 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2356 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2357 2358 if (!psp->securedisplay_context.context.initialized) { 2359 ret = psp_ta_init_shared_buf(psp, 2360 &psp->securedisplay_context.context.mem_context); 2361 if (ret) 2362 return ret; 2363 } 2364 2365 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2366 if (!ret && !psp->securedisplay_context.context.resp_status) { 2367 psp->securedisplay_context.context.initialized = true; 2368 mutex_init(&psp->securedisplay_context.mutex); 2369 } else { 2370 /* don't try again */ 2371 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2372 return ret; 2373 } 2374 2375 mutex_lock(&psp->securedisplay_context.mutex); 2376 2377 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2378 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2379 2380 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2381 2382 mutex_unlock(&psp->securedisplay_context.mutex); 2383 2384 if (ret) { 2385 psp_securedisplay_terminate(psp); 2386 /* free securedisplay shared memory */ 2387 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2388 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2389 return -EINVAL; 2390 } 2391 2392 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2393 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2394 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2395 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2396 /* don't try again */ 2397 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2398 } 2399 2400 return 0; 2401 } 2402 2403 static int psp_securedisplay_terminate(struct psp_context *psp) 2404 { 2405 int ret; 2406 2407 /* 2408 * TODO:bypass the terminate in sriov for now 2409 */ 2410 if (amdgpu_sriov_vf(psp->adev)) 2411 return 0; 2412 2413 if (!psp->securedisplay_context.context.initialized) 2414 return 0; 2415 2416 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2417 2418 psp->securedisplay_context.context.initialized = false; 2419 2420 return ret; 2421 } 2422 2423 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2424 { 2425 int ret; 2426 2427 if (!psp->securedisplay_context.context.initialized) 2428 return -EINVAL; 2429 2430 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2431 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2432 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2433 return -EINVAL; 2434 2435 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2436 2437 return ret; 2438 } 2439 /* SECUREDISPLAY end */ 2440 2441 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2442 { 2443 struct psp_context *psp = &adev->psp; 2444 int ret = 0; 2445 2446 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2447 ret = psp->funcs->wait_for_bootloader(psp); 2448 2449 return ret; 2450 } 2451 2452 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2453 { 2454 if (psp->funcs && 2455 psp->funcs->get_ras_capability) { 2456 return psp->funcs->get_ras_capability(psp); 2457 } else { 2458 return false; 2459 } 2460 } 2461 2462 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2463 { 2464 struct psp_context *psp = &adev->psp; 2465 2466 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2467 return false; 2468 2469 if (psp->funcs && psp->funcs->is_reload_needed) 2470 return psp->funcs->is_reload_needed(psp); 2471 2472 return false; 2473 } 2474 2475 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2476 { 2477 struct psp_context *psp = &adev->psp; 2478 2479 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2480 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2481 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2482 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2483 } 2484 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2485 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2486 } 2487 2488 static int psp_hw_start(struct psp_context *psp) 2489 { 2490 struct amdgpu_device *adev = psp->adev; 2491 int ret; 2492 2493 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2494 psp_update_gpu_addresses(adev); 2495 2496 if (!amdgpu_sriov_vf(adev)) { 2497 if ((is_psp_fw_valid(psp->kdb)) && 2498 (psp->funcs->bootloader_load_kdb != NULL)) { 2499 ret = psp_bootloader_load_kdb(psp); 2500 if (ret) { 2501 dev_err(adev->dev, "PSP load kdb failed!\n"); 2502 return ret; 2503 } 2504 } 2505 2506 if ((is_psp_fw_valid(psp->spl)) && 2507 (psp->funcs->bootloader_load_spl != NULL)) { 2508 ret = psp_bootloader_load_spl(psp); 2509 if (ret) { 2510 dev_err(adev->dev, "PSP load spl failed!\n"); 2511 return ret; 2512 } 2513 } 2514 2515 if ((is_psp_fw_valid(psp->sys)) && 2516 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2517 ret = psp_bootloader_load_sysdrv(psp); 2518 if (ret) { 2519 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2520 return ret; 2521 } 2522 } 2523 2524 if ((is_psp_fw_valid(psp->soc_drv)) && 2525 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2526 ret = psp_bootloader_load_soc_drv(psp); 2527 if (ret) { 2528 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2529 return ret; 2530 } 2531 } 2532 2533 if ((is_psp_fw_valid(psp->intf_drv)) && 2534 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2535 ret = psp_bootloader_load_intf_drv(psp); 2536 if (ret) { 2537 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2538 return ret; 2539 } 2540 } 2541 2542 if ((is_psp_fw_valid(psp->dbg_drv)) && 2543 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2544 ret = psp_bootloader_load_dbg_drv(psp); 2545 if (ret) { 2546 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2547 return ret; 2548 } 2549 } 2550 2551 if ((is_psp_fw_valid(psp->ras_drv)) && 2552 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2553 ret = psp_bootloader_load_ras_drv(psp); 2554 if (ret) { 2555 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2556 return ret; 2557 } 2558 } 2559 2560 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2561 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2562 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2563 if (ret) { 2564 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2565 return ret; 2566 } 2567 } 2568 2569 if ((is_psp_fw_valid(psp->spdm_drv)) && 2570 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2571 ret = psp_bootloader_load_spdm_drv(psp); 2572 if (ret) { 2573 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2574 return ret; 2575 } 2576 } 2577 2578 if ((is_psp_fw_valid(psp->sos)) && 2579 (psp->funcs->bootloader_load_sos != NULL)) { 2580 ret = psp_bootloader_load_sos(psp); 2581 if (ret) { 2582 dev_err(adev->dev, "PSP load sos failed!\n"); 2583 return ret; 2584 } 2585 } 2586 } 2587 2588 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2589 if (ret) { 2590 dev_err(adev->dev, "PSP create ring failed!\n"); 2591 return ret; 2592 } 2593 2594 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2595 ret = psp_update_fw_reservation(psp); 2596 if (ret) { 2597 dev_err(adev->dev, "update fw reservation failed!\n"); 2598 return ret; 2599 } 2600 } 2601 2602 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2603 goto skip_pin_bo; 2604 2605 if (!psp->boot_time_tmr || psp->autoload_supported) { 2606 ret = psp_tmr_init(psp); 2607 if (ret) { 2608 dev_err(adev->dev, "PSP tmr init failed!\n"); 2609 return ret; 2610 } 2611 } 2612 2613 skip_pin_bo: 2614 /* 2615 * For ASICs with DF Cstate management centralized 2616 * to PMFW, TMR setup should be performed after PMFW 2617 * loaded and before other non-psp firmware loaded. 2618 */ 2619 if (psp->pmfw_centralized_cstate_management) { 2620 ret = psp_load_smu_fw(psp); 2621 if (ret) 2622 return ret; 2623 } 2624 2625 ret = psp_tmr_load(psp); 2626 if (ret) { 2627 dev_err(adev->dev, "PSP load tmr failed!\n"); 2628 return ret; 2629 } 2630 2631 return 0; 2632 } 2633 2634 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2635 enum psp_gfx_fw_type *type) 2636 { 2637 switch (ucode->ucode_id) { 2638 case AMDGPU_UCODE_ID_CAP: 2639 *type = GFX_FW_TYPE_CAP; 2640 break; 2641 case AMDGPU_UCODE_ID_SDMA0: 2642 *type = GFX_FW_TYPE_SDMA0; 2643 break; 2644 case AMDGPU_UCODE_ID_SDMA1: 2645 *type = GFX_FW_TYPE_SDMA1; 2646 break; 2647 case AMDGPU_UCODE_ID_SDMA2: 2648 *type = GFX_FW_TYPE_SDMA2; 2649 break; 2650 case AMDGPU_UCODE_ID_SDMA3: 2651 *type = GFX_FW_TYPE_SDMA3; 2652 break; 2653 case AMDGPU_UCODE_ID_SDMA4: 2654 *type = GFX_FW_TYPE_SDMA4; 2655 break; 2656 case AMDGPU_UCODE_ID_SDMA5: 2657 *type = GFX_FW_TYPE_SDMA5; 2658 break; 2659 case AMDGPU_UCODE_ID_SDMA6: 2660 *type = GFX_FW_TYPE_SDMA6; 2661 break; 2662 case AMDGPU_UCODE_ID_SDMA7: 2663 *type = GFX_FW_TYPE_SDMA7; 2664 break; 2665 case AMDGPU_UCODE_ID_CP_MES: 2666 *type = GFX_FW_TYPE_CP_MES; 2667 break; 2668 case AMDGPU_UCODE_ID_CP_MES_DATA: 2669 *type = GFX_FW_TYPE_MES_STACK; 2670 break; 2671 case AMDGPU_UCODE_ID_CP_MES1: 2672 *type = GFX_FW_TYPE_CP_MES_KIQ; 2673 break; 2674 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2675 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2676 break; 2677 case AMDGPU_UCODE_ID_CP_CE: 2678 *type = GFX_FW_TYPE_CP_CE; 2679 break; 2680 case AMDGPU_UCODE_ID_CP_PFP: 2681 *type = GFX_FW_TYPE_CP_PFP; 2682 break; 2683 case AMDGPU_UCODE_ID_CP_ME: 2684 *type = GFX_FW_TYPE_CP_ME; 2685 break; 2686 case AMDGPU_UCODE_ID_CP_MEC1: 2687 *type = GFX_FW_TYPE_CP_MEC; 2688 break; 2689 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2690 *type = GFX_FW_TYPE_CP_MEC_ME1; 2691 break; 2692 case AMDGPU_UCODE_ID_CP_MEC2: 2693 *type = GFX_FW_TYPE_CP_MEC; 2694 break; 2695 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2696 *type = GFX_FW_TYPE_CP_MEC_ME2; 2697 break; 2698 case AMDGPU_UCODE_ID_RLC_P: 2699 *type = GFX_FW_TYPE_RLC_P; 2700 break; 2701 case AMDGPU_UCODE_ID_RLC_V: 2702 *type = GFX_FW_TYPE_RLC_V; 2703 break; 2704 case AMDGPU_UCODE_ID_RLC_G: 2705 *type = GFX_FW_TYPE_RLC_G; 2706 break; 2707 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2708 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2709 break; 2710 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2711 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2712 break; 2713 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2714 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2715 break; 2716 case AMDGPU_UCODE_ID_RLC_IRAM: 2717 *type = GFX_FW_TYPE_RLC_IRAM; 2718 break; 2719 case AMDGPU_UCODE_ID_RLC_DRAM: 2720 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2721 break; 2722 case AMDGPU_UCODE_ID_RLC_IRAM_1: 2723 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 2724 break; 2725 case AMDGPU_UCODE_ID_RLC_DRAM_1: 2726 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 2727 break; 2728 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2729 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2730 break; 2731 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2732 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2733 break; 2734 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2735 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2736 break; 2737 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2738 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2739 break; 2740 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2741 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2742 break; 2743 case AMDGPU_UCODE_ID_SMC: 2744 *type = GFX_FW_TYPE_SMU; 2745 break; 2746 case AMDGPU_UCODE_ID_PPTABLE: 2747 *type = GFX_FW_TYPE_PPTABLE; 2748 break; 2749 case AMDGPU_UCODE_ID_UVD: 2750 *type = GFX_FW_TYPE_UVD; 2751 break; 2752 case AMDGPU_UCODE_ID_UVD1: 2753 *type = GFX_FW_TYPE_UVD1; 2754 break; 2755 case AMDGPU_UCODE_ID_VCE: 2756 *type = GFX_FW_TYPE_VCE; 2757 break; 2758 case AMDGPU_UCODE_ID_VCN: 2759 *type = GFX_FW_TYPE_VCN; 2760 break; 2761 case AMDGPU_UCODE_ID_VCN1: 2762 *type = GFX_FW_TYPE_VCN1; 2763 break; 2764 case AMDGPU_UCODE_ID_DMCU_ERAM: 2765 *type = GFX_FW_TYPE_DMCU_ERAM; 2766 break; 2767 case AMDGPU_UCODE_ID_DMCU_INTV: 2768 *type = GFX_FW_TYPE_DMCU_ISR; 2769 break; 2770 case AMDGPU_UCODE_ID_VCN0_RAM: 2771 *type = GFX_FW_TYPE_VCN0_RAM; 2772 break; 2773 case AMDGPU_UCODE_ID_VCN1_RAM: 2774 *type = GFX_FW_TYPE_VCN1_RAM; 2775 break; 2776 case AMDGPU_UCODE_ID_DMCUB: 2777 *type = GFX_FW_TYPE_DMUB; 2778 break; 2779 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2780 case AMDGPU_UCODE_ID_SDMA_RS64: 2781 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2782 break; 2783 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2784 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2785 break; 2786 case AMDGPU_UCODE_ID_IMU_I: 2787 *type = GFX_FW_TYPE_IMU_I; 2788 break; 2789 case AMDGPU_UCODE_ID_IMU_D: 2790 *type = GFX_FW_TYPE_IMU_D; 2791 break; 2792 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2793 *type = GFX_FW_TYPE_RS64_PFP; 2794 break; 2795 case AMDGPU_UCODE_ID_CP_RS64_ME: 2796 *type = GFX_FW_TYPE_RS64_ME; 2797 break; 2798 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2799 *type = GFX_FW_TYPE_RS64_MEC; 2800 break; 2801 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2802 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2803 break; 2804 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2805 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2806 break; 2807 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2808 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2809 break; 2810 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2811 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2812 break; 2813 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2814 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2815 break; 2816 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2817 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2818 break; 2819 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2820 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2821 break; 2822 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2823 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2824 break; 2825 case AMDGPU_UCODE_ID_VPE_CTX: 2826 *type = GFX_FW_TYPE_VPEC_FW1; 2827 break; 2828 case AMDGPU_UCODE_ID_VPE_CTL: 2829 *type = GFX_FW_TYPE_VPEC_FW2; 2830 break; 2831 case AMDGPU_UCODE_ID_VPE: 2832 *type = GFX_FW_TYPE_VPE; 2833 break; 2834 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2835 *type = GFX_FW_TYPE_UMSCH_UCODE; 2836 break; 2837 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2838 *type = GFX_FW_TYPE_UMSCH_DATA; 2839 break; 2840 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2841 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2842 break; 2843 case AMDGPU_UCODE_ID_P2S_TABLE: 2844 *type = GFX_FW_TYPE_P2S_TABLE; 2845 break; 2846 case AMDGPU_UCODE_ID_JPEG_RAM: 2847 *type = GFX_FW_TYPE_JPEG_RAM; 2848 break; 2849 case AMDGPU_UCODE_ID_ISP: 2850 *type = GFX_FW_TYPE_ISP; 2851 break; 2852 case AMDGPU_UCODE_ID_MAXIMUM: 2853 default: 2854 return -EINVAL; 2855 } 2856 2857 return 0; 2858 } 2859 2860 static void psp_print_fw_hdr(struct psp_context *psp, 2861 struct amdgpu_firmware_info *ucode) 2862 { 2863 struct amdgpu_device *adev = psp->adev; 2864 struct common_firmware_header *hdr; 2865 2866 switch (ucode->ucode_id) { 2867 case AMDGPU_UCODE_ID_SDMA0: 2868 case AMDGPU_UCODE_ID_SDMA1: 2869 case AMDGPU_UCODE_ID_SDMA2: 2870 case AMDGPU_UCODE_ID_SDMA3: 2871 case AMDGPU_UCODE_ID_SDMA4: 2872 case AMDGPU_UCODE_ID_SDMA5: 2873 case AMDGPU_UCODE_ID_SDMA6: 2874 case AMDGPU_UCODE_ID_SDMA7: 2875 hdr = (struct common_firmware_header *) 2876 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2877 amdgpu_ucode_print_sdma_hdr(hdr); 2878 break; 2879 case AMDGPU_UCODE_ID_CP_CE: 2880 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2881 amdgpu_ucode_print_gfx_hdr(hdr); 2882 break; 2883 case AMDGPU_UCODE_ID_CP_PFP: 2884 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2885 amdgpu_ucode_print_gfx_hdr(hdr); 2886 break; 2887 case AMDGPU_UCODE_ID_CP_ME: 2888 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2889 amdgpu_ucode_print_gfx_hdr(hdr); 2890 break; 2891 case AMDGPU_UCODE_ID_CP_MEC1: 2892 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2893 amdgpu_ucode_print_gfx_hdr(hdr); 2894 break; 2895 case AMDGPU_UCODE_ID_RLC_G: 2896 case AMDGPU_UCODE_ID_RLC_DRAM_1: 2897 case AMDGPU_UCODE_ID_RLC_IRAM_1: 2898 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2899 amdgpu_ucode_print_rlc_hdr(hdr); 2900 break; 2901 case AMDGPU_UCODE_ID_SMC: 2902 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2903 amdgpu_ucode_print_smc_hdr(hdr); 2904 break; 2905 default: 2906 break; 2907 } 2908 } 2909 2910 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2911 struct amdgpu_firmware_info *ucode, 2912 struct psp_gfx_cmd_resp *cmd) 2913 { 2914 int ret; 2915 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2916 2917 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2918 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2919 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2920 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2921 2922 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2923 if (ret) 2924 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 2925 return ret; 2926 } 2927 2928 int psp_execute_ip_fw_load(struct psp_context *psp, 2929 struct amdgpu_firmware_info *ucode) 2930 { 2931 int ret = 0; 2932 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2933 2934 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2935 if (!ret) { 2936 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2937 psp->fence_buf_mc_addr); 2938 } 2939 2940 release_psp_cmd_buf(psp); 2941 2942 return ret; 2943 } 2944 2945 static int psp_load_p2s_table(struct psp_context *psp) 2946 { 2947 int ret; 2948 struct amdgpu_device *adev = psp->adev; 2949 struct amdgpu_firmware_info *ucode = 2950 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2951 2952 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2953 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2954 return 0; 2955 2956 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2957 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2958 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2959 0x0036003C; 2960 if (psp->sos.fw_version < supp_vers) 2961 return 0; 2962 } 2963 2964 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2965 return 0; 2966 2967 ret = psp_execute_ip_fw_load(psp, ucode); 2968 2969 return ret; 2970 } 2971 2972 static int psp_load_smu_fw(struct psp_context *psp) 2973 { 2974 int ret; 2975 struct amdgpu_device *adev = psp->adev; 2976 struct amdgpu_firmware_info *ucode = 2977 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2978 struct amdgpu_ras *ras = psp->ras_context.ras; 2979 2980 /* 2981 * Skip SMU FW reloading in case of using BACO for runpm only, 2982 * as SMU is always alive. 2983 */ 2984 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2985 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2986 return 0; 2987 2988 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2989 return 0; 2990 2991 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2992 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2993 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2994 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2995 if (ret) 2996 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2997 } 2998 2999 ret = psp_execute_ip_fw_load(psp, ucode); 3000 3001 if (ret) 3002 dev_err(adev->dev, "PSP load smu failed!\n"); 3003 3004 return ret; 3005 } 3006 3007 static bool fw_load_skip_check(struct psp_context *psp, 3008 struct amdgpu_firmware_info *ucode) 3009 { 3010 if (!ucode->fw || !ucode->ucode_size) 3011 return true; 3012 3013 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3014 return true; 3015 3016 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3017 (psp_smu_reload_quirk(psp) || 3018 psp->autoload_supported || 3019 psp->pmfw_centralized_cstate_management)) 3020 return true; 3021 3022 if (amdgpu_sriov_vf(psp->adev) && 3023 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3024 return true; 3025 3026 if (psp->autoload_supported && 3027 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3028 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3029 /* skip mec JT when autoload is enabled */ 3030 return true; 3031 3032 return false; 3033 } 3034 3035 int psp_load_fw_list(struct psp_context *psp, 3036 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3037 { 3038 int ret = 0, i; 3039 struct amdgpu_firmware_info *ucode; 3040 3041 for (i = 0; i < ucode_count; ++i) { 3042 ucode = ucode_list[i]; 3043 psp_print_fw_hdr(psp, ucode); 3044 ret = psp_execute_ip_fw_load(psp, ucode); 3045 if (ret) 3046 return ret; 3047 } 3048 return ret; 3049 } 3050 3051 static int psp_load_non_psp_fw(struct psp_context *psp) 3052 { 3053 int i, ret; 3054 struct amdgpu_firmware_info *ucode; 3055 struct amdgpu_device *adev = psp->adev; 3056 3057 if (psp->autoload_supported && 3058 !psp->pmfw_centralized_cstate_management) { 3059 ret = psp_load_smu_fw(psp); 3060 if (ret) 3061 return ret; 3062 } 3063 3064 /* Load P2S table first if it's available */ 3065 psp_load_p2s_table(psp); 3066 3067 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3068 ucode = &adev->firmware.ucode[i]; 3069 3070 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3071 !fw_load_skip_check(psp, ucode)) { 3072 ret = psp_load_smu_fw(psp); 3073 if (ret) 3074 return ret; 3075 continue; 3076 } 3077 3078 if (fw_load_skip_check(psp, ucode)) 3079 continue; 3080 3081 if (psp->autoload_supported && 3082 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3083 IP_VERSION(11, 0, 7) || 3084 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3085 IP_VERSION(11, 0, 11) || 3086 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3087 IP_VERSION(11, 0, 12) || 3088 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3089 IP_VERSION(15, 0, 0) || 3090 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3091 IP_VERSION(15, 0, 8)) && 3092 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3093 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3094 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3095 /* PSP only receive one SDMA fw for sienna_cichlid, 3096 * as all four sdma fw are same 3097 */ 3098 continue; 3099 3100 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3101 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3102 IP_VERSION(15, 0, 8) && 3103 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3104 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3105 continue; 3106 3107 psp_print_fw_hdr(psp, ucode); 3108 3109 ret = psp_execute_ip_fw_load(psp, ucode); 3110 if (ret) 3111 return ret; 3112 3113 /* Start rlc autoload after psp received all the gfx firmware */ 3114 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3115 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3116 ret = psp_rlc_autoload_start(psp); 3117 if (ret) { 3118 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3119 return ret; 3120 } 3121 } 3122 } 3123 3124 return 0; 3125 } 3126 3127 static int psp_load_fw(struct amdgpu_device *adev) 3128 { 3129 int ret; 3130 struct psp_context *psp = &adev->psp; 3131 3132 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3133 /* should not destroy ring, only stop */ 3134 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3135 } else { 3136 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3137 3138 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3139 if (ret) { 3140 dev_err(adev->dev, "PSP ring init failed!\n"); 3141 goto failed; 3142 } 3143 } 3144 3145 ret = psp_hw_start(psp); 3146 if (ret) 3147 goto failed; 3148 3149 ret = psp_load_non_psp_fw(psp); 3150 if (ret) 3151 goto failed1; 3152 3153 ret = psp_asd_initialize(psp); 3154 if (ret) { 3155 dev_err(adev->dev, "PSP load asd failed!\n"); 3156 goto failed1; 3157 } 3158 3159 ret = psp_rl_load(adev); 3160 if (ret) { 3161 dev_err(adev->dev, "PSP load RL failed!\n"); 3162 goto failed1; 3163 } 3164 3165 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3166 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3167 ret = psp_xgmi_initialize(psp, false, true); 3168 /* Warning the XGMI seesion initialize failure 3169 * Instead of stop driver initialization 3170 */ 3171 if (ret) 3172 dev_err(psp->adev->dev, 3173 "XGMI: Failed to initialize XGMI session\n"); 3174 } 3175 } 3176 3177 if (psp->ta_fw) { 3178 ret = psp_ras_initialize(psp); 3179 if (ret) 3180 dev_err(psp->adev->dev, 3181 "RAS: Failed to initialize RAS\n"); 3182 3183 ret = psp_hdcp_initialize(psp); 3184 if (ret) 3185 dev_err(psp->adev->dev, 3186 "HDCP: Failed to initialize HDCP\n"); 3187 3188 ret = psp_dtm_initialize(psp); 3189 if (ret) 3190 dev_err(psp->adev->dev, 3191 "DTM: Failed to initialize DTM\n"); 3192 3193 ret = psp_rap_initialize(psp); 3194 if (ret) 3195 dev_err(psp->adev->dev, 3196 "RAP: Failed to initialize RAP\n"); 3197 3198 ret = psp_securedisplay_initialize(psp); 3199 if (ret) 3200 dev_err(psp->adev->dev, 3201 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3202 } 3203 3204 return 0; 3205 3206 failed1: 3207 psp_free_shared_bufs(psp); 3208 failed: 3209 /* 3210 * all cleanup jobs (xgmi terminate, ras terminate, 3211 * ring destroy, cmd/fence/fw buffers destory, 3212 * psp->cmd destory) are delayed to psp_hw_fini 3213 */ 3214 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3215 return ret; 3216 } 3217 3218 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3219 { 3220 int ret; 3221 struct amdgpu_device *adev = ip_block->adev; 3222 3223 mutex_lock(&adev->firmware.mutex); 3224 3225 ret = amdgpu_ucode_init_bo(adev); 3226 if (ret) 3227 goto failed; 3228 3229 ret = psp_load_fw(adev); 3230 if (ret) { 3231 dev_err(adev->dev, "PSP firmware loading failed\n"); 3232 goto failed; 3233 } 3234 3235 mutex_unlock(&adev->firmware.mutex); 3236 return 0; 3237 3238 failed: 3239 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3240 mutex_unlock(&adev->firmware.mutex); 3241 return -EINVAL; 3242 } 3243 3244 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3245 { 3246 struct amdgpu_device *adev = ip_block->adev; 3247 struct psp_context *psp = &adev->psp; 3248 3249 if (psp->ta_fw) { 3250 psp_ras_terminate(psp); 3251 psp_securedisplay_terminate(psp); 3252 psp_rap_terminate(psp); 3253 psp_dtm_terminate(psp); 3254 psp_hdcp_terminate(psp); 3255 3256 if (adev->gmc.xgmi.num_physical_nodes > 1) 3257 psp_xgmi_terminate(psp); 3258 } 3259 3260 psp_asd_terminate(psp); 3261 psp_tmr_terminate(psp); 3262 3263 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3264 3265 return 0; 3266 } 3267 3268 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3269 { 3270 int ret = 0; 3271 struct amdgpu_device *adev = ip_block->adev; 3272 struct psp_context *psp = &adev->psp; 3273 3274 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3275 psp->xgmi_context.context.initialized) { 3276 ret = psp_xgmi_terminate(psp); 3277 if (ret) { 3278 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3279 goto out; 3280 } 3281 } 3282 3283 if (psp->ta_fw) { 3284 ret = psp_ras_terminate(psp); 3285 if (ret) { 3286 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3287 goto out; 3288 } 3289 ret = psp_hdcp_terminate(psp); 3290 if (ret) { 3291 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3292 goto out; 3293 } 3294 ret = psp_dtm_terminate(psp); 3295 if (ret) { 3296 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3297 goto out; 3298 } 3299 ret = psp_rap_terminate(psp); 3300 if (ret) { 3301 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3302 goto out; 3303 } 3304 ret = psp_securedisplay_terminate(psp); 3305 if (ret) { 3306 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3307 goto out; 3308 } 3309 } 3310 3311 ret = psp_asd_terminate(psp); 3312 if (ret) { 3313 dev_err(adev->dev, "Failed to terminate asd\n"); 3314 goto out; 3315 } 3316 3317 ret = psp_tmr_terminate(psp); 3318 if (ret) { 3319 dev_err(adev->dev, "Failed to terminate tmr\n"); 3320 goto out; 3321 } 3322 3323 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3324 if (ret) 3325 dev_err(adev->dev, "PSP ring stop failed\n"); 3326 3327 out: 3328 return ret; 3329 } 3330 3331 static int psp_resume(struct amdgpu_ip_block *ip_block) 3332 { 3333 int ret; 3334 struct amdgpu_device *adev = ip_block->adev; 3335 struct psp_context *psp = &adev->psp; 3336 3337 dev_info(adev->dev, "PSP is resuming...\n"); 3338 3339 if (psp->mem_train_ctx.enable_mem_training) { 3340 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3341 if (ret) { 3342 dev_err(adev->dev, "Failed to process memory training!\n"); 3343 return ret; 3344 } 3345 } 3346 3347 mutex_lock(&adev->firmware.mutex); 3348 3349 ret = amdgpu_ucode_init_bo(adev); 3350 if (ret) 3351 goto failed; 3352 3353 ret = psp_hw_start(psp); 3354 if (ret) 3355 goto failed; 3356 3357 ret = psp_load_non_psp_fw(psp); 3358 if (ret) 3359 goto failed; 3360 3361 ret = psp_asd_initialize(psp); 3362 if (ret) { 3363 dev_err(adev->dev, "PSP load asd failed!\n"); 3364 goto failed; 3365 } 3366 3367 ret = psp_rl_load(adev); 3368 if (ret) { 3369 dev_err(adev->dev, "PSP load RL failed!\n"); 3370 goto failed; 3371 } 3372 3373 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3374 ret = psp_xgmi_initialize(psp, false, true); 3375 /* Warning the XGMI seesion initialize failure 3376 * Instead of stop driver initialization 3377 */ 3378 if (ret) 3379 dev_err(psp->adev->dev, 3380 "XGMI: Failed to initialize XGMI session\n"); 3381 } 3382 3383 if (psp->ta_fw) { 3384 ret = psp_ras_initialize(psp); 3385 if (ret) 3386 dev_err(psp->adev->dev, 3387 "RAS: Failed to initialize RAS\n"); 3388 3389 ret = psp_hdcp_initialize(psp); 3390 if (ret) 3391 dev_err(psp->adev->dev, 3392 "HDCP: Failed to initialize HDCP\n"); 3393 3394 ret = psp_dtm_initialize(psp); 3395 if (ret) 3396 dev_err(psp->adev->dev, 3397 "DTM: Failed to initialize DTM\n"); 3398 3399 ret = psp_rap_initialize(psp); 3400 if (ret) 3401 dev_err(psp->adev->dev, 3402 "RAP: Failed to initialize RAP\n"); 3403 3404 ret = psp_securedisplay_initialize(psp); 3405 if (ret) 3406 dev_err(psp->adev->dev, 3407 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3408 } 3409 3410 mutex_unlock(&adev->firmware.mutex); 3411 3412 return 0; 3413 3414 failed: 3415 dev_err(adev->dev, "PSP resume failed\n"); 3416 mutex_unlock(&adev->firmware.mutex); 3417 return ret; 3418 } 3419 3420 int psp_gpu_reset(struct amdgpu_device *adev) 3421 { 3422 int ret; 3423 3424 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3425 return 0; 3426 3427 mutex_lock(&adev->psp.mutex); 3428 ret = psp_mode1_reset(&adev->psp); 3429 mutex_unlock(&adev->psp.mutex); 3430 3431 return ret; 3432 } 3433 3434 int psp_rlc_autoload_start(struct psp_context *psp) 3435 { 3436 int ret; 3437 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3438 3439 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3440 3441 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3442 psp->fence_buf_mc_addr); 3443 3444 release_psp_cmd_buf(psp); 3445 3446 return ret; 3447 } 3448 3449 int psp_ring_cmd_submit(struct psp_context *psp, 3450 uint64_t cmd_buf_mc_addr, 3451 uint64_t fence_mc_addr, 3452 int index) 3453 { 3454 unsigned int psp_write_ptr_reg = 0; 3455 struct psp_gfx_rb_frame *write_frame; 3456 struct psp_ring *ring = &psp->km_ring; 3457 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3458 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3459 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3460 struct amdgpu_device *adev = psp->adev; 3461 uint32_t ring_size_dw = ring->ring_size / 4; 3462 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3463 3464 /* KM (GPCOM) prepare write pointer */ 3465 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3466 3467 /* Update KM RB frame pointer to new frame */ 3468 /* write_frame ptr increments by size of rb_frame in bytes */ 3469 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3470 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3471 write_frame = ring_buffer_start; 3472 else 3473 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3474 /* Check invalid write_frame ptr address */ 3475 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3476 dev_err(adev->dev, 3477 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3478 ring_buffer_start, ring_buffer_end, write_frame); 3479 dev_err(adev->dev, 3480 "write_frame is pointing to address out of bounds\n"); 3481 return -EINVAL; 3482 } 3483 3484 /* Initialize KM RB frame */ 3485 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3486 3487 /* Update KM RB frame */ 3488 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3489 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3490 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3491 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3492 write_frame->fence_value = index; 3493 amdgpu_device_flush_hdp(adev, NULL); 3494 3495 /* Update the write Pointer in DWORDs */ 3496 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3497 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3498 return 0; 3499 } 3500 3501 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3502 { 3503 struct amdgpu_device *adev = psp->adev; 3504 const struct psp_firmware_header_v1_0 *asd_hdr; 3505 int err = 0; 3506 3507 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3508 "amdgpu/%s_asd.bin", chip_name); 3509 if (err) 3510 goto out; 3511 3512 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3513 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3514 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3515 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3516 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3517 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3518 return 0; 3519 out: 3520 amdgpu_ucode_release(&adev->psp.asd_fw); 3521 return err; 3522 } 3523 3524 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3525 { 3526 struct amdgpu_device *adev = psp->adev; 3527 const struct psp_firmware_header_v1_0 *toc_hdr; 3528 int err = 0; 3529 3530 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3531 "amdgpu/%s_toc.bin", chip_name); 3532 if (err) 3533 goto out; 3534 3535 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3536 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3537 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3538 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3539 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3540 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3541 return 0; 3542 out: 3543 amdgpu_ucode_release(&adev->psp.toc_fw); 3544 return err; 3545 } 3546 3547 static int parse_sos_bin_descriptor(struct psp_context *psp, 3548 const struct psp_fw_bin_desc *desc, 3549 const struct psp_firmware_header_v2_0 *sos_hdr) 3550 { 3551 uint8_t *ucode_start_addr = NULL; 3552 3553 if (!psp || !desc || !sos_hdr) 3554 return -EINVAL; 3555 3556 ucode_start_addr = (uint8_t *)sos_hdr + 3557 le32_to_cpu(desc->offset_bytes) + 3558 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3559 3560 switch (desc->fw_type) { 3561 case PSP_FW_TYPE_PSP_SOS: 3562 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3563 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3564 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3565 psp->sos.start_addr = ucode_start_addr; 3566 break; 3567 case PSP_FW_TYPE_PSP_SYS_DRV: 3568 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3569 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3570 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3571 psp->sys.start_addr = ucode_start_addr; 3572 break; 3573 case PSP_FW_TYPE_PSP_KDB: 3574 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3575 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3576 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3577 psp->kdb.start_addr = ucode_start_addr; 3578 break; 3579 case PSP_FW_TYPE_PSP_TOC: 3580 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3581 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3582 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3583 psp->toc.start_addr = ucode_start_addr; 3584 break; 3585 case PSP_FW_TYPE_PSP_SPL: 3586 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3587 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3588 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3589 psp->spl.start_addr = ucode_start_addr; 3590 break; 3591 case PSP_FW_TYPE_PSP_RL: 3592 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3593 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3594 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3595 psp->rl.start_addr = ucode_start_addr; 3596 break; 3597 case PSP_FW_TYPE_PSP_SOC_DRV: 3598 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3599 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3600 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3601 psp->soc_drv.start_addr = ucode_start_addr; 3602 break; 3603 case PSP_FW_TYPE_PSP_INTF_DRV: 3604 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3605 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3606 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3607 psp->intf_drv.start_addr = ucode_start_addr; 3608 break; 3609 case PSP_FW_TYPE_PSP_DBG_DRV: 3610 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3611 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3612 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3613 psp->dbg_drv.start_addr = ucode_start_addr; 3614 break; 3615 case PSP_FW_TYPE_PSP_RAS_DRV: 3616 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3617 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3618 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3619 psp->ras_drv.start_addr = ucode_start_addr; 3620 break; 3621 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3622 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3623 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3624 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3625 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3626 break; 3627 case PSP_FW_TYPE_PSP_SPDM_DRV: 3628 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 3629 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 3630 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3631 psp->spdm_drv.start_addr = ucode_start_addr; 3632 break; 3633 default: 3634 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3635 break; 3636 } 3637 3638 return 0; 3639 } 3640 3641 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3642 { 3643 const struct psp_firmware_header_v1_0 *sos_hdr; 3644 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3645 uint8_t *ucode_array_start_addr; 3646 3647 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3648 ucode_array_start_addr = (uint8_t *)sos_hdr + 3649 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3650 3651 if (adev->gmc.xgmi.connected_to_cpu || 3652 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3653 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3654 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3655 3656 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3657 adev->psp.sys.start_addr = ucode_array_start_addr; 3658 3659 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3660 adev->psp.sos.start_addr = ucode_array_start_addr + 3661 le32_to_cpu(sos_hdr->sos.offset_bytes); 3662 } else { 3663 /* Load alternate PSP SOS FW */ 3664 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3665 3666 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3667 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3668 3669 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3670 adev->psp.sys.start_addr = ucode_array_start_addr + 3671 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3672 3673 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3674 adev->psp.sos.start_addr = ucode_array_start_addr + 3675 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3676 } 3677 3678 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3679 dev_warn(adev->dev, "PSP SOS FW not available"); 3680 return -EINVAL; 3681 } 3682 3683 return 0; 3684 } 3685 3686 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3687 { 3688 struct amdgpu_device *adev = psp->adev; 3689 const struct psp_firmware_header_v1_0 *sos_hdr; 3690 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3691 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3692 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3693 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3694 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 3695 int fw_index, fw_bin_count, start_index = 0; 3696 const struct psp_fw_bin_desc *fw_bin; 3697 uint8_t *ucode_array_start_addr; 3698 int err = 0; 3699 3700 if (amdgpu_is_kicker_fw(adev)) 3701 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3702 "amdgpu/%s_sos_kicker.bin", chip_name); 3703 else 3704 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 3705 "amdgpu/%s_sos.bin", chip_name); 3706 if (err) 3707 goto out; 3708 3709 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3710 ucode_array_start_addr = (uint8_t *)sos_hdr + 3711 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3712 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3713 3714 switch (sos_hdr->header.header_version_major) { 3715 case 1: 3716 err = psp_init_sos_base_fw(adev); 3717 if (err) 3718 goto out; 3719 3720 if (sos_hdr->header.header_version_minor == 1) { 3721 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3722 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3723 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3724 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3725 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3726 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3727 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3728 } 3729 if (sos_hdr->header.header_version_minor == 2) { 3730 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3731 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3732 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3733 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3734 } 3735 if (sos_hdr->header.header_version_minor == 3) { 3736 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3737 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3738 adev->psp.toc.start_addr = ucode_array_start_addr + 3739 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3740 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3741 adev->psp.kdb.start_addr = ucode_array_start_addr + 3742 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3743 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3744 adev->psp.spl.start_addr = ucode_array_start_addr + 3745 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3746 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3747 adev->psp.rl.start_addr = ucode_array_start_addr + 3748 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3749 } 3750 break; 3751 case 2: 3752 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3753 3754 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 3755 3756 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 3757 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3758 err = -EINVAL; 3759 goto out; 3760 } 3761 3762 if (sos_hdr_v2_0->header.header_version_minor == 1) { 3763 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 3764 3765 fw_bin = sos_hdr_v2_1->psp_fw_bin; 3766 3767 if (psp_is_aux_sos_load_required(psp)) 3768 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3769 else 3770 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 3771 3772 } else { 3773 fw_bin = sos_hdr_v2_0->psp_fw_bin; 3774 } 3775 3776 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 3777 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 3778 sos_hdr_v2_0); 3779 if (err) 3780 goto out; 3781 } 3782 break; 3783 default: 3784 dev_err(adev->dev, 3785 "unsupported psp sos firmware\n"); 3786 err = -EINVAL; 3787 goto out; 3788 } 3789 3790 return 0; 3791 out: 3792 amdgpu_ucode_release(&adev->psp.sos_fw); 3793 3794 return err; 3795 } 3796 3797 static bool is_ta_fw_applicable(struct psp_context *psp, 3798 const struct psp_fw_bin_desc *desc) 3799 { 3800 struct amdgpu_device *adev = psp->adev; 3801 uint32_t fw_version; 3802 3803 switch (desc->fw_type) { 3804 case TA_FW_TYPE_PSP_XGMI: 3805 case TA_FW_TYPE_PSP_XGMI_AUX: 3806 /* for now, AUX TA only exists on 13.0.6 ta bin, 3807 * from v20.00.0x.14 3808 */ 3809 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3810 IP_VERSION(13, 0, 6)) { 3811 fw_version = le32_to_cpu(desc->fw_version); 3812 3813 if (adev->flags & AMD_IS_APU && 3814 (fw_version & 0xff) >= 0x14) 3815 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 3816 else 3817 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 3818 } 3819 break; 3820 default: 3821 break; 3822 } 3823 3824 return true; 3825 } 3826 3827 static int parse_ta_bin_descriptor(struct psp_context *psp, 3828 const struct psp_fw_bin_desc *desc, 3829 const struct ta_firmware_header_v2_0 *ta_hdr) 3830 { 3831 uint8_t *ucode_start_addr = NULL; 3832 3833 if (!psp || !desc || !ta_hdr) 3834 return -EINVAL; 3835 3836 if (!is_ta_fw_applicable(psp, desc)) 3837 return 0; 3838 3839 ucode_start_addr = (uint8_t *)ta_hdr + 3840 le32_to_cpu(desc->offset_bytes) + 3841 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3842 3843 switch (desc->fw_type) { 3844 case TA_FW_TYPE_PSP_ASD: 3845 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3846 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3847 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3848 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3849 break; 3850 case TA_FW_TYPE_PSP_XGMI: 3851 case TA_FW_TYPE_PSP_XGMI_AUX: 3852 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3853 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3854 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3855 break; 3856 case TA_FW_TYPE_PSP_RAS: 3857 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3858 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3859 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3860 break; 3861 case TA_FW_TYPE_PSP_HDCP: 3862 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3863 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3864 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3865 break; 3866 case TA_FW_TYPE_PSP_DTM: 3867 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3868 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3869 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3870 break; 3871 case TA_FW_TYPE_PSP_RAP: 3872 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3873 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3874 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3875 break; 3876 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3877 psp->securedisplay_context.context.bin_desc.fw_version = 3878 le32_to_cpu(desc->fw_version); 3879 psp->securedisplay_context.context.bin_desc.size_bytes = 3880 le32_to_cpu(desc->size_bytes); 3881 psp->securedisplay_context.context.bin_desc.start_addr = 3882 ucode_start_addr; 3883 break; 3884 default: 3885 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3886 break; 3887 } 3888 3889 return 0; 3890 } 3891 3892 static int parse_ta_v1_microcode(struct psp_context *psp) 3893 { 3894 const struct ta_firmware_header_v1_0 *ta_hdr; 3895 struct amdgpu_device *adev = psp->adev; 3896 3897 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3898 3899 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3900 return -EINVAL; 3901 3902 adev->psp.xgmi_context.context.bin_desc.fw_version = 3903 le32_to_cpu(ta_hdr->xgmi.fw_version); 3904 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3905 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3906 adev->psp.xgmi_context.context.bin_desc.start_addr = 3907 (uint8_t *)ta_hdr + 3908 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3909 3910 adev->psp.ras_context.context.bin_desc.fw_version = 3911 le32_to_cpu(ta_hdr->ras.fw_version); 3912 adev->psp.ras_context.context.bin_desc.size_bytes = 3913 le32_to_cpu(ta_hdr->ras.size_bytes); 3914 adev->psp.ras_context.context.bin_desc.start_addr = 3915 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3916 le32_to_cpu(ta_hdr->ras.offset_bytes); 3917 3918 adev->psp.hdcp_context.context.bin_desc.fw_version = 3919 le32_to_cpu(ta_hdr->hdcp.fw_version); 3920 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3921 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3922 adev->psp.hdcp_context.context.bin_desc.start_addr = 3923 (uint8_t *)ta_hdr + 3924 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3925 3926 adev->psp.dtm_context.context.bin_desc.fw_version = 3927 le32_to_cpu(ta_hdr->dtm.fw_version); 3928 adev->psp.dtm_context.context.bin_desc.size_bytes = 3929 le32_to_cpu(ta_hdr->dtm.size_bytes); 3930 adev->psp.dtm_context.context.bin_desc.start_addr = 3931 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3932 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3933 3934 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3935 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3936 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3937 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3938 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3939 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3940 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3941 3942 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3943 3944 return 0; 3945 } 3946 3947 static int parse_ta_v2_microcode(struct psp_context *psp) 3948 { 3949 const struct ta_firmware_header_v2_0 *ta_hdr; 3950 struct amdgpu_device *adev = psp->adev; 3951 int err = 0; 3952 int ta_index = 0; 3953 3954 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3955 3956 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3957 return -EINVAL; 3958 3959 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3960 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3961 return -EINVAL; 3962 } 3963 3964 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3965 err = parse_ta_bin_descriptor(psp, 3966 &ta_hdr->ta_fw_bin[ta_index], 3967 ta_hdr); 3968 if (err) 3969 return err; 3970 } 3971 3972 return 0; 3973 } 3974 3975 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3976 { 3977 const struct common_firmware_header *hdr; 3978 struct amdgpu_device *adev = psp->adev; 3979 int err; 3980 3981 if (amdgpu_is_kicker_fw(adev)) 3982 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3983 "amdgpu/%s_ta_kicker.bin", chip_name); 3984 else 3985 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 3986 "amdgpu/%s_ta.bin", chip_name); 3987 if (err) 3988 return err; 3989 3990 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3991 switch (le16_to_cpu(hdr->header_version_major)) { 3992 case 1: 3993 err = parse_ta_v1_microcode(psp); 3994 break; 3995 case 2: 3996 err = parse_ta_v2_microcode(psp); 3997 break; 3998 default: 3999 dev_err(adev->dev, "unsupported TA header version\n"); 4000 err = -EINVAL; 4001 } 4002 4003 if (err) 4004 amdgpu_ucode_release(&adev->psp.ta_fw); 4005 4006 return err; 4007 } 4008 4009 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4010 { 4011 struct amdgpu_device *adev = psp->adev; 4012 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4013 struct amdgpu_firmware_info *info = NULL; 4014 int err = 0; 4015 4016 if (!amdgpu_sriov_vf(adev)) { 4017 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4018 return -EINVAL; 4019 } 4020 4021 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4022 "amdgpu/%s_cap.bin", chip_name); 4023 if (err) { 4024 if (err == -ENODEV) { 4025 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4026 err = 0; 4027 } else { 4028 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4029 } 4030 goto out; 4031 } 4032 4033 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4034 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4035 info->fw = adev->psp.cap_fw; 4036 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4037 adev->psp.cap_fw->data; 4038 adev->firmware.fw_size += ALIGN( 4039 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4040 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4041 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4042 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4043 4044 return 0; 4045 4046 out: 4047 amdgpu_ucode_release(&adev->psp.cap_fw); 4048 return err; 4049 } 4050 4051 int psp_config_sq_perfmon(struct psp_context *psp, 4052 uint32_t xcp_id, bool core_override_enable, 4053 bool reg_override_enable, bool perfmon_override_enable) 4054 { 4055 int ret; 4056 4057 if (amdgpu_sriov_vf(psp->adev)) 4058 return 0; 4059 4060 if (xcp_id > MAX_XCP) { 4061 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4062 return -EINVAL; 4063 } 4064 4065 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4066 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4067 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4068 return -EINVAL; 4069 } 4070 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4071 4072 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4073 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4074 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4075 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4076 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4077 4078 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4079 if (ret) 4080 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4081 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4082 4083 release_psp_cmd_buf(psp); 4084 return ret; 4085 } 4086 4087 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4088 enum amd_clockgating_state state) 4089 { 4090 return 0; 4091 } 4092 4093 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4094 enum amd_powergating_state state) 4095 { 4096 return 0; 4097 } 4098 4099 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4100 struct device_attribute *attr, 4101 char *buf) 4102 { 4103 struct drm_device *ddev = dev_get_drvdata(dev); 4104 struct amdgpu_device *adev = drm_to_adev(ddev); 4105 struct amdgpu_ip_block *ip_block; 4106 uint32_t fw_ver; 4107 int ret; 4108 4109 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4110 if (!ip_block || !ip_block->status.late_initialized) { 4111 dev_info(adev->dev, "PSP block is not ready yet\n."); 4112 return -EBUSY; 4113 } 4114 4115 mutex_lock(&adev->psp.mutex); 4116 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4117 mutex_unlock(&adev->psp.mutex); 4118 4119 if (ret) { 4120 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4121 return ret; 4122 } 4123 4124 return sysfs_emit(buf, "%x\n", fw_ver); 4125 } 4126 4127 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4128 struct device_attribute *attr, 4129 const char *buf, 4130 size_t count) 4131 { 4132 struct drm_device *ddev = dev_get_drvdata(dev); 4133 struct amdgpu_device *adev = drm_to_adev(ddev); 4134 int ret, idx; 4135 const struct firmware *usbc_pd_fw; 4136 struct amdgpu_bo *fw_buf_bo = NULL; 4137 uint64_t fw_pri_mc_addr; 4138 void *fw_pri_cpu_addr; 4139 struct amdgpu_ip_block *ip_block; 4140 4141 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4142 if (!ip_block || !ip_block->status.late_initialized) { 4143 dev_err(adev->dev, "PSP block is not ready yet."); 4144 return -EBUSY; 4145 } 4146 4147 if (!drm_dev_enter(ddev, &idx)) 4148 return -ENODEV; 4149 4150 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4151 "amdgpu/%s", buf); 4152 if (ret) 4153 goto fail; 4154 4155 /* LFB address which is aligned to 1MB boundary per PSP request */ 4156 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4157 AMDGPU_GEM_DOMAIN_VRAM | 4158 AMDGPU_GEM_DOMAIN_GTT, 4159 &fw_buf_bo, &fw_pri_mc_addr, 4160 &fw_pri_cpu_addr); 4161 if (ret) 4162 goto rel_buf; 4163 4164 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4165 4166 mutex_lock(&adev->psp.mutex); 4167 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4168 mutex_unlock(&adev->psp.mutex); 4169 4170 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4171 4172 rel_buf: 4173 amdgpu_ucode_release(&usbc_pd_fw); 4174 fail: 4175 if (ret) { 4176 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4177 count = ret; 4178 } 4179 4180 drm_dev_exit(idx); 4181 return count; 4182 } 4183 4184 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4185 { 4186 int idx; 4187 4188 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4189 return; 4190 4191 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4192 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4193 4194 drm_dev_exit(idx); 4195 } 4196 4197 /** 4198 * DOC: usbc_pd_fw 4199 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4200 * this file will trigger the update process. 4201 */ 4202 static DEVICE_ATTR(usbc_pd_fw, 0644, 4203 psp_usbc_pd_fw_sysfs_read, 4204 psp_usbc_pd_fw_sysfs_write); 4205 4206 int is_psp_fw_valid(struct psp_bin_desc bin) 4207 { 4208 return bin.size_bytes; 4209 } 4210 4211 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4212 const struct bin_attribute *bin_attr, 4213 char *buffer, loff_t pos, size_t count) 4214 { 4215 struct device *dev = kobj_to_dev(kobj); 4216 struct drm_device *ddev = dev_get_drvdata(dev); 4217 struct amdgpu_device *adev = drm_to_adev(ddev); 4218 4219 adev->psp.vbflash_done = false; 4220 4221 /* Safeguard against memory drain */ 4222 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4223 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4224 kvfree(adev->psp.vbflash_tmp_buf); 4225 adev->psp.vbflash_tmp_buf = NULL; 4226 adev->psp.vbflash_image_size = 0; 4227 return -ENOMEM; 4228 } 4229 4230 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4231 if (!adev->psp.vbflash_tmp_buf) { 4232 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4233 if (!adev->psp.vbflash_tmp_buf) 4234 return -ENOMEM; 4235 } 4236 4237 mutex_lock(&adev->psp.mutex); 4238 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4239 adev->psp.vbflash_image_size += count; 4240 mutex_unlock(&adev->psp.mutex); 4241 4242 dev_dbg(adev->dev, "IFWI staged for update\n"); 4243 4244 return count; 4245 } 4246 4247 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4248 const struct bin_attribute *bin_attr, char *buffer, 4249 loff_t pos, size_t count) 4250 { 4251 struct device *dev = kobj_to_dev(kobj); 4252 struct drm_device *ddev = dev_get_drvdata(dev); 4253 struct amdgpu_device *adev = drm_to_adev(ddev); 4254 struct amdgpu_bo *fw_buf_bo = NULL; 4255 uint64_t fw_pri_mc_addr; 4256 void *fw_pri_cpu_addr; 4257 int ret; 4258 4259 if (adev->psp.vbflash_image_size == 0) 4260 return -EINVAL; 4261 4262 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4263 4264 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4265 AMDGPU_GPU_PAGE_SIZE, 4266 AMDGPU_GEM_DOMAIN_VRAM, 4267 &fw_buf_bo, 4268 &fw_pri_mc_addr, 4269 &fw_pri_cpu_addr); 4270 if (ret) 4271 goto rel_buf; 4272 4273 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4274 4275 mutex_lock(&adev->psp.mutex); 4276 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4277 mutex_unlock(&adev->psp.mutex); 4278 4279 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4280 4281 rel_buf: 4282 kvfree(adev->psp.vbflash_tmp_buf); 4283 adev->psp.vbflash_tmp_buf = NULL; 4284 adev->psp.vbflash_image_size = 0; 4285 4286 if (ret) { 4287 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4288 return ret; 4289 } 4290 4291 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4292 return 0; 4293 } 4294 4295 /** 4296 * DOC: psp_vbflash 4297 * Writing to this file will stage an IFWI for update. Reading from this file 4298 * will trigger the update process. 4299 */ 4300 static const struct bin_attribute psp_vbflash_bin_attr = { 4301 .attr = {.name = "psp_vbflash", .mode = 0660}, 4302 .size = 0, 4303 .write = amdgpu_psp_vbflash_write, 4304 .read = amdgpu_psp_vbflash_read, 4305 }; 4306 4307 /** 4308 * DOC: psp_vbflash_status 4309 * The status of the flash process. 4310 * 0: IFWI flash not complete. 4311 * 1: IFWI flash complete. 4312 */ 4313 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4314 struct device_attribute *attr, 4315 char *buf) 4316 { 4317 struct drm_device *ddev = dev_get_drvdata(dev); 4318 struct amdgpu_device *adev = drm_to_adev(ddev); 4319 uint32_t vbflash_status; 4320 4321 vbflash_status = psp_vbflash_status(&adev->psp); 4322 if (!adev->psp.vbflash_done) 4323 vbflash_status = 0; 4324 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4325 vbflash_status = 1; 4326 4327 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4328 } 4329 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4330 4331 static const struct bin_attribute *const bin_flash_attrs[] = { 4332 &psp_vbflash_bin_attr, 4333 NULL 4334 }; 4335 4336 static struct attribute *flash_attrs[] = { 4337 &dev_attr_psp_vbflash_status.attr, 4338 &dev_attr_usbc_pd_fw.attr, 4339 NULL 4340 }; 4341 4342 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4343 { 4344 struct device *dev = kobj_to_dev(kobj); 4345 struct drm_device *ddev = dev_get_drvdata(dev); 4346 struct amdgpu_device *adev = drm_to_adev(ddev); 4347 4348 if (attr == &dev_attr_usbc_pd_fw.attr) 4349 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4350 4351 return adev->psp.sup_ifwi_up ? 0440 : 0; 4352 } 4353 4354 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4355 const struct bin_attribute *attr, 4356 int idx) 4357 { 4358 struct device *dev = kobj_to_dev(kobj); 4359 struct drm_device *ddev = dev_get_drvdata(dev); 4360 struct amdgpu_device *adev = drm_to_adev(ddev); 4361 4362 return adev->psp.sup_ifwi_up ? 0660 : 0; 4363 } 4364 4365 const struct attribute_group amdgpu_flash_attr_group = { 4366 .attrs = flash_attrs, 4367 .bin_attrs = bin_flash_attrs, 4368 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4369 .is_visible = amdgpu_flash_attr_is_visible, 4370 }; 4371 4372 #if defined(CONFIG_DEBUG_FS) 4373 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4374 { 4375 struct amdgpu_device *adev = filp->f_inode->i_private; 4376 struct spirom_bo *bo_triplet; 4377 int ret; 4378 4379 /* serialize the open() file calling */ 4380 if (!mutex_trylock(&adev->psp.mutex)) 4381 return -EBUSY; 4382 4383 /* 4384 * make sure only one userpace process is alive for dumping so that 4385 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4386 * let's say the case where one process try opening the file while 4387 * another one has proceeded to read or release. In this way, eliminate 4388 * the use of mutex for read() or release() callback as well. 4389 */ 4390 if (adev->psp.spirom_dump_trip) { 4391 mutex_unlock(&adev->psp.mutex); 4392 return -EBUSY; 4393 } 4394 4395 bo_triplet = kzalloc_obj(struct spirom_bo); 4396 if (!bo_triplet) { 4397 mutex_unlock(&adev->psp.mutex); 4398 return -ENOMEM; 4399 } 4400 4401 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4402 AMDGPU_GPU_PAGE_SIZE, 4403 AMDGPU_GEM_DOMAIN_GTT, 4404 &bo_triplet->bo, 4405 &bo_triplet->mc_addr, 4406 &bo_triplet->cpu_addr); 4407 if (ret) 4408 goto rel_trip; 4409 4410 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4411 if (ret) 4412 goto rel_bo; 4413 4414 adev->psp.spirom_dump_trip = bo_triplet; 4415 mutex_unlock(&adev->psp.mutex); 4416 return 0; 4417 rel_bo: 4418 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4419 &bo_triplet->cpu_addr); 4420 rel_trip: 4421 kfree(bo_triplet); 4422 mutex_unlock(&adev->psp.mutex); 4423 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4424 return ret; 4425 } 4426 4427 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4428 loff_t *pos) 4429 { 4430 struct amdgpu_device *adev = filp->f_inode->i_private; 4431 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4432 4433 if (!bo_triplet) 4434 return -EINVAL; 4435 4436 return simple_read_from_buffer(buf, 4437 size, 4438 pos, bo_triplet->cpu_addr, 4439 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4440 } 4441 4442 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4443 { 4444 struct amdgpu_device *adev = filp->f_inode->i_private; 4445 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4446 4447 if (bo_triplet) { 4448 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4449 &bo_triplet->cpu_addr); 4450 kfree(bo_triplet); 4451 } 4452 4453 adev->psp.spirom_dump_trip = NULL; 4454 return 0; 4455 } 4456 4457 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4458 .owner = THIS_MODULE, 4459 .open = psp_read_spirom_debugfs_open, 4460 .read = psp_read_spirom_debugfs_read, 4461 .release = psp_read_spirom_debugfs_release, 4462 .llseek = default_llseek, 4463 }; 4464 #endif 4465 4466 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4467 { 4468 #if defined(CONFIG_DEBUG_FS) 4469 struct drm_minor *minor = adev_to_drm(adev)->primary; 4470 4471 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4472 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4473 #endif 4474 } 4475 4476 const struct amd_ip_funcs psp_ip_funcs = { 4477 .name = "psp", 4478 .early_init = psp_early_init, 4479 .sw_init = psp_sw_init, 4480 .sw_fini = psp_sw_fini, 4481 .hw_init = psp_hw_init, 4482 .hw_fini = psp_hw_fini, 4483 .suspend = psp_suspend, 4484 .resume = psp_resume, 4485 .set_clockgating_state = psp_set_clockgating_state, 4486 .set_powergating_state = psp_set_powergating_state, 4487 }; 4488 4489 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4490 .type = AMD_IP_BLOCK_TYPE_PSP, 4491 .major = 3, 4492 .minor = 1, 4493 .rev = 0, 4494 .funcs = &psp_ip_funcs, 4495 }; 4496 4497 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4498 .type = AMD_IP_BLOCK_TYPE_PSP, 4499 .major = 10, 4500 .minor = 0, 4501 .rev = 0, 4502 .funcs = &psp_ip_funcs, 4503 }; 4504 4505 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4506 .type = AMD_IP_BLOCK_TYPE_PSP, 4507 .major = 11, 4508 .minor = 0, 4509 .rev = 0, 4510 .funcs = &psp_ip_funcs, 4511 }; 4512 4513 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4514 .type = AMD_IP_BLOCK_TYPE_PSP, 4515 .major = 11, 4516 .minor = 0, 4517 .rev = 8, 4518 .funcs = &psp_ip_funcs, 4519 }; 4520 4521 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4522 .type = AMD_IP_BLOCK_TYPE_PSP, 4523 .major = 12, 4524 .minor = 0, 4525 .rev = 0, 4526 .funcs = &psp_ip_funcs, 4527 }; 4528 4529 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4530 .type = AMD_IP_BLOCK_TYPE_PSP, 4531 .major = 13, 4532 .minor = 0, 4533 .rev = 0, 4534 .funcs = &psp_ip_funcs, 4535 }; 4536 4537 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4538 .type = AMD_IP_BLOCK_TYPE_PSP, 4539 .major = 13, 4540 .minor = 0, 4541 .rev = 4, 4542 .funcs = &psp_ip_funcs, 4543 }; 4544 4545 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4546 .type = AMD_IP_BLOCK_TYPE_PSP, 4547 .major = 14, 4548 .minor = 0, 4549 .rev = 0, 4550 .funcs = &psp_ip_funcs, 4551 }; 4552 4553 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 4554 .type = AMD_IP_BLOCK_TYPE_PSP, 4555 .major = 15, 4556 .minor = 0, 4557 .rev = 0, 4558 .funcs = &psp_ip_funcs, 4559 }; 4560 4561 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 4562 .type = AMD_IP_BLOCK_TYPE_PSP, 4563 .major = 15, 4564 .minor = 0, 4565 .rev = 8, 4566 .funcs = &psp_ip_funcs, 4567 }; 4568