1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/dma-mapping.h> 28 #include <drm/drm_drv.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 #include <drm/drm_drv.h> 45 46 static int psp_sysfs_init(struct amdgpu_device *adev); 47 static void psp_sysfs_fini(struct amdgpu_device *adev); 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 51 /* 52 * Due to DF Cstate management centralized to PMFW, the firmware 53 * loading sequence will be updated as below: 54 * - Load KDB 55 * - Load SYS_DRV 56 * - Load tOS 57 * - Load PMFW 58 * - Setup TMR 59 * - Load other non-psp fw 60 * - Load ASD 61 * - Load XGMI/RAS/HDCP/DTM TA if any 62 * 63 * This new sequence is required for 64 * - Arcturus and onwards 65 * - Navi12 and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 psp->pmfw_centralized_cstate_management = false; 72 73 if (amdgpu_sriov_vf(adev)) 74 return; 75 76 if (adev->flags & AMD_IS_APU) 77 return; 78 79 if ((adev->asic_type >= CHIP_ARCTURUS) || 80 (adev->asic_type >= CHIP_NAVI12)) 81 psp->pmfw_centralized_cstate_management = true; 82 } 83 84 static int psp_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 struct psp_context *psp = &adev->psp; 88 89 switch (adev->asic_type) { 90 case CHIP_VEGA10: 91 case CHIP_VEGA12: 92 psp_v3_1_set_psp_funcs(psp); 93 psp->autoload_supported = false; 94 break; 95 case CHIP_RAVEN: 96 psp_v10_0_set_psp_funcs(psp); 97 psp->autoload_supported = false; 98 break; 99 case CHIP_VEGA20: 100 case CHIP_ARCTURUS: 101 psp_v11_0_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case CHIP_NAVI10: 105 case CHIP_NAVI14: 106 case CHIP_NAVI12: 107 case CHIP_SIENNA_CICHLID: 108 case CHIP_NAVY_FLOUNDER: 109 case CHIP_VANGOGH: 110 case CHIP_DIMGREY_CAVEFISH: 111 case CHIP_BEIGE_GOBY: 112 psp_v11_0_set_psp_funcs(psp); 113 psp->autoload_supported = true; 114 break; 115 case CHIP_RENOIR: 116 psp_v12_0_set_psp_funcs(psp); 117 break; 118 case CHIP_ALDEBARAN: 119 psp_v13_0_set_psp_funcs(psp); 120 break; 121 case CHIP_YELLOW_CARP: 122 psp_v13_0_set_psp_funcs(psp); 123 psp->autoload_supported = true; 124 break; 125 default: 126 return -EINVAL; 127 } 128 129 psp->adev = adev; 130 131 psp_check_pmfw_centralized_cstate_management(psp); 132 133 return 0; 134 } 135 136 static void psp_memory_training_fini(struct psp_context *psp) 137 { 138 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 139 140 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 141 kfree(ctx->sys_cache); 142 ctx->sys_cache = NULL; 143 } 144 145 static int psp_memory_training_init(struct psp_context *psp) 146 { 147 int ret; 148 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 149 150 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 151 DRM_DEBUG("memory training is not supported!\n"); 152 return 0; 153 } 154 155 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 156 if (ctx->sys_cache == NULL) { 157 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 158 ret = -ENOMEM; 159 goto Err_out; 160 } 161 162 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 163 ctx->train_data_size, 164 ctx->p2c_train_data_offset, 165 ctx->c2p_train_data_offset); 166 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 167 return 0; 168 169 Err_out: 170 psp_memory_training_fini(psp); 171 return ret; 172 } 173 174 static int psp_sw_init(void *handle) 175 { 176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 177 struct psp_context *psp = &adev->psp; 178 int ret; 179 180 if (!amdgpu_sriov_vf(adev)) { 181 ret = psp_init_microcode(psp); 182 if (ret) { 183 DRM_ERROR("Failed to load psp firmware!\n"); 184 return ret; 185 } 186 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 187 ret = psp_init_ta_microcode(psp, "aldebaran"); 188 if (ret) { 189 DRM_ERROR("Failed to initialize ta microcode!\n"); 190 return ret; 191 } 192 } 193 194 ret = psp_memory_training_init(psp); 195 if (ret) { 196 DRM_ERROR("Failed to initialize memory training!\n"); 197 return ret; 198 } 199 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 200 if (ret) { 201 DRM_ERROR("Failed to process memory training!\n"); 202 return ret; 203 } 204 205 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 206 ret= psp_sysfs_init(adev); 207 if (ret) { 208 return ret; 209 } 210 } 211 212 return 0; 213 } 214 215 static int psp_sw_fini(void *handle) 216 { 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 219 psp_memory_training_fini(&adev->psp); 220 if (adev->psp.sos_fw) { 221 release_firmware(adev->psp.sos_fw); 222 adev->psp.sos_fw = NULL; 223 } 224 if (adev->psp.asd_fw) { 225 release_firmware(adev->psp.asd_fw); 226 adev->psp.asd_fw = NULL; 227 } 228 if (adev->psp.ta_fw) { 229 release_firmware(adev->psp.ta_fw); 230 adev->psp.ta_fw = NULL; 231 } 232 233 if (adev->asic_type == CHIP_NAVI10 || 234 adev->asic_type == CHIP_SIENNA_CICHLID) 235 psp_sysfs_fini(adev); 236 237 return 0; 238 } 239 240 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 241 uint32_t reg_val, uint32_t mask, bool check_changed) 242 { 243 uint32_t val; 244 int i; 245 struct amdgpu_device *adev = psp->adev; 246 247 if (psp->adev->no_hw_access) 248 return 0; 249 250 for (i = 0; i < adev->usec_timeout; i++) { 251 val = RREG32(reg_index); 252 if (check_changed) { 253 if (val != reg_val) 254 return 0; 255 } else { 256 if ((val & mask) == reg_val) 257 return 0; 258 } 259 udelay(1); 260 } 261 262 return -ETIME; 263 } 264 265 static int 266 psp_cmd_submit_buf(struct psp_context *psp, 267 struct amdgpu_firmware_info *ucode, 268 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 269 { 270 int ret; 271 int index, idx; 272 int timeout = 20000; 273 bool ras_intr = false; 274 bool skip_unsupport = false; 275 276 if (psp->adev->no_hw_access) 277 return 0; 278 279 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 280 return 0; 281 282 mutex_lock(&psp->mutex); 283 284 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 285 286 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 287 288 index = atomic_inc_return(&psp->fence_value); 289 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 290 if (ret) { 291 atomic_dec(&psp->fence_value); 292 goto exit; 293 } 294 295 amdgpu_device_invalidate_hdp(psp->adev, NULL); 296 while (*((unsigned int *)psp->fence_buf) != index) { 297 if (--timeout == 0) 298 break; 299 /* 300 * Shouldn't wait for timeout when err_event_athub occurs, 301 * because gpu reset thread triggered and lock resource should 302 * be released for psp resume sequence. 303 */ 304 ras_intr = amdgpu_ras_intr_triggered(); 305 if (ras_intr) 306 break; 307 usleep_range(10, 100); 308 amdgpu_device_invalidate_hdp(psp->adev, NULL); 309 } 310 311 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 312 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 313 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 314 315 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 316 317 /* In some cases, psp response status is not 0 even there is no 318 * problem while the command is submitted. Some version of PSP FW 319 * doesn't write 0 to that field. 320 * So here we would like to only print a warning instead of an error 321 * during psp initialization to avoid breaking hw_init and it doesn't 322 * return -EINVAL. 323 */ 324 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 325 if (ucode) 326 DRM_WARN("failed to load ucode id (%d) ", 327 ucode->ucode_id); 328 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n", 329 psp->cmd_buf_mem->cmd_id, 330 psp->cmd_buf_mem->resp.status); 331 if (!timeout) { 332 ret = -EINVAL; 333 goto exit; 334 } 335 } 336 337 if (ucode) { 338 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 339 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 340 } 341 342 exit: 343 mutex_unlock(&psp->mutex); 344 drm_dev_exit(idx); 345 return ret; 346 } 347 348 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 349 struct psp_gfx_cmd_resp *cmd, 350 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 351 { 352 struct amdgpu_device *adev = psp->adev; 353 uint32_t size = amdgpu_bo_size(tmr_bo); 354 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 355 356 if (amdgpu_sriov_vf(psp->adev)) 357 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 358 else 359 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 360 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 361 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 362 cmd->cmd.cmd_setup_tmr.buf_size = size; 363 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 364 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 365 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 366 } 367 368 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 369 uint64_t pri_buf_mc, uint32_t size) 370 { 371 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 372 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 373 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 374 cmd->cmd.cmd_load_toc.toc_size = size; 375 } 376 377 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 378 static int psp_load_toc(struct psp_context *psp, 379 uint32_t *tmr_size) 380 { 381 int ret; 382 struct psp_gfx_cmd_resp *cmd; 383 384 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 385 if (!cmd) 386 return -ENOMEM; 387 /* Copy toc to psp firmware private buffer */ 388 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size); 389 390 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 391 392 ret = psp_cmd_submit_buf(psp, NULL, cmd, 393 psp->fence_buf_mc_addr); 394 if (!ret) 395 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 396 kfree(cmd); 397 return ret; 398 } 399 400 /* Set up Trusted Memory Region */ 401 static int psp_tmr_init(struct psp_context *psp) 402 { 403 int ret; 404 int tmr_size; 405 void *tmr_buf; 406 void **pptr; 407 408 /* 409 * According to HW engineer, they prefer the TMR address be "naturally 410 * aligned" , e.g. the start address be an integer divide of TMR size. 411 * 412 * Note: this memory need be reserved till the driver 413 * uninitializes. 414 */ 415 tmr_size = PSP_TMR_SIZE(psp->adev); 416 417 /* For ASICs support RLC autoload, psp will parse the toc 418 * and calculate the total size of TMR needed */ 419 if (!amdgpu_sriov_vf(psp->adev) && 420 psp->toc_start_addr && 421 psp->toc_bin_size && 422 psp->fw_pri_buf) { 423 ret = psp_load_toc(psp, &tmr_size); 424 if (ret) { 425 DRM_ERROR("Failed to load toc\n"); 426 return ret; 427 } 428 } 429 430 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 431 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 432 AMDGPU_GEM_DOMAIN_VRAM, 433 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 434 435 return ret; 436 } 437 438 static bool psp_skip_tmr(struct psp_context *psp) 439 { 440 switch (psp->adev->asic_type) { 441 case CHIP_NAVI12: 442 case CHIP_SIENNA_CICHLID: 443 case CHIP_ALDEBARAN: 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 static int psp_tmr_load(struct psp_context *psp) 451 { 452 int ret; 453 struct psp_gfx_cmd_resp *cmd; 454 455 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 456 * Already set up by host driver. 457 */ 458 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 459 return 0; 460 461 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 462 if (!cmd) 463 return -ENOMEM; 464 465 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 466 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 467 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 468 469 ret = psp_cmd_submit_buf(psp, NULL, cmd, 470 psp->fence_buf_mc_addr); 471 472 kfree(cmd); 473 474 return ret; 475 } 476 477 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 478 struct psp_gfx_cmd_resp *cmd) 479 { 480 if (amdgpu_sriov_vf(psp->adev)) 481 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 482 else 483 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 484 } 485 486 static int psp_tmr_unload(struct psp_context *psp) 487 { 488 int ret; 489 struct psp_gfx_cmd_resp *cmd; 490 491 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 492 if (!cmd) 493 return -ENOMEM; 494 495 psp_prep_tmr_unload_cmd_buf(psp, cmd); 496 DRM_INFO("free PSP TMR buffer\n"); 497 498 ret = psp_cmd_submit_buf(psp, NULL, cmd, 499 psp->fence_buf_mc_addr); 500 501 kfree(cmd); 502 503 return ret; 504 } 505 506 static int psp_tmr_terminate(struct psp_context *psp) 507 { 508 int ret; 509 void *tmr_buf; 510 void **pptr; 511 512 ret = psp_tmr_unload(psp); 513 if (ret) 514 return ret; 515 516 /* free TMR memory buffer */ 517 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 518 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 519 520 return 0; 521 } 522 523 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 524 uint64_t *output_ptr) 525 { 526 int ret; 527 struct psp_gfx_cmd_resp *cmd; 528 529 if (!output_ptr) 530 return -EINVAL; 531 532 if (amdgpu_sriov_vf(psp->adev)) 533 return 0; 534 535 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 536 if (!cmd) 537 return -ENOMEM; 538 539 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 540 541 ret = psp_cmd_submit_buf(psp, NULL, cmd, 542 psp->fence_buf_mc_addr); 543 544 if (!ret) { 545 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 546 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 547 } 548 549 kfree(cmd); 550 551 return ret; 552 } 553 554 static int psp_boot_config_set(struct amdgpu_device *adev) 555 { 556 struct psp_context *psp = &adev->psp; 557 struct psp_gfx_cmd_resp *cmd = psp->cmd; 558 559 if (amdgpu_sriov_vf(adev)) 560 return 0; 561 562 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 563 564 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 565 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 566 cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC; 567 cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC; 568 569 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 570 } 571 572 static int psp_rl_load(struct amdgpu_device *adev) 573 { 574 struct psp_context *psp = &adev->psp; 575 struct psp_gfx_cmd_resp *cmd = psp->cmd; 576 577 if (psp->rl_bin_size == 0) 578 return 0; 579 580 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 581 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size); 582 583 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 584 585 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 586 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 587 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 588 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size; 589 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 590 591 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 592 } 593 594 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 595 uint64_t asd_mc, uint32_t size) 596 { 597 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 598 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 599 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 600 cmd->cmd.cmd_load_ta.app_len = size; 601 602 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 603 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 604 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 605 } 606 607 static int psp_asd_load(struct psp_context *psp) 608 { 609 int ret; 610 struct psp_gfx_cmd_resp *cmd; 611 612 /* If PSP version doesn't match ASD version, asd loading will be failed. 613 * add workaround to bypass it for sriov now. 614 * TODO: add version check to make it common 615 */ 616 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 617 return 0; 618 619 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 620 if (!cmd) 621 return -ENOMEM; 622 623 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 624 625 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 626 psp->asd_ucode_size); 627 628 ret = psp_cmd_submit_buf(psp, NULL, cmd, 629 psp->fence_buf_mc_addr); 630 if (!ret) { 631 psp->asd_context.asd_initialized = true; 632 psp->asd_context.session_id = cmd->resp.session_id; 633 } 634 635 kfree(cmd); 636 637 return ret; 638 } 639 640 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 641 uint32_t session_id) 642 { 643 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 644 cmd->cmd.cmd_unload_ta.session_id = session_id; 645 } 646 647 static int psp_asd_unload(struct psp_context *psp) 648 { 649 int ret; 650 struct psp_gfx_cmd_resp *cmd; 651 652 if (amdgpu_sriov_vf(psp->adev)) 653 return 0; 654 655 if (!psp->asd_context.asd_initialized) 656 return 0; 657 658 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 659 if (!cmd) 660 return -ENOMEM; 661 662 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 663 664 ret = psp_cmd_submit_buf(psp, NULL, cmd, 665 psp->fence_buf_mc_addr); 666 if (!ret) 667 psp->asd_context.asd_initialized = false; 668 669 kfree(cmd); 670 671 return ret; 672 } 673 674 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 675 uint32_t id, uint32_t value) 676 { 677 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 678 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 679 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 680 } 681 682 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 683 uint32_t value) 684 { 685 struct psp_gfx_cmd_resp *cmd = NULL; 686 int ret = 0; 687 688 if (reg >= PSP_REG_LAST) 689 return -EINVAL; 690 691 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 692 if (!cmd) 693 return -ENOMEM; 694 695 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 696 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 697 if (ret) 698 DRM_ERROR("PSP failed to program reg id %d", reg); 699 700 kfree(cmd); 701 return ret; 702 } 703 704 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 705 uint64_t ta_bin_mc, 706 uint32_t ta_bin_size, 707 uint64_t ta_shared_mc, 708 uint32_t ta_shared_size) 709 { 710 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 711 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 712 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 713 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 714 715 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 716 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 717 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 718 } 719 720 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 721 { 722 int ret; 723 724 /* 725 * Allocate 16k memory aligned to 4k from Frame Buffer (local 726 * physical) for xgmi ta <-> Driver 727 */ 728 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 729 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 730 &psp->xgmi_context.xgmi_shared_bo, 731 &psp->xgmi_context.xgmi_shared_mc_addr, 732 &psp->xgmi_context.xgmi_shared_buf); 733 734 return ret; 735 } 736 737 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 738 uint32_t ta_cmd_id, 739 uint32_t session_id) 740 { 741 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 742 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 743 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 744 } 745 746 static int psp_ta_invoke(struct psp_context *psp, 747 uint32_t ta_cmd_id, 748 uint32_t session_id) 749 { 750 int ret; 751 struct psp_gfx_cmd_resp *cmd; 752 753 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 754 if (!cmd) 755 return -ENOMEM; 756 757 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 758 759 ret = psp_cmd_submit_buf(psp, NULL, cmd, 760 psp->fence_buf_mc_addr); 761 762 kfree(cmd); 763 764 return ret; 765 } 766 767 static int psp_xgmi_load(struct psp_context *psp) 768 { 769 int ret; 770 struct psp_gfx_cmd_resp *cmd; 771 772 /* 773 * TODO: bypass the loading in sriov for now 774 */ 775 776 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 777 if (!cmd) 778 return -ENOMEM; 779 780 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 781 782 psp_prep_ta_load_cmd_buf(cmd, 783 psp->fw_pri_mc_addr, 784 psp->ta_xgmi_ucode_size, 785 psp->xgmi_context.xgmi_shared_mc_addr, 786 PSP_XGMI_SHARED_MEM_SIZE); 787 788 ret = psp_cmd_submit_buf(psp, NULL, cmd, 789 psp->fence_buf_mc_addr); 790 791 if (!ret) { 792 psp->xgmi_context.initialized = 1; 793 psp->xgmi_context.session_id = cmd->resp.session_id; 794 } 795 796 kfree(cmd); 797 798 return ret; 799 } 800 801 static int psp_xgmi_unload(struct psp_context *psp) 802 { 803 int ret; 804 struct psp_gfx_cmd_resp *cmd; 805 struct amdgpu_device *adev = psp->adev; 806 807 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 808 if (adev->asic_type == CHIP_ARCTURUS || 809 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 810 return 0; 811 812 /* 813 * TODO: bypass the unloading in sriov for now 814 */ 815 816 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 817 if (!cmd) 818 return -ENOMEM; 819 820 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 821 822 ret = psp_cmd_submit_buf(psp, NULL, cmd, 823 psp->fence_buf_mc_addr); 824 825 kfree(cmd); 826 827 return ret; 828 } 829 830 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 831 { 832 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 833 } 834 835 int psp_xgmi_terminate(struct psp_context *psp) 836 { 837 int ret; 838 839 if (!psp->xgmi_context.initialized) 840 return 0; 841 842 ret = psp_xgmi_unload(psp); 843 if (ret) 844 return ret; 845 846 psp->xgmi_context.initialized = 0; 847 848 /* free xgmi shared memory */ 849 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 850 &psp->xgmi_context.xgmi_shared_mc_addr, 851 &psp->xgmi_context.xgmi_shared_buf); 852 853 return 0; 854 } 855 856 int psp_xgmi_initialize(struct psp_context *psp) 857 { 858 struct ta_xgmi_shared_memory *xgmi_cmd; 859 int ret; 860 861 if (!psp->adev->psp.ta_fw || 862 !psp->adev->psp.ta_xgmi_ucode_size || 863 !psp->adev->psp.ta_xgmi_start_addr) 864 return -ENOENT; 865 866 if (!psp->xgmi_context.initialized) { 867 ret = psp_xgmi_init_shared_buf(psp); 868 if (ret) 869 return ret; 870 } 871 872 /* Load XGMI TA */ 873 ret = psp_xgmi_load(psp); 874 if (ret) 875 return ret; 876 877 /* Initialize XGMI session */ 878 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 879 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 880 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 881 882 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 883 884 return ret; 885 } 886 887 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 888 { 889 struct ta_xgmi_shared_memory *xgmi_cmd; 890 int ret; 891 892 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 893 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 894 895 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 896 897 /* Invoke xgmi ta to get hive id */ 898 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 899 if (ret) 900 return ret; 901 902 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 903 904 return 0; 905 } 906 907 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 908 { 909 struct ta_xgmi_shared_memory *xgmi_cmd; 910 int ret; 911 912 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 913 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 914 915 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 916 917 /* Invoke xgmi ta to get the node id */ 918 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 919 if (ret) 920 return ret; 921 922 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 923 924 return 0; 925 } 926 927 int psp_xgmi_get_topology_info(struct psp_context *psp, 928 int number_devices, 929 struct psp_xgmi_topology_info *topology) 930 { 931 struct ta_xgmi_shared_memory *xgmi_cmd; 932 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 933 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 934 int i; 935 int ret; 936 937 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 938 return -EINVAL; 939 940 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 941 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 942 943 /* Fill in the shared memory with topology information as input */ 944 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 945 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 946 topology_info_input->num_nodes = number_devices; 947 948 for (i = 0; i < topology_info_input->num_nodes; i++) { 949 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 950 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 951 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 952 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 953 } 954 955 /* Invoke xgmi ta to get the topology information */ 956 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 957 if (ret) 958 return ret; 959 960 /* Read the output topology information from the shared memory */ 961 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 962 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 963 for (i = 0; i < topology->num_nodes; i++) { 964 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 965 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 966 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 967 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 968 } 969 970 return 0; 971 } 972 973 int psp_xgmi_set_topology_info(struct psp_context *psp, 974 int number_devices, 975 struct psp_xgmi_topology_info *topology) 976 { 977 struct ta_xgmi_shared_memory *xgmi_cmd; 978 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 979 int i; 980 981 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 982 return -EINVAL; 983 984 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 985 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 986 987 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 988 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 989 topology_info_input->num_nodes = number_devices; 990 991 for (i = 0; i < topology_info_input->num_nodes; i++) { 992 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 993 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 994 topology_info_input->nodes[i].is_sharing_enabled = 1; 995 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 996 } 997 998 /* Invoke xgmi ta to set topology information */ 999 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1000 } 1001 1002 // ras begin 1003 static int psp_ras_init_shared_buf(struct psp_context *psp) 1004 { 1005 int ret; 1006 1007 /* 1008 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1009 * physical) for ras ta <-> Driver 1010 */ 1011 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1012 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1013 &psp->ras.ras_shared_bo, 1014 &psp->ras.ras_shared_mc_addr, 1015 &psp->ras.ras_shared_buf); 1016 1017 return ret; 1018 } 1019 1020 static int psp_ras_load(struct psp_context *psp) 1021 { 1022 int ret; 1023 struct psp_gfx_cmd_resp *cmd; 1024 struct ta_ras_shared_memory *ras_cmd; 1025 1026 /* 1027 * TODO: bypass the loading in sriov for now 1028 */ 1029 if (amdgpu_sriov_vf(psp->adev)) 1030 return 0; 1031 1032 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1033 if (!cmd) 1034 return -ENOMEM; 1035 1036 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1037 1038 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1039 1040 if (psp->adev->gmc.xgmi.connected_to_cpu) 1041 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1042 else 1043 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1044 1045 psp_prep_ta_load_cmd_buf(cmd, 1046 psp->fw_pri_mc_addr, 1047 psp->ta_ras_ucode_size, 1048 psp->ras.ras_shared_mc_addr, 1049 PSP_RAS_SHARED_MEM_SIZE); 1050 1051 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1052 psp->fence_buf_mc_addr); 1053 1054 if (!ret) { 1055 psp->ras.session_id = cmd->resp.session_id; 1056 1057 if (!ras_cmd->ras_status) 1058 psp->ras.ras_initialized = true; 1059 else 1060 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1061 } 1062 1063 if (ret || ras_cmd->ras_status) 1064 amdgpu_ras_fini(psp->adev); 1065 1066 kfree(cmd); 1067 1068 return ret; 1069 } 1070 1071 static int psp_ras_unload(struct psp_context *psp) 1072 { 1073 int ret; 1074 struct psp_gfx_cmd_resp *cmd; 1075 1076 /* 1077 * TODO: bypass the unloading in sriov for now 1078 */ 1079 if (amdgpu_sriov_vf(psp->adev)) 1080 return 0; 1081 1082 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1083 if (!cmd) 1084 return -ENOMEM; 1085 1086 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1087 1088 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1089 psp->fence_buf_mc_addr); 1090 1091 kfree(cmd); 1092 1093 return ret; 1094 } 1095 1096 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1097 { 1098 struct ta_ras_shared_memory *ras_cmd; 1099 int ret; 1100 1101 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1102 1103 /* 1104 * TODO: bypass the loading in sriov for now 1105 */ 1106 if (amdgpu_sriov_vf(psp->adev)) 1107 return 0; 1108 1109 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1110 1111 if (amdgpu_ras_intr_triggered()) 1112 return ret; 1113 1114 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1115 { 1116 DRM_WARN("RAS: Unsupported Interface"); 1117 return -EINVAL; 1118 } 1119 1120 if (!ret) { 1121 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1122 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1123 1124 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1125 } 1126 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1127 dev_warn(psp->adev->dev, 1128 "RAS internal register access blocked\n"); 1129 } 1130 1131 return ret; 1132 } 1133 1134 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1135 enum ta_ras_status ras_status) 1136 { 1137 int ret = -EINVAL; 1138 1139 switch (ras_status) { 1140 case TA_RAS_STATUS__SUCCESS: 1141 ret = 0; 1142 break; 1143 case TA_RAS_STATUS__RESET_NEEDED: 1144 ret = -EAGAIN; 1145 break; 1146 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1147 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1148 break; 1149 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1150 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1151 break; 1152 default: 1153 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1154 } 1155 1156 return ret; 1157 } 1158 1159 int psp_ras_enable_features(struct psp_context *psp, 1160 union ta_ras_cmd_input *info, bool enable) 1161 { 1162 struct ta_ras_shared_memory *ras_cmd; 1163 int ret; 1164 1165 if (!psp->ras.ras_initialized) 1166 return -EINVAL; 1167 1168 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1169 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1170 1171 if (enable) 1172 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1173 else 1174 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1175 1176 ras_cmd->ras_in_message = *info; 1177 1178 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1179 if (ret) 1180 return -EINVAL; 1181 1182 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1183 } 1184 1185 static int psp_ras_terminate(struct psp_context *psp) 1186 { 1187 int ret; 1188 1189 /* 1190 * TODO: bypass the terminate in sriov for now 1191 */ 1192 if (amdgpu_sriov_vf(psp->adev)) 1193 return 0; 1194 1195 if (!psp->ras.ras_initialized) 1196 return 0; 1197 1198 ret = psp_ras_unload(psp); 1199 if (ret) 1200 return ret; 1201 1202 psp->ras.ras_initialized = false; 1203 1204 /* free ras shared memory */ 1205 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1206 &psp->ras.ras_shared_mc_addr, 1207 &psp->ras.ras_shared_buf); 1208 1209 return 0; 1210 } 1211 1212 static int psp_ras_initialize(struct psp_context *psp) 1213 { 1214 int ret; 1215 1216 /* 1217 * TODO: bypass the initialize in sriov for now 1218 */ 1219 if (amdgpu_sriov_vf(psp->adev)) 1220 return 0; 1221 1222 if (!psp->adev->psp.ta_ras_ucode_size || 1223 !psp->adev->psp.ta_ras_start_addr) { 1224 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n"); 1225 return 0; 1226 } 1227 1228 if (!psp->ras.ras_initialized) { 1229 ret = psp_ras_init_shared_buf(psp); 1230 if (ret) 1231 return ret; 1232 } 1233 1234 ret = psp_ras_load(psp); 1235 if (ret) 1236 return ret; 1237 1238 return 0; 1239 } 1240 1241 int psp_ras_trigger_error(struct psp_context *psp, 1242 struct ta_ras_trigger_error_input *info) 1243 { 1244 struct ta_ras_shared_memory *ras_cmd; 1245 int ret; 1246 1247 if (!psp->ras.ras_initialized) 1248 return -EINVAL; 1249 1250 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1251 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1252 1253 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1254 ras_cmd->ras_in_message.trigger_error = *info; 1255 1256 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1257 if (ret) 1258 return -EINVAL; 1259 1260 /* If err_event_athub occurs error inject was successful, however 1261 return status from TA is no long reliable */ 1262 if (amdgpu_ras_intr_triggered()) 1263 return 0; 1264 1265 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1266 } 1267 // ras end 1268 1269 // HDCP start 1270 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1271 { 1272 int ret; 1273 1274 /* 1275 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1276 * physical) for hdcp ta <-> Driver 1277 */ 1278 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1279 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1280 &psp->hdcp_context.hdcp_shared_bo, 1281 &psp->hdcp_context.hdcp_shared_mc_addr, 1282 &psp->hdcp_context.hdcp_shared_buf); 1283 1284 return ret; 1285 } 1286 1287 static int psp_hdcp_load(struct psp_context *psp) 1288 { 1289 int ret; 1290 struct psp_gfx_cmd_resp *cmd; 1291 1292 /* 1293 * TODO: bypass the loading in sriov for now 1294 */ 1295 if (amdgpu_sriov_vf(psp->adev)) 1296 return 0; 1297 1298 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1299 if (!cmd) 1300 return -ENOMEM; 1301 1302 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1303 psp->ta_hdcp_ucode_size); 1304 1305 psp_prep_ta_load_cmd_buf(cmd, 1306 psp->fw_pri_mc_addr, 1307 psp->ta_hdcp_ucode_size, 1308 psp->hdcp_context.hdcp_shared_mc_addr, 1309 PSP_HDCP_SHARED_MEM_SIZE); 1310 1311 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1312 1313 if (!ret) { 1314 psp->hdcp_context.hdcp_initialized = true; 1315 psp->hdcp_context.session_id = cmd->resp.session_id; 1316 mutex_init(&psp->hdcp_context.mutex); 1317 } 1318 1319 kfree(cmd); 1320 1321 return ret; 1322 } 1323 static int psp_hdcp_initialize(struct psp_context *psp) 1324 { 1325 int ret; 1326 1327 /* 1328 * TODO: bypass the initialize in sriov for now 1329 */ 1330 if (amdgpu_sriov_vf(psp->adev)) 1331 return 0; 1332 1333 if (!psp->adev->psp.ta_hdcp_ucode_size || 1334 !psp->adev->psp.ta_hdcp_start_addr) { 1335 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1336 return 0; 1337 } 1338 1339 if (!psp->hdcp_context.hdcp_initialized) { 1340 ret = psp_hdcp_init_shared_buf(psp); 1341 if (ret) 1342 return ret; 1343 } 1344 1345 ret = psp_hdcp_load(psp); 1346 if (ret) 1347 return ret; 1348 1349 return 0; 1350 } 1351 1352 static int psp_hdcp_unload(struct psp_context *psp) 1353 { 1354 int ret; 1355 struct psp_gfx_cmd_resp *cmd; 1356 1357 /* 1358 * TODO: bypass the unloading in sriov for now 1359 */ 1360 if (amdgpu_sriov_vf(psp->adev)) 1361 return 0; 1362 1363 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1364 if (!cmd) 1365 return -ENOMEM; 1366 1367 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1368 1369 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1370 1371 kfree(cmd); 1372 1373 return ret; 1374 } 1375 1376 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1377 { 1378 /* 1379 * TODO: bypass the loading in sriov for now 1380 */ 1381 if (amdgpu_sriov_vf(psp->adev)) 1382 return 0; 1383 1384 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1385 } 1386 1387 static int psp_hdcp_terminate(struct psp_context *psp) 1388 { 1389 int ret; 1390 1391 /* 1392 * TODO: bypass the terminate in sriov for now 1393 */ 1394 if (amdgpu_sriov_vf(psp->adev)) 1395 return 0; 1396 1397 if (!psp->hdcp_context.hdcp_initialized) { 1398 if (psp->hdcp_context.hdcp_shared_buf) 1399 goto out; 1400 else 1401 return 0; 1402 } 1403 1404 ret = psp_hdcp_unload(psp); 1405 if (ret) 1406 return ret; 1407 1408 psp->hdcp_context.hdcp_initialized = false; 1409 1410 out: 1411 /* free hdcp shared memory */ 1412 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1413 &psp->hdcp_context.hdcp_shared_mc_addr, 1414 &psp->hdcp_context.hdcp_shared_buf); 1415 1416 return 0; 1417 } 1418 // HDCP end 1419 1420 // DTM start 1421 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1422 { 1423 int ret; 1424 1425 /* 1426 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1427 * physical) for dtm ta <-> Driver 1428 */ 1429 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1430 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1431 &psp->dtm_context.dtm_shared_bo, 1432 &psp->dtm_context.dtm_shared_mc_addr, 1433 &psp->dtm_context.dtm_shared_buf); 1434 1435 return ret; 1436 } 1437 1438 static int psp_dtm_load(struct psp_context *psp) 1439 { 1440 int ret; 1441 struct psp_gfx_cmd_resp *cmd; 1442 1443 /* 1444 * TODO: bypass the loading in sriov for now 1445 */ 1446 if (amdgpu_sriov_vf(psp->adev)) 1447 return 0; 1448 1449 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1450 if (!cmd) 1451 return -ENOMEM; 1452 1453 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1454 1455 psp_prep_ta_load_cmd_buf(cmd, 1456 psp->fw_pri_mc_addr, 1457 psp->ta_dtm_ucode_size, 1458 psp->dtm_context.dtm_shared_mc_addr, 1459 PSP_DTM_SHARED_MEM_SIZE); 1460 1461 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1462 1463 if (!ret) { 1464 psp->dtm_context.dtm_initialized = true; 1465 psp->dtm_context.session_id = cmd->resp.session_id; 1466 mutex_init(&psp->dtm_context.mutex); 1467 } 1468 1469 kfree(cmd); 1470 1471 return ret; 1472 } 1473 1474 static int psp_dtm_initialize(struct psp_context *psp) 1475 { 1476 int ret; 1477 1478 /* 1479 * TODO: bypass the initialize in sriov for now 1480 */ 1481 if (amdgpu_sriov_vf(psp->adev)) 1482 return 0; 1483 1484 if (!psp->adev->psp.ta_dtm_ucode_size || 1485 !psp->adev->psp.ta_dtm_start_addr) { 1486 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1487 return 0; 1488 } 1489 1490 if (!psp->dtm_context.dtm_initialized) { 1491 ret = psp_dtm_init_shared_buf(psp); 1492 if (ret) 1493 return ret; 1494 } 1495 1496 ret = psp_dtm_load(psp); 1497 if (ret) 1498 return ret; 1499 1500 return 0; 1501 } 1502 1503 static int psp_dtm_unload(struct psp_context *psp) 1504 { 1505 int ret; 1506 struct psp_gfx_cmd_resp *cmd; 1507 1508 /* 1509 * TODO: bypass the unloading in sriov for now 1510 */ 1511 if (amdgpu_sriov_vf(psp->adev)) 1512 return 0; 1513 1514 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1515 if (!cmd) 1516 return -ENOMEM; 1517 1518 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1519 1520 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1521 1522 kfree(cmd); 1523 1524 return ret; 1525 } 1526 1527 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1528 { 1529 /* 1530 * TODO: bypass the loading in sriov for now 1531 */ 1532 if (amdgpu_sriov_vf(psp->adev)) 1533 return 0; 1534 1535 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1536 } 1537 1538 static int psp_dtm_terminate(struct psp_context *psp) 1539 { 1540 int ret; 1541 1542 /* 1543 * TODO: bypass the terminate in sriov for now 1544 */ 1545 if (amdgpu_sriov_vf(psp->adev)) 1546 return 0; 1547 1548 if (!psp->dtm_context.dtm_initialized) { 1549 if (psp->dtm_context.dtm_shared_buf) 1550 goto out; 1551 else 1552 return 0; 1553 } 1554 1555 ret = psp_dtm_unload(psp); 1556 if (ret) 1557 return ret; 1558 1559 psp->dtm_context.dtm_initialized = false; 1560 1561 out: 1562 /* free hdcp shared memory */ 1563 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1564 &psp->dtm_context.dtm_shared_mc_addr, 1565 &psp->dtm_context.dtm_shared_buf); 1566 1567 return 0; 1568 } 1569 // DTM end 1570 1571 // RAP start 1572 static int psp_rap_init_shared_buf(struct psp_context *psp) 1573 { 1574 int ret; 1575 1576 /* 1577 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1578 * physical) for rap ta <-> Driver 1579 */ 1580 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1581 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1582 &psp->rap_context.rap_shared_bo, 1583 &psp->rap_context.rap_shared_mc_addr, 1584 &psp->rap_context.rap_shared_buf); 1585 1586 return ret; 1587 } 1588 1589 static int psp_rap_load(struct psp_context *psp) 1590 { 1591 int ret; 1592 struct psp_gfx_cmd_resp *cmd; 1593 1594 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1595 if (!cmd) 1596 return -ENOMEM; 1597 1598 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1599 1600 psp_prep_ta_load_cmd_buf(cmd, 1601 psp->fw_pri_mc_addr, 1602 psp->ta_rap_ucode_size, 1603 psp->rap_context.rap_shared_mc_addr, 1604 PSP_RAP_SHARED_MEM_SIZE); 1605 1606 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1607 1608 if (!ret) { 1609 psp->rap_context.rap_initialized = true; 1610 psp->rap_context.session_id = cmd->resp.session_id; 1611 mutex_init(&psp->rap_context.mutex); 1612 } 1613 1614 kfree(cmd); 1615 1616 return ret; 1617 } 1618 1619 static int psp_rap_unload(struct psp_context *psp) 1620 { 1621 int ret; 1622 struct psp_gfx_cmd_resp *cmd; 1623 1624 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1625 if (!cmd) 1626 return -ENOMEM; 1627 1628 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1629 1630 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1631 1632 kfree(cmd); 1633 1634 return ret; 1635 } 1636 1637 static int psp_rap_initialize(struct psp_context *psp) 1638 { 1639 int ret; 1640 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1641 1642 /* 1643 * TODO: bypass the initialize in sriov for now 1644 */ 1645 if (amdgpu_sriov_vf(psp->adev)) 1646 return 0; 1647 1648 if (!psp->adev->psp.ta_rap_ucode_size || 1649 !psp->adev->psp.ta_rap_start_addr) { 1650 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1651 return 0; 1652 } 1653 1654 if (!psp->rap_context.rap_initialized) { 1655 ret = psp_rap_init_shared_buf(psp); 1656 if (ret) 1657 return ret; 1658 } 1659 1660 ret = psp_rap_load(psp); 1661 if (ret) 1662 return ret; 1663 1664 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1665 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1666 psp_rap_unload(psp); 1667 1668 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1669 &psp->rap_context.rap_shared_mc_addr, 1670 &psp->rap_context.rap_shared_buf); 1671 1672 psp->rap_context.rap_initialized = false; 1673 1674 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1675 ret, status); 1676 1677 return ret; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static int psp_rap_terminate(struct psp_context *psp) 1684 { 1685 int ret; 1686 1687 if (!psp->rap_context.rap_initialized) 1688 return 0; 1689 1690 ret = psp_rap_unload(psp); 1691 1692 psp->rap_context.rap_initialized = false; 1693 1694 /* free rap shared memory */ 1695 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1696 &psp->rap_context.rap_shared_mc_addr, 1697 &psp->rap_context.rap_shared_buf); 1698 1699 return ret; 1700 } 1701 1702 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1703 { 1704 struct ta_rap_shared_memory *rap_cmd; 1705 int ret = 0; 1706 1707 if (!psp->rap_context.rap_initialized) 1708 return 0; 1709 1710 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1711 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1712 return -EINVAL; 1713 1714 mutex_lock(&psp->rap_context.mutex); 1715 1716 rap_cmd = (struct ta_rap_shared_memory *) 1717 psp->rap_context.rap_shared_buf; 1718 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1719 1720 rap_cmd->cmd_id = ta_cmd_id; 1721 rap_cmd->validation_method_id = METHOD_A; 1722 1723 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1724 if (ret) 1725 goto out_unlock; 1726 1727 if (status) 1728 *status = rap_cmd->rap_status; 1729 1730 out_unlock: 1731 mutex_unlock(&psp->rap_context.mutex); 1732 1733 return ret; 1734 } 1735 // RAP end 1736 1737 /* securedisplay start */ 1738 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1739 { 1740 int ret; 1741 1742 /* 1743 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1744 * physical) for sa ta <-> Driver 1745 */ 1746 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1747 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1748 &psp->securedisplay_context.securedisplay_shared_bo, 1749 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1750 &psp->securedisplay_context.securedisplay_shared_buf); 1751 1752 return ret; 1753 } 1754 1755 static int psp_securedisplay_load(struct psp_context *psp) 1756 { 1757 int ret; 1758 struct psp_gfx_cmd_resp *cmd; 1759 1760 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1761 if (!cmd) 1762 return -ENOMEM; 1763 1764 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1765 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1766 1767 psp_prep_ta_load_cmd_buf(cmd, 1768 psp->fw_pri_mc_addr, 1769 psp->ta_securedisplay_ucode_size, 1770 psp->securedisplay_context.securedisplay_shared_mc_addr, 1771 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1772 1773 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1774 1775 if (ret) 1776 goto failed; 1777 1778 psp->securedisplay_context.securedisplay_initialized = true; 1779 psp->securedisplay_context.session_id = cmd->resp.session_id; 1780 mutex_init(&psp->securedisplay_context.mutex); 1781 1782 failed: 1783 kfree(cmd); 1784 return ret; 1785 } 1786 1787 static int psp_securedisplay_unload(struct psp_context *psp) 1788 { 1789 int ret; 1790 struct psp_gfx_cmd_resp *cmd; 1791 1792 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1793 if (!cmd) 1794 return -ENOMEM; 1795 1796 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 1797 1798 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1799 1800 kfree(cmd); 1801 1802 return ret; 1803 } 1804 1805 static int psp_securedisplay_initialize(struct psp_context *psp) 1806 { 1807 int ret; 1808 struct securedisplay_cmd *securedisplay_cmd; 1809 1810 /* 1811 * TODO: bypass the initialize in sriov for now 1812 */ 1813 if (amdgpu_sriov_vf(psp->adev)) 1814 return 0; 1815 1816 if (!psp->adev->psp.ta_securedisplay_ucode_size || 1817 !psp->adev->psp.ta_securedisplay_start_addr) { 1818 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1819 return 0; 1820 } 1821 1822 if (!psp->securedisplay_context.securedisplay_initialized) { 1823 ret = psp_securedisplay_init_shared_buf(psp); 1824 if (ret) 1825 return ret; 1826 } 1827 1828 ret = psp_securedisplay_load(psp); 1829 if (ret) 1830 return ret; 1831 1832 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1833 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1834 1835 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1836 if (ret) { 1837 psp_securedisplay_unload(psp); 1838 1839 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1840 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1841 &psp->securedisplay_context.securedisplay_shared_buf); 1842 1843 psp->securedisplay_context.securedisplay_initialized = false; 1844 1845 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1846 return -EINVAL; 1847 } 1848 1849 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1850 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1851 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1852 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1853 } 1854 1855 return 0; 1856 } 1857 1858 static int psp_securedisplay_terminate(struct psp_context *psp) 1859 { 1860 int ret; 1861 1862 /* 1863 * TODO:bypass the terminate in sriov for now 1864 */ 1865 if (amdgpu_sriov_vf(psp->adev)) 1866 return 0; 1867 1868 if (!psp->securedisplay_context.securedisplay_initialized) 1869 return 0; 1870 1871 ret = psp_securedisplay_unload(psp); 1872 if (ret) 1873 return ret; 1874 1875 psp->securedisplay_context.securedisplay_initialized = false; 1876 1877 /* free securedisplay shared memory */ 1878 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 1879 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1880 &psp->securedisplay_context.securedisplay_shared_buf); 1881 1882 return ret; 1883 } 1884 1885 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1886 { 1887 int ret; 1888 1889 if (!psp->securedisplay_context.securedisplay_initialized) 1890 return -EINVAL; 1891 1892 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1893 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1894 return -EINVAL; 1895 1896 mutex_lock(&psp->securedisplay_context.mutex); 1897 1898 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 1899 1900 mutex_unlock(&psp->securedisplay_context.mutex); 1901 1902 return ret; 1903 } 1904 /* SECUREDISPLAY end */ 1905 1906 static int psp_hw_start(struct psp_context *psp) 1907 { 1908 struct amdgpu_device *adev = psp->adev; 1909 int ret; 1910 1911 if (!amdgpu_sriov_vf(adev)) { 1912 if (psp->kdb_bin_size && 1913 (psp->funcs->bootloader_load_kdb != NULL)) { 1914 ret = psp_bootloader_load_kdb(psp); 1915 if (ret) { 1916 DRM_ERROR("PSP load kdb failed!\n"); 1917 return ret; 1918 } 1919 } 1920 1921 if (psp->spl_bin_size) { 1922 ret = psp_bootloader_load_spl(psp); 1923 if (ret) { 1924 DRM_ERROR("PSP load spl failed!\n"); 1925 return ret; 1926 } 1927 } 1928 1929 ret = psp_bootloader_load_sysdrv(psp); 1930 if (ret) { 1931 DRM_ERROR("PSP load sysdrv failed!\n"); 1932 return ret; 1933 } 1934 1935 ret = psp_bootloader_load_sos(psp); 1936 if (ret) { 1937 DRM_ERROR("PSP load sos failed!\n"); 1938 return ret; 1939 } 1940 } 1941 1942 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1943 if (ret) { 1944 DRM_ERROR("PSP create ring failed!\n"); 1945 return ret; 1946 } 1947 1948 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1949 ret = psp_boot_config_set(adev); 1950 if (ret) 1951 dev_warn(adev->dev, "PSP set boot config failed\n"); 1952 } 1953 1954 ret = psp_tmr_init(psp); 1955 if (ret) { 1956 DRM_ERROR("PSP tmr init failed!\n"); 1957 return ret; 1958 } 1959 1960 /* 1961 * For ASICs with DF Cstate management centralized 1962 * to PMFW, TMR setup should be performed after PMFW 1963 * loaded and before other non-psp firmware loaded. 1964 */ 1965 if (psp->pmfw_centralized_cstate_management) { 1966 ret = psp_load_smu_fw(psp); 1967 if (ret) 1968 return ret; 1969 } 1970 1971 ret = psp_tmr_load(psp); 1972 if (ret) { 1973 DRM_ERROR("PSP load tmr failed!\n"); 1974 return ret; 1975 } 1976 1977 return 0; 1978 } 1979 1980 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1981 enum psp_gfx_fw_type *type) 1982 { 1983 switch (ucode->ucode_id) { 1984 case AMDGPU_UCODE_ID_SDMA0: 1985 *type = GFX_FW_TYPE_SDMA0; 1986 break; 1987 case AMDGPU_UCODE_ID_SDMA1: 1988 *type = GFX_FW_TYPE_SDMA1; 1989 break; 1990 case AMDGPU_UCODE_ID_SDMA2: 1991 *type = GFX_FW_TYPE_SDMA2; 1992 break; 1993 case AMDGPU_UCODE_ID_SDMA3: 1994 *type = GFX_FW_TYPE_SDMA3; 1995 break; 1996 case AMDGPU_UCODE_ID_SDMA4: 1997 *type = GFX_FW_TYPE_SDMA4; 1998 break; 1999 case AMDGPU_UCODE_ID_SDMA5: 2000 *type = GFX_FW_TYPE_SDMA5; 2001 break; 2002 case AMDGPU_UCODE_ID_SDMA6: 2003 *type = GFX_FW_TYPE_SDMA6; 2004 break; 2005 case AMDGPU_UCODE_ID_SDMA7: 2006 *type = GFX_FW_TYPE_SDMA7; 2007 break; 2008 case AMDGPU_UCODE_ID_CP_MES: 2009 *type = GFX_FW_TYPE_CP_MES; 2010 break; 2011 case AMDGPU_UCODE_ID_CP_MES_DATA: 2012 *type = GFX_FW_TYPE_MES_STACK; 2013 break; 2014 case AMDGPU_UCODE_ID_CP_CE: 2015 *type = GFX_FW_TYPE_CP_CE; 2016 break; 2017 case AMDGPU_UCODE_ID_CP_PFP: 2018 *type = GFX_FW_TYPE_CP_PFP; 2019 break; 2020 case AMDGPU_UCODE_ID_CP_ME: 2021 *type = GFX_FW_TYPE_CP_ME; 2022 break; 2023 case AMDGPU_UCODE_ID_CP_MEC1: 2024 *type = GFX_FW_TYPE_CP_MEC; 2025 break; 2026 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2027 *type = GFX_FW_TYPE_CP_MEC_ME1; 2028 break; 2029 case AMDGPU_UCODE_ID_CP_MEC2: 2030 *type = GFX_FW_TYPE_CP_MEC; 2031 break; 2032 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2033 *type = GFX_FW_TYPE_CP_MEC_ME2; 2034 break; 2035 case AMDGPU_UCODE_ID_RLC_G: 2036 *type = GFX_FW_TYPE_RLC_G; 2037 break; 2038 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2039 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2040 break; 2041 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2042 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2043 break; 2044 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2045 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2046 break; 2047 case AMDGPU_UCODE_ID_RLC_IRAM: 2048 *type = GFX_FW_TYPE_RLC_IRAM; 2049 break; 2050 case AMDGPU_UCODE_ID_RLC_DRAM: 2051 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2052 break; 2053 case AMDGPU_UCODE_ID_SMC: 2054 *type = GFX_FW_TYPE_SMU; 2055 break; 2056 case AMDGPU_UCODE_ID_UVD: 2057 *type = GFX_FW_TYPE_UVD; 2058 break; 2059 case AMDGPU_UCODE_ID_UVD1: 2060 *type = GFX_FW_TYPE_UVD1; 2061 break; 2062 case AMDGPU_UCODE_ID_VCE: 2063 *type = GFX_FW_TYPE_VCE; 2064 break; 2065 case AMDGPU_UCODE_ID_VCN: 2066 *type = GFX_FW_TYPE_VCN; 2067 break; 2068 case AMDGPU_UCODE_ID_VCN1: 2069 *type = GFX_FW_TYPE_VCN1; 2070 break; 2071 case AMDGPU_UCODE_ID_DMCU_ERAM: 2072 *type = GFX_FW_TYPE_DMCU_ERAM; 2073 break; 2074 case AMDGPU_UCODE_ID_DMCU_INTV: 2075 *type = GFX_FW_TYPE_DMCU_ISR; 2076 break; 2077 case AMDGPU_UCODE_ID_VCN0_RAM: 2078 *type = GFX_FW_TYPE_VCN0_RAM; 2079 break; 2080 case AMDGPU_UCODE_ID_VCN1_RAM: 2081 *type = GFX_FW_TYPE_VCN1_RAM; 2082 break; 2083 case AMDGPU_UCODE_ID_DMCUB: 2084 *type = GFX_FW_TYPE_DMUB; 2085 break; 2086 case AMDGPU_UCODE_ID_MAXIMUM: 2087 default: 2088 return -EINVAL; 2089 } 2090 2091 return 0; 2092 } 2093 2094 static void psp_print_fw_hdr(struct psp_context *psp, 2095 struct amdgpu_firmware_info *ucode) 2096 { 2097 struct amdgpu_device *adev = psp->adev; 2098 struct common_firmware_header *hdr; 2099 2100 switch (ucode->ucode_id) { 2101 case AMDGPU_UCODE_ID_SDMA0: 2102 case AMDGPU_UCODE_ID_SDMA1: 2103 case AMDGPU_UCODE_ID_SDMA2: 2104 case AMDGPU_UCODE_ID_SDMA3: 2105 case AMDGPU_UCODE_ID_SDMA4: 2106 case AMDGPU_UCODE_ID_SDMA5: 2107 case AMDGPU_UCODE_ID_SDMA6: 2108 case AMDGPU_UCODE_ID_SDMA7: 2109 hdr = (struct common_firmware_header *) 2110 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2111 amdgpu_ucode_print_sdma_hdr(hdr); 2112 break; 2113 case AMDGPU_UCODE_ID_CP_CE: 2114 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2115 amdgpu_ucode_print_gfx_hdr(hdr); 2116 break; 2117 case AMDGPU_UCODE_ID_CP_PFP: 2118 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2119 amdgpu_ucode_print_gfx_hdr(hdr); 2120 break; 2121 case AMDGPU_UCODE_ID_CP_ME: 2122 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2123 amdgpu_ucode_print_gfx_hdr(hdr); 2124 break; 2125 case AMDGPU_UCODE_ID_CP_MEC1: 2126 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2127 amdgpu_ucode_print_gfx_hdr(hdr); 2128 break; 2129 case AMDGPU_UCODE_ID_RLC_G: 2130 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2131 amdgpu_ucode_print_rlc_hdr(hdr); 2132 break; 2133 case AMDGPU_UCODE_ID_SMC: 2134 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2135 amdgpu_ucode_print_smc_hdr(hdr); 2136 break; 2137 default: 2138 break; 2139 } 2140 } 2141 2142 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2143 struct psp_gfx_cmd_resp *cmd) 2144 { 2145 int ret; 2146 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2147 2148 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2149 2150 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2151 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2152 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2153 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2154 2155 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2156 if (ret) 2157 DRM_ERROR("Unknown firmware type\n"); 2158 2159 return ret; 2160 } 2161 2162 static int psp_execute_np_fw_load(struct psp_context *psp, 2163 struct amdgpu_firmware_info *ucode) 2164 { 2165 int ret = 0; 2166 2167 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2168 if (ret) 2169 return ret; 2170 2171 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2172 psp->fence_buf_mc_addr); 2173 2174 return ret; 2175 } 2176 2177 static int psp_load_smu_fw(struct psp_context *psp) 2178 { 2179 int ret; 2180 struct amdgpu_device *adev = psp->adev; 2181 struct amdgpu_firmware_info *ucode = 2182 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2183 struct amdgpu_ras *ras = psp->ras.ras; 2184 2185 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2186 return 0; 2187 2188 if ((amdgpu_in_reset(adev) && 2189 ras && adev->ras_enabled && 2190 (adev->asic_type == CHIP_ARCTURUS || 2191 adev->asic_type == CHIP_VEGA20)) || 2192 (adev->in_runpm && 2193 adev->asic_type >= CHIP_NAVI10 && 2194 adev->asic_type <= CHIP_NAVI12)) { 2195 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2196 if (ret) { 2197 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2198 } 2199 } 2200 2201 ret = psp_execute_np_fw_load(psp, ucode); 2202 2203 if (ret) 2204 DRM_ERROR("PSP load smu failed!\n"); 2205 2206 return ret; 2207 } 2208 2209 static bool fw_load_skip_check(struct psp_context *psp, 2210 struct amdgpu_firmware_info *ucode) 2211 { 2212 if (!ucode->fw) 2213 return true; 2214 2215 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2216 (psp_smu_reload_quirk(psp) || 2217 psp->autoload_supported || 2218 psp->pmfw_centralized_cstate_management)) 2219 return true; 2220 2221 if (amdgpu_sriov_vf(psp->adev) && 2222 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2223 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2224 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2225 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2226 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2227 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2228 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2229 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2230 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2231 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2232 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2233 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2234 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2235 /*skip ucode loading in SRIOV VF */ 2236 return true; 2237 2238 if (psp->autoload_supported && 2239 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2240 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2241 /* skip mec JT when autoload is enabled */ 2242 return true; 2243 2244 return false; 2245 } 2246 2247 int psp_load_fw_list(struct psp_context *psp, 2248 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2249 { 2250 int ret = 0, i; 2251 struct amdgpu_firmware_info *ucode; 2252 2253 for (i = 0; i < ucode_count; ++i) { 2254 ucode = ucode_list[i]; 2255 psp_print_fw_hdr(psp, ucode); 2256 ret = psp_execute_np_fw_load(psp, ucode); 2257 if (ret) 2258 return ret; 2259 } 2260 return ret; 2261 } 2262 2263 static int psp_np_fw_load(struct psp_context *psp) 2264 { 2265 int i, ret; 2266 struct amdgpu_firmware_info *ucode; 2267 struct amdgpu_device *adev = psp->adev; 2268 2269 if (psp->autoload_supported && 2270 !psp->pmfw_centralized_cstate_management) { 2271 ret = psp_load_smu_fw(psp); 2272 if (ret) 2273 return ret; 2274 } 2275 2276 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2277 ucode = &adev->firmware.ucode[i]; 2278 2279 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2280 !fw_load_skip_check(psp, ucode)) { 2281 ret = psp_load_smu_fw(psp); 2282 if (ret) 2283 return ret; 2284 continue; 2285 } 2286 2287 if (fw_load_skip_check(psp, ucode)) 2288 continue; 2289 2290 if (psp->autoload_supported && 2291 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2292 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2293 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2294 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2295 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2296 /* PSP only receive one SDMA fw for sienna_cichlid, 2297 * as all four sdma fw are same */ 2298 continue; 2299 2300 psp_print_fw_hdr(psp, ucode); 2301 2302 ret = psp_execute_np_fw_load(psp, ucode); 2303 if (ret) 2304 return ret; 2305 2306 /* Start rlc autoload after psp recieved all the gfx firmware */ 2307 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2308 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2309 ret = psp_rlc_autoload_start(psp); 2310 if (ret) { 2311 DRM_ERROR("Failed to start rlc autoload\n"); 2312 return ret; 2313 } 2314 } 2315 } 2316 2317 return 0; 2318 } 2319 2320 static int psp_load_fw(struct amdgpu_device *adev) 2321 { 2322 int ret; 2323 struct psp_context *psp = &adev->psp; 2324 2325 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2326 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2327 goto skip_memalloc; 2328 } 2329 2330 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2331 if (!psp->cmd) 2332 return -ENOMEM; 2333 2334 if (amdgpu_sriov_vf(adev)) { 2335 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2336 AMDGPU_GEM_DOMAIN_VRAM, 2337 &psp->fw_pri_bo, 2338 &psp->fw_pri_mc_addr, 2339 &psp->fw_pri_buf); 2340 } else { 2341 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2342 AMDGPU_GEM_DOMAIN_GTT, 2343 &psp->fw_pri_bo, 2344 &psp->fw_pri_mc_addr, 2345 &psp->fw_pri_buf); 2346 } 2347 2348 if (ret) 2349 goto failed; 2350 2351 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2352 AMDGPU_GEM_DOMAIN_VRAM, 2353 &psp->fence_buf_bo, 2354 &psp->fence_buf_mc_addr, 2355 &psp->fence_buf); 2356 if (ret) 2357 goto failed; 2358 2359 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2360 AMDGPU_GEM_DOMAIN_VRAM, 2361 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2362 (void **)&psp->cmd_buf_mem); 2363 if (ret) 2364 goto failed; 2365 2366 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2367 2368 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2369 if (ret) { 2370 DRM_ERROR("PSP ring init failed!\n"); 2371 goto failed; 2372 } 2373 2374 skip_memalloc: 2375 ret = psp_hw_start(psp); 2376 if (ret) 2377 goto failed; 2378 2379 ret = psp_np_fw_load(psp); 2380 if (ret) 2381 goto failed; 2382 2383 ret = psp_asd_load(psp); 2384 if (ret) { 2385 DRM_ERROR("PSP load asd failed!\n"); 2386 return ret; 2387 } 2388 2389 ret = psp_rl_load(adev); 2390 if (ret) { 2391 DRM_ERROR("PSP load RL failed!\n"); 2392 return ret; 2393 } 2394 2395 if (psp->adev->psp.ta_fw) { 2396 ret = psp_ras_initialize(psp); 2397 if (ret) 2398 dev_err(psp->adev->dev, 2399 "RAS: Failed to initialize RAS\n"); 2400 2401 ret = psp_hdcp_initialize(psp); 2402 if (ret) 2403 dev_err(psp->adev->dev, 2404 "HDCP: Failed to initialize HDCP\n"); 2405 2406 ret = psp_dtm_initialize(psp); 2407 if (ret) 2408 dev_err(psp->adev->dev, 2409 "DTM: Failed to initialize DTM\n"); 2410 2411 ret = psp_rap_initialize(psp); 2412 if (ret) 2413 dev_err(psp->adev->dev, 2414 "RAP: Failed to initialize RAP\n"); 2415 2416 ret = psp_securedisplay_initialize(psp); 2417 if (ret) 2418 dev_err(psp->adev->dev, 2419 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2420 } 2421 2422 return 0; 2423 2424 failed: 2425 /* 2426 * all cleanup jobs (xgmi terminate, ras terminate, 2427 * ring destroy, cmd/fence/fw buffers destory, 2428 * psp->cmd destory) are delayed to psp_hw_fini 2429 */ 2430 return ret; 2431 } 2432 2433 static int psp_hw_init(void *handle) 2434 { 2435 int ret; 2436 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2437 2438 mutex_lock(&adev->firmware.mutex); 2439 /* 2440 * This sequence is just used on hw_init only once, no need on 2441 * resume. 2442 */ 2443 ret = amdgpu_ucode_init_bo(adev); 2444 if (ret) 2445 goto failed; 2446 2447 ret = psp_load_fw(adev); 2448 if (ret) { 2449 DRM_ERROR("PSP firmware loading failed\n"); 2450 goto failed; 2451 } 2452 2453 mutex_unlock(&adev->firmware.mutex); 2454 return 0; 2455 2456 failed: 2457 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2458 mutex_unlock(&adev->firmware.mutex); 2459 return -EINVAL; 2460 } 2461 2462 static int psp_hw_fini(void *handle) 2463 { 2464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2465 struct psp_context *psp = &adev->psp; 2466 2467 if (psp->adev->psp.ta_fw) { 2468 psp_ras_terminate(psp); 2469 psp_securedisplay_terminate(psp); 2470 psp_rap_terminate(psp); 2471 psp_dtm_terminate(psp); 2472 psp_hdcp_terminate(psp); 2473 } 2474 2475 psp_asd_unload(psp); 2476 2477 psp_tmr_terminate(psp); 2478 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2479 2480 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2481 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2482 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2483 &psp->fence_buf_mc_addr, &psp->fence_buf); 2484 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2485 (void **)&psp->cmd_buf_mem); 2486 2487 kfree(psp->cmd); 2488 psp->cmd = NULL; 2489 2490 return 0; 2491 } 2492 2493 static int psp_suspend(void *handle) 2494 { 2495 int ret; 2496 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2497 struct psp_context *psp = &adev->psp; 2498 2499 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2500 psp->xgmi_context.initialized == 1) { 2501 ret = psp_xgmi_terminate(psp); 2502 if (ret) { 2503 DRM_ERROR("Failed to terminate xgmi ta\n"); 2504 return ret; 2505 } 2506 } 2507 2508 if (psp->adev->psp.ta_fw) { 2509 ret = psp_ras_terminate(psp); 2510 if (ret) { 2511 DRM_ERROR("Failed to terminate ras ta\n"); 2512 return ret; 2513 } 2514 ret = psp_hdcp_terminate(psp); 2515 if (ret) { 2516 DRM_ERROR("Failed to terminate hdcp ta\n"); 2517 return ret; 2518 } 2519 ret = psp_dtm_terminate(psp); 2520 if (ret) { 2521 DRM_ERROR("Failed to terminate dtm ta\n"); 2522 return ret; 2523 } 2524 ret = psp_rap_terminate(psp); 2525 if (ret) { 2526 DRM_ERROR("Failed to terminate rap ta\n"); 2527 return ret; 2528 } 2529 ret = psp_securedisplay_terminate(psp); 2530 if (ret) { 2531 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2532 return ret; 2533 } 2534 } 2535 2536 ret = psp_asd_unload(psp); 2537 if (ret) { 2538 DRM_ERROR("Failed to unload asd\n"); 2539 return ret; 2540 } 2541 2542 ret = psp_tmr_terminate(psp); 2543 if (ret) { 2544 DRM_ERROR("Failed to terminate tmr\n"); 2545 return ret; 2546 } 2547 2548 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2549 if (ret) { 2550 DRM_ERROR("PSP ring stop failed\n"); 2551 return ret; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int psp_resume(void *handle) 2558 { 2559 int ret; 2560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2561 struct psp_context *psp = &adev->psp; 2562 2563 DRM_INFO("PSP is resuming...\n"); 2564 2565 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2566 if (ret) { 2567 DRM_ERROR("Failed to process memory training!\n"); 2568 return ret; 2569 } 2570 2571 mutex_lock(&adev->firmware.mutex); 2572 2573 ret = psp_hw_start(psp); 2574 if (ret) 2575 goto failed; 2576 2577 ret = psp_np_fw_load(psp); 2578 if (ret) 2579 goto failed; 2580 2581 ret = psp_asd_load(psp); 2582 if (ret) { 2583 DRM_ERROR("PSP load asd failed!\n"); 2584 goto failed; 2585 } 2586 2587 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2588 ret = psp_xgmi_initialize(psp); 2589 /* Warning the XGMI seesion initialize failure 2590 * Instead of stop driver initialization 2591 */ 2592 if (ret) 2593 dev_err(psp->adev->dev, 2594 "XGMI: Failed to initialize XGMI session\n"); 2595 } 2596 2597 if (psp->adev->psp.ta_fw) { 2598 ret = psp_ras_initialize(psp); 2599 if (ret) 2600 dev_err(psp->adev->dev, 2601 "RAS: Failed to initialize RAS\n"); 2602 2603 ret = psp_hdcp_initialize(psp); 2604 if (ret) 2605 dev_err(psp->adev->dev, 2606 "HDCP: Failed to initialize HDCP\n"); 2607 2608 ret = psp_dtm_initialize(psp); 2609 if (ret) 2610 dev_err(psp->adev->dev, 2611 "DTM: Failed to initialize DTM\n"); 2612 2613 ret = psp_rap_initialize(psp); 2614 if (ret) 2615 dev_err(psp->adev->dev, 2616 "RAP: Failed to initialize RAP\n"); 2617 2618 ret = psp_securedisplay_initialize(psp); 2619 if (ret) 2620 dev_err(psp->adev->dev, 2621 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2622 } 2623 2624 mutex_unlock(&adev->firmware.mutex); 2625 2626 return 0; 2627 2628 failed: 2629 DRM_ERROR("PSP resume failed\n"); 2630 mutex_unlock(&adev->firmware.mutex); 2631 return ret; 2632 } 2633 2634 int psp_gpu_reset(struct amdgpu_device *adev) 2635 { 2636 int ret; 2637 2638 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2639 return 0; 2640 2641 mutex_lock(&adev->psp.mutex); 2642 ret = psp_mode1_reset(&adev->psp); 2643 mutex_unlock(&adev->psp.mutex); 2644 2645 return ret; 2646 } 2647 2648 int psp_rlc_autoload_start(struct psp_context *psp) 2649 { 2650 int ret; 2651 struct psp_gfx_cmd_resp *cmd; 2652 2653 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2654 if (!cmd) 2655 return -ENOMEM; 2656 2657 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2658 2659 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2660 psp->fence_buf_mc_addr); 2661 kfree(cmd); 2662 return ret; 2663 } 2664 2665 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2666 uint64_t cmd_gpu_addr, int cmd_size) 2667 { 2668 struct amdgpu_firmware_info ucode = {0}; 2669 2670 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2671 AMDGPU_UCODE_ID_VCN0_RAM; 2672 ucode.mc_addr = cmd_gpu_addr; 2673 ucode.ucode_size = cmd_size; 2674 2675 return psp_execute_np_fw_load(&adev->psp, &ucode); 2676 } 2677 2678 int psp_ring_cmd_submit(struct psp_context *psp, 2679 uint64_t cmd_buf_mc_addr, 2680 uint64_t fence_mc_addr, 2681 int index) 2682 { 2683 unsigned int psp_write_ptr_reg = 0; 2684 struct psp_gfx_rb_frame *write_frame; 2685 struct psp_ring *ring = &psp->km_ring; 2686 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2687 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2688 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2689 struct amdgpu_device *adev = psp->adev; 2690 uint32_t ring_size_dw = ring->ring_size / 4; 2691 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2692 2693 /* KM (GPCOM) prepare write pointer */ 2694 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2695 2696 /* Update KM RB frame pointer to new frame */ 2697 /* write_frame ptr increments by size of rb_frame in bytes */ 2698 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2699 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2700 write_frame = ring_buffer_start; 2701 else 2702 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2703 /* Check invalid write_frame ptr address */ 2704 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2705 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2706 ring_buffer_start, ring_buffer_end, write_frame); 2707 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2708 return -EINVAL; 2709 } 2710 2711 /* Initialize KM RB frame */ 2712 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2713 2714 /* Update KM RB frame */ 2715 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2716 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2717 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2718 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2719 write_frame->fence_value = index; 2720 amdgpu_device_flush_hdp(adev, NULL); 2721 2722 /* Update the write Pointer in DWORDs */ 2723 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2724 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2725 return 0; 2726 } 2727 2728 int psp_init_asd_microcode(struct psp_context *psp, 2729 const char *chip_name) 2730 { 2731 struct amdgpu_device *adev = psp->adev; 2732 char fw_name[PSP_FW_NAME_LEN]; 2733 const struct psp_firmware_header_v1_0 *asd_hdr; 2734 int err = 0; 2735 2736 if (!chip_name) { 2737 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2738 return -EINVAL; 2739 } 2740 2741 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2742 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2743 if (err) 2744 goto out; 2745 2746 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2747 if (err) 2748 goto out; 2749 2750 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2751 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2752 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 2753 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2754 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2755 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2756 return 0; 2757 out: 2758 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2759 release_firmware(adev->psp.asd_fw); 2760 adev->psp.asd_fw = NULL; 2761 return err; 2762 } 2763 2764 int psp_init_toc_microcode(struct psp_context *psp, 2765 const char *chip_name) 2766 { 2767 struct amdgpu_device *adev = psp->adev; 2768 char fw_name[30]; 2769 const struct psp_firmware_header_v1_0 *toc_hdr; 2770 int err = 0; 2771 2772 if (!chip_name) { 2773 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2774 return -EINVAL; 2775 } 2776 2777 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2778 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2779 if (err) 2780 goto out; 2781 2782 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2783 if (err) 2784 goto out; 2785 2786 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2787 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2788 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version); 2789 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2790 adev->psp.toc_start_addr = (uint8_t *)toc_hdr + 2791 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2792 return 0; 2793 out: 2794 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2795 release_firmware(adev->psp.toc_fw); 2796 adev->psp.toc_fw = NULL; 2797 return err; 2798 } 2799 2800 int psp_init_sos_microcode(struct psp_context *psp, 2801 const char *chip_name) 2802 { 2803 struct amdgpu_device *adev = psp->adev; 2804 char fw_name[PSP_FW_NAME_LEN]; 2805 const struct psp_firmware_header_v1_0 *sos_hdr; 2806 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 2807 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 2808 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2809 int err = 0; 2810 2811 if (!chip_name) { 2812 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 2813 return -EINVAL; 2814 } 2815 2816 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 2817 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 2818 if (err) 2819 goto out; 2820 2821 err = amdgpu_ucode_validate(adev->psp.sos_fw); 2822 if (err) 2823 goto out; 2824 2825 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2826 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 2827 2828 switch (sos_hdr->header.header_version_major) { 2829 case 1: 2830 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 2831 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 2832 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 2833 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 2834 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 2835 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2836 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2837 le32_to_cpu(sos_hdr->sos_offset_bytes); 2838 if (sos_hdr->header.header_version_minor == 1) { 2839 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 2840 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 2841 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2842 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 2843 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 2844 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2845 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 2846 } 2847 if (sos_hdr->header.header_version_minor == 2) { 2848 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 2849 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 2850 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2851 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 2852 } 2853 if (sos_hdr->header.header_version_minor == 3) { 2854 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 2855 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes); 2856 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2857 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes); 2858 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes); 2859 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2860 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes); 2861 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes); 2862 adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2863 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes); 2864 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes); 2865 adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr + 2866 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes); 2867 } 2868 break; 2869 default: 2870 dev_err(adev->dev, 2871 "unsupported psp sos firmware\n"); 2872 err = -EINVAL; 2873 goto out; 2874 } 2875 2876 return 0; 2877 out: 2878 dev_err(adev->dev, 2879 "failed to init sos firmware\n"); 2880 release_firmware(adev->psp.sos_fw); 2881 adev->psp.sos_fw = NULL; 2882 2883 return err; 2884 } 2885 2886 static int parse_ta_bin_descriptor(struct psp_context *psp, 2887 const struct ta_fw_bin_desc *desc, 2888 const struct ta_firmware_header_v2_0 *ta_hdr) 2889 { 2890 uint8_t *ucode_start_addr = NULL; 2891 2892 if (!psp || !desc || !ta_hdr) 2893 return -EINVAL; 2894 2895 ucode_start_addr = (uint8_t *)ta_hdr + 2896 le32_to_cpu(desc->offset_bytes) + 2897 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 2898 2899 switch (desc->fw_type) { 2900 case TA_FW_TYPE_PSP_ASD: 2901 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 2902 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 2903 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 2904 psp->asd_start_addr = ucode_start_addr; 2905 break; 2906 case TA_FW_TYPE_PSP_XGMI: 2907 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 2908 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 2909 psp->ta_xgmi_start_addr = ucode_start_addr; 2910 break; 2911 case TA_FW_TYPE_PSP_RAS: 2912 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 2913 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 2914 psp->ta_ras_start_addr = ucode_start_addr; 2915 break; 2916 case TA_FW_TYPE_PSP_HDCP: 2917 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 2918 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 2919 psp->ta_hdcp_start_addr = ucode_start_addr; 2920 break; 2921 case TA_FW_TYPE_PSP_DTM: 2922 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 2923 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 2924 psp->ta_dtm_start_addr = ucode_start_addr; 2925 break; 2926 case TA_FW_TYPE_PSP_RAP: 2927 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 2928 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 2929 psp->ta_rap_start_addr = ucode_start_addr; 2930 break; 2931 case TA_FW_TYPE_PSP_SECUREDISPLAY: 2932 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 2933 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 2934 psp->ta_securedisplay_start_addr = ucode_start_addr; 2935 break; 2936 default: 2937 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 2938 break; 2939 } 2940 2941 return 0; 2942 } 2943 2944 int psp_init_ta_microcode(struct psp_context *psp, 2945 const char *chip_name) 2946 { 2947 struct amdgpu_device *adev = psp->adev; 2948 char fw_name[PSP_FW_NAME_LEN]; 2949 const struct ta_firmware_header_v2_0 *ta_hdr; 2950 int err = 0; 2951 int ta_index = 0; 2952 2953 if (!chip_name) { 2954 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 2955 return -EINVAL; 2956 } 2957 2958 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 2959 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 2960 if (err) 2961 goto out; 2962 2963 err = amdgpu_ucode_validate(adev->psp.ta_fw); 2964 if (err) 2965 goto out; 2966 2967 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 2968 2969 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 2970 dev_err(adev->dev, "unsupported TA header version\n"); 2971 err = -EINVAL; 2972 goto out; 2973 } 2974 2975 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 2976 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 2977 err = -EINVAL; 2978 goto out; 2979 } 2980 2981 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 2982 err = parse_ta_bin_descriptor(psp, 2983 &ta_hdr->ta_fw_bin[ta_index], 2984 ta_hdr); 2985 if (err) 2986 goto out; 2987 } 2988 2989 return 0; 2990 out: 2991 dev_err(adev->dev, "fail to initialize ta microcode\n"); 2992 release_firmware(adev->psp.ta_fw); 2993 adev->psp.ta_fw = NULL; 2994 return err; 2995 } 2996 2997 static int psp_set_clockgating_state(void *handle, 2998 enum amd_clockgating_state state) 2999 { 3000 return 0; 3001 } 3002 3003 static int psp_set_powergating_state(void *handle, 3004 enum amd_powergating_state state) 3005 { 3006 return 0; 3007 } 3008 3009 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3010 struct device_attribute *attr, 3011 char *buf) 3012 { 3013 struct drm_device *ddev = dev_get_drvdata(dev); 3014 struct amdgpu_device *adev = drm_to_adev(ddev); 3015 uint32_t fw_ver; 3016 int ret; 3017 3018 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3019 DRM_INFO("PSP block is not ready yet."); 3020 return -EBUSY; 3021 } 3022 3023 mutex_lock(&adev->psp.mutex); 3024 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3025 mutex_unlock(&adev->psp.mutex); 3026 3027 if (ret) { 3028 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3029 return ret; 3030 } 3031 3032 return sysfs_emit(buf, "%x\n", fw_ver); 3033 } 3034 3035 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3036 struct device_attribute *attr, 3037 const char *buf, 3038 size_t count) 3039 { 3040 struct drm_device *ddev = dev_get_drvdata(dev); 3041 struct amdgpu_device *adev = drm_to_adev(ddev); 3042 void *cpu_addr; 3043 dma_addr_t dma_addr; 3044 int ret, idx; 3045 char fw_name[100]; 3046 const struct firmware *usbc_pd_fw; 3047 3048 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3049 DRM_INFO("PSP block is not ready yet."); 3050 return -EBUSY; 3051 } 3052 3053 if (!drm_dev_enter(ddev, &idx)) 3054 return -ENODEV; 3055 3056 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3057 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3058 if (ret) 3059 goto fail; 3060 3061 /* We need contiguous physical mem to place the FW for psp to access */ 3062 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL); 3063 3064 ret = dma_mapping_error(adev->dev, dma_addr); 3065 if (ret) 3066 goto rel_buf; 3067 3068 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3069 3070 /* 3071 * x86 specific workaround. 3072 * Without it the buffer is invisible in PSP. 3073 * 3074 * TODO Remove once PSP starts snooping CPU cache 3075 */ 3076 #ifdef CONFIG_X86 3077 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1))); 3078 #endif 3079 3080 mutex_lock(&adev->psp.mutex); 3081 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr); 3082 mutex_unlock(&adev->psp.mutex); 3083 3084 rel_buf: 3085 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr); 3086 release_firmware(usbc_pd_fw); 3087 fail: 3088 if (ret) { 3089 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3090 count = ret; 3091 } 3092 3093 drm_dev_exit(idx); 3094 return count; 3095 } 3096 3097 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3098 { 3099 int idx; 3100 3101 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3102 return; 3103 3104 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3105 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3106 3107 drm_dev_exit(idx); 3108 } 3109 3110 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3111 psp_usbc_pd_fw_sysfs_read, 3112 psp_usbc_pd_fw_sysfs_write); 3113 3114 3115 3116 const struct amd_ip_funcs psp_ip_funcs = { 3117 .name = "psp", 3118 .early_init = psp_early_init, 3119 .late_init = NULL, 3120 .sw_init = psp_sw_init, 3121 .sw_fini = psp_sw_fini, 3122 .hw_init = psp_hw_init, 3123 .hw_fini = psp_hw_fini, 3124 .suspend = psp_suspend, 3125 .resume = psp_resume, 3126 .is_idle = NULL, 3127 .check_soft_reset = NULL, 3128 .wait_for_idle = NULL, 3129 .soft_reset = NULL, 3130 .set_clockgating_state = psp_set_clockgating_state, 3131 .set_powergating_state = psp_set_powergating_state, 3132 }; 3133 3134 static int psp_sysfs_init(struct amdgpu_device *adev) 3135 { 3136 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3137 3138 if (ret) 3139 DRM_ERROR("Failed to create USBC PD FW control file!"); 3140 3141 return ret; 3142 } 3143 3144 static void psp_sysfs_fini(struct amdgpu_device *adev) 3145 { 3146 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3147 } 3148 3149 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3150 { 3151 .type = AMD_IP_BLOCK_TYPE_PSP, 3152 .major = 3, 3153 .minor = 1, 3154 .rev = 0, 3155 .funcs = &psp_ip_funcs, 3156 }; 3157 3158 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3159 { 3160 .type = AMD_IP_BLOCK_TYPE_PSP, 3161 .major = 10, 3162 .minor = 0, 3163 .rev = 0, 3164 .funcs = &psp_ip_funcs, 3165 }; 3166 3167 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3168 { 3169 .type = AMD_IP_BLOCK_TYPE_PSP, 3170 .major = 11, 3171 .minor = 0, 3172 .rev = 0, 3173 .funcs = &psp_ip_funcs, 3174 }; 3175 3176 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3177 { 3178 .type = AMD_IP_BLOCK_TYPE_PSP, 3179 .major = 12, 3180 .minor = 0, 3181 .rev = 0, 3182 .funcs = &psp_ip_funcs, 3183 }; 3184 3185 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3186 .type = AMD_IP_BLOCK_TYPE_PSP, 3187 .major = 13, 3188 .minor = 0, 3189 .rev = 0, 3190 .funcs = &psp_ip_funcs, 3191 }; 3192