1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 static int psp_ring_init(struct psp_context *psp, 53 enum psp_ring_type ring_type) 54 { 55 int ret = 0; 56 struct psp_ring *ring; 57 struct amdgpu_device *adev = psp->adev; 58 59 ring = &psp->km_ring; 60 61 ring->ring_type = ring_type; 62 63 /* allocate 4k Page of Local Frame Buffer memory for ring */ 64 ring->ring_size = 0x1000; 65 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 66 AMDGPU_GEM_DOMAIN_VRAM | 67 AMDGPU_GEM_DOMAIN_GTT, 68 &adev->firmware.rbuf, 69 &ring->ring_mem_mc_addr, 70 (void **)&ring->ring_mem); 71 if (ret) { 72 ring->ring_size = 0; 73 return ret; 74 } 75 76 return 0; 77 } 78 79 /* 80 * Due to DF Cstate management centralized to PMFW, the firmware 81 * loading sequence will be updated as below: 82 * - Load KDB 83 * - Load SYS_DRV 84 * - Load tOS 85 * - Load PMFW 86 * - Setup TMR 87 * - Load other non-psp fw 88 * - Load ASD 89 * - Load XGMI/RAS/HDCP/DTM TA if any 90 * 91 * This new sequence is required for 92 * - Arcturus and onwards 93 */ 94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 95 { 96 struct amdgpu_device *adev = psp->adev; 97 98 if (amdgpu_sriov_vf(adev)) { 99 psp->pmfw_centralized_cstate_management = false; 100 return; 101 } 102 103 switch (adev->ip_versions[MP0_HWIP][0]) { 104 case IP_VERSION(11, 0, 0): 105 case IP_VERSION(11, 0, 4): 106 case IP_VERSION(11, 0, 5): 107 case IP_VERSION(11, 0, 7): 108 case IP_VERSION(11, 0, 9): 109 case IP_VERSION(11, 0, 11): 110 case IP_VERSION(11, 0, 12): 111 case IP_VERSION(11, 0, 13): 112 case IP_VERSION(13, 0, 0): 113 case IP_VERSION(13, 0, 2): 114 case IP_VERSION(13, 0, 7): 115 psp->pmfw_centralized_cstate_management = true; 116 break; 117 default: 118 psp->pmfw_centralized_cstate_management = false; 119 break; 120 } 121 } 122 123 static int psp_init_sriov_microcode(struct psp_context *psp) 124 { 125 struct amdgpu_device *adev = psp->adev; 126 char ucode_prefix[30]; 127 int ret = 0; 128 129 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 130 131 switch (adev->ip_versions[MP0_HWIP][0]) { 132 case IP_VERSION(9, 0, 0): 133 case IP_VERSION(11, 0, 7): 134 case IP_VERSION(11, 0, 9): 135 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 136 ret = psp_init_cap_microcode(psp, ucode_prefix); 137 break; 138 case IP_VERSION(13, 0, 2): 139 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 140 ret = psp_init_cap_microcode(psp, ucode_prefix); 141 ret &= psp_init_ta_microcode(psp, ucode_prefix); 142 break; 143 case IP_VERSION(13, 0, 0): 144 adev->virt.autoload_ucode_id = 0; 145 break; 146 case IP_VERSION(13, 0, 6): 147 ret = psp_init_cap_microcode(psp, ucode_prefix); 148 break; 149 case IP_VERSION(13, 0, 10): 150 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 151 ret = psp_init_cap_microcode(psp, ucode_prefix); 152 break; 153 default: 154 return -EINVAL; 155 } 156 return ret; 157 } 158 159 static int psp_early_init(void *handle) 160 { 161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 162 struct psp_context *psp = &adev->psp; 163 164 switch (adev->ip_versions[MP0_HWIP][0]) { 165 case IP_VERSION(9, 0, 0): 166 psp_v3_1_set_psp_funcs(psp); 167 psp->autoload_supported = false; 168 break; 169 case IP_VERSION(10, 0, 0): 170 case IP_VERSION(10, 0, 1): 171 psp_v10_0_set_psp_funcs(psp); 172 psp->autoload_supported = false; 173 break; 174 case IP_VERSION(11, 0, 2): 175 case IP_VERSION(11, 0, 4): 176 psp_v11_0_set_psp_funcs(psp); 177 psp->autoload_supported = false; 178 break; 179 case IP_VERSION(11, 0, 0): 180 case IP_VERSION(11, 0, 7): 181 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 182 fallthrough; 183 case IP_VERSION(11, 0, 5): 184 case IP_VERSION(11, 0, 9): 185 case IP_VERSION(11, 0, 11): 186 case IP_VERSION(11, 5, 0): 187 case IP_VERSION(11, 0, 12): 188 case IP_VERSION(11, 0, 13): 189 psp_v11_0_set_psp_funcs(psp); 190 psp->autoload_supported = true; 191 break; 192 case IP_VERSION(11, 0, 3): 193 case IP_VERSION(12, 0, 1): 194 psp_v12_0_set_psp_funcs(psp); 195 break; 196 case IP_VERSION(13, 0, 2): 197 case IP_VERSION(13, 0, 6): 198 psp_v13_0_set_psp_funcs(psp); 199 break; 200 case IP_VERSION(13, 0, 1): 201 case IP_VERSION(13, 0, 3): 202 case IP_VERSION(13, 0, 5): 203 case IP_VERSION(13, 0, 8): 204 case IP_VERSION(13, 0, 11): 205 psp_v13_0_set_psp_funcs(psp); 206 psp->autoload_supported = true; 207 break; 208 case IP_VERSION(11, 0, 8): 209 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 210 psp_v11_0_8_set_psp_funcs(psp); 211 psp->autoload_supported = false; 212 } 213 break; 214 case IP_VERSION(13, 0, 0): 215 case IP_VERSION(13, 0, 7): 216 case IP_VERSION(13, 0, 10): 217 psp_v13_0_set_psp_funcs(psp); 218 psp->autoload_supported = true; 219 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 220 break; 221 case IP_VERSION(13, 0, 4): 222 psp_v13_0_4_set_psp_funcs(psp); 223 psp->autoload_supported = true; 224 break; 225 default: 226 return -EINVAL; 227 } 228 229 psp->adev = adev; 230 231 psp_check_pmfw_centralized_cstate_management(psp); 232 233 if (amdgpu_sriov_vf(adev)) 234 return psp_init_sriov_microcode(psp); 235 else 236 return psp_init_microcode(psp); 237 } 238 239 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 240 { 241 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 242 &mem_ctx->shared_buf); 243 mem_ctx->shared_bo = NULL; 244 } 245 246 static void psp_free_shared_bufs(struct psp_context *psp) 247 { 248 void *tmr_buf; 249 void **pptr; 250 251 /* free TMR memory buffer */ 252 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 253 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 254 psp->tmr_bo = NULL; 255 256 /* free xgmi shared memory */ 257 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 258 259 /* free ras shared memory */ 260 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 261 262 /* free hdcp shared memory */ 263 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 264 265 /* free dtm shared memory */ 266 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 267 268 /* free rap shared memory */ 269 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 270 271 /* free securedisplay shared memory */ 272 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 273 274 275 } 276 277 static void psp_memory_training_fini(struct psp_context *psp) 278 { 279 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 280 281 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 282 kfree(ctx->sys_cache); 283 ctx->sys_cache = NULL; 284 } 285 286 static int psp_memory_training_init(struct psp_context *psp) 287 { 288 int ret; 289 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 290 291 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 292 DRM_DEBUG("memory training is not supported!\n"); 293 return 0; 294 } 295 296 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 297 if (ctx->sys_cache == NULL) { 298 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 299 ret = -ENOMEM; 300 goto Err_out; 301 } 302 303 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 304 ctx->train_data_size, 305 ctx->p2c_train_data_offset, 306 ctx->c2p_train_data_offset); 307 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 308 return 0; 309 310 Err_out: 311 psp_memory_training_fini(psp); 312 return ret; 313 } 314 315 /* 316 * Helper funciton to query psp runtime database entry 317 * 318 * @adev: amdgpu_device pointer 319 * @entry_type: the type of psp runtime database entry 320 * @db_entry: runtime database entry pointer 321 * 322 * Return false if runtime database doesn't exit or entry is invalid 323 * or true if the specific database entry is found, and copy to @db_entry 324 */ 325 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 326 enum psp_runtime_entry_type entry_type, 327 void *db_entry) 328 { 329 uint64_t db_header_pos, db_dir_pos; 330 struct psp_runtime_data_header db_header = {0}; 331 struct psp_runtime_data_directory db_dir = {0}; 332 bool ret = false; 333 int i; 334 335 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 336 return false; 337 338 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 339 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 340 341 /* read runtime db header from vram */ 342 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 343 sizeof(struct psp_runtime_data_header), false); 344 345 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 346 /* runtime db doesn't exist, exit */ 347 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 348 return false; 349 } 350 351 /* read runtime database entry from vram */ 352 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 353 sizeof(struct psp_runtime_data_directory), false); 354 355 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 356 /* invalid db entry count, exit */ 357 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 358 return false; 359 } 360 361 /* look up for requested entry type */ 362 for (i = 0; i < db_dir.entry_count && !ret; i++) { 363 if (db_dir.entry_list[i].entry_type == entry_type) { 364 switch (entry_type) { 365 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 366 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 367 /* invalid db entry size */ 368 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 369 return false; 370 } 371 /* read runtime database entry */ 372 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 373 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 374 ret = true; 375 break; 376 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 377 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 378 /* invalid db entry size */ 379 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 380 return false; 381 } 382 /* read runtime database entry */ 383 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 384 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 385 ret = true; 386 break; 387 default: 388 ret = false; 389 break; 390 } 391 } 392 } 393 394 return ret; 395 } 396 397 static int psp_sw_init(void *handle) 398 { 399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 400 struct psp_context *psp = &adev->psp; 401 int ret; 402 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 403 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 404 struct psp_runtime_scpm_entry scpm_entry; 405 406 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 407 if (!psp->cmd) { 408 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 409 ret = -ENOMEM; 410 } 411 412 adev->psp.xgmi_context.supports_extended_data = 413 !adev->gmc.xgmi.connected_to_cpu && 414 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 415 416 memset(&scpm_entry, 0, sizeof(scpm_entry)); 417 if ((psp_get_runtime_db_entry(adev, 418 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 419 &scpm_entry)) && 420 (scpm_entry.scpm_status != SCPM_DISABLE)) { 421 adev->scpm_enabled = true; 422 adev->scpm_status = scpm_entry.scpm_status; 423 } else { 424 adev->scpm_enabled = false; 425 adev->scpm_status = SCPM_DISABLE; 426 } 427 428 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 429 430 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 431 if (psp_get_runtime_db_entry(adev, 432 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 433 &boot_cfg_entry)) { 434 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 435 if ((psp->boot_cfg_bitmask) & 436 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 437 /* If psp runtime database exists, then 438 * only enable two stage memory training 439 * when TWO_STAGE_DRAM_TRAINING bit is set 440 * in runtime database */ 441 mem_training_ctx->enable_mem_training = true; 442 } 443 444 } else { 445 /* If psp runtime database doesn't exist or 446 * is invalid, force enable two stage memory 447 * training */ 448 mem_training_ctx->enable_mem_training = true; 449 } 450 451 if (mem_training_ctx->enable_mem_training) { 452 ret = psp_memory_training_init(psp); 453 if (ret) { 454 DRM_ERROR("Failed to initialize memory training!\n"); 455 return ret; 456 } 457 458 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 459 if (ret) { 460 DRM_ERROR("Failed to process memory training!\n"); 461 return ret; 462 } 463 } 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 466 amdgpu_sriov_vf(adev) ? 467 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 468 &psp->fw_pri_bo, 469 &psp->fw_pri_mc_addr, 470 &psp->fw_pri_buf); 471 if (ret) 472 return ret; 473 474 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 475 AMDGPU_GEM_DOMAIN_VRAM | 476 AMDGPU_GEM_DOMAIN_GTT, 477 &psp->fence_buf_bo, 478 &psp->fence_buf_mc_addr, 479 &psp->fence_buf); 480 if (ret) 481 goto failed1; 482 483 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 484 AMDGPU_GEM_DOMAIN_VRAM | 485 AMDGPU_GEM_DOMAIN_GTT, 486 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 487 (void **)&psp->cmd_buf_mem); 488 if (ret) 489 goto failed2; 490 491 return 0; 492 493 failed2: 494 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 495 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 496 failed1: 497 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 498 &psp->fence_buf_mc_addr, &psp->fence_buf); 499 return ret; 500 } 501 502 static int psp_sw_fini(void *handle) 503 { 504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 505 struct psp_context *psp = &adev->psp; 506 struct psp_gfx_cmd_resp *cmd = psp->cmd; 507 508 psp_memory_training_fini(psp); 509 510 amdgpu_ucode_release(&psp->sos_fw); 511 amdgpu_ucode_release(&psp->asd_fw); 512 amdgpu_ucode_release(&psp->ta_fw); 513 amdgpu_ucode_release(&psp->cap_fw); 514 amdgpu_ucode_release(&psp->toc_fw); 515 516 kfree(cmd); 517 cmd = NULL; 518 519 psp_free_shared_bufs(psp); 520 521 if (psp->km_ring.ring_mem) 522 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 523 &psp->km_ring.ring_mem_mc_addr, 524 (void **)&psp->km_ring.ring_mem); 525 526 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 527 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 528 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 529 &psp->fence_buf_mc_addr, &psp->fence_buf); 530 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 531 (void **)&psp->cmd_buf_mem); 532 533 return 0; 534 } 535 536 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 537 uint32_t reg_val, uint32_t mask, bool check_changed) 538 { 539 uint32_t val; 540 int i; 541 struct amdgpu_device *adev = psp->adev; 542 543 if (psp->adev->no_hw_access) 544 return 0; 545 546 for (i = 0; i < adev->usec_timeout; i++) { 547 val = RREG32(reg_index); 548 if (check_changed) { 549 if (val != reg_val) 550 return 0; 551 } else { 552 if ((val & mask) == reg_val) 553 return 0; 554 } 555 udelay(1); 556 } 557 558 return -ETIME; 559 } 560 561 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 562 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 563 { 564 uint32_t val; 565 int i; 566 struct amdgpu_device *adev = psp->adev; 567 568 if (psp->adev->no_hw_access) 569 return 0; 570 571 for (i = 0; i < msec_timeout; i++) { 572 val = RREG32(reg_index); 573 if ((val & mask) == reg_val) 574 return 0; 575 msleep(1); 576 } 577 578 return -ETIME; 579 } 580 581 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 582 { 583 switch (cmd_id) { 584 case GFX_CMD_ID_LOAD_TA: 585 return "LOAD_TA"; 586 case GFX_CMD_ID_UNLOAD_TA: 587 return "UNLOAD_TA"; 588 case GFX_CMD_ID_INVOKE_CMD: 589 return "INVOKE_CMD"; 590 case GFX_CMD_ID_LOAD_ASD: 591 return "LOAD_ASD"; 592 case GFX_CMD_ID_SETUP_TMR: 593 return "SETUP_TMR"; 594 case GFX_CMD_ID_LOAD_IP_FW: 595 return "LOAD_IP_FW"; 596 case GFX_CMD_ID_DESTROY_TMR: 597 return "DESTROY_TMR"; 598 case GFX_CMD_ID_SAVE_RESTORE: 599 return "SAVE_RESTORE_IP_FW"; 600 case GFX_CMD_ID_SETUP_VMR: 601 return "SETUP_VMR"; 602 case GFX_CMD_ID_DESTROY_VMR: 603 return "DESTROY_VMR"; 604 case GFX_CMD_ID_PROG_REG: 605 return "PROG_REG"; 606 case GFX_CMD_ID_GET_FW_ATTESTATION: 607 return "GET_FW_ATTESTATION"; 608 case GFX_CMD_ID_LOAD_TOC: 609 return "ID_LOAD_TOC"; 610 case GFX_CMD_ID_AUTOLOAD_RLC: 611 return "AUTOLOAD_RLC"; 612 case GFX_CMD_ID_BOOT_CFG: 613 return "BOOT_CFG"; 614 default: 615 return "UNKNOWN CMD"; 616 } 617 } 618 619 static int 620 psp_cmd_submit_buf(struct psp_context *psp, 621 struct amdgpu_firmware_info *ucode, 622 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 623 { 624 int ret; 625 int index; 626 int timeout = 20000; 627 bool ras_intr = false; 628 bool skip_unsupport = false; 629 630 if (psp->adev->no_hw_access) 631 return 0; 632 633 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 634 635 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 636 637 index = atomic_inc_return(&psp->fence_value); 638 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 639 if (ret) { 640 atomic_dec(&psp->fence_value); 641 goto exit; 642 } 643 644 amdgpu_device_invalidate_hdp(psp->adev, NULL); 645 while (*((unsigned int *)psp->fence_buf) != index) { 646 if (--timeout == 0) 647 break; 648 /* 649 * Shouldn't wait for timeout when err_event_athub occurs, 650 * because gpu reset thread triggered and lock resource should 651 * be released for psp resume sequence. 652 */ 653 ras_intr = amdgpu_ras_intr_triggered(); 654 if (ras_intr) 655 break; 656 usleep_range(10, 100); 657 amdgpu_device_invalidate_hdp(psp->adev, NULL); 658 } 659 660 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 661 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 662 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 663 664 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 665 666 /* In some cases, psp response status is not 0 even there is no 667 * problem while the command is submitted. Some version of PSP FW 668 * doesn't write 0 to that field. 669 * So here we would like to only print a warning instead of an error 670 * during psp initialization to avoid breaking hw_init and it doesn't 671 * return -EINVAL. 672 */ 673 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 674 if (ucode) 675 DRM_WARN("failed to load ucode %s(0x%X) ", 676 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 677 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 678 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 679 psp->cmd_buf_mem->resp.status); 680 /* If any firmware (including CAP) load fails under SRIOV, it should 681 * return failure to stop the VF from initializing. 682 * Also return failure in case of timeout 683 */ 684 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 685 ret = -EINVAL; 686 goto exit; 687 } 688 } 689 690 if (ucode) { 691 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 692 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 693 } 694 695 exit: 696 return ret; 697 } 698 699 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 700 { 701 struct psp_gfx_cmd_resp *cmd = psp->cmd; 702 703 mutex_lock(&psp->mutex); 704 705 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 706 707 return cmd; 708 } 709 710 static void release_psp_cmd_buf(struct psp_context *psp) 711 { 712 mutex_unlock(&psp->mutex); 713 } 714 715 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 716 struct psp_gfx_cmd_resp *cmd, 717 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 718 { 719 struct amdgpu_device *adev = psp->adev; 720 uint32_t size = 0; 721 uint64_t tmr_pa = 0; 722 723 if (tmr_bo) { 724 size = amdgpu_bo_size(tmr_bo); 725 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 726 } 727 728 if (amdgpu_sriov_vf(psp->adev)) 729 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 730 else 731 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 732 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 733 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 734 cmd->cmd.cmd_setup_tmr.buf_size = size; 735 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 736 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 737 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 738 } 739 740 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 741 uint64_t pri_buf_mc, uint32_t size) 742 { 743 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 744 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 745 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 746 cmd->cmd.cmd_load_toc.toc_size = size; 747 } 748 749 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 750 static int psp_load_toc(struct psp_context *psp, 751 uint32_t *tmr_size) 752 { 753 int ret; 754 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 755 756 /* Copy toc to psp firmware private buffer */ 757 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 758 759 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 760 761 ret = psp_cmd_submit_buf(psp, NULL, cmd, 762 psp->fence_buf_mc_addr); 763 if (!ret) 764 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 765 766 release_psp_cmd_buf(psp); 767 768 return ret; 769 } 770 771 static bool psp_boottime_tmr(struct psp_context *psp) 772 { 773 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 774 case IP_VERSION(13, 0, 6): 775 return true; 776 default: 777 return false; 778 } 779 } 780 781 /* Set up Trusted Memory Region */ 782 static int psp_tmr_init(struct psp_context *psp) 783 { 784 int ret = 0; 785 int tmr_size; 786 void *tmr_buf; 787 void **pptr; 788 789 /* 790 * According to HW engineer, they prefer the TMR address be "naturally 791 * aligned" , e.g. the start address be an integer divide of TMR size. 792 * 793 * Note: this memory need be reserved till the driver 794 * uninitializes. 795 */ 796 tmr_size = PSP_TMR_SIZE(psp->adev); 797 798 /* For ASICs support RLC autoload, psp will parse the toc 799 * and calculate the total size of TMR needed */ 800 if (!amdgpu_sriov_vf(psp->adev) && 801 psp->toc.start_addr && 802 psp->toc.size_bytes && 803 psp->fw_pri_buf) { 804 ret = psp_load_toc(psp, &tmr_size); 805 if (ret) { 806 DRM_ERROR("Failed to load toc\n"); 807 return ret; 808 } 809 } 810 811 if (!psp->tmr_bo) { 812 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 813 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 814 PSP_TMR_ALIGNMENT, 815 AMDGPU_HAS_VRAM(psp->adev) ? 816 AMDGPU_GEM_DOMAIN_VRAM : 817 AMDGPU_GEM_DOMAIN_GTT, 818 &psp->tmr_bo, &psp->tmr_mc_addr, 819 pptr); 820 } 821 822 return ret; 823 } 824 825 static bool psp_skip_tmr(struct psp_context *psp) 826 { 827 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 828 case IP_VERSION(11, 0, 9): 829 case IP_VERSION(11, 0, 7): 830 case IP_VERSION(13, 0, 2): 831 case IP_VERSION(13, 0, 6): 832 case IP_VERSION(13, 0, 10): 833 return true; 834 default: 835 return false; 836 } 837 } 838 839 static int psp_tmr_load(struct psp_context *psp) 840 { 841 int ret; 842 struct psp_gfx_cmd_resp *cmd; 843 844 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 845 * Already set up by host driver. 846 */ 847 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 848 return 0; 849 850 cmd = acquire_psp_cmd_buf(psp); 851 852 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 853 if (psp->tmr_bo) 854 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 855 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 856 857 ret = psp_cmd_submit_buf(psp, NULL, cmd, 858 psp->fence_buf_mc_addr); 859 860 release_psp_cmd_buf(psp); 861 862 return ret; 863 } 864 865 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 866 struct psp_gfx_cmd_resp *cmd) 867 { 868 if (amdgpu_sriov_vf(psp->adev)) 869 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 870 else 871 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 872 } 873 874 static int psp_tmr_unload(struct psp_context *psp) 875 { 876 int ret; 877 struct psp_gfx_cmd_resp *cmd; 878 879 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 880 * as TMR is not loaded at all 881 */ 882 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 883 return 0; 884 885 cmd = acquire_psp_cmd_buf(psp); 886 887 psp_prep_tmr_unload_cmd_buf(psp, cmd); 888 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 889 890 ret = psp_cmd_submit_buf(psp, NULL, cmd, 891 psp->fence_buf_mc_addr); 892 893 release_psp_cmd_buf(psp); 894 895 return ret; 896 } 897 898 static int psp_tmr_terminate(struct psp_context *psp) 899 { 900 return psp_tmr_unload(psp); 901 } 902 903 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 904 uint64_t *output_ptr) 905 { 906 int ret; 907 struct psp_gfx_cmd_resp *cmd; 908 909 if (!output_ptr) 910 return -EINVAL; 911 912 if (amdgpu_sriov_vf(psp->adev)) 913 return 0; 914 915 cmd = acquire_psp_cmd_buf(psp); 916 917 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 918 919 ret = psp_cmd_submit_buf(psp, NULL, cmd, 920 psp->fence_buf_mc_addr); 921 922 if (!ret) { 923 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 924 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 925 } 926 927 release_psp_cmd_buf(psp); 928 929 return ret; 930 } 931 932 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 933 { 934 struct psp_context *psp = &adev->psp; 935 struct psp_gfx_cmd_resp *cmd; 936 int ret; 937 938 if (amdgpu_sriov_vf(adev)) 939 return 0; 940 941 cmd = acquire_psp_cmd_buf(psp); 942 943 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 944 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 945 946 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 947 if (!ret) { 948 *boot_cfg = 949 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 950 } 951 952 release_psp_cmd_buf(psp); 953 954 return ret; 955 } 956 957 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 958 { 959 int ret; 960 struct psp_context *psp = &adev->psp; 961 struct psp_gfx_cmd_resp *cmd; 962 963 if (amdgpu_sriov_vf(adev)) 964 return 0; 965 966 cmd = acquire_psp_cmd_buf(psp); 967 968 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 969 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 970 cmd->cmd.boot_cfg.boot_config = boot_cfg; 971 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 972 973 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 974 975 release_psp_cmd_buf(psp); 976 977 return ret; 978 } 979 980 static int psp_rl_load(struct amdgpu_device *adev) 981 { 982 int ret; 983 struct psp_context *psp = &adev->psp; 984 struct psp_gfx_cmd_resp *cmd; 985 986 if (!is_psp_fw_valid(psp->rl)) 987 return 0; 988 989 cmd = acquire_psp_cmd_buf(psp); 990 991 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 992 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 993 994 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 995 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 996 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 997 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 998 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 999 1000 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1001 1002 release_psp_cmd_buf(psp); 1003 1004 return ret; 1005 } 1006 1007 int psp_spatial_partition(struct psp_context *psp, int mode) 1008 { 1009 struct psp_gfx_cmd_resp *cmd; 1010 int ret; 1011 1012 if (amdgpu_sriov_vf(psp->adev)) 1013 return 0; 1014 1015 cmd = acquire_psp_cmd_buf(psp); 1016 1017 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1018 cmd->cmd.cmd_spatial_part.mode = mode; 1019 1020 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1021 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1022 1023 release_psp_cmd_buf(psp); 1024 1025 return ret; 1026 } 1027 1028 static int psp_asd_initialize(struct psp_context *psp) 1029 { 1030 int ret; 1031 1032 /* If PSP version doesn't match ASD version, asd loading will be failed. 1033 * add workaround to bypass it for sriov now. 1034 * TODO: add version check to make it common 1035 */ 1036 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1037 return 0; 1038 1039 psp->asd_context.mem_context.shared_mc_addr = 0; 1040 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1041 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1042 1043 ret = psp_ta_load(psp, &psp->asd_context); 1044 if (!ret) 1045 psp->asd_context.initialized = true; 1046 1047 return ret; 1048 } 1049 1050 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1051 uint32_t session_id) 1052 { 1053 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1054 cmd->cmd.cmd_unload_ta.session_id = session_id; 1055 } 1056 1057 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1058 { 1059 int ret; 1060 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1061 1062 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1063 1064 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1065 1066 context->resp_status = cmd->resp.status; 1067 1068 release_psp_cmd_buf(psp); 1069 1070 return ret; 1071 } 1072 1073 static int psp_asd_terminate(struct psp_context *psp) 1074 { 1075 int ret; 1076 1077 if (amdgpu_sriov_vf(psp->adev)) 1078 return 0; 1079 1080 if (!psp->asd_context.initialized) 1081 return 0; 1082 1083 ret = psp_ta_unload(psp, &psp->asd_context); 1084 if (!ret) 1085 psp->asd_context.initialized = false; 1086 1087 return ret; 1088 } 1089 1090 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1091 uint32_t id, uint32_t value) 1092 { 1093 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1094 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1095 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1096 } 1097 1098 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1099 uint32_t value) 1100 { 1101 struct psp_gfx_cmd_resp *cmd; 1102 int ret = 0; 1103 1104 if (reg >= PSP_REG_LAST) 1105 return -EINVAL; 1106 1107 cmd = acquire_psp_cmd_buf(psp); 1108 1109 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1110 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1111 if (ret) 1112 DRM_ERROR("PSP failed to program reg id %d", reg); 1113 1114 release_psp_cmd_buf(psp); 1115 1116 return ret; 1117 } 1118 1119 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1120 uint64_t ta_bin_mc, 1121 struct ta_context *context) 1122 { 1123 cmd->cmd_id = context->ta_load_type; 1124 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1125 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1126 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1127 1128 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1129 lower_32_bits(context->mem_context.shared_mc_addr); 1130 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1131 upper_32_bits(context->mem_context.shared_mc_addr); 1132 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1133 } 1134 1135 int psp_ta_init_shared_buf(struct psp_context *psp, 1136 struct ta_mem_context *mem_ctx) 1137 { 1138 /* 1139 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1140 * physical) for ta to host memory 1141 */ 1142 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1143 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1144 AMDGPU_GEM_DOMAIN_GTT, 1145 &mem_ctx->shared_bo, 1146 &mem_ctx->shared_mc_addr, 1147 &mem_ctx->shared_buf); 1148 } 1149 1150 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1151 uint32_t ta_cmd_id, 1152 uint32_t session_id) 1153 { 1154 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1155 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1156 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1157 } 1158 1159 int psp_ta_invoke(struct psp_context *psp, 1160 uint32_t ta_cmd_id, 1161 struct ta_context *context) 1162 { 1163 int ret; 1164 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1165 1166 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1167 1168 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1169 psp->fence_buf_mc_addr); 1170 1171 context->resp_status = cmd->resp.status; 1172 1173 release_psp_cmd_buf(psp); 1174 1175 return ret; 1176 } 1177 1178 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1179 { 1180 int ret; 1181 struct psp_gfx_cmd_resp *cmd; 1182 1183 cmd = acquire_psp_cmd_buf(psp); 1184 1185 psp_copy_fw(psp, context->bin_desc.start_addr, 1186 context->bin_desc.size_bytes); 1187 1188 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1189 1190 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1191 psp->fence_buf_mc_addr); 1192 1193 context->resp_status = cmd->resp.status; 1194 1195 if (!ret) 1196 context->session_id = cmd->resp.session_id; 1197 1198 release_psp_cmd_buf(psp); 1199 1200 return ret; 1201 } 1202 1203 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1204 { 1205 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1206 } 1207 1208 int psp_xgmi_terminate(struct psp_context *psp) 1209 { 1210 int ret; 1211 struct amdgpu_device *adev = psp->adev; 1212 1213 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1214 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1215 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1216 adev->gmc.xgmi.connected_to_cpu)) 1217 return 0; 1218 1219 if (!psp->xgmi_context.context.initialized) 1220 return 0; 1221 1222 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1223 1224 psp->xgmi_context.context.initialized = false; 1225 1226 return ret; 1227 } 1228 1229 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1230 { 1231 struct ta_xgmi_shared_memory *xgmi_cmd; 1232 int ret; 1233 1234 if (!psp->ta_fw || 1235 !psp->xgmi_context.context.bin_desc.size_bytes || 1236 !psp->xgmi_context.context.bin_desc.start_addr) 1237 return -ENOENT; 1238 1239 if (!load_ta) 1240 goto invoke; 1241 1242 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1243 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1244 1245 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1246 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1247 if (ret) 1248 return ret; 1249 } 1250 1251 /* Load XGMI TA */ 1252 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1253 if (!ret) 1254 psp->xgmi_context.context.initialized = true; 1255 else 1256 return ret; 1257 1258 invoke: 1259 /* Initialize XGMI session */ 1260 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1261 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1262 xgmi_cmd->flag_extend_link_record = set_extended_data; 1263 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1264 1265 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1266 1267 return ret; 1268 } 1269 1270 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1271 { 1272 struct ta_xgmi_shared_memory *xgmi_cmd; 1273 int ret; 1274 1275 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1276 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1277 1278 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1279 1280 /* Invoke xgmi ta to get hive id */ 1281 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1282 if (ret) 1283 return ret; 1284 1285 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1286 1287 return 0; 1288 } 1289 1290 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1291 { 1292 struct ta_xgmi_shared_memory *xgmi_cmd; 1293 int ret; 1294 1295 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1296 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1297 1298 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1299 1300 /* Invoke xgmi ta to get the node id */ 1301 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1302 if (ret) 1303 return ret; 1304 1305 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1306 1307 return 0; 1308 } 1309 1310 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1311 { 1312 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1313 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1314 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6); 1315 } 1316 1317 /* 1318 * Chips that support extended topology information require the driver to 1319 * reflect topology information in the opposite direction. This is 1320 * because the TA has already exceeded its link record limit and if the 1321 * TA holds bi-directional information, the driver would have to do 1322 * multiple fetches instead of just two. 1323 */ 1324 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1325 struct psp_xgmi_node_info node_info) 1326 { 1327 struct amdgpu_device *mirror_adev; 1328 struct amdgpu_hive_info *hive; 1329 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1330 uint64_t dst_node_id = node_info.node_id; 1331 uint8_t dst_num_hops = node_info.num_hops; 1332 uint8_t dst_num_links = node_info.num_links; 1333 1334 hive = amdgpu_get_xgmi_hive(psp->adev); 1335 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1336 struct psp_xgmi_topology_info *mirror_top_info; 1337 int j; 1338 1339 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1340 continue; 1341 1342 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1343 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1344 if (mirror_top_info->nodes[j].node_id != src_node_id) 1345 continue; 1346 1347 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1348 /* 1349 * prevent 0 num_links value re-reflection since reflection 1350 * criteria is based on num_hops (direct or indirect). 1351 * 1352 */ 1353 if (dst_num_links) 1354 mirror_top_info->nodes[j].num_links = dst_num_links; 1355 1356 break; 1357 } 1358 1359 break; 1360 } 1361 1362 amdgpu_put_xgmi_hive(hive); 1363 } 1364 1365 int psp_xgmi_get_topology_info(struct psp_context *psp, 1366 int number_devices, 1367 struct psp_xgmi_topology_info *topology, 1368 bool get_extended_data) 1369 { 1370 struct ta_xgmi_shared_memory *xgmi_cmd; 1371 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1372 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1373 int i; 1374 int ret; 1375 1376 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1377 return -EINVAL; 1378 1379 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1380 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1381 xgmi_cmd->flag_extend_link_record = get_extended_data; 1382 1383 /* Fill in the shared memory with topology information as input */ 1384 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1385 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1386 topology_info_input->num_nodes = number_devices; 1387 1388 for (i = 0; i < topology_info_input->num_nodes; i++) { 1389 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1390 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1391 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1392 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1393 } 1394 1395 /* Invoke xgmi ta to get the topology information */ 1396 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1397 if (ret) 1398 return ret; 1399 1400 /* Read the output topology information from the shared memory */ 1401 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1402 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1403 for (i = 0; i < topology->num_nodes; i++) { 1404 /* extended data will either be 0 or equal to non-extended data */ 1405 if (topology_info_output->nodes[i].num_hops) 1406 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1407 1408 /* non-extended data gets everything here so no need to update */ 1409 if (!get_extended_data) { 1410 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1411 topology->nodes[i].is_sharing_enabled = 1412 topology_info_output->nodes[i].is_sharing_enabled; 1413 topology->nodes[i].sdma_engine = 1414 topology_info_output->nodes[i].sdma_engine; 1415 } 1416 1417 } 1418 1419 /* Invoke xgmi ta again to get the link information */ 1420 if (psp_xgmi_peer_link_info_supported(psp)) { 1421 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1422 bool requires_reflection = 1423 (psp->xgmi_context.supports_extended_data && get_extended_data) || 1424 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6); 1425 1426 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1427 1428 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1429 1430 if (ret) 1431 return ret; 1432 1433 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1434 for (i = 0; i < topology->num_nodes; i++) { 1435 /* accumulate num_links on extended data */ 1436 topology->nodes[i].num_links = get_extended_data ? 1437 topology->nodes[i].num_links + 1438 link_info_output->nodes[i].num_links : 1439 ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links : 1440 link_info_output->nodes[i].num_links); 1441 1442 /* reflect the topology information for bi-directionality */ 1443 if (requires_reflection && topology->nodes[i].num_hops) 1444 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1445 } 1446 } 1447 1448 return 0; 1449 } 1450 1451 int psp_xgmi_set_topology_info(struct psp_context *psp, 1452 int number_devices, 1453 struct psp_xgmi_topology_info *topology) 1454 { 1455 struct ta_xgmi_shared_memory *xgmi_cmd; 1456 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1457 int i; 1458 1459 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1460 return -EINVAL; 1461 1462 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1463 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1464 1465 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1466 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1467 topology_info_input->num_nodes = number_devices; 1468 1469 for (i = 0; i < topology_info_input->num_nodes; i++) { 1470 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1471 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1472 topology_info_input->nodes[i].is_sharing_enabled = 1; 1473 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1474 } 1475 1476 /* Invoke xgmi ta to set topology information */ 1477 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1478 } 1479 1480 // ras begin 1481 static void psp_ras_ta_check_status(struct psp_context *psp) 1482 { 1483 struct ta_ras_shared_memory *ras_cmd = 1484 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1485 1486 switch (ras_cmd->ras_status) { 1487 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1488 dev_warn(psp->adev->dev, 1489 "RAS WARNING: cmd failed due to unsupported ip\n"); 1490 break; 1491 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1492 dev_warn(psp->adev->dev, 1493 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1494 break; 1495 case TA_RAS_STATUS__SUCCESS: 1496 break; 1497 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1498 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1499 dev_warn(psp->adev->dev, 1500 "RAS WARNING: Inject error to critical region is not allowed\n"); 1501 break; 1502 default: 1503 dev_warn(psp->adev->dev, 1504 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1505 break; 1506 } 1507 } 1508 1509 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1510 { 1511 struct ta_ras_shared_memory *ras_cmd; 1512 int ret; 1513 1514 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1515 1516 /* 1517 * TODO: bypass the loading in sriov for now 1518 */ 1519 if (amdgpu_sriov_vf(psp->adev)) 1520 return 0; 1521 1522 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1523 1524 if (amdgpu_ras_intr_triggered()) 1525 return ret; 1526 1527 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1528 DRM_WARN("RAS: Unsupported Interface"); 1529 return -EINVAL; 1530 } 1531 1532 if (!ret) { 1533 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1534 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1535 1536 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1537 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1538 dev_warn(psp->adev->dev, 1539 "RAS internal register access blocked\n"); 1540 1541 psp_ras_ta_check_status(psp); 1542 } 1543 1544 return ret; 1545 } 1546 1547 int psp_ras_enable_features(struct psp_context *psp, 1548 union ta_ras_cmd_input *info, bool enable) 1549 { 1550 struct ta_ras_shared_memory *ras_cmd; 1551 int ret; 1552 1553 if (!psp->ras_context.context.initialized) 1554 return -EINVAL; 1555 1556 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1557 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1558 1559 if (enable) 1560 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1561 else 1562 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1563 1564 ras_cmd->ras_in_message = *info; 1565 1566 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1567 if (ret) 1568 return -EINVAL; 1569 1570 return 0; 1571 } 1572 1573 int psp_ras_terminate(struct psp_context *psp) 1574 { 1575 int ret; 1576 1577 /* 1578 * TODO: bypass the terminate in sriov for now 1579 */ 1580 if (amdgpu_sriov_vf(psp->adev)) 1581 return 0; 1582 1583 if (!psp->ras_context.context.initialized) 1584 return 0; 1585 1586 ret = psp_ta_unload(psp, &psp->ras_context.context); 1587 1588 psp->ras_context.context.initialized = false; 1589 1590 return ret; 1591 } 1592 1593 int psp_ras_initialize(struct psp_context *psp) 1594 { 1595 int ret; 1596 uint32_t boot_cfg = 0xFF; 1597 struct amdgpu_device *adev = psp->adev; 1598 struct ta_ras_shared_memory *ras_cmd; 1599 1600 /* 1601 * TODO: bypass the initialize in sriov for now 1602 */ 1603 if (amdgpu_sriov_vf(adev)) 1604 return 0; 1605 1606 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1607 !adev->psp.ras_context.context.bin_desc.start_addr) { 1608 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1609 return 0; 1610 } 1611 1612 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1613 /* query GECC enablement status from boot config 1614 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1615 */ 1616 ret = psp_boot_config_get(adev, &boot_cfg); 1617 if (ret) 1618 dev_warn(adev->dev, "PSP get boot config failed\n"); 1619 1620 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1621 if (!boot_cfg) { 1622 dev_info(adev->dev, "GECC is disabled\n"); 1623 } else { 1624 /* disable GECC in next boot cycle if ras is 1625 * disabled by module parameter amdgpu_ras_enable 1626 * and/or amdgpu_ras_mask, or boot_config_get call 1627 * is failed 1628 */ 1629 ret = psp_boot_config_set(adev, 0); 1630 if (ret) 1631 dev_warn(adev->dev, "PSP set boot config failed\n"); 1632 else 1633 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1634 } 1635 } else { 1636 if (boot_cfg == 1) { 1637 dev_info(adev->dev, "GECC is enabled\n"); 1638 } else { 1639 /* enable GECC in next boot cycle if it is disabled 1640 * in boot config, or force enable GECC if failed to 1641 * get boot configuration 1642 */ 1643 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1644 if (ret) 1645 dev_warn(adev->dev, "PSP set boot config failed\n"); 1646 else 1647 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1648 } 1649 } 1650 } 1651 1652 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1653 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1654 1655 if (!psp->ras_context.context.mem_context.shared_buf) { 1656 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1657 if (ret) 1658 return ret; 1659 } 1660 1661 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1662 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1663 1664 if (amdgpu_ras_is_poison_mode_supported(adev)) 1665 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1666 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1667 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1668 ras_cmd->ras_in_message.init_flags.xcc_mask = 1669 adev->gfx.xcc_mask; 1670 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1671 1672 ret = psp_ta_load(psp, &psp->ras_context.context); 1673 1674 if (!ret && !ras_cmd->ras_status) 1675 psp->ras_context.context.initialized = true; 1676 else { 1677 if (ras_cmd->ras_status) 1678 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1679 1680 /* fail to load RAS TA */ 1681 psp->ras_context.context.initialized = false; 1682 } 1683 1684 return ret; 1685 } 1686 1687 int psp_ras_trigger_error(struct psp_context *psp, 1688 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1689 { 1690 struct ta_ras_shared_memory *ras_cmd; 1691 struct amdgpu_device *adev = psp->adev; 1692 int ret; 1693 uint32_t dev_mask; 1694 1695 if (!psp->ras_context.context.initialized) 1696 return -EINVAL; 1697 1698 switch (info->block_id) { 1699 case TA_RAS_BLOCK__GFX: 1700 dev_mask = GET_MASK(GC, instance_mask); 1701 break; 1702 case TA_RAS_BLOCK__SDMA: 1703 dev_mask = GET_MASK(SDMA0, instance_mask); 1704 break; 1705 case TA_RAS_BLOCK__VCN: 1706 case TA_RAS_BLOCK__JPEG: 1707 dev_mask = GET_MASK(VCN, instance_mask); 1708 break; 1709 default: 1710 dev_mask = instance_mask; 1711 break; 1712 } 1713 1714 /* reuse sub_block_index for backward compatibility */ 1715 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1716 dev_mask &= AMDGPU_RAS_INST_MASK; 1717 info->sub_block_index |= dev_mask; 1718 1719 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1720 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1721 1722 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1723 ras_cmd->ras_in_message.trigger_error = *info; 1724 1725 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1726 if (ret) 1727 return -EINVAL; 1728 1729 /* If err_event_athub occurs error inject was successful, however 1730 return status from TA is no long reliable */ 1731 if (amdgpu_ras_intr_triggered()) 1732 return 0; 1733 1734 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1735 return -EACCES; 1736 else if (ras_cmd->ras_status) 1737 return -EINVAL; 1738 1739 return 0; 1740 } 1741 // ras end 1742 1743 // HDCP start 1744 static int psp_hdcp_initialize(struct psp_context *psp) 1745 { 1746 int ret; 1747 1748 /* 1749 * TODO: bypass the initialize in sriov for now 1750 */ 1751 if (amdgpu_sriov_vf(psp->adev)) 1752 return 0; 1753 1754 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1755 !psp->hdcp_context.context.bin_desc.start_addr) { 1756 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1757 return 0; 1758 } 1759 1760 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1761 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1762 1763 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1764 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1765 if (ret) 1766 return ret; 1767 } 1768 1769 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1770 if (!ret) { 1771 psp->hdcp_context.context.initialized = true; 1772 mutex_init(&psp->hdcp_context.mutex); 1773 } 1774 1775 return ret; 1776 } 1777 1778 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1779 { 1780 /* 1781 * TODO: bypass the loading in sriov for now 1782 */ 1783 if (amdgpu_sriov_vf(psp->adev)) 1784 return 0; 1785 1786 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1787 } 1788 1789 static int psp_hdcp_terminate(struct psp_context *psp) 1790 { 1791 int ret; 1792 1793 /* 1794 * TODO: bypass the terminate in sriov for now 1795 */ 1796 if (amdgpu_sriov_vf(psp->adev)) 1797 return 0; 1798 1799 if (!psp->hdcp_context.context.initialized) 1800 return 0; 1801 1802 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1803 1804 psp->hdcp_context.context.initialized = false; 1805 1806 return ret; 1807 } 1808 // HDCP end 1809 1810 // DTM start 1811 static int psp_dtm_initialize(struct psp_context *psp) 1812 { 1813 int ret; 1814 1815 /* 1816 * TODO: bypass the initialize in sriov for now 1817 */ 1818 if (amdgpu_sriov_vf(psp->adev)) 1819 return 0; 1820 1821 if (!psp->dtm_context.context.bin_desc.size_bytes || 1822 !psp->dtm_context.context.bin_desc.start_addr) { 1823 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1824 return 0; 1825 } 1826 1827 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1828 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1829 1830 if (!psp->dtm_context.context.mem_context.shared_buf) { 1831 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1832 if (ret) 1833 return ret; 1834 } 1835 1836 ret = psp_ta_load(psp, &psp->dtm_context.context); 1837 if (!ret) { 1838 psp->dtm_context.context.initialized = true; 1839 mutex_init(&psp->dtm_context.mutex); 1840 } 1841 1842 return ret; 1843 } 1844 1845 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1846 { 1847 /* 1848 * TODO: bypass the loading in sriov for now 1849 */ 1850 if (amdgpu_sriov_vf(psp->adev)) 1851 return 0; 1852 1853 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1854 } 1855 1856 static int psp_dtm_terminate(struct psp_context *psp) 1857 { 1858 int ret; 1859 1860 /* 1861 * TODO: bypass the terminate in sriov for now 1862 */ 1863 if (amdgpu_sriov_vf(psp->adev)) 1864 return 0; 1865 1866 if (!psp->dtm_context.context.initialized) 1867 return 0; 1868 1869 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1870 1871 psp->dtm_context.context.initialized = false; 1872 1873 return ret; 1874 } 1875 // DTM end 1876 1877 // RAP start 1878 static int psp_rap_initialize(struct psp_context *psp) 1879 { 1880 int ret; 1881 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1882 1883 /* 1884 * TODO: bypass the initialize in sriov for now 1885 */ 1886 if (amdgpu_sriov_vf(psp->adev)) 1887 return 0; 1888 1889 if (!psp->rap_context.context.bin_desc.size_bytes || 1890 !psp->rap_context.context.bin_desc.start_addr) { 1891 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1892 return 0; 1893 } 1894 1895 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1896 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1897 1898 if (!psp->rap_context.context.mem_context.shared_buf) { 1899 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1900 if (ret) 1901 return ret; 1902 } 1903 1904 ret = psp_ta_load(psp, &psp->rap_context.context); 1905 if (!ret) { 1906 psp->rap_context.context.initialized = true; 1907 mutex_init(&psp->rap_context.mutex); 1908 } else 1909 return ret; 1910 1911 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1912 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1913 psp_rap_terminate(psp); 1914 /* free rap shared memory */ 1915 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1916 1917 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1918 ret, status); 1919 1920 return ret; 1921 } 1922 1923 return 0; 1924 } 1925 1926 static int psp_rap_terminate(struct psp_context *psp) 1927 { 1928 int ret; 1929 1930 if (!psp->rap_context.context.initialized) 1931 return 0; 1932 1933 ret = psp_ta_unload(psp, &psp->rap_context.context); 1934 1935 psp->rap_context.context.initialized = false; 1936 1937 return ret; 1938 } 1939 1940 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1941 { 1942 struct ta_rap_shared_memory *rap_cmd; 1943 int ret = 0; 1944 1945 if (!psp->rap_context.context.initialized) 1946 return 0; 1947 1948 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1949 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1950 return -EINVAL; 1951 1952 mutex_lock(&psp->rap_context.mutex); 1953 1954 rap_cmd = (struct ta_rap_shared_memory *) 1955 psp->rap_context.context.mem_context.shared_buf; 1956 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1957 1958 rap_cmd->cmd_id = ta_cmd_id; 1959 rap_cmd->validation_method_id = METHOD_A; 1960 1961 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1962 if (ret) 1963 goto out_unlock; 1964 1965 if (status) 1966 *status = rap_cmd->rap_status; 1967 1968 out_unlock: 1969 mutex_unlock(&psp->rap_context.mutex); 1970 1971 return ret; 1972 } 1973 // RAP end 1974 1975 /* securedisplay start */ 1976 static int psp_securedisplay_initialize(struct psp_context *psp) 1977 { 1978 int ret; 1979 struct ta_securedisplay_cmd *securedisplay_cmd; 1980 1981 /* 1982 * TODO: bypass the initialize in sriov for now 1983 */ 1984 if (amdgpu_sriov_vf(psp->adev)) 1985 return 0; 1986 1987 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1988 !psp->securedisplay_context.context.bin_desc.start_addr) { 1989 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1990 return 0; 1991 } 1992 1993 psp->securedisplay_context.context.mem_context.shared_mem_size = 1994 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1995 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1996 1997 if (!psp->securedisplay_context.context.initialized) { 1998 ret = psp_ta_init_shared_buf(psp, 1999 &psp->securedisplay_context.context.mem_context); 2000 if (ret) 2001 return ret; 2002 } 2003 2004 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2005 if (!ret) { 2006 psp->securedisplay_context.context.initialized = true; 2007 mutex_init(&psp->securedisplay_context.mutex); 2008 } else 2009 return ret; 2010 2011 mutex_lock(&psp->securedisplay_context.mutex); 2012 2013 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2014 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2015 2016 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2017 2018 mutex_unlock(&psp->securedisplay_context.mutex); 2019 2020 if (ret) { 2021 psp_securedisplay_terminate(psp); 2022 /* free securedisplay shared memory */ 2023 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2024 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2025 return -EINVAL; 2026 } 2027 2028 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2029 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2030 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2031 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2032 /* don't try again */ 2033 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int psp_securedisplay_terminate(struct psp_context *psp) 2040 { 2041 int ret; 2042 2043 /* 2044 * TODO:bypass the terminate in sriov for now 2045 */ 2046 if (amdgpu_sriov_vf(psp->adev)) 2047 return 0; 2048 2049 if (!psp->securedisplay_context.context.initialized) 2050 return 0; 2051 2052 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2053 2054 psp->securedisplay_context.context.initialized = false; 2055 2056 return ret; 2057 } 2058 2059 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2060 { 2061 int ret; 2062 2063 if (!psp->securedisplay_context.context.initialized) 2064 return -EINVAL; 2065 2066 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2067 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2068 return -EINVAL; 2069 2070 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2071 2072 return ret; 2073 } 2074 /* SECUREDISPLAY end */ 2075 2076 static int psp_hw_start(struct psp_context *psp) 2077 { 2078 struct amdgpu_device *adev = psp->adev; 2079 int ret; 2080 2081 if (!amdgpu_sriov_vf(adev)) { 2082 if ((is_psp_fw_valid(psp->kdb)) && 2083 (psp->funcs->bootloader_load_kdb != NULL)) { 2084 ret = psp_bootloader_load_kdb(psp); 2085 if (ret) { 2086 DRM_ERROR("PSP load kdb failed!\n"); 2087 return ret; 2088 } 2089 } 2090 2091 if ((is_psp_fw_valid(psp->spl)) && 2092 (psp->funcs->bootloader_load_spl != NULL)) { 2093 ret = psp_bootloader_load_spl(psp); 2094 if (ret) { 2095 DRM_ERROR("PSP load spl failed!\n"); 2096 return ret; 2097 } 2098 } 2099 2100 if ((is_psp_fw_valid(psp->sys)) && 2101 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2102 ret = psp_bootloader_load_sysdrv(psp); 2103 if (ret) { 2104 DRM_ERROR("PSP load sys drv failed!\n"); 2105 return ret; 2106 } 2107 } 2108 2109 if ((is_psp_fw_valid(psp->soc_drv)) && 2110 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2111 ret = psp_bootloader_load_soc_drv(psp); 2112 if (ret) { 2113 DRM_ERROR("PSP load soc drv failed!\n"); 2114 return ret; 2115 } 2116 } 2117 2118 if ((is_psp_fw_valid(psp->intf_drv)) && 2119 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2120 ret = psp_bootloader_load_intf_drv(psp); 2121 if (ret) { 2122 DRM_ERROR("PSP load intf drv failed!\n"); 2123 return ret; 2124 } 2125 } 2126 2127 if ((is_psp_fw_valid(psp->dbg_drv)) && 2128 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2129 ret = psp_bootloader_load_dbg_drv(psp); 2130 if (ret) { 2131 DRM_ERROR("PSP load dbg drv failed!\n"); 2132 return ret; 2133 } 2134 } 2135 2136 if ((is_psp_fw_valid(psp->ras_drv)) && 2137 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2138 ret = psp_bootloader_load_ras_drv(psp); 2139 if (ret) { 2140 DRM_ERROR("PSP load ras_drv failed!\n"); 2141 return ret; 2142 } 2143 } 2144 2145 if ((is_psp_fw_valid(psp->sos)) && 2146 (psp->funcs->bootloader_load_sos != NULL)) { 2147 ret = psp_bootloader_load_sos(psp); 2148 if (ret) { 2149 DRM_ERROR("PSP load sos failed!\n"); 2150 return ret; 2151 } 2152 } 2153 } 2154 2155 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2156 if (ret) { 2157 DRM_ERROR("PSP create ring failed!\n"); 2158 return ret; 2159 } 2160 2161 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2162 goto skip_pin_bo; 2163 2164 if (!psp_boottime_tmr(psp)) { 2165 ret = psp_tmr_init(psp); 2166 if (ret) { 2167 DRM_ERROR("PSP tmr init failed!\n"); 2168 return ret; 2169 } 2170 } 2171 2172 skip_pin_bo: 2173 /* 2174 * For ASICs with DF Cstate management centralized 2175 * to PMFW, TMR setup should be performed after PMFW 2176 * loaded and before other non-psp firmware loaded. 2177 */ 2178 if (psp->pmfw_centralized_cstate_management) { 2179 ret = psp_load_smu_fw(psp); 2180 if (ret) 2181 return ret; 2182 } 2183 2184 ret = psp_tmr_load(psp); 2185 if (ret) { 2186 DRM_ERROR("PSP load tmr failed!\n"); 2187 return ret; 2188 } 2189 2190 return 0; 2191 } 2192 2193 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2194 enum psp_gfx_fw_type *type) 2195 { 2196 switch (ucode->ucode_id) { 2197 case AMDGPU_UCODE_ID_CAP: 2198 *type = GFX_FW_TYPE_CAP; 2199 break; 2200 case AMDGPU_UCODE_ID_SDMA0: 2201 *type = GFX_FW_TYPE_SDMA0; 2202 break; 2203 case AMDGPU_UCODE_ID_SDMA1: 2204 *type = GFX_FW_TYPE_SDMA1; 2205 break; 2206 case AMDGPU_UCODE_ID_SDMA2: 2207 *type = GFX_FW_TYPE_SDMA2; 2208 break; 2209 case AMDGPU_UCODE_ID_SDMA3: 2210 *type = GFX_FW_TYPE_SDMA3; 2211 break; 2212 case AMDGPU_UCODE_ID_SDMA4: 2213 *type = GFX_FW_TYPE_SDMA4; 2214 break; 2215 case AMDGPU_UCODE_ID_SDMA5: 2216 *type = GFX_FW_TYPE_SDMA5; 2217 break; 2218 case AMDGPU_UCODE_ID_SDMA6: 2219 *type = GFX_FW_TYPE_SDMA6; 2220 break; 2221 case AMDGPU_UCODE_ID_SDMA7: 2222 *type = GFX_FW_TYPE_SDMA7; 2223 break; 2224 case AMDGPU_UCODE_ID_CP_MES: 2225 *type = GFX_FW_TYPE_CP_MES; 2226 break; 2227 case AMDGPU_UCODE_ID_CP_MES_DATA: 2228 *type = GFX_FW_TYPE_MES_STACK; 2229 break; 2230 case AMDGPU_UCODE_ID_CP_MES1: 2231 *type = GFX_FW_TYPE_CP_MES_KIQ; 2232 break; 2233 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2234 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2235 break; 2236 case AMDGPU_UCODE_ID_CP_CE: 2237 *type = GFX_FW_TYPE_CP_CE; 2238 break; 2239 case AMDGPU_UCODE_ID_CP_PFP: 2240 *type = GFX_FW_TYPE_CP_PFP; 2241 break; 2242 case AMDGPU_UCODE_ID_CP_ME: 2243 *type = GFX_FW_TYPE_CP_ME; 2244 break; 2245 case AMDGPU_UCODE_ID_CP_MEC1: 2246 *type = GFX_FW_TYPE_CP_MEC; 2247 break; 2248 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2249 *type = GFX_FW_TYPE_CP_MEC_ME1; 2250 break; 2251 case AMDGPU_UCODE_ID_CP_MEC2: 2252 *type = GFX_FW_TYPE_CP_MEC; 2253 break; 2254 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2255 *type = GFX_FW_TYPE_CP_MEC_ME2; 2256 break; 2257 case AMDGPU_UCODE_ID_RLC_P: 2258 *type = GFX_FW_TYPE_RLC_P; 2259 break; 2260 case AMDGPU_UCODE_ID_RLC_V: 2261 *type = GFX_FW_TYPE_RLC_V; 2262 break; 2263 case AMDGPU_UCODE_ID_RLC_G: 2264 *type = GFX_FW_TYPE_RLC_G; 2265 break; 2266 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2267 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2268 break; 2269 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2270 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2271 break; 2272 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2273 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2274 break; 2275 case AMDGPU_UCODE_ID_RLC_IRAM: 2276 *type = GFX_FW_TYPE_RLC_IRAM; 2277 break; 2278 case AMDGPU_UCODE_ID_RLC_DRAM: 2279 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2280 break; 2281 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2282 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2283 break; 2284 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2285 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2286 break; 2287 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2288 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2289 break; 2290 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2291 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2292 break; 2293 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2294 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2295 break; 2296 case AMDGPU_UCODE_ID_SMC: 2297 *type = GFX_FW_TYPE_SMU; 2298 break; 2299 case AMDGPU_UCODE_ID_PPTABLE: 2300 *type = GFX_FW_TYPE_PPTABLE; 2301 break; 2302 case AMDGPU_UCODE_ID_UVD: 2303 *type = GFX_FW_TYPE_UVD; 2304 break; 2305 case AMDGPU_UCODE_ID_UVD1: 2306 *type = GFX_FW_TYPE_UVD1; 2307 break; 2308 case AMDGPU_UCODE_ID_VCE: 2309 *type = GFX_FW_TYPE_VCE; 2310 break; 2311 case AMDGPU_UCODE_ID_VCN: 2312 *type = GFX_FW_TYPE_VCN; 2313 break; 2314 case AMDGPU_UCODE_ID_VCN1: 2315 *type = GFX_FW_TYPE_VCN1; 2316 break; 2317 case AMDGPU_UCODE_ID_DMCU_ERAM: 2318 *type = GFX_FW_TYPE_DMCU_ERAM; 2319 break; 2320 case AMDGPU_UCODE_ID_DMCU_INTV: 2321 *type = GFX_FW_TYPE_DMCU_ISR; 2322 break; 2323 case AMDGPU_UCODE_ID_VCN0_RAM: 2324 *type = GFX_FW_TYPE_VCN0_RAM; 2325 break; 2326 case AMDGPU_UCODE_ID_VCN1_RAM: 2327 *type = GFX_FW_TYPE_VCN1_RAM; 2328 break; 2329 case AMDGPU_UCODE_ID_DMCUB: 2330 *type = GFX_FW_TYPE_DMUB; 2331 break; 2332 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2333 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2334 break; 2335 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2336 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2337 break; 2338 case AMDGPU_UCODE_ID_IMU_I: 2339 *type = GFX_FW_TYPE_IMU_I; 2340 break; 2341 case AMDGPU_UCODE_ID_IMU_D: 2342 *type = GFX_FW_TYPE_IMU_D; 2343 break; 2344 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2345 *type = GFX_FW_TYPE_RS64_PFP; 2346 break; 2347 case AMDGPU_UCODE_ID_CP_RS64_ME: 2348 *type = GFX_FW_TYPE_RS64_ME; 2349 break; 2350 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2351 *type = GFX_FW_TYPE_RS64_MEC; 2352 break; 2353 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2354 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2355 break; 2356 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2357 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2358 break; 2359 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2360 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2361 break; 2362 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2363 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2364 break; 2365 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2366 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2367 break; 2368 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2369 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2370 break; 2371 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2372 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2373 break; 2374 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2375 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2376 break; 2377 case AMDGPU_UCODE_ID_MAXIMUM: 2378 default: 2379 return -EINVAL; 2380 } 2381 2382 return 0; 2383 } 2384 2385 static void psp_print_fw_hdr(struct psp_context *psp, 2386 struct amdgpu_firmware_info *ucode) 2387 { 2388 struct amdgpu_device *adev = psp->adev; 2389 struct common_firmware_header *hdr; 2390 2391 switch (ucode->ucode_id) { 2392 case AMDGPU_UCODE_ID_SDMA0: 2393 case AMDGPU_UCODE_ID_SDMA1: 2394 case AMDGPU_UCODE_ID_SDMA2: 2395 case AMDGPU_UCODE_ID_SDMA3: 2396 case AMDGPU_UCODE_ID_SDMA4: 2397 case AMDGPU_UCODE_ID_SDMA5: 2398 case AMDGPU_UCODE_ID_SDMA6: 2399 case AMDGPU_UCODE_ID_SDMA7: 2400 hdr = (struct common_firmware_header *) 2401 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2402 amdgpu_ucode_print_sdma_hdr(hdr); 2403 break; 2404 case AMDGPU_UCODE_ID_CP_CE: 2405 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2406 amdgpu_ucode_print_gfx_hdr(hdr); 2407 break; 2408 case AMDGPU_UCODE_ID_CP_PFP: 2409 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2410 amdgpu_ucode_print_gfx_hdr(hdr); 2411 break; 2412 case AMDGPU_UCODE_ID_CP_ME: 2413 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2414 amdgpu_ucode_print_gfx_hdr(hdr); 2415 break; 2416 case AMDGPU_UCODE_ID_CP_MEC1: 2417 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2418 amdgpu_ucode_print_gfx_hdr(hdr); 2419 break; 2420 case AMDGPU_UCODE_ID_RLC_G: 2421 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2422 amdgpu_ucode_print_rlc_hdr(hdr); 2423 break; 2424 case AMDGPU_UCODE_ID_SMC: 2425 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2426 amdgpu_ucode_print_smc_hdr(hdr); 2427 break; 2428 default: 2429 break; 2430 } 2431 } 2432 2433 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2434 struct psp_gfx_cmd_resp *cmd) 2435 { 2436 int ret; 2437 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2438 2439 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2440 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2441 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2442 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2443 2444 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2445 if (ret) 2446 DRM_ERROR("Unknown firmware type\n"); 2447 2448 return ret; 2449 } 2450 2451 int psp_execute_ip_fw_load(struct psp_context *psp, 2452 struct amdgpu_firmware_info *ucode) 2453 { 2454 int ret = 0; 2455 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2456 2457 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2458 if (!ret) { 2459 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2460 psp->fence_buf_mc_addr); 2461 } 2462 2463 release_psp_cmd_buf(psp); 2464 2465 return ret; 2466 } 2467 2468 static int psp_load_smu_fw(struct psp_context *psp) 2469 { 2470 int ret; 2471 struct amdgpu_device *adev = psp->adev; 2472 struct amdgpu_firmware_info *ucode = 2473 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2474 struct amdgpu_ras *ras = psp->ras_context.ras; 2475 2476 /* 2477 * Skip SMU FW reloading in case of using BACO for runpm only, 2478 * as SMU is always alive. 2479 */ 2480 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2481 return 0; 2482 2483 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2484 return 0; 2485 2486 if ((amdgpu_in_reset(adev) && 2487 ras && adev->ras_enabled && 2488 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2489 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2490 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2491 if (ret) 2492 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2493 } 2494 2495 ret = psp_execute_ip_fw_load(psp, ucode); 2496 2497 if (ret) 2498 DRM_ERROR("PSP load smu failed!\n"); 2499 2500 return ret; 2501 } 2502 2503 static bool fw_load_skip_check(struct psp_context *psp, 2504 struct amdgpu_firmware_info *ucode) 2505 { 2506 if (!ucode->fw || !ucode->ucode_size) 2507 return true; 2508 2509 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2510 (psp_smu_reload_quirk(psp) || 2511 psp->autoload_supported || 2512 psp->pmfw_centralized_cstate_management)) 2513 return true; 2514 2515 if (amdgpu_sriov_vf(psp->adev) && 2516 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2517 return true; 2518 2519 if (psp->autoload_supported && 2520 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2521 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2522 /* skip mec JT when autoload is enabled */ 2523 return true; 2524 2525 return false; 2526 } 2527 2528 int psp_load_fw_list(struct psp_context *psp, 2529 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2530 { 2531 int ret = 0, i; 2532 struct amdgpu_firmware_info *ucode; 2533 2534 for (i = 0; i < ucode_count; ++i) { 2535 ucode = ucode_list[i]; 2536 psp_print_fw_hdr(psp, ucode); 2537 ret = psp_execute_ip_fw_load(psp, ucode); 2538 if (ret) 2539 return ret; 2540 } 2541 return ret; 2542 } 2543 2544 static int psp_load_non_psp_fw(struct psp_context *psp) 2545 { 2546 int i, ret; 2547 struct amdgpu_firmware_info *ucode; 2548 struct amdgpu_device *adev = psp->adev; 2549 2550 if (psp->autoload_supported && 2551 !psp->pmfw_centralized_cstate_management) { 2552 ret = psp_load_smu_fw(psp); 2553 if (ret) 2554 return ret; 2555 } 2556 2557 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2558 ucode = &adev->firmware.ucode[i]; 2559 2560 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2561 !fw_load_skip_check(psp, ucode)) { 2562 ret = psp_load_smu_fw(psp); 2563 if (ret) 2564 return ret; 2565 continue; 2566 } 2567 2568 if (fw_load_skip_check(psp, ucode)) 2569 continue; 2570 2571 if (psp->autoload_supported && 2572 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2573 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2574 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2575 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2576 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2577 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2578 /* PSP only receive one SDMA fw for sienna_cichlid, 2579 * as all four sdma fw are same */ 2580 continue; 2581 2582 psp_print_fw_hdr(psp, ucode); 2583 2584 ret = psp_execute_ip_fw_load(psp, ucode); 2585 if (ret) 2586 return ret; 2587 2588 /* Start rlc autoload after psp recieved all the gfx firmware */ 2589 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2590 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2591 ret = psp_rlc_autoload_start(psp); 2592 if (ret) { 2593 DRM_ERROR("Failed to start rlc autoload\n"); 2594 return ret; 2595 } 2596 } 2597 } 2598 2599 return 0; 2600 } 2601 2602 static int psp_load_fw(struct amdgpu_device *adev) 2603 { 2604 int ret; 2605 struct psp_context *psp = &adev->psp; 2606 2607 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2608 /* should not destroy ring, only stop */ 2609 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2610 } else { 2611 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2612 2613 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2614 if (ret) { 2615 DRM_ERROR("PSP ring init failed!\n"); 2616 goto failed; 2617 } 2618 } 2619 2620 ret = psp_hw_start(psp); 2621 if (ret) 2622 goto failed; 2623 2624 ret = psp_load_non_psp_fw(psp); 2625 if (ret) 2626 goto failed1; 2627 2628 ret = psp_asd_initialize(psp); 2629 if (ret) { 2630 DRM_ERROR("PSP load asd failed!\n"); 2631 goto failed1; 2632 } 2633 2634 ret = psp_rl_load(adev); 2635 if (ret) { 2636 DRM_ERROR("PSP load RL failed!\n"); 2637 goto failed1; 2638 } 2639 2640 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2641 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2642 ret = psp_xgmi_initialize(psp, false, true); 2643 /* Warning the XGMI seesion initialize failure 2644 * Instead of stop driver initialization 2645 */ 2646 if (ret) 2647 dev_err(psp->adev->dev, 2648 "XGMI: Failed to initialize XGMI session\n"); 2649 } 2650 } 2651 2652 if (psp->ta_fw) { 2653 ret = psp_ras_initialize(psp); 2654 if (ret) 2655 dev_err(psp->adev->dev, 2656 "RAS: Failed to initialize RAS\n"); 2657 2658 ret = psp_hdcp_initialize(psp); 2659 if (ret) 2660 dev_err(psp->adev->dev, 2661 "HDCP: Failed to initialize HDCP\n"); 2662 2663 ret = psp_dtm_initialize(psp); 2664 if (ret) 2665 dev_err(psp->adev->dev, 2666 "DTM: Failed to initialize DTM\n"); 2667 2668 ret = psp_rap_initialize(psp); 2669 if (ret) 2670 dev_err(psp->adev->dev, 2671 "RAP: Failed to initialize RAP\n"); 2672 2673 ret = psp_securedisplay_initialize(psp); 2674 if (ret) 2675 dev_err(psp->adev->dev, 2676 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2677 } 2678 2679 return 0; 2680 2681 failed1: 2682 psp_free_shared_bufs(psp); 2683 failed: 2684 /* 2685 * all cleanup jobs (xgmi terminate, ras terminate, 2686 * ring destroy, cmd/fence/fw buffers destory, 2687 * psp->cmd destory) are delayed to psp_hw_fini 2688 */ 2689 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2690 return ret; 2691 } 2692 2693 static int psp_hw_init(void *handle) 2694 { 2695 int ret; 2696 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2697 2698 mutex_lock(&adev->firmware.mutex); 2699 /* 2700 * This sequence is just used on hw_init only once, no need on 2701 * resume. 2702 */ 2703 ret = amdgpu_ucode_init_bo(adev); 2704 if (ret) 2705 goto failed; 2706 2707 ret = psp_load_fw(adev); 2708 if (ret) { 2709 DRM_ERROR("PSP firmware loading failed\n"); 2710 goto failed; 2711 } 2712 2713 mutex_unlock(&adev->firmware.mutex); 2714 return 0; 2715 2716 failed: 2717 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2718 mutex_unlock(&adev->firmware.mutex); 2719 return -EINVAL; 2720 } 2721 2722 static int psp_hw_fini(void *handle) 2723 { 2724 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2725 struct psp_context *psp = &adev->psp; 2726 2727 if (psp->ta_fw) { 2728 psp_ras_terminate(psp); 2729 psp_securedisplay_terminate(psp); 2730 psp_rap_terminate(psp); 2731 psp_dtm_terminate(psp); 2732 psp_hdcp_terminate(psp); 2733 2734 if (adev->gmc.xgmi.num_physical_nodes > 1) 2735 psp_xgmi_terminate(psp); 2736 } 2737 2738 psp_asd_terminate(psp); 2739 psp_tmr_terminate(psp); 2740 2741 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2742 2743 return 0; 2744 } 2745 2746 static int psp_suspend(void *handle) 2747 { 2748 int ret = 0; 2749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2750 struct psp_context *psp = &adev->psp; 2751 2752 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2753 psp->xgmi_context.context.initialized) { 2754 ret = psp_xgmi_terminate(psp); 2755 if (ret) { 2756 DRM_ERROR("Failed to terminate xgmi ta\n"); 2757 goto out; 2758 } 2759 } 2760 2761 if (psp->ta_fw) { 2762 ret = psp_ras_terminate(psp); 2763 if (ret) { 2764 DRM_ERROR("Failed to terminate ras ta\n"); 2765 goto out; 2766 } 2767 ret = psp_hdcp_terminate(psp); 2768 if (ret) { 2769 DRM_ERROR("Failed to terminate hdcp ta\n"); 2770 goto out; 2771 } 2772 ret = psp_dtm_terminate(psp); 2773 if (ret) { 2774 DRM_ERROR("Failed to terminate dtm ta\n"); 2775 goto out; 2776 } 2777 ret = psp_rap_terminate(psp); 2778 if (ret) { 2779 DRM_ERROR("Failed to terminate rap ta\n"); 2780 goto out; 2781 } 2782 ret = psp_securedisplay_terminate(psp); 2783 if (ret) { 2784 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2785 goto out; 2786 } 2787 } 2788 2789 ret = psp_asd_terminate(psp); 2790 if (ret) { 2791 DRM_ERROR("Failed to terminate asd\n"); 2792 goto out; 2793 } 2794 2795 ret = psp_tmr_terminate(psp); 2796 if (ret) { 2797 DRM_ERROR("Failed to terminate tmr\n"); 2798 goto out; 2799 } 2800 2801 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2802 if (ret) 2803 DRM_ERROR("PSP ring stop failed\n"); 2804 2805 out: 2806 return ret; 2807 } 2808 2809 static int psp_resume(void *handle) 2810 { 2811 int ret; 2812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2813 struct psp_context *psp = &adev->psp; 2814 2815 DRM_INFO("PSP is resuming...\n"); 2816 2817 if (psp->mem_train_ctx.enable_mem_training) { 2818 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2819 if (ret) { 2820 DRM_ERROR("Failed to process memory training!\n"); 2821 return ret; 2822 } 2823 } 2824 2825 mutex_lock(&adev->firmware.mutex); 2826 2827 ret = psp_hw_start(psp); 2828 if (ret) 2829 goto failed; 2830 2831 ret = psp_load_non_psp_fw(psp); 2832 if (ret) 2833 goto failed; 2834 2835 ret = psp_asd_initialize(psp); 2836 if (ret) { 2837 DRM_ERROR("PSP load asd failed!\n"); 2838 goto failed; 2839 } 2840 2841 ret = psp_rl_load(adev); 2842 if (ret) { 2843 dev_err(adev->dev, "PSP load RL failed!\n"); 2844 goto failed; 2845 } 2846 2847 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2848 ret = psp_xgmi_initialize(psp, false, true); 2849 /* Warning the XGMI seesion initialize failure 2850 * Instead of stop driver initialization 2851 */ 2852 if (ret) 2853 dev_err(psp->adev->dev, 2854 "XGMI: Failed to initialize XGMI session\n"); 2855 } 2856 2857 if (psp->ta_fw) { 2858 ret = psp_ras_initialize(psp); 2859 if (ret) 2860 dev_err(psp->adev->dev, 2861 "RAS: Failed to initialize RAS\n"); 2862 2863 ret = psp_hdcp_initialize(psp); 2864 if (ret) 2865 dev_err(psp->adev->dev, 2866 "HDCP: Failed to initialize HDCP\n"); 2867 2868 ret = psp_dtm_initialize(psp); 2869 if (ret) 2870 dev_err(psp->adev->dev, 2871 "DTM: Failed to initialize DTM\n"); 2872 2873 ret = psp_rap_initialize(psp); 2874 if (ret) 2875 dev_err(psp->adev->dev, 2876 "RAP: Failed to initialize RAP\n"); 2877 2878 ret = psp_securedisplay_initialize(psp); 2879 if (ret) 2880 dev_err(psp->adev->dev, 2881 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2882 } 2883 2884 mutex_unlock(&adev->firmware.mutex); 2885 2886 return 0; 2887 2888 failed: 2889 DRM_ERROR("PSP resume failed\n"); 2890 mutex_unlock(&adev->firmware.mutex); 2891 return ret; 2892 } 2893 2894 int psp_gpu_reset(struct amdgpu_device *adev) 2895 { 2896 int ret; 2897 2898 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2899 return 0; 2900 2901 mutex_lock(&adev->psp.mutex); 2902 ret = psp_mode1_reset(&adev->psp); 2903 mutex_unlock(&adev->psp.mutex); 2904 2905 return ret; 2906 } 2907 2908 int psp_rlc_autoload_start(struct psp_context *psp) 2909 { 2910 int ret; 2911 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2912 2913 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2914 2915 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2916 psp->fence_buf_mc_addr); 2917 2918 release_psp_cmd_buf(psp); 2919 2920 return ret; 2921 } 2922 2923 int psp_ring_cmd_submit(struct psp_context *psp, 2924 uint64_t cmd_buf_mc_addr, 2925 uint64_t fence_mc_addr, 2926 int index) 2927 { 2928 unsigned int psp_write_ptr_reg = 0; 2929 struct psp_gfx_rb_frame *write_frame; 2930 struct psp_ring *ring = &psp->km_ring; 2931 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2932 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2933 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2934 struct amdgpu_device *adev = psp->adev; 2935 uint32_t ring_size_dw = ring->ring_size / 4; 2936 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2937 2938 /* KM (GPCOM) prepare write pointer */ 2939 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2940 2941 /* Update KM RB frame pointer to new frame */ 2942 /* write_frame ptr increments by size of rb_frame in bytes */ 2943 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2944 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2945 write_frame = ring_buffer_start; 2946 else 2947 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2948 /* Check invalid write_frame ptr address */ 2949 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2950 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2951 ring_buffer_start, ring_buffer_end, write_frame); 2952 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2953 return -EINVAL; 2954 } 2955 2956 /* Initialize KM RB frame */ 2957 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2958 2959 /* Update KM RB frame */ 2960 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2961 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2962 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2963 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2964 write_frame->fence_value = index; 2965 amdgpu_device_flush_hdp(adev, NULL); 2966 2967 /* Update the write Pointer in DWORDs */ 2968 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2969 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2970 return 0; 2971 } 2972 2973 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 2974 { 2975 struct amdgpu_device *adev = psp->adev; 2976 char fw_name[PSP_FW_NAME_LEN]; 2977 const struct psp_firmware_header_v1_0 *asd_hdr; 2978 int err = 0; 2979 2980 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2981 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 2982 if (err) 2983 goto out; 2984 2985 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2986 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2987 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2988 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2989 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2990 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2991 return 0; 2992 out: 2993 amdgpu_ucode_release(&adev->psp.asd_fw); 2994 return err; 2995 } 2996 2997 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 2998 { 2999 struct amdgpu_device *adev = psp->adev; 3000 char fw_name[PSP_FW_NAME_LEN]; 3001 const struct psp_firmware_header_v1_0 *toc_hdr; 3002 int err = 0; 3003 3004 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3005 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3006 if (err) 3007 goto out; 3008 3009 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3010 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3011 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3012 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3013 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3014 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3015 return 0; 3016 out: 3017 amdgpu_ucode_release(&adev->psp.toc_fw); 3018 return err; 3019 } 3020 3021 static int parse_sos_bin_descriptor(struct psp_context *psp, 3022 const struct psp_fw_bin_desc *desc, 3023 const struct psp_firmware_header_v2_0 *sos_hdr) 3024 { 3025 uint8_t *ucode_start_addr = NULL; 3026 3027 if (!psp || !desc || !sos_hdr) 3028 return -EINVAL; 3029 3030 ucode_start_addr = (uint8_t *)sos_hdr + 3031 le32_to_cpu(desc->offset_bytes) + 3032 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3033 3034 switch (desc->fw_type) { 3035 case PSP_FW_TYPE_PSP_SOS: 3036 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3037 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3038 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3039 psp->sos.start_addr = ucode_start_addr; 3040 break; 3041 case PSP_FW_TYPE_PSP_SYS_DRV: 3042 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3043 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3044 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3045 psp->sys.start_addr = ucode_start_addr; 3046 break; 3047 case PSP_FW_TYPE_PSP_KDB: 3048 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3049 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3050 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3051 psp->kdb.start_addr = ucode_start_addr; 3052 break; 3053 case PSP_FW_TYPE_PSP_TOC: 3054 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3055 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3056 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3057 psp->toc.start_addr = ucode_start_addr; 3058 break; 3059 case PSP_FW_TYPE_PSP_SPL: 3060 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3061 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3062 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3063 psp->spl.start_addr = ucode_start_addr; 3064 break; 3065 case PSP_FW_TYPE_PSP_RL: 3066 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3067 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3068 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3069 psp->rl.start_addr = ucode_start_addr; 3070 break; 3071 case PSP_FW_TYPE_PSP_SOC_DRV: 3072 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3073 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3074 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3075 psp->soc_drv.start_addr = ucode_start_addr; 3076 break; 3077 case PSP_FW_TYPE_PSP_INTF_DRV: 3078 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3079 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3080 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3081 psp->intf_drv.start_addr = ucode_start_addr; 3082 break; 3083 case PSP_FW_TYPE_PSP_DBG_DRV: 3084 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3085 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3086 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3087 psp->dbg_drv.start_addr = ucode_start_addr; 3088 break; 3089 case PSP_FW_TYPE_PSP_RAS_DRV: 3090 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3091 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3092 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3093 psp->ras_drv.start_addr = ucode_start_addr; 3094 break; 3095 default: 3096 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3097 break; 3098 } 3099 3100 return 0; 3101 } 3102 3103 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3104 { 3105 const struct psp_firmware_header_v1_0 *sos_hdr; 3106 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3107 uint8_t *ucode_array_start_addr; 3108 3109 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3110 ucode_array_start_addr = (uint8_t *)sos_hdr + 3111 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3112 3113 if (adev->gmc.xgmi.connected_to_cpu || 3114 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3115 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3116 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3117 3118 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3119 adev->psp.sys.start_addr = ucode_array_start_addr; 3120 3121 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3122 adev->psp.sos.start_addr = ucode_array_start_addr + 3123 le32_to_cpu(sos_hdr->sos.offset_bytes); 3124 } else { 3125 /* Load alternate PSP SOS FW */ 3126 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3127 3128 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3129 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3130 3131 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3132 adev->psp.sys.start_addr = ucode_array_start_addr + 3133 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3134 3135 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3136 adev->psp.sos.start_addr = ucode_array_start_addr + 3137 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3138 } 3139 3140 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3141 dev_warn(adev->dev, "PSP SOS FW not available"); 3142 return -EINVAL; 3143 } 3144 3145 return 0; 3146 } 3147 3148 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3149 { 3150 struct amdgpu_device *adev = psp->adev; 3151 char fw_name[PSP_FW_NAME_LEN]; 3152 const struct psp_firmware_header_v1_0 *sos_hdr; 3153 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3154 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3155 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3156 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3157 int err = 0; 3158 uint8_t *ucode_array_start_addr; 3159 int fw_index = 0; 3160 3161 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3162 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3163 if (err) 3164 goto out; 3165 3166 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3167 ucode_array_start_addr = (uint8_t *)sos_hdr + 3168 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3169 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3170 3171 switch (sos_hdr->header.header_version_major) { 3172 case 1: 3173 err = psp_init_sos_base_fw(adev); 3174 if (err) 3175 goto out; 3176 3177 if (sos_hdr->header.header_version_minor == 1) { 3178 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3179 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3180 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3181 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3182 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3183 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3184 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3185 } 3186 if (sos_hdr->header.header_version_minor == 2) { 3187 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3188 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3189 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3190 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3191 } 3192 if (sos_hdr->header.header_version_minor == 3) { 3193 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3194 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3195 adev->psp.toc.start_addr = ucode_array_start_addr + 3196 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3197 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3198 adev->psp.kdb.start_addr = ucode_array_start_addr + 3199 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3200 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3201 adev->psp.spl.start_addr = ucode_array_start_addr + 3202 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3203 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3204 adev->psp.rl.start_addr = ucode_array_start_addr + 3205 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3206 } 3207 break; 3208 case 2: 3209 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3210 3211 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3212 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3213 err = -EINVAL; 3214 goto out; 3215 } 3216 3217 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3218 err = parse_sos_bin_descriptor(psp, 3219 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3220 sos_hdr_v2_0); 3221 if (err) 3222 goto out; 3223 } 3224 break; 3225 default: 3226 dev_err(adev->dev, 3227 "unsupported psp sos firmware\n"); 3228 err = -EINVAL; 3229 goto out; 3230 } 3231 3232 return 0; 3233 out: 3234 amdgpu_ucode_release(&adev->psp.sos_fw); 3235 3236 return err; 3237 } 3238 3239 static int parse_ta_bin_descriptor(struct psp_context *psp, 3240 const struct psp_fw_bin_desc *desc, 3241 const struct ta_firmware_header_v2_0 *ta_hdr) 3242 { 3243 uint8_t *ucode_start_addr = NULL; 3244 3245 if (!psp || !desc || !ta_hdr) 3246 return -EINVAL; 3247 3248 ucode_start_addr = (uint8_t *)ta_hdr + 3249 le32_to_cpu(desc->offset_bytes) + 3250 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3251 3252 switch (desc->fw_type) { 3253 case TA_FW_TYPE_PSP_ASD: 3254 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3255 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3256 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3257 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3258 break; 3259 case TA_FW_TYPE_PSP_XGMI: 3260 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3261 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3262 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3263 break; 3264 case TA_FW_TYPE_PSP_RAS: 3265 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3266 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3267 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3268 break; 3269 case TA_FW_TYPE_PSP_HDCP: 3270 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3271 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3272 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3273 break; 3274 case TA_FW_TYPE_PSP_DTM: 3275 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3276 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3277 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3278 break; 3279 case TA_FW_TYPE_PSP_RAP: 3280 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3281 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3282 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3283 break; 3284 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3285 psp->securedisplay_context.context.bin_desc.fw_version = 3286 le32_to_cpu(desc->fw_version); 3287 psp->securedisplay_context.context.bin_desc.size_bytes = 3288 le32_to_cpu(desc->size_bytes); 3289 psp->securedisplay_context.context.bin_desc.start_addr = 3290 ucode_start_addr; 3291 break; 3292 default: 3293 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3294 break; 3295 } 3296 3297 return 0; 3298 } 3299 3300 static int parse_ta_v1_microcode(struct psp_context *psp) 3301 { 3302 const struct ta_firmware_header_v1_0 *ta_hdr; 3303 struct amdgpu_device *adev = psp->adev; 3304 3305 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3306 3307 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3308 return -EINVAL; 3309 3310 adev->psp.xgmi_context.context.bin_desc.fw_version = 3311 le32_to_cpu(ta_hdr->xgmi.fw_version); 3312 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3313 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3314 adev->psp.xgmi_context.context.bin_desc.start_addr = 3315 (uint8_t *)ta_hdr + 3316 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3317 3318 adev->psp.ras_context.context.bin_desc.fw_version = 3319 le32_to_cpu(ta_hdr->ras.fw_version); 3320 adev->psp.ras_context.context.bin_desc.size_bytes = 3321 le32_to_cpu(ta_hdr->ras.size_bytes); 3322 adev->psp.ras_context.context.bin_desc.start_addr = 3323 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3324 le32_to_cpu(ta_hdr->ras.offset_bytes); 3325 3326 adev->psp.hdcp_context.context.bin_desc.fw_version = 3327 le32_to_cpu(ta_hdr->hdcp.fw_version); 3328 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3329 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3330 adev->psp.hdcp_context.context.bin_desc.start_addr = 3331 (uint8_t *)ta_hdr + 3332 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3333 3334 adev->psp.dtm_context.context.bin_desc.fw_version = 3335 le32_to_cpu(ta_hdr->dtm.fw_version); 3336 adev->psp.dtm_context.context.bin_desc.size_bytes = 3337 le32_to_cpu(ta_hdr->dtm.size_bytes); 3338 adev->psp.dtm_context.context.bin_desc.start_addr = 3339 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3340 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3341 3342 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3343 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3344 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3345 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3346 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3347 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3348 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3349 3350 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3351 3352 return 0; 3353 } 3354 3355 static int parse_ta_v2_microcode(struct psp_context *psp) 3356 { 3357 const struct ta_firmware_header_v2_0 *ta_hdr; 3358 struct amdgpu_device *adev = psp->adev; 3359 int err = 0; 3360 int ta_index = 0; 3361 3362 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3363 3364 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3365 return -EINVAL; 3366 3367 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3368 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3369 return -EINVAL; 3370 } 3371 3372 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3373 err = parse_ta_bin_descriptor(psp, 3374 &ta_hdr->ta_fw_bin[ta_index], 3375 ta_hdr); 3376 if (err) 3377 return err; 3378 } 3379 3380 return 0; 3381 } 3382 3383 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3384 { 3385 const struct common_firmware_header *hdr; 3386 struct amdgpu_device *adev = psp->adev; 3387 char fw_name[PSP_FW_NAME_LEN]; 3388 int err; 3389 3390 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3391 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3392 if (err) 3393 return err; 3394 3395 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3396 switch (le16_to_cpu(hdr->header_version_major)) { 3397 case 1: 3398 err = parse_ta_v1_microcode(psp); 3399 break; 3400 case 2: 3401 err = parse_ta_v2_microcode(psp); 3402 break; 3403 default: 3404 dev_err(adev->dev, "unsupported TA header version\n"); 3405 err = -EINVAL; 3406 } 3407 3408 if (err) 3409 amdgpu_ucode_release(&adev->psp.ta_fw); 3410 3411 return err; 3412 } 3413 3414 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3415 { 3416 struct amdgpu_device *adev = psp->adev; 3417 char fw_name[PSP_FW_NAME_LEN]; 3418 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3419 struct amdgpu_firmware_info *info = NULL; 3420 int err = 0; 3421 3422 if (!amdgpu_sriov_vf(adev)) { 3423 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3424 return -EINVAL; 3425 } 3426 3427 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3428 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3429 if (err) { 3430 if (err == -ENODEV) { 3431 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3432 err = 0; 3433 goto out; 3434 } 3435 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3436 } 3437 3438 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3439 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3440 info->fw = adev->psp.cap_fw; 3441 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3442 adev->psp.cap_fw->data; 3443 adev->firmware.fw_size += ALIGN( 3444 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3445 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3446 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3447 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3448 3449 return 0; 3450 3451 out: 3452 amdgpu_ucode_release(&adev->psp.cap_fw); 3453 return err; 3454 } 3455 3456 static int psp_set_clockgating_state(void *handle, 3457 enum amd_clockgating_state state) 3458 { 3459 return 0; 3460 } 3461 3462 static int psp_set_powergating_state(void *handle, 3463 enum amd_powergating_state state) 3464 { 3465 return 0; 3466 } 3467 3468 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3469 struct device_attribute *attr, 3470 char *buf) 3471 { 3472 struct drm_device *ddev = dev_get_drvdata(dev); 3473 struct amdgpu_device *adev = drm_to_adev(ddev); 3474 uint32_t fw_ver; 3475 int ret; 3476 3477 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3478 DRM_INFO("PSP block is not ready yet."); 3479 return -EBUSY; 3480 } 3481 3482 mutex_lock(&adev->psp.mutex); 3483 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3484 mutex_unlock(&adev->psp.mutex); 3485 3486 if (ret) { 3487 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3488 return ret; 3489 } 3490 3491 return sysfs_emit(buf, "%x\n", fw_ver); 3492 } 3493 3494 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3495 struct device_attribute *attr, 3496 const char *buf, 3497 size_t count) 3498 { 3499 struct drm_device *ddev = dev_get_drvdata(dev); 3500 struct amdgpu_device *adev = drm_to_adev(ddev); 3501 int ret, idx; 3502 char fw_name[100]; 3503 const struct firmware *usbc_pd_fw; 3504 struct amdgpu_bo *fw_buf_bo = NULL; 3505 uint64_t fw_pri_mc_addr; 3506 void *fw_pri_cpu_addr; 3507 3508 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3509 DRM_INFO("PSP block is not ready yet."); 3510 return -EBUSY; 3511 } 3512 3513 if (!drm_dev_enter(ddev, &idx)) 3514 return -ENODEV; 3515 3516 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3517 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3518 if (ret) 3519 goto fail; 3520 3521 /* LFB address which is aligned to 1MB boundary per PSP request */ 3522 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3523 AMDGPU_GEM_DOMAIN_VRAM | 3524 AMDGPU_GEM_DOMAIN_GTT, 3525 &fw_buf_bo, &fw_pri_mc_addr, 3526 &fw_pri_cpu_addr); 3527 if (ret) 3528 goto rel_buf; 3529 3530 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3531 3532 mutex_lock(&adev->psp.mutex); 3533 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3534 mutex_unlock(&adev->psp.mutex); 3535 3536 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3537 3538 rel_buf: 3539 release_firmware(usbc_pd_fw); 3540 fail: 3541 if (ret) { 3542 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3543 count = ret; 3544 } 3545 3546 drm_dev_exit(idx); 3547 return count; 3548 } 3549 3550 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3551 { 3552 int idx; 3553 3554 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3555 return; 3556 3557 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3558 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3559 3560 drm_dev_exit(idx); 3561 } 3562 3563 /** 3564 * DOC: usbc_pd_fw 3565 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3566 * this file will trigger the update process. 3567 */ 3568 static DEVICE_ATTR(usbc_pd_fw, 0644, 3569 psp_usbc_pd_fw_sysfs_read, 3570 psp_usbc_pd_fw_sysfs_write); 3571 3572 int is_psp_fw_valid(struct psp_bin_desc bin) 3573 { 3574 return bin.size_bytes; 3575 } 3576 3577 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3578 struct bin_attribute *bin_attr, 3579 char *buffer, loff_t pos, size_t count) 3580 { 3581 struct device *dev = kobj_to_dev(kobj); 3582 struct drm_device *ddev = dev_get_drvdata(dev); 3583 struct amdgpu_device *adev = drm_to_adev(ddev); 3584 3585 adev->psp.vbflash_done = false; 3586 3587 /* Safeguard against memory drain */ 3588 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3589 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3590 kvfree(adev->psp.vbflash_tmp_buf); 3591 adev->psp.vbflash_tmp_buf = NULL; 3592 adev->psp.vbflash_image_size = 0; 3593 return -ENOMEM; 3594 } 3595 3596 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3597 if (!adev->psp.vbflash_tmp_buf) { 3598 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3599 if (!adev->psp.vbflash_tmp_buf) 3600 return -ENOMEM; 3601 } 3602 3603 mutex_lock(&adev->psp.mutex); 3604 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3605 adev->psp.vbflash_image_size += count; 3606 mutex_unlock(&adev->psp.mutex); 3607 3608 dev_dbg(adev->dev, "IFWI staged for update"); 3609 3610 return count; 3611 } 3612 3613 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3614 struct bin_attribute *bin_attr, char *buffer, 3615 loff_t pos, size_t count) 3616 { 3617 struct device *dev = kobj_to_dev(kobj); 3618 struct drm_device *ddev = dev_get_drvdata(dev); 3619 struct amdgpu_device *adev = drm_to_adev(ddev); 3620 struct amdgpu_bo *fw_buf_bo = NULL; 3621 uint64_t fw_pri_mc_addr; 3622 void *fw_pri_cpu_addr; 3623 int ret; 3624 3625 if (adev->psp.vbflash_image_size == 0) 3626 return -EINVAL; 3627 3628 dev_dbg(adev->dev, "PSP IFWI flash process initiated"); 3629 3630 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3631 AMDGPU_GPU_PAGE_SIZE, 3632 AMDGPU_GEM_DOMAIN_VRAM, 3633 &fw_buf_bo, 3634 &fw_pri_mc_addr, 3635 &fw_pri_cpu_addr); 3636 if (ret) 3637 goto rel_buf; 3638 3639 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3640 3641 mutex_lock(&adev->psp.mutex); 3642 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3643 mutex_unlock(&adev->psp.mutex); 3644 3645 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3646 3647 rel_buf: 3648 kvfree(adev->psp.vbflash_tmp_buf); 3649 adev->psp.vbflash_tmp_buf = NULL; 3650 adev->psp.vbflash_image_size = 0; 3651 3652 if (ret) { 3653 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret); 3654 return ret; 3655 } 3656 3657 dev_dbg(adev->dev, "PSP IFWI flash process done"); 3658 return 0; 3659 } 3660 3661 /** 3662 * DOC: psp_vbflash 3663 * Writing to this file will stage an IFWI for update. Reading from this file 3664 * will trigger the update process. 3665 */ 3666 static struct bin_attribute psp_vbflash_bin_attr = { 3667 .attr = {.name = "psp_vbflash", .mode = 0660}, 3668 .size = 0, 3669 .write = amdgpu_psp_vbflash_write, 3670 .read = amdgpu_psp_vbflash_read, 3671 }; 3672 3673 /** 3674 * DOC: psp_vbflash_status 3675 * The status of the flash process. 3676 * 0: IFWI flash not complete. 3677 * 1: IFWI flash complete. 3678 */ 3679 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3680 struct device_attribute *attr, 3681 char *buf) 3682 { 3683 struct drm_device *ddev = dev_get_drvdata(dev); 3684 struct amdgpu_device *adev = drm_to_adev(ddev); 3685 uint32_t vbflash_status; 3686 3687 vbflash_status = psp_vbflash_status(&adev->psp); 3688 if (!adev->psp.vbflash_done) 3689 vbflash_status = 0; 3690 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3691 vbflash_status = 1; 3692 3693 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3694 } 3695 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3696 3697 static struct bin_attribute *bin_flash_attrs[] = { 3698 &psp_vbflash_bin_attr, 3699 NULL 3700 }; 3701 3702 static struct attribute *flash_attrs[] = { 3703 &dev_attr_psp_vbflash_status.attr, 3704 &dev_attr_usbc_pd_fw.attr, 3705 NULL 3706 }; 3707 3708 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3709 { 3710 struct device *dev = kobj_to_dev(kobj); 3711 struct drm_device *ddev = dev_get_drvdata(dev); 3712 struct amdgpu_device *adev = drm_to_adev(ddev); 3713 3714 if (attr == &dev_attr_usbc_pd_fw.attr) 3715 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3716 3717 return adev->psp.sup_ifwi_up ? 0440 : 0; 3718 } 3719 3720 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3721 struct bin_attribute *attr, 3722 int idx) 3723 { 3724 struct device *dev = kobj_to_dev(kobj); 3725 struct drm_device *ddev = dev_get_drvdata(dev); 3726 struct amdgpu_device *adev = drm_to_adev(ddev); 3727 3728 return adev->psp.sup_ifwi_up ? 0660 : 0; 3729 } 3730 3731 const struct attribute_group amdgpu_flash_attr_group = { 3732 .attrs = flash_attrs, 3733 .bin_attrs = bin_flash_attrs, 3734 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3735 .is_visible = amdgpu_flash_attr_is_visible, 3736 }; 3737 3738 const struct amd_ip_funcs psp_ip_funcs = { 3739 .name = "psp", 3740 .early_init = psp_early_init, 3741 .late_init = NULL, 3742 .sw_init = psp_sw_init, 3743 .sw_fini = psp_sw_fini, 3744 .hw_init = psp_hw_init, 3745 .hw_fini = psp_hw_fini, 3746 .suspend = psp_suspend, 3747 .resume = psp_resume, 3748 .is_idle = NULL, 3749 .check_soft_reset = NULL, 3750 .wait_for_idle = NULL, 3751 .soft_reset = NULL, 3752 .set_clockgating_state = psp_set_clockgating_state, 3753 .set_powergating_state = psp_set_powergating_state, 3754 }; 3755 3756 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3757 .type = AMD_IP_BLOCK_TYPE_PSP, 3758 .major = 3, 3759 .minor = 1, 3760 .rev = 0, 3761 .funcs = &psp_ip_funcs, 3762 }; 3763 3764 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3765 .type = AMD_IP_BLOCK_TYPE_PSP, 3766 .major = 10, 3767 .minor = 0, 3768 .rev = 0, 3769 .funcs = &psp_ip_funcs, 3770 }; 3771 3772 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3773 .type = AMD_IP_BLOCK_TYPE_PSP, 3774 .major = 11, 3775 .minor = 0, 3776 .rev = 0, 3777 .funcs = &psp_ip_funcs, 3778 }; 3779 3780 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3781 .type = AMD_IP_BLOCK_TYPE_PSP, 3782 .major = 11, 3783 .minor = 0, 3784 .rev = 8, 3785 .funcs = &psp_ip_funcs, 3786 }; 3787 3788 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3789 .type = AMD_IP_BLOCK_TYPE_PSP, 3790 .major = 12, 3791 .minor = 0, 3792 .rev = 0, 3793 .funcs = &psp_ip_funcs, 3794 }; 3795 3796 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3797 .type = AMD_IP_BLOCK_TYPE_PSP, 3798 .major = 13, 3799 .minor = 0, 3800 .rev = 0, 3801 .funcs = &psp_ip_funcs, 3802 }; 3803 3804 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3805 .type = AMD_IP_BLOCK_TYPE_PSP, 3806 .major = 13, 3807 .minor = 0, 3808 .rev = 4, 3809 .funcs = &psp_ip_funcs, 3810 }; 3811