1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 50 static int psp_ta_load(struct psp_context *psp, struct ta_context *context); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 2): 88 psp->pmfw_centralized_cstate_management = true; 89 break; 90 default: 91 psp->pmfw_centralized_cstate_management = false; 92 break; 93 } 94 } 95 96 static int psp_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 struct psp_context *psp = &adev->psp; 100 101 switch (adev->ip_versions[MP0_HWIP][0]) { 102 case IP_VERSION(9, 0, 0): 103 psp_v3_1_set_psp_funcs(psp); 104 psp->autoload_supported = false; 105 break; 106 case IP_VERSION(10, 0, 0): 107 case IP_VERSION(10, 0, 1): 108 psp_v10_0_set_psp_funcs(psp); 109 psp->autoload_supported = false; 110 break; 111 case IP_VERSION(11, 0, 2): 112 case IP_VERSION(11, 0, 4): 113 psp_v11_0_set_psp_funcs(psp); 114 psp->autoload_supported = false; 115 break; 116 case IP_VERSION(11, 0, 0): 117 case IP_VERSION(11, 0, 5): 118 case IP_VERSION(11, 0, 9): 119 case IP_VERSION(11, 0, 7): 120 case IP_VERSION(11, 0, 11): 121 case IP_VERSION(11, 5, 0): 122 case IP_VERSION(11, 0, 12): 123 case IP_VERSION(11, 0, 13): 124 psp_v11_0_set_psp_funcs(psp); 125 psp->autoload_supported = true; 126 break; 127 case IP_VERSION(11, 0, 3): 128 case IP_VERSION(12, 0, 1): 129 psp_v12_0_set_psp_funcs(psp); 130 break; 131 case IP_VERSION(13, 0, 2): 132 psp_v13_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 1): 135 case IP_VERSION(13, 0, 3): 136 case IP_VERSION(13, 0, 8): 137 psp_v13_0_set_psp_funcs(psp); 138 psp->autoload_supported = true; 139 break; 140 case IP_VERSION(11, 0, 8): 141 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 142 psp_v11_0_8_set_psp_funcs(psp); 143 psp->autoload_supported = false; 144 } 145 break; 146 default: 147 return -EINVAL; 148 } 149 150 psp->adev = adev; 151 152 psp_check_pmfw_centralized_cstate_management(psp); 153 154 return 0; 155 } 156 157 static void psp_memory_training_fini(struct psp_context *psp) 158 { 159 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 160 161 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 162 kfree(ctx->sys_cache); 163 ctx->sys_cache = NULL; 164 } 165 166 static int psp_memory_training_init(struct psp_context *psp) 167 { 168 int ret; 169 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 170 171 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 172 DRM_DEBUG("memory training is not supported!\n"); 173 return 0; 174 } 175 176 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 177 if (ctx->sys_cache == NULL) { 178 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 179 ret = -ENOMEM; 180 goto Err_out; 181 } 182 183 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 184 ctx->train_data_size, 185 ctx->p2c_train_data_offset, 186 ctx->c2p_train_data_offset); 187 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 188 return 0; 189 190 Err_out: 191 psp_memory_training_fini(psp); 192 return ret; 193 } 194 195 /* 196 * Helper funciton to query psp runtime database entry 197 * 198 * @adev: amdgpu_device pointer 199 * @entry_type: the type of psp runtime database entry 200 * @db_entry: runtime database entry pointer 201 * 202 * Return false if runtime database doesn't exit or entry is invalid 203 * or true if the specific database entry is found, and copy to @db_entry 204 */ 205 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 206 enum psp_runtime_entry_type entry_type, 207 void *db_entry) 208 { 209 uint64_t db_header_pos, db_dir_pos; 210 struct psp_runtime_data_header db_header = {0}; 211 struct psp_runtime_data_directory db_dir = {0}; 212 bool ret = false; 213 int i; 214 215 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 216 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 217 218 /* read runtime db header from vram */ 219 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 220 sizeof(struct psp_runtime_data_header), false); 221 222 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 223 /* runtime db doesn't exist, exit */ 224 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 225 return false; 226 } 227 228 /* read runtime database entry from vram */ 229 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 230 sizeof(struct psp_runtime_data_directory), false); 231 232 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 233 /* invalid db entry count, exit */ 234 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 235 return false; 236 } 237 238 /* look up for requested entry type */ 239 for (i = 0; i < db_dir.entry_count && !ret; i++) { 240 if (db_dir.entry_list[i].entry_type == entry_type) { 241 switch (entry_type) { 242 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 243 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 244 /* invalid db entry size */ 245 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 246 return false; 247 } 248 /* read runtime database entry */ 249 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 250 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 251 ret = true; 252 break; 253 default: 254 ret = false; 255 break; 256 } 257 } 258 } 259 260 return ret; 261 } 262 263 static int psp_init_sriov_microcode(struct psp_context *psp) 264 { 265 struct amdgpu_device *adev = psp->adev; 266 int ret = 0; 267 268 switch (adev->ip_versions[MP0_HWIP][0]) { 269 case IP_VERSION(9, 0, 0): 270 ret = psp_init_cap_microcode(psp, "vega10"); 271 break; 272 case IP_VERSION(11, 0, 9): 273 ret = psp_init_cap_microcode(psp, "navi12"); 274 break; 275 case IP_VERSION(11, 0, 7): 276 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 277 break; 278 case IP_VERSION(13, 0, 2): 279 ret = psp_init_ta_microcode(psp, "aldebaran"); 280 break; 281 default: 282 BUG(); 283 break; 284 } 285 286 return ret; 287 } 288 289 static int psp_sw_init(void *handle) 290 { 291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 292 struct psp_context *psp = &adev->psp; 293 int ret; 294 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 295 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 296 297 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 298 if (!psp->cmd) { 299 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 300 ret = -ENOMEM; 301 } 302 303 if (amdgpu_sriov_vf(adev)) 304 ret = psp_init_sriov_microcode(psp); 305 else 306 ret = psp_init_microcode(psp); 307 if (ret) { 308 DRM_ERROR("Failed to load psp firmware!\n"); 309 return ret; 310 } 311 312 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 313 if (psp_get_runtime_db_entry(adev, 314 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 315 &boot_cfg_entry)) { 316 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 317 if ((psp->boot_cfg_bitmask) & 318 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 319 /* If psp runtime database exists, then 320 * only enable two stage memory training 321 * when TWO_STAGE_DRAM_TRAINING bit is set 322 * in runtime database */ 323 mem_training_ctx->enable_mem_training = true; 324 } 325 326 } else { 327 /* If psp runtime database doesn't exist or 328 * is invalid, force enable two stage memory 329 * training */ 330 mem_training_ctx->enable_mem_training = true; 331 } 332 333 if (mem_training_ctx->enable_mem_training) { 334 ret = psp_memory_training_init(psp); 335 if (ret) { 336 DRM_ERROR("Failed to initialize memory training!\n"); 337 return ret; 338 } 339 340 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 341 if (ret) { 342 DRM_ERROR("Failed to process memory training!\n"); 343 return ret; 344 } 345 } 346 347 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 348 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 349 ret= psp_sysfs_init(adev); 350 if (ret) { 351 return ret; 352 } 353 } 354 355 return 0; 356 } 357 358 static int psp_sw_fini(void *handle) 359 { 360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 361 struct psp_context *psp = &adev->psp; 362 struct psp_gfx_cmd_resp *cmd = psp->cmd; 363 364 psp_memory_training_fini(psp); 365 if (psp->sos_fw) { 366 release_firmware(psp->sos_fw); 367 psp->sos_fw = NULL; 368 } 369 if (psp->asd_fw) { 370 release_firmware(psp->asd_fw); 371 psp->asd_fw = NULL; 372 } 373 if (psp->ta_fw) { 374 release_firmware(psp->ta_fw); 375 psp->ta_fw = NULL; 376 } 377 if (adev->psp.cap_fw) { 378 release_firmware(psp->cap_fw); 379 psp->cap_fw = NULL; 380 } 381 382 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 383 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 384 psp_sysfs_fini(adev); 385 386 kfree(cmd); 387 cmd = NULL; 388 389 return 0; 390 } 391 392 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 393 uint32_t reg_val, uint32_t mask, bool check_changed) 394 { 395 uint32_t val; 396 int i; 397 struct amdgpu_device *adev = psp->adev; 398 399 if (psp->adev->no_hw_access) 400 return 0; 401 402 for (i = 0; i < adev->usec_timeout; i++) { 403 val = RREG32(reg_index); 404 if (check_changed) { 405 if (val != reg_val) 406 return 0; 407 } else { 408 if ((val & mask) == reg_val) 409 return 0; 410 } 411 udelay(1); 412 } 413 414 return -ETIME; 415 } 416 417 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 418 { 419 switch (cmd_id) { 420 case GFX_CMD_ID_LOAD_TA: 421 return "LOAD_TA"; 422 case GFX_CMD_ID_UNLOAD_TA: 423 return "UNLOAD_TA"; 424 case GFX_CMD_ID_INVOKE_CMD: 425 return "INVOKE_CMD"; 426 case GFX_CMD_ID_LOAD_ASD: 427 return "LOAD_ASD"; 428 case GFX_CMD_ID_SETUP_TMR: 429 return "SETUP_TMR"; 430 case GFX_CMD_ID_LOAD_IP_FW: 431 return "LOAD_IP_FW"; 432 case GFX_CMD_ID_DESTROY_TMR: 433 return "DESTROY_TMR"; 434 case GFX_CMD_ID_SAVE_RESTORE: 435 return "SAVE_RESTORE_IP_FW"; 436 case GFX_CMD_ID_SETUP_VMR: 437 return "SETUP_VMR"; 438 case GFX_CMD_ID_DESTROY_VMR: 439 return "DESTROY_VMR"; 440 case GFX_CMD_ID_PROG_REG: 441 return "PROG_REG"; 442 case GFX_CMD_ID_GET_FW_ATTESTATION: 443 return "GET_FW_ATTESTATION"; 444 case GFX_CMD_ID_LOAD_TOC: 445 return "ID_LOAD_TOC"; 446 case GFX_CMD_ID_AUTOLOAD_RLC: 447 return "AUTOLOAD_RLC"; 448 case GFX_CMD_ID_BOOT_CFG: 449 return "BOOT_CFG"; 450 default: 451 return "UNKNOWN CMD"; 452 } 453 } 454 455 static int 456 psp_cmd_submit_buf(struct psp_context *psp, 457 struct amdgpu_firmware_info *ucode, 458 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 459 { 460 int ret; 461 int index, idx; 462 int timeout = 20000; 463 bool ras_intr = false; 464 bool skip_unsupport = false; 465 466 if (psp->adev->no_hw_access) 467 return 0; 468 469 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 470 return 0; 471 472 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 473 474 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 475 476 index = atomic_inc_return(&psp->fence_value); 477 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 478 if (ret) { 479 atomic_dec(&psp->fence_value); 480 goto exit; 481 } 482 483 amdgpu_device_invalidate_hdp(psp->adev, NULL); 484 while (*((unsigned int *)psp->fence_buf) != index) { 485 if (--timeout == 0) 486 break; 487 /* 488 * Shouldn't wait for timeout when err_event_athub occurs, 489 * because gpu reset thread triggered and lock resource should 490 * be released for psp resume sequence. 491 */ 492 ras_intr = amdgpu_ras_intr_triggered(); 493 if (ras_intr) 494 break; 495 usleep_range(10, 100); 496 amdgpu_device_invalidate_hdp(psp->adev, NULL); 497 } 498 499 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 500 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 501 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 502 503 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 504 505 /* In some cases, psp response status is not 0 even there is no 506 * problem while the command is submitted. Some version of PSP FW 507 * doesn't write 0 to that field. 508 * So here we would like to only print a warning instead of an error 509 * during psp initialization to avoid breaking hw_init and it doesn't 510 * return -EINVAL. 511 */ 512 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 513 if (ucode) 514 DRM_WARN("failed to load ucode %s(0x%X) ", 515 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 516 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 517 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 518 psp->cmd_buf_mem->resp.status); 519 /* If we load CAP FW, PSP must return 0 under SRIOV 520 * also return failure in case of timeout 521 */ 522 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 523 ret = -EINVAL; 524 goto exit; 525 } 526 } 527 528 if (ucode) { 529 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 530 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 531 } 532 533 exit: 534 drm_dev_exit(idx); 535 return ret; 536 } 537 538 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 539 { 540 struct psp_gfx_cmd_resp *cmd = psp->cmd; 541 542 mutex_lock(&psp->mutex); 543 544 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 545 546 return cmd; 547 } 548 549 static void release_psp_cmd_buf(struct psp_context *psp) 550 { 551 mutex_unlock(&psp->mutex); 552 } 553 554 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 555 struct psp_gfx_cmd_resp *cmd, 556 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 557 { 558 struct amdgpu_device *adev = psp->adev; 559 uint32_t size = amdgpu_bo_size(tmr_bo); 560 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 561 562 if (amdgpu_sriov_vf(psp->adev)) 563 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 564 else 565 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 566 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 567 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 568 cmd->cmd.cmd_setup_tmr.buf_size = size; 569 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 570 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 571 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 572 } 573 574 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 575 uint64_t pri_buf_mc, uint32_t size) 576 { 577 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 578 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 579 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 580 cmd->cmd.cmd_load_toc.toc_size = size; 581 } 582 583 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 584 static int psp_load_toc(struct psp_context *psp, 585 uint32_t *tmr_size) 586 { 587 int ret; 588 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 589 590 /* Copy toc to psp firmware private buffer */ 591 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 592 593 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 594 595 ret = psp_cmd_submit_buf(psp, NULL, cmd, 596 psp->fence_buf_mc_addr); 597 if (!ret) 598 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 599 600 release_psp_cmd_buf(psp); 601 602 return ret; 603 } 604 605 /* Set up Trusted Memory Region */ 606 static int psp_tmr_init(struct psp_context *psp) 607 { 608 int ret; 609 int tmr_size; 610 void *tmr_buf; 611 void **pptr; 612 613 /* 614 * According to HW engineer, they prefer the TMR address be "naturally 615 * aligned" , e.g. the start address be an integer divide of TMR size. 616 * 617 * Note: this memory need be reserved till the driver 618 * uninitializes. 619 */ 620 tmr_size = PSP_TMR_SIZE(psp->adev); 621 622 /* For ASICs support RLC autoload, psp will parse the toc 623 * and calculate the total size of TMR needed */ 624 if (!amdgpu_sriov_vf(psp->adev) && 625 psp->toc.start_addr && 626 psp->toc.size_bytes && 627 psp->fw_pri_buf) { 628 ret = psp_load_toc(psp, &tmr_size); 629 if (ret) { 630 DRM_ERROR("Failed to load toc\n"); 631 return ret; 632 } 633 } 634 635 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 636 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 637 AMDGPU_GEM_DOMAIN_VRAM, 638 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 639 640 return ret; 641 } 642 643 static bool psp_skip_tmr(struct psp_context *psp) 644 { 645 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 646 case IP_VERSION(11, 0, 9): 647 case IP_VERSION(11, 0, 7): 648 case IP_VERSION(13, 0, 2): 649 return true; 650 default: 651 return false; 652 } 653 } 654 655 static int psp_tmr_load(struct psp_context *psp) 656 { 657 int ret; 658 struct psp_gfx_cmd_resp *cmd; 659 660 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 661 * Already set up by host driver. 662 */ 663 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 664 return 0; 665 666 cmd = acquire_psp_cmd_buf(psp); 667 668 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 669 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 670 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 671 672 ret = psp_cmd_submit_buf(psp, NULL, cmd, 673 psp->fence_buf_mc_addr); 674 675 release_psp_cmd_buf(psp); 676 677 return ret; 678 } 679 680 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 681 struct psp_gfx_cmd_resp *cmd) 682 { 683 if (amdgpu_sriov_vf(psp->adev)) 684 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 685 else 686 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 687 } 688 689 static int psp_tmr_unload(struct psp_context *psp) 690 { 691 int ret; 692 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 693 694 psp_prep_tmr_unload_cmd_buf(psp, cmd); 695 DRM_INFO("free PSP TMR buffer\n"); 696 697 ret = psp_cmd_submit_buf(psp, NULL, cmd, 698 psp->fence_buf_mc_addr); 699 700 release_psp_cmd_buf(psp); 701 702 return ret; 703 } 704 705 static int psp_tmr_terminate(struct psp_context *psp) 706 { 707 int ret; 708 void *tmr_buf; 709 void **pptr; 710 711 ret = psp_tmr_unload(psp); 712 if (ret) 713 return ret; 714 715 /* free TMR memory buffer */ 716 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 717 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 718 719 return 0; 720 } 721 722 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 723 uint64_t *output_ptr) 724 { 725 int ret; 726 struct psp_gfx_cmd_resp *cmd; 727 728 if (!output_ptr) 729 return -EINVAL; 730 731 if (amdgpu_sriov_vf(psp->adev)) 732 return 0; 733 734 cmd = acquire_psp_cmd_buf(psp); 735 736 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 737 738 ret = psp_cmd_submit_buf(psp, NULL, cmd, 739 psp->fence_buf_mc_addr); 740 741 if (!ret) { 742 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 743 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 744 } 745 746 release_psp_cmd_buf(psp); 747 748 return ret; 749 } 750 751 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 752 { 753 struct psp_context *psp = &adev->psp; 754 struct psp_gfx_cmd_resp *cmd; 755 int ret; 756 757 if (amdgpu_sriov_vf(adev)) 758 return 0; 759 760 cmd = acquire_psp_cmd_buf(psp); 761 762 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 763 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 764 765 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 766 if (!ret) { 767 *boot_cfg = 768 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 769 } 770 771 release_psp_cmd_buf(psp); 772 773 return ret; 774 } 775 776 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 777 { 778 int ret; 779 struct psp_context *psp = &adev->psp; 780 struct psp_gfx_cmd_resp *cmd; 781 782 if (amdgpu_sriov_vf(adev)) 783 return 0; 784 785 cmd = acquire_psp_cmd_buf(psp); 786 787 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 788 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 789 cmd->cmd.boot_cfg.boot_config = boot_cfg; 790 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 791 792 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 793 794 release_psp_cmd_buf(psp); 795 796 return ret; 797 } 798 799 static int psp_rl_load(struct amdgpu_device *adev) 800 { 801 int ret; 802 struct psp_context *psp = &adev->psp; 803 struct psp_gfx_cmd_resp *cmd; 804 805 if (!is_psp_fw_valid(psp->rl)) 806 return 0; 807 808 cmd = acquire_psp_cmd_buf(psp); 809 810 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 811 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 812 813 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 814 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 815 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 816 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 817 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 818 819 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 820 821 release_psp_cmd_buf(psp); 822 823 return ret; 824 } 825 826 static int psp_asd_load(struct psp_context *psp) 827 { 828 return psp_ta_load(psp, &psp->asd_context); 829 } 830 831 static int psp_asd_initialize(struct psp_context *psp) 832 { 833 int ret; 834 835 /* If PSP version doesn't match ASD version, asd loading will be failed. 836 * add workaround to bypass it for sriov now. 837 * TODO: add version check to make it common 838 */ 839 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 840 return 0; 841 842 psp->asd_context.mem_context.shared_mc_addr = 0; 843 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 844 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 845 846 ret = psp_asd_load(psp); 847 if (!ret) 848 psp->asd_context.initialized = true; 849 850 return ret; 851 } 852 853 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 854 uint32_t session_id) 855 { 856 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 857 cmd->cmd.cmd_unload_ta.session_id = session_id; 858 } 859 860 static int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 861 { 862 int ret; 863 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 864 865 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 866 867 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 868 869 release_psp_cmd_buf(psp); 870 871 return ret; 872 } 873 874 static int psp_asd_unload(struct psp_context *psp) 875 { 876 return psp_ta_unload(psp, &psp->asd_context); 877 } 878 879 static int psp_asd_terminate(struct psp_context *psp) 880 { 881 int ret; 882 883 if (amdgpu_sriov_vf(psp->adev)) 884 return 0; 885 886 if (!psp->asd_context.initialized) 887 return 0; 888 889 ret = psp_asd_unload(psp); 890 891 if (!ret) 892 psp->asd_context.initialized = false; 893 894 return ret; 895 } 896 897 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 898 uint32_t id, uint32_t value) 899 { 900 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 901 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 902 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 903 } 904 905 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 906 uint32_t value) 907 { 908 struct psp_gfx_cmd_resp *cmd; 909 int ret = 0; 910 911 if (reg >= PSP_REG_LAST) 912 return -EINVAL; 913 914 cmd = acquire_psp_cmd_buf(psp); 915 916 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 917 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 918 if (ret) 919 DRM_ERROR("PSP failed to program reg id %d", reg); 920 921 release_psp_cmd_buf(psp); 922 923 return ret; 924 } 925 926 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 927 uint64_t ta_bin_mc, 928 struct ta_context *context) 929 { 930 cmd->cmd_id = context->ta_load_type; 931 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 932 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 933 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 934 935 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 936 lower_32_bits(context->mem_context.shared_mc_addr); 937 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 938 upper_32_bits(context->mem_context.shared_mc_addr); 939 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 940 } 941 942 static int psp_ta_init_shared_buf(struct psp_context *psp, 943 struct ta_mem_context *mem_ctx) 944 { 945 /* 946 * Allocate 16k memory aligned to 4k from Frame Buffer (local 947 * physical) for ta to host memory 948 */ 949 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 950 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 951 &mem_ctx->shared_bo, 952 &mem_ctx->shared_mc_addr, 953 &mem_ctx->shared_buf); 954 } 955 956 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 957 { 958 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 959 &mem_ctx->shared_buf); 960 } 961 962 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 963 { 964 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 965 } 966 967 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 968 uint32_t ta_cmd_id, 969 uint32_t session_id) 970 { 971 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 972 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 973 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 974 } 975 976 static int psp_ta_invoke(struct psp_context *psp, 977 uint32_t ta_cmd_id, 978 struct ta_context *context) 979 { 980 int ret; 981 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 982 983 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 984 985 ret = psp_cmd_submit_buf(psp, NULL, cmd, 986 psp->fence_buf_mc_addr); 987 988 release_psp_cmd_buf(psp); 989 990 return ret; 991 } 992 993 static int psp_ta_load(struct psp_context *psp, struct ta_context *context) 994 { 995 int ret; 996 struct psp_gfx_cmd_resp *cmd; 997 998 cmd = acquire_psp_cmd_buf(psp); 999 1000 psp_copy_fw(psp, context->bin_desc.start_addr, 1001 context->bin_desc.size_bytes); 1002 1003 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1004 1005 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1006 psp->fence_buf_mc_addr); 1007 1008 if (!ret) { 1009 context->session_id = cmd->resp.session_id; 1010 } 1011 1012 release_psp_cmd_buf(psp); 1013 1014 return ret; 1015 } 1016 1017 static int psp_xgmi_load(struct psp_context *psp) 1018 { 1019 return psp_ta_load(psp, &psp->xgmi_context.context); 1020 } 1021 1022 static int psp_xgmi_unload(struct psp_context *psp) 1023 { 1024 return psp_ta_unload(psp, &psp->xgmi_context.context); 1025 } 1026 1027 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1028 { 1029 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1030 } 1031 1032 int psp_xgmi_terminate(struct psp_context *psp) 1033 { 1034 int ret; 1035 struct amdgpu_device *adev = psp->adev; 1036 1037 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1038 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1039 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1040 adev->gmc.xgmi.connected_to_cpu)) 1041 return 0; 1042 1043 if (!psp->xgmi_context.context.initialized) 1044 return 0; 1045 1046 ret = psp_xgmi_unload(psp); 1047 if (ret) 1048 return ret; 1049 1050 psp->xgmi_context.context.initialized = false; 1051 1052 /* free xgmi shared memory */ 1053 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1054 1055 return 0; 1056 } 1057 1058 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1059 { 1060 struct ta_xgmi_shared_memory *xgmi_cmd; 1061 int ret; 1062 1063 if (!psp->ta_fw || 1064 !psp->xgmi_context.context.bin_desc.size_bytes || 1065 !psp->xgmi_context.context.bin_desc.start_addr) 1066 return -ENOENT; 1067 1068 if (!load_ta) 1069 goto invoke; 1070 1071 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1072 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1073 1074 if (!psp->xgmi_context.context.initialized) { 1075 ret = psp_xgmi_init_shared_buf(psp); 1076 if (ret) 1077 return ret; 1078 } 1079 1080 /* Load XGMI TA */ 1081 ret = psp_xgmi_load(psp); 1082 if (!ret) 1083 psp->xgmi_context.context.initialized = true; 1084 else 1085 return ret; 1086 1087 invoke: 1088 /* Initialize XGMI session */ 1089 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1090 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1091 xgmi_cmd->flag_extend_link_record = set_extended_data; 1092 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1093 1094 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1095 1096 return ret; 1097 } 1098 1099 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1100 { 1101 struct ta_xgmi_shared_memory *xgmi_cmd; 1102 int ret; 1103 1104 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1105 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1106 1107 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1108 1109 /* Invoke xgmi ta to get hive id */ 1110 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1111 if (ret) 1112 return ret; 1113 1114 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1115 1116 return 0; 1117 } 1118 1119 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1120 { 1121 struct ta_xgmi_shared_memory *xgmi_cmd; 1122 int ret; 1123 1124 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1125 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1126 1127 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1128 1129 /* Invoke xgmi ta to get the node id */ 1130 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1131 if (ret) 1132 return ret; 1133 1134 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1135 1136 return 0; 1137 } 1138 1139 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1140 { 1141 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1142 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1143 } 1144 1145 /* 1146 * Chips that support extended topology information require the driver to 1147 * reflect topology information in the opposite direction. This is 1148 * because the TA has already exceeded its link record limit and if the 1149 * TA holds bi-directional information, the driver would have to do 1150 * multiple fetches instead of just two. 1151 */ 1152 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1153 struct psp_xgmi_node_info node_info) 1154 { 1155 struct amdgpu_device *mirror_adev; 1156 struct amdgpu_hive_info *hive; 1157 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1158 uint64_t dst_node_id = node_info.node_id; 1159 uint8_t dst_num_hops = node_info.num_hops; 1160 uint8_t dst_num_links = node_info.num_links; 1161 1162 hive = amdgpu_get_xgmi_hive(psp->adev); 1163 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1164 struct psp_xgmi_topology_info *mirror_top_info; 1165 int j; 1166 1167 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1168 continue; 1169 1170 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1171 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1172 if (mirror_top_info->nodes[j].node_id != src_node_id) 1173 continue; 1174 1175 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1176 /* 1177 * prevent 0 num_links value re-reflection since reflection 1178 * criteria is based on num_hops (direct or indirect). 1179 * 1180 */ 1181 if (dst_num_links) 1182 mirror_top_info->nodes[j].num_links = dst_num_links; 1183 1184 break; 1185 } 1186 1187 break; 1188 } 1189 } 1190 1191 int psp_xgmi_get_topology_info(struct psp_context *psp, 1192 int number_devices, 1193 struct psp_xgmi_topology_info *topology, 1194 bool get_extended_data) 1195 { 1196 struct ta_xgmi_shared_memory *xgmi_cmd; 1197 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1198 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1199 int i; 1200 int ret; 1201 1202 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1203 return -EINVAL; 1204 1205 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1206 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1207 xgmi_cmd->flag_extend_link_record = get_extended_data; 1208 1209 /* Fill in the shared memory with topology information as input */ 1210 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1211 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1212 topology_info_input->num_nodes = number_devices; 1213 1214 for (i = 0; i < topology_info_input->num_nodes; i++) { 1215 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1216 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1217 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1218 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1219 } 1220 1221 /* Invoke xgmi ta to get the topology information */ 1222 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1223 if (ret) 1224 return ret; 1225 1226 /* Read the output topology information from the shared memory */ 1227 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1228 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1229 for (i = 0; i < topology->num_nodes; i++) { 1230 /* extended data will either be 0 or equal to non-extended data */ 1231 if (topology_info_output->nodes[i].num_hops) 1232 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1233 1234 /* non-extended data gets everything here so no need to update */ 1235 if (!get_extended_data) { 1236 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1237 topology->nodes[i].is_sharing_enabled = 1238 topology_info_output->nodes[i].is_sharing_enabled; 1239 topology->nodes[i].sdma_engine = 1240 topology_info_output->nodes[i].sdma_engine; 1241 } 1242 1243 } 1244 1245 /* Invoke xgmi ta again to get the link information */ 1246 if (psp_xgmi_peer_link_info_supported(psp)) { 1247 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1248 1249 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1250 1251 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1252 1253 if (ret) 1254 return ret; 1255 1256 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1257 for (i = 0; i < topology->num_nodes; i++) { 1258 /* accumulate num_links on extended data */ 1259 topology->nodes[i].num_links = get_extended_data ? 1260 topology->nodes[i].num_links + 1261 link_info_output->nodes[i].num_links : 1262 link_info_output->nodes[i].num_links; 1263 1264 /* reflect the topology information for bi-directionality */ 1265 if (psp->xgmi_context.supports_extended_data && 1266 get_extended_data && topology->nodes[i].num_hops) 1267 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1268 } 1269 } 1270 1271 return 0; 1272 } 1273 1274 int psp_xgmi_set_topology_info(struct psp_context *psp, 1275 int number_devices, 1276 struct psp_xgmi_topology_info *topology) 1277 { 1278 struct ta_xgmi_shared_memory *xgmi_cmd; 1279 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1280 int i; 1281 1282 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1283 return -EINVAL; 1284 1285 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1286 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1287 1288 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1289 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1290 topology_info_input->num_nodes = number_devices; 1291 1292 for (i = 0; i < topology_info_input->num_nodes; i++) { 1293 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1294 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1295 topology_info_input->nodes[i].is_sharing_enabled = 1; 1296 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1297 } 1298 1299 /* Invoke xgmi ta to set topology information */ 1300 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1301 } 1302 1303 // ras begin 1304 static int psp_ras_init_shared_buf(struct psp_context *psp) 1305 { 1306 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1307 } 1308 1309 static int psp_ras_load(struct psp_context *psp) 1310 { 1311 return psp_ta_load(psp, &psp->ras_context.context); 1312 } 1313 1314 static int psp_ras_unload(struct psp_context *psp) 1315 { 1316 return psp_ta_unload(psp, &psp->ras_context.context); 1317 } 1318 1319 static void psp_ras_ta_check_status(struct psp_context *psp) 1320 { 1321 struct ta_ras_shared_memory *ras_cmd = 1322 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1323 1324 switch (ras_cmd->ras_status) { 1325 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1326 dev_warn(psp->adev->dev, 1327 "RAS WARNING: cmd failed due to unsupported ip\n"); 1328 break; 1329 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1330 dev_warn(psp->adev->dev, 1331 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1332 break; 1333 case TA_RAS_STATUS__SUCCESS: 1334 break; 1335 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1336 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1337 dev_warn(psp->adev->dev, 1338 "RAS WARNING: Inject error to critical region is not allowed\n"); 1339 break; 1340 default: 1341 dev_warn(psp->adev->dev, 1342 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1343 break; 1344 } 1345 } 1346 1347 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1348 { 1349 struct ta_ras_shared_memory *ras_cmd; 1350 int ret; 1351 1352 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1353 1354 /* 1355 * TODO: bypass the loading in sriov for now 1356 */ 1357 if (amdgpu_sriov_vf(psp->adev)) 1358 return 0; 1359 1360 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1361 1362 if (amdgpu_ras_intr_triggered()) 1363 return ret; 1364 1365 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1366 { 1367 DRM_WARN("RAS: Unsupported Interface"); 1368 return -EINVAL; 1369 } 1370 1371 if (!ret) { 1372 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1373 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1374 1375 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1376 } 1377 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1378 dev_warn(psp->adev->dev, 1379 "RAS internal register access blocked\n"); 1380 1381 psp_ras_ta_check_status(psp); 1382 } 1383 1384 return ret; 1385 } 1386 1387 int psp_ras_enable_features(struct psp_context *psp, 1388 union ta_ras_cmd_input *info, bool enable) 1389 { 1390 struct ta_ras_shared_memory *ras_cmd; 1391 int ret; 1392 1393 if (!psp->ras_context.context.initialized) 1394 return -EINVAL; 1395 1396 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1397 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1398 1399 if (enable) 1400 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1401 else 1402 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1403 1404 ras_cmd->ras_in_message = *info; 1405 1406 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1407 if (ret) 1408 return -EINVAL; 1409 1410 return 0; 1411 } 1412 1413 static int psp_ras_terminate(struct psp_context *psp) 1414 { 1415 int ret; 1416 1417 /* 1418 * TODO: bypass the terminate in sriov for now 1419 */ 1420 if (amdgpu_sriov_vf(psp->adev)) 1421 return 0; 1422 1423 if (!psp->ras_context.context.initialized) 1424 return 0; 1425 1426 ret = psp_ras_unload(psp); 1427 if (ret) 1428 return ret; 1429 1430 psp->ras_context.context.initialized = false; 1431 1432 /* free ras shared memory */ 1433 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1434 1435 return 0; 1436 } 1437 1438 static int psp_ras_initialize(struct psp_context *psp) 1439 { 1440 int ret; 1441 uint32_t boot_cfg = 0xFF; 1442 struct amdgpu_device *adev = psp->adev; 1443 struct ta_ras_shared_memory *ras_cmd; 1444 1445 /* 1446 * TODO: bypass the initialize in sriov for now 1447 */ 1448 if (amdgpu_sriov_vf(adev)) 1449 return 0; 1450 1451 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1452 !adev->psp.ras_context.context.bin_desc.start_addr) { 1453 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1454 return 0; 1455 } 1456 1457 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1458 /* query GECC enablement status from boot config 1459 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1460 */ 1461 ret = psp_boot_config_get(adev, &boot_cfg); 1462 if (ret) 1463 dev_warn(adev->dev, "PSP get boot config failed\n"); 1464 1465 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1466 if (!boot_cfg) { 1467 dev_info(adev->dev, "GECC is disabled\n"); 1468 } else { 1469 /* disable GECC in next boot cycle if ras is 1470 * disabled by module parameter amdgpu_ras_enable 1471 * and/or amdgpu_ras_mask, or boot_config_get call 1472 * is failed 1473 */ 1474 ret = psp_boot_config_set(adev, 0); 1475 if (ret) 1476 dev_warn(adev->dev, "PSP set boot config failed\n"); 1477 else 1478 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1479 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1480 } 1481 } else { 1482 if (1 == boot_cfg) { 1483 dev_info(adev->dev, "GECC is enabled\n"); 1484 } else { 1485 /* enable GECC in next boot cycle if it is disabled 1486 * in boot config, or force enable GECC if failed to 1487 * get boot configuration 1488 */ 1489 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1490 if (ret) 1491 dev_warn(adev->dev, "PSP set boot config failed\n"); 1492 else 1493 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1494 } 1495 } 1496 } 1497 1498 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1499 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1500 1501 if (!psp->ras_context.context.initialized) { 1502 ret = psp_ras_init_shared_buf(psp); 1503 if (ret) 1504 return ret; 1505 } 1506 1507 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1508 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1509 1510 if (amdgpu_ras_is_poison_mode_supported(adev)) 1511 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1512 if (!adev->gmc.xgmi.connected_to_cpu) 1513 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1514 1515 ret = psp_ras_load(psp); 1516 1517 if (!ret && !ras_cmd->ras_status) 1518 psp->ras_context.context.initialized = true; 1519 else { 1520 if (ras_cmd->ras_status) 1521 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1522 amdgpu_ras_fini(psp->adev); 1523 } 1524 1525 return ret; 1526 } 1527 1528 int psp_ras_trigger_error(struct psp_context *psp, 1529 struct ta_ras_trigger_error_input *info) 1530 { 1531 struct ta_ras_shared_memory *ras_cmd; 1532 int ret; 1533 1534 if (!psp->ras_context.context.initialized) 1535 return -EINVAL; 1536 1537 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1538 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1539 1540 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1541 ras_cmd->ras_in_message.trigger_error = *info; 1542 1543 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1544 if (ret) 1545 return -EINVAL; 1546 1547 /* If err_event_athub occurs error inject was successful, however 1548 return status from TA is no long reliable */ 1549 if (amdgpu_ras_intr_triggered()) 1550 return 0; 1551 1552 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1553 return -EACCES; 1554 else if (ras_cmd->ras_status) 1555 return -EINVAL; 1556 1557 return 0; 1558 } 1559 // ras end 1560 1561 // HDCP start 1562 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1563 { 1564 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1565 } 1566 1567 static int psp_hdcp_load(struct psp_context *psp) 1568 { 1569 return psp_ta_load(psp, &psp->hdcp_context.context); 1570 } 1571 1572 static int psp_hdcp_initialize(struct psp_context *psp) 1573 { 1574 int ret; 1575 1576 /* 1577 * TODO: bypass the initialize in sriov for now 1578 */ 1579 if (amdgpu_sriov_vf(psp->adev)) 1580 return 0; 1581 1582 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1583 !psp->hdcp_context.context.bin_desc.start_addr) { 1584 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1585 return 0; 1586 } 1587 1588 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1589 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1590 1591 if (!psp->hdcp_context.context.initialized) { 1592 ret = psp_hdcp_init_shared_buf(psp); 1593 if (ret) 1594 return ret; 1595 } 1596 1597 ret = psp_hdcp_load(psp); 1598 if (!ret) { 1599 psp->hdcp_context.context.initialized = true; 1600 mutex_init(&psp->hdcp_context.mutex); 1601 } 1602 1603 return ret; 1604 } 1605 1606 static int psp_hdcp_unload(struct psp_context *psp) 1607 { 1608 return psp_ta_unload(psp, &psp->hdcp_context.context); 1609 } 1610 1611 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1612 { 1613 /* 1614 * TODO: bypass the loading in sriov for now 1615 */ 1616 if (amdgpu_sriov_vf(psp->adev)) 1617 return 0; 1618 1619 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1620 } 1621 1622 static int psp_hdcp_terminate(struct psp_context *psp) 1623 { 1624 int ret; 1625 1626 /* 1627 * TODO: bypass the terminate in sriov for now 1628 */ 1629 if (amdgpu_sriov_vf(psp->adev)) 1630 return 0; 1631 1632 if (!psp->hdcp_context.context.initialized) { 1633 if (psp->hdcp_context.context.mem_context.shared_buf) 1634 goto out; 1635 else 1636 return 0; 1637 } 1638 1639 ret = psp_hdcp_unload(psp); 1640 if (ret) 1641 return ret; 1642 1643 psp->hdcp_context.context.initialized = false; 1644 1645 out: 1646 /* free hdcp shared memory */ 1647 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1648 1649 return 0; 1650 } 1651 // HDCP end 1652 1653 // DTM start 1654 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1655 { 1656 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1657 } 1658 1659 static int psp_dtm_load(struct psp_context *psp) 1660 { 1661 return psp_ta_load(psp, &psp->dtm_context.context); 1662 } 1663 1664 static int psp_dtm_initialize(struct psp_context *psp) 1665 { 1666 int ret; 1667 1668 /* 1669 * TODO: bypass the initialize in sriov for now 1670 */ 1671 if (amdgpu_sriov_vf(psp->adev)) 1672 return 0; 1673 1674 if (!psp->dtm_context.context.bin_desc.size_bytes || 1675 !psp->dtm_context.context.bin_desc.start_addr) { 1676 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1677 return 0; 1678 } 1679 1680 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1681 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1682 1683 if (!psp->dtm_context.context.initialized) { 1684 ret = psp_dtm_init_shared_buf(psp); 1685 if (ret) 1686 return ret; 1687 } 1688 1689 ret = psp_dtm_load(psp); 1690 if (!ret) { 1691 psp->dtm_context.context.initialized = true; 1692 mutex_init(&psp->dtm_context.mutex); 1693 } 1694 1695 return ret; 1696 } 1697 1698 static int psp_dtm_unload(struct psp_context *psp) 1699 { 1700 return psp_ta_unload(psp, &psp->dtm_context.context); 1701 } 1702 1703 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1704 { 1705 /* 1706 * TODO: bypass the loading in sriov for now 1707 */ 1708 if (amdgpu_sriov_vf(psp->adev)) 1709 return 0; 1710 1711 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1712 } 1713 1714 static int psp_dtm_terminate(struct psp_context *psp) 1715 { 1716 int ret; 1717 1718 /* 1719 * TODO: bypass the terminate in sriov for now 1720 */ 1721 if (amdgpu_sriov_vf(psp->adev)) 1722 return 0; 1723 1724 if (!psp->dtm_context.context.initialized) { 1725 if (psp->dtm_context.context.mem_context.shared_buf) 1726 goto out; 1727 else 1728 return 0; 1729 } 1730 1731 ret = psp_dtm_unload(psp); 1732 if (ret) 1733 return ret; 1734 1735 psp->dtm_context.context.initialized = false; 1736 1737 out: 1738 /* free dtm shared memory */ 1739 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1740 1741 return 0; 1742 } 1743 // DTM end 1744 1745 // RAP start 1746 static int psp_rap_init_shared_buf(struct psp_context *psp) 1747 { 1748 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1749 } 1750 1751 static int psp_rap_load(struct psp_context *psp) 1752 { 1753 return psp_ta_load(psp, &psp->rap_context.context); 1754 } 1755 1756 static int psp_rap_unload(struct psp_context *psp) 1757 { 1758 return psp_ta_unload(psp, &psp->rap_context.context); 1759 } 1760 1761 static int psp_rap_initialize(struct psp_context *psp) 1762 { 1763 int ret; 1764 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1765 1766 /* 1767 * TODO: bypass the initialize in sriov for now 1768 */ 1769 if (amdgpu_sriov_vf(psp->adev)) 1770 return 0; 1771 1772 if (!psp->rap_context.context.bin_desc.size_bytes || 1773 !psp->rap_context.context.bin_desc.start_addr) { 1774 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1775 return 0; 1776 } 1777 1778 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1779 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1780 1781 if (!psp->rap_context.context.initialized) { 1782 ret = psp_rap_init_shared_buf(psp); 1783 if (ret) 1784 return ret; 1785 } 1786 1787 ret = psp_rap_load(psp); 1788 if (!ret) { 1789 psp->rap_context.context.initialized = true; 1790 mutex_init(&psp->rap_context.mutex); 1791 } else 1792 return ret; 1793 1794 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1795 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1796 psp_rap_terminate(psp); 1797 1798 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1799 ret, status); 1800 1801 return ret; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int psp_rap_terminate(struct psp_context *psp) 1808 { 1809 int ret; 1810 1811 if (!psp->rap_context.context.initialized) 1812 return 0; 1813 1814 ret = psp_rap_unload(psp); 1815 1816 psp->rap_context.context.initialized = false; 1817 1818 /* free rap shared memory */ 1819 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1820 1821 return ret; 1822 } 1823 1824 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1825 { 1826 struct ta_rap_shared_memory *rap_cmd; 1827 int ret = 0; 1828 1829 if (!psp->rap_context.context.initialized) 1830 return 0; 1831 1832 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1833 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1834 return -EINVAL; 1835 1836 mutex_lock(&psp->rap_context.mutex); 1837 1838 rap_cmd = (struct ta_rap_shared_memory *) 1839 psp->rap_context.context.mem_context.shared_buf; 1840 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1841 1842 rap_cmd->cmd_id = ta_cmd_id; 1843 rap_cmd->validation_method_id = METHOD_A; 1844 1845 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1846 if (ret) 1847 goto out_unlock; 1848 1849 if (status) 1850 *status = rap_cmd->rap_status; 1851 1852 out_unlock: 1853 mutex_unlock(&psp->rap_context.mutex); 1854 1855 return ret; 1856 } 1857 // RAP end 1858 1859 /* securedisplay start */ 1860 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1861 { 1862 return psp_ta_init_shared_buf( 1863 psp, &psp->securedisplay_context.context.mem_context); 1864 } 1865 1866 static int psp_securedisplay_load(struct psp_context *psp) 1867 { 1868 return psp_ta_load(psp, &psp->securedisplay_context.context); 1869 } 1870 1871 static int psp_securedisplay_unload(struct psp_context *psp) 1872 { 1873 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1874 } 1875 1876 static int psp_securedisplay_initialize(struct psp_context *psp) 1877 { 1878 int ret; 1879 struct securedisplay_cmd *securedisplay_cmd; 1880 1881 /* 1882 * TODO: bypass the initialize in sriov for now 1883 */ 1884 if (amdgpu_sriov_vf(psp->adev)) 1885 return 0; 1886 1887 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1888 !psp->securedisplay_context.context.bin_desc.start_addr) { 1889 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1890 return 0; 1891 } 1892 1893 psp->securedisplay_context.context.mem_context.shared_mem_size = 1894 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1895 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1896 1897 if (!psp->securedisplay_context.context.initialized) { 1898 ret = psp_securedisplay_init_shared_buf(psp); 1899 if (ret) 1900 return ret; 1901 } 1902 1903 ret = psp_securedisplay_load(psp); 1904 if (!ret) { 1905 psp->securedisplay_context.context.initialized = true; 1906 mutex_init(&psp->securedisplay_context.mutex); 1907 } else 1908 return ret; 1909 1910 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1911 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1912 1913 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1914 if (ret) { 1915 psp_securedisplay_terminate(psp); 1916 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1917 return -EINVAL; 1918 } 1919 1920 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1921 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1922 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1923 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int psp_securedisplay_terminate(struct psp_context *psp) 1930 { 1931 int ret; 1932 1933 /* 1934 * TODO:bypass the terminate in sriov for now 1935 */ 1936 if (amdgpu_sriov_vf(psp->adev)) 1937 return 0; 1938 1939 if (!psp->securedisplay_context.context.initialized) 1940 return 0; 1941 1942 ret = psp_securedisplay_unload(psp); 1943 if (ret) 1944 return ret; 1945 1946 psp->securedisplay_context.context.initialized = false; 1947 1948 /* free securedisplay shared memory */ 1949 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1950 1951 return ret; 1952 } 1953 1954 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1955 { 1956 int ret; 1957 1958 if (!psp->securedisplay_context.context.initialized) 1959 return -EINVAL; 1960 1961 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1962 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1963 return -EINVAL; 1964 1965 mutex_lock(&psp->securedisplay_context.mutex); 1966 1967 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1968 1969 mutex_unlock(&psp->securedisplay_context.mutex); 1970 1971 return ret; 1972 } 1973 /* SECUREDISPLAY end */ 1974 1975 static int psp_hw_start(struct psp_context *psp) 1976 { 1977 struct amdgpu_device *adev = psp->adev; 1978 int ret; 1979 1980 if (!amdgpu_sriov_vf(adev)) { 1981 if ((is_psp_fw_valid(psp->kdb)) && 1982 (psp->funcs->bootloader_load_kdb != NULL)) { 1983 ret = psp_bootloader_load_kdb(psp); 1984 if (ret) { 1985 DRM_ERROR("PSP load kdb failed!\n"); 1986 return ret; 1987 } 1988 } 1989 1990 if ((is_psp_fw_valid(psp->spl)) && 1991 (psp->funcs->bootloader_load_spl != NULL)) { 1992 ret = psp_bootloader_load_spl(psp); 1993 if (ret) { 1994 DRM_ERROR("PSP load spl failed!\n"); 1995 return ret; 1996 } 1997 } 1998 1999 if ((is_psp_fw_valid(psp->sys)) && 2000 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2001 ret = psp_bootloader_load_sysdrv(psp); 2002 if (ret) { 2003 DRM_ERROR("PSP load sys drv failed!\n"); 2004 return ret; 2005 } 2006 } 2007 2008 if ((is_psp_fw_valid(psp->soc_drv)) && 2009 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2010 ret = psp_bootloader_load_soc_drv(psp); 2011 if (ret) { 2012 DRM_ERROR("PSP load soc drv failed!\n"); 2013 return ret; 2014 } 2015 } 2016 2017 if ((is_psp_fw_valid(psp->intf_drv)) && 2018 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2019 ret = psp_bootloader_load_intf_drv(psp); 2020 if (ret) { 2021 DRM_ERROR("PSP load intf drv failed!\n"); 2022 return ret; 2023 } 2024 } 2025 2026 if ((is_psp_fw_valid(psp->dbg_drv)) && 2027 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2028 ret = psp_bootloader_load_dbg_drv(psp); 2029 if (ret) { 2030 DRM_ERROR("PSP load dbg drv failed!\n"); 2031 return ret; 2032 } 2033 } 2034 2035 if ((is_psp_fw_valid(psp->sos)) && 2036 (psp->funcs->bootloader_load_sos != NULL)) { 2037 ret = psp_bootloader_load_sos(psp); 2038 if (ret) { 2039 DRM_ERROR("PSP load sos failed!\n"); 2040 return ret; 2041 } 2042 } 2043 } 2044 2045 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2046 if (ret) { 2047 DRM_ERROR("PSP create ring failed!\n"); 2048 return ret; 2049 } 2050 2051 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2052 goto skip_pin_bo; 2053 2054 ret = psp_tmr_init(psp); 2055 if (ret) { 2056 DRM_ERROR("PSP tmr init failed!\n"); 2057 return ret; 2058 } 2059 2060 skip_pin_bo: 2061 /* 2062 * For ASICs with DF Cstate management centralized 2063 * to PMFW, TMR setup should be performed after PMFW 2064 * loaded and before other non-psp firmware loaded. 2065 */ 2066 if (psp->pmfw_centralized_cstate_management) { 2067 ret = psp_load_smu_fw(psp); 2068 if (ret) 2069 return ret; 2070 } 2071 2072 ret = psp_tmr_load(psp); 2073 if (ret) { 2074 DRM_ERROR("PSP load tmr failed!\n"); 2075 return ret; 2076 } 2077 2078 return 0; 2079 } 2080 2081 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2082 enum psp_gfx_fw_type *type) 2083 { 2084 switch (ucode->ucode_id) { 2085 case AMDGPU_UCODE_ID_CAP: 2086 *type = GFX_FW_TYPE_CAP; 2087 break; 2088 case AMDGPU_UCODE_ID_SDMA0: 2089 *type = GFX_FW_TYPE_SDMA0; 2090 break; 2091 case AMDGPU_UCODE_ID_SDMA1: 2092 *type = GFX_FW_TYPE_SDMA1; 2093 break; 2094 case AMDGPU_UCODE_ID_SDMA2: 2095 *type = GFX_FW_TYPE_SDMA2; 2096 break; 2097 case AMDGPU_UCODE_ID_SDMA3: 2098 *type = GFX_FW_TYPE_SDMA3; 2099 break; 2100 case AMDGPU_UCODE_ID_SDMA4: 2101 *type = GFX_FW_TYPE_SDMA4; 2102 break; 2103 case AMDGPU_UCODE_ID_SDMA5: 2104 *type = GFX_FW_TYPE_SDMA5; 2105 break; 2106 case AMDGPU_UCODE_ID_SDMA6: 2107 *type = GFX_FW_TYPE_SDMA6; 2108 break; 2109 case AMDGPU_UCODE_ID_SDMA7: 2110 *type = GFX_FW_TYPE_SDMA7; 2111 break; 2112 case AMDGPU_UCODE_ID_CP_MES: 2113 *type = GFX_FW_TYPE_CP_MES; 2114 break; 2115 case AMDGPU_UCODE_ID_CP_MES_DATA: 2116 *type = GFX_FW_TYPE_MES_STACK; 2117 break; 2118 case AMDGPU_UCODE_ID_CP_CE: 2119 *type = GFX_FW_TYPE_CP_CE; 2120 break; 2121 case AMDGPU_UCODE_ID_CP_PFP: 2122 *type = GFX_FW_TYPE_CP_PFP; 2123 break; 2124 case AMDGPU_UCODE_ID_CP_ME: 2125 *type = GFX_FW_TYPE_CP_ME; 2126 break; 2127 case AMDGPU_UCODE_ID_CP_MEC1: 2128 *type = GFX_FW_TYPE_CP_MEC; 2129 break; 2130 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2131 *type = GFX_FW_TYPE_CP_MEC_ME1; 2132 break; 2133 case AMDGPU_UCODE_ID_CP_MEC2: 2134 *type = GFX_FW_TYPE_CP_MEC; 2135 break; 2136 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2137 *type = GFX_FW_TYPE_CP_MEC_ME2; 2138 break; 2139 case AMDGPU_UCODE_ID_RLC_G: 2140 *type = GFX_FW_TYPE_RLC_G; 2141 break; 2142 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2143 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2144 break; 2145 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2146 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2147 break; 2148 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2149 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2150 break; 2151 case AMDGPU_UCODE_ID_RLC_IRAM: 2152 *type = GFX_FW_TYPE_RLC_IRAM; 2153 break; 2154 case AMDGPU_UCODE_ID_RLC_DRAM: 2155 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2156 break; 2157 case AMDGPU_UCODE_ID_SMC: 2158 *type = GFX_FW_TYPE_SMU; 2159 break; 2160 case AMDGPU_UCODE_ID_UVD: 2161 *type = GFX_FW_TYPE_UVD; 2162 break; 2163 case AMDGPU_UCODE_ID_UVD1: 2164 *type = GFX_FW_TYPE_UVD1; 2165 break; 2166 case AMDGPU_UCODE_ID_VCE: 2167 *type = GFX_FW_TYPE_VCE; 2168 break; 2169 case AMDGPU_UCODE_ID_VCN: 2170 *type = GFX_FW_TYPE_VCN; 2171 break; 2172 case AMDGPU_UCODE_ID_VCN1: 2173 *type = GFX_FW_TYPE_VCN1; 2174 break; 2175 case AMDGPU_UCODE_ID_DMCU_ERAM: 2176 *type = GFX_FW_TYPE_DMCU_ERAM; 2177 break; 2178 case AMDGPU_UCODE_ID_DMCU_INTV: 2179 *type = GFX_FW_TYPE_DMCU_ISR; 2180 break; 2181 case AMDGPU_UCODE_ID_VCN0_RAM: 2182 *type = GFX_FW_TYPE_VCN0_RAM; 2183 break; 2184 case AMDGPU_UCODE_ID_VCN1_RAM: 2185 *type = GFX_FW_TYPE_VCN1_RAM; 2186 break; 2187 case AMDGPU_UCODE_ID_DMCUB: 2188 *type = GFX_FW_TYPE_DMUB; 2189 break; 2190 case AMDGPU_UCODE_ID_MAXIMUM: 2191 default: 2192 return -EINVAL; 2193 } 2194 2195 return 0; 2196 } 2197 2198 static void psp_print_fw_hdr(struct psp_context *psp, 2199 struct amdgpu_firmware_info *ucode) 2200 { 2201 struct amdgpu_device *adev = psp->adev; 2202 struct common_firmware_header *hdr; 2203 2204 switch (ucode->ucode_id) { 2205 case AMDGPU_UCODE_ID_SDMA0: 2206 case AMDGPU_UCODE_ID_SDMA1: 2207 case AMDGPU_UCODE_ID_SDMA2: 2208 case AMDGPU_UCODE_ID_SDMA3: 2209 case AMDGPU_UCODE_ID_SDMA4: 2210 case AMDGPU_UCODE_ID_SDMA5: 2211 case AMDGPU_UCODE_ID_SDMA6: 2212 case AMDGPU_UCODE_ID_SDMA7: 2213 hdr = (struct common_firmware_header *) 2214 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2215 amdgpu_ucode_print_sdma_hdr(hdr); 2216 break; 2217 case AMDGPU_UCODE_ID_CP_CE: 2218 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2219 amdgpu_ucode_print_gfx_hdr(hdr); 2220 break; 2221 case AMDGPU_UCODE_ID_CP_PFP: 2222 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2223 amdgpu_ucode_print_gfx_hdr(hdr); 2224 break; 2225 case AMDGPU_UCODE_ID_CP_ME: 2226 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2227 amdgpu_ucode_print_gfx_hdr(hdr); 2228 break; 2229 case AMDGPU_UCODE_ID_CP_MEC1: 2230 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2231 amdgpu_ucode_print_gfx_hdr(hdr); 2232 break; 2233 case AMDGPU_UCODE_ID_RLC_G: 2234 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2235 amdgpu_ucode_print_rlc_hdr(hdr); 2236 break; 2237 case AMDGPU_UCODE_ID_SMC: 2238 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2239 amdgpu_ucode_print_smc_hdr(hdr); 2240 break; 2241 default: 2242 break; 2243 } 2244 } 2245 2246 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2247 struct psp_gfx_cmd_resp *cmd) 2248 { 2249 int ret; 2250 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2251 2252 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2253 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2254 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2255 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2256 2257 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2258 if (ret) 2259 DRM_ERROR("Unknown firmware type\n"); 2260 2261 return ret; 2262 } 2263 2264 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2265 struct amdgpu_firmware_info *ucode) 2266 { 2267 int ret = 0; 2268 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2269 2270 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2271 if (!ret) { 2272 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2273 psp->fence_buf_mc_addr); 2274 } 2275 2276 release_psp_cmd_buf(psp); 2277 2278 return ret; 2279 } 2280 2281 static int psp_load_smu_fw(struct psp_context *psp) 2282 { 2283 int ret; 2284 struct amdgpu_device *adev = psp->adev; 2285 struct amdgpu_firmware_info *ucode = 2286 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2287 struct amdgpu_ras *ras = psp->ras_context.ras; 2288 2289 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2290 return 0; 2291 2292 if ((amdgpu_in_reset(adev) && 2293 ras && adev->ras_enabled && 2294 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2295 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2296 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2297 if (ret) { 2298 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2299 } 2300 } 2301 2302 ret = psp_execute_non_psp_fw_load(psp, ucode); 2303 2304 if (ret) 2305 DRM_ERROR("PSP load smu failed!\n"); 2306 2307 return ret; 2308 } 2309 2310 static bool fw_load_skip_check(struct psp_context *psp, 2311 struct amdgpu_firmware_info *ucode) 2312 { 2313 if (!ucode->fw) 2314 return true; 2315 2316 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2317 (psp_smu_reload_quirk(psp) || 2318 psp->autoload_supported || 2319 psp->pmfw_centralized_cstate_management)) 2320 return true; 2321 2322 if (amdgpu_sriov_vf(psp->adev) && 2323 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2324 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2325 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2326 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2327 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2328 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2329 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2330 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2331 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2332 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2333 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2334 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2335 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2336 /*skip ucode loading in SRIOV VF */ 2337 return true; 2338 2339 if (psp->autoload_supported && 2340 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2341 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2342 /* skip mec JT when autoload is enabled */ 2343 return true; 2344 2345 return false; 2346 } 2347 2348 int psp_load_fw_list(struct psp_context *psp, 2349 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2350 { 2351 int ret = 0, i; 2352 struct amdgpu_firmware_info *ucode; 2353 2354 for (i = 0; i < ucode_count; ++i) { 2355 ucode = ucode_list[i]; 2356 psp_print_fw_hdr(psp, ucode); 2357 ret = psp_execute_non_psp_fw_load(psp, ucode); 2358 if (ret) 2359 return ret; 2360 } 2361 return ret; 2362 } 2363 2364 static int psp_load_non_psp_fw(struct psp_context *psp) 2365 { 2366 int i, ret; 2367 struct amdgpu_firmware_info *ucode; 2368 struct amdgpu_device *adev = psp->adev; 2369 2370 if (psp->autoload_supported && 2371 !psp->pmfw_centralized_cstate_management) { 2372 ret = psp_load_smu_fw(psp); 2373 if (ret) 2374 return ret; 2375 } 2376 2377 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2378 ucode = &adev->firmware.ucode[i]; 2379 2380 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2381 !fw_load_skip_check(psp, ucode)) { 2382 ret = psp_load_smu_fw(psp); 2383 if (ret) 2384 return ret; 2385 continue; 2386 } 2387 2388 if (fw_load_skip_check(psp, ucode)) 2389 continue; 2390 2391 if (psp->autoload_supported && 2392 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2393 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2394 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2395 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2396 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2397 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2398 /* PSP only receive one SDMA fw for sienna_cichlid, 2399 * as all four sdma fw are same */ 2400 continue; 2401 2402 psp_print_fw_hdr(psp, ucode); 2403 2404 ret = psp_execute_non_psp_fw_load(psp, ucode); 2405 if (ret) 2406 return ret; 2407 2408 /* Start rlc autoload after psp recieved all the gfx firmware */ 2409 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2410 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2411 ret = psp_rlc_autoload_start(psp); 2412 if (ret) { 2413 DRM_ERROR("Failed to start rlc autoload\n"); 2414 return ret; 2415 } 2416 } 2417 } 2418 2419 return 0; 2420 } 2421 2422 static int psp_load_fw(struct amdgpu_device *adev) 2423 { 2424 int ret; 2425 struct psp_context *psp = &adev->psp; 2426 2427 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2428 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2429 goto skip_memalloc; 2430 } 2431 2432 if (amdgpu_sriov_vf(adev)) { 2433 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2434 AMDGPU_GEM_DOMAIN_VRAM, 2435 &psp->fw_pri_bo, 2436 &psp->fw_pri_mc_addr, 2437 &psp->fw_pri_buf); 2438 } else { 2439 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2440 AMDGPU_GEM_DOMAIN_GTT, 2441 &psp->fw_pri_bo, 2442 &psp->fw_pri_mc_addr, 2443 &psp->fw_pri_buf); 2444 } 2445 2446 if (ret) 2447 goto failed; 2448 2449 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2450 AMDGPU_GEM_DOMAIN_VRAM, 2451 &psp->fence_buf_bo, 2452 &psp->fence_buf_mc_addr, 2453 &psp->fence_buf); 2454 if (ret) 2455 goto failed; 2456 2457 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2458 AMDGPU_GEM_DOMAIN_VRAM, 2459 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2460 (void **)&psp->cmd_buf_mem); 2461 if (ret) 2462 goto failed; 2463 2464 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2465 2466 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2467 if (ret) { 2468 DRM_ERROR("PSP ring init failed!\n"); 2469 goto failed; 2470 } 2471 2472 skip_memalloc: 2473 ret = psp_hw_start(psp); 2474 if (ret) 2475 goto failed; 2476 2477 ret = psp_load_non_psp_fw(psp); 2478 if (ret) 2479 goto failed; 2480 2481 ret = psp_asd_initialize(psp); 2482 if (ret) { 2483 DRM_ERROR("PSP load asd failed!\n"); 2484 return ret; 2485 } 2486 2487 ret = psp_rl_load(adev); 2488 if (ret) { 2489 DRM_ERROR("PSP load RL failed!\n"); 2490 return ret; 2491 } 2492 2493 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2494 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2495 ret = psp_xgmi_initialize(psp, false, true); 2496 /* Warning the XGMI seesion initialize failure 2497 * Instead of stop driver initialization 2498 */ 2499 if (ret) 2500 dev_err(psp->adev->dev, 2501 "XGMI: Failed to initialize XGMI session\n"); 2502 } 2503 } 2504 2505 if (psp->ta_fw) { 2506 ret = psp_ras_initialize(psp); 2507 if (ret) 2508 dev_err(psp->adev->dev, 2509 "RAS: Failed to initialize RAS\n"); 2510 2511 ret = psp_hdcp_initialize(psp); 2512 if (ret) 2513 dev_err(psp->adev->dev, 2514 "HDCP: Failed to initialize HDCP\n"); 2515 2516 ret = psp_dtm_initialize(psp); 2517 if (ret) 2518 dev_err(psp->adev->dev, 2519 "DTM: Failed to initialize DTM\n"); 2520 2521 ret = psp_rap_initialize(psp); 2522 if (ret) 2523 dev_err(psp->adev->dev, 2524 "RAP: Failed to initialize RAP\n"); 2525 2526 ret = psp_securedisplay_initialize(psp); 2527 if (ret) 2528 dev_err(psp->adev->dev, 2529 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2530 } 2531 2532 return 0; 2533 2534 failed: 2535 /* 2536 * all cleanup jobs (xgmi terminate, ras terminate, 2537 * ring destroy, cmd/fence/fw buffers destory, 2538 * psp->cmd destory) are delayed to psp_hw_fini 2539 */ 2540 return ret; 2541 } 2542 2543 static int psp_hw_init(void *handle) 2544 { 2545 int ret; 2546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2547 2548 mutex_lock(&adev->firmware.mutex); 2549 /* 2550 * This sequence is just used on hw_init only once, no need on 2551 * resume. 2552 */ 2553 ret = amdgpu_ucode_init_bo(adev); 2554 if (ret) 2555 goto failed; 2556 2557 ret = psp_load_fw(adev); 2558 if (ret) { 2559 DRM_ERROR("PSP firmware loading failed\n"); 2560 goto failed; 2561 } 2562 2563 mutex_unlock(&adev->firmware.mutex); 2564 return 0; 2565 2566 failed: 2567 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2568 mutex_unlock(&adev->firmware.mutex); 2569 return -EINVAL; 2570 } 2571 2572 static int psp_hw_fini(void *handle) 2573 { 2574 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2575 struct psp_context *psp = &adev->psp; 2576 2577 if (psp->ta_fw) { 2578 psp_ras_terminate(psp); 2579 psp_securedisplay_terminate(psp); 2580 psp_rap_terminate(psp); 2581 psp_dtm_terminate(psp); 2582 psp_hdcp_terminate(psp); 2583 } 2584 2585 psp_asd_terminate(psp); 2586 2587 psp_tmr_terminate(psp); 2588 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2589 2590 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2591 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2592 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2593 &psp->fence_buf_mc_addr, &psp->fence_buf); 2594 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2595 (void **)&psp->cmd_buf_mem); 2596 2597 return 0; 2598 } 2599 2600 static int psp_suspend(void *handle) 2601 { 2602 int ret; 2603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2604 struct psp_context *psp = &adev->psp; 2605 2606 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2607 psp->xgmi_context.context.initialized) { 2608 ret = psp_xgmi_terminate(psp); 2609 if (ret) { 2610 DRM_ERROR("Failed to terminate xgmi ta\n"); 2611 return ret; 2612 } 2613 } 2614 2615 if (psp->ta_fw) { 2616 ret = psp_ras_terminate(psp); 2617 if (ret) { 2618 DRM_ERROR("Failed to terminate ras ta\n"); 2619 return ret; 2620 } 2621 ret = psp_hdcp_terminate(psp); 2622 if (ret) { 2623 DRM_ERROR("Failed to terminate hdcp ta\n"); 2624 return ret; 2625 } 2626 ret = psp_dtm_terminate(psp); 2627 if (ret) { 2628 DRM_ERROR("Failed to terminate dtm ta\n"); 2629 return ret; 2630 } 2631 ret = psp_rap_terminate(psp); 2632 if (ret) { 2633 DRM_ERROR("Failed to terminate rap ta\n"); 2634 return ret; 2635 } 2636 ret = psp_securedisplay_terminate(psp); 2637 if (ret) { 2638 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2639 return ret; 2640 } 2641 } 2642 2643 ret = psp_asd_terminate(psp); 2644 if (ret) { 2645 DRM_ERROR("Failed to terminate asd\n"); 2646 return ret; 2647 } 2648 2649 ret = psp_tmr_terminate(psp); 2650 if (ret) { 2651 DRM_ERROR("Failed to terminate tmr\n"); 2652 return ret; 2653 } 2654 2655 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2656 if (ret) { 2657 DRM_ERROR("PSP ring stop failed\n"); 2658 return ret; 2659 } 2660 2661 return 0; 2662 } 2663 2664 static int psp_resume(void *handle) 2665 { 2666 int ret; 2667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2668 struct psp_context *psp = &adev->psp; 2669 2670 DRM_INFO("PSP is resuming...\n"); 2671 2672 if (psp->mem_train_ctx.enable_mem_training) { 2673 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2674 if (ret) { 2675 DRM_ERROR("Failed to process memory training!\n"); 2676 return ret; 2677 } 2678 } 2679 2680 mutex_lock(&adev->firmware.mutex); 2681 2682 ret = psp_hw_start(psp); 2683 if (ret) 2684 goto failed; 2685 2686 ret = psp_load_non_psp_fw(psp); 2687 if (ret) 2688 goto failed; 2689 2690 ret = psp_asd_initialize(psp); 2691 if (ret) { 2692 DRM_ERROR("PSP load asd failed!\n"); 2693 goto failed; 2694 } 2695 2696 ret = psp_rl_load(adev); 2697 if (ret) { 2698 dev_err(adev->dev, "PSP load RL failed!\n"); 2699 goto failed; 2700 } 2701 2702 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2703 ret = psp_xgmi_initialize(psp, false, true); 2704 /* Warning the XGMI seesion initialize failure 2705 * Instead of stop driver initialization 2706 */ 2707 if (ret) 2708 dev_err(psp->adev->dev, 2709 "XGMI: Failed to initialize XGMI session\n"); 2710 } 2711 2712 if (psp->ta_fw) { 2713 ret = psp_ras_initialize(psp); 2714 if (ret) 2715 dev_err(psp->adev->dev, 2716 "RAS: Failed to initialize RAS\n"); 2717 2718 ret = psp_hdcp_initialize(psp); 2719 if (ret) 2720 dev_err(psp->adev->dev, 2721 "HDCP: Failed to initialize HDCP\n"); 2722 2723 ret = psp_dtm_initialize(psp); 2724 if (ret) 2725 dev_err(psp->adev->dev, 2726 "DTM: Failed to initialize DTM\n"); 2727 2728 ret = psp_rap_initialize(psp); 2729 if (ret) 2730 dev_err(psp->adev->dev, 2731 "RAP: Failed to initialize RAP\n"); 2732 2733 ret = psp_securedisplay_initialize(psp); 2734 if (ret) 2735 dev_err(psp->adev->dev, 2736 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2737 } 2738 2739 mutex_unlock(&adev->firmware.mutex); 2740 2741 return 0; 2742 2743 failed: 2744 DRM_ERROR("PSP resume failed\n"); 2745 mutex_unlock(&adev->firmware.mutex); 2746 return ret; 2747 } 2748 2749 int psp_gpu_reset(struct amdgpu_device *adev) 2750 { 2751 int ret; 2752 2753 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2754 return 0; 2755 2756 mutex_lock(&adev->psp.mutex); 2757 ret = psp_mode1_reset(&adev->psp); 2758 mutex_unlock(&adev->psp.mutex); 2759 2760 return ret; 2761 } 2762 2763 int psp_rlc_autoload_start(struct psp_context *psp) 2764 { 2765 int ret; 2766 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2767 2768 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2769 2770 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2771 psp->fence_buf_mc_addr); 2772 2773 release_psp_cmd_buf(psp); 2774 2775 return ret; 2776 } 2777 2778 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2779 uint64_t cmd_gpu_addr, int cmd_size) 2780 { 2781 struct amdgpu_firmware_info ucode = {0}; 2782 2783 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2784 AMDGPU_UCODE_ID_VCN0_RAM; 2785 ucode.mc_addr = cmd_gpu_addr; 2786 ucode.ucode_size = cmd_size; 2787 2788 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2789 } 2790 2791 int psp_ring_cmd_submit(struct psp_context *psp, 2792 uint64_t cmd_buf_mc_addr, 2793 uint64_t fence_mc_addr, 2794 int index) 2795 { 2796 unsigned int psp_write_ptr_reg = 0; 2797 struct psp_gfx_rb_frame *write_frame; 2798 struct psp_ring *ring = &psp->km_ring; 2799 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2800 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2801 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2802 struct amdgpu_device *adev = psp->adev; 2803 uint32_t ring_size_dw = ring->ring_size / 4; 2804 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2805 2806 /* KM (GPCOM) prepare write pointer */ 2807 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2808 2809 /* Update KM RB frame pointer to new frame */ 2810 /* write_frame ptr increments by size of rb_frame in bytes */ 2811 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2812 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2813 write_frame = ring_buffer_start; 2814 else 2815 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2816 /* Check invalid write_frame ptr address */ 2817 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2818 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2819 ring_buffer_start, ring_buffer_end, write_frame); 2820 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2821 return -EINVAL; 2822 } 2823 2824 /* Initialize KM RB frame */ 2825 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2826 2827 /* Update KM RB frame */ 2828 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2829 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2830 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2831 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2832 write_frame->fence_value = index; 2833 amdgpu_device_flush_hdp(adev, NULL); 2834 2835 /* Update the write Pointer in DWORDs */ 2836 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2837 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2838 return 0; 2839 } 2840 2841 int psp_init_asd_microcode(struct psp_context *psp, 2842 const char *chip_name) 2843 { 2844 struct amdgpu_device *adev = psp->adev; 2845 char fw_name[PSP_FW_NAME_LEN]; 2846 const struct psp_firmware_header_v1_0 *asd_hdr; 2847 int err = 0; 2848 2849 if (!chip_name) { 2850 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2851 return -EINVAL; 2852 } 2853 2854 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2855 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2856 if (err) 2857 goto out; 2858 2859 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2860 if (err) 2861 goto out; 2862 2863 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2864 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2865 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2866 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2867 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2868 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2869 return 0; 2870 out: 2871 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2872 release_firmware(adev->psp.asd_fw); 2873 adev->psp.asd_fw = NULL; 2874 return err; 2875 } 2876 2877 int psp_init_toc_microcode(struct psp_context *psp, 2878 const char *chip_name) 2879 { 2880 struct amdgpu_device *adev = psp->adev; 2881 char fw_name[PSP_FW_NAME_LEN]; 2882 const struct psp_firmware_header_v1_0 *toc_hdr; 2883 int err = 0; 2884 2885 if (!chip_name) { 2886 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2887 return -EINVAL; 2888 } 2889 2890 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2891 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2892 if (err) 2893 goto out; 2894 2895 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2896 if (err) 2897 goto out; 2898 2899 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2900 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2901 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2902 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2903 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2904 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2905 return 0; 2906 out: 2907 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2908 release_firmware(adev->psp.toc_fw); 2909 adev->psp.toc_fw = NULL; 2910 return err; 2911 } 2912 2913 static int parse_sos_bin_descriptor(struct psp_context *psp, 2914 const struct psp_fw_bin_desc *desc, 2915 const struct psp_firmware_header_v2_0 *sos_hdr) 2916 { 2917 uint8_t *ucode_start_addr = NULL; 2918 2919 if (!psp || !desc || !sos_hdr) 2920 return -EINVAL; 2921 2922 ucode_start_addr = (uint8_t *)sos_hdr + 2923 le32_to_cpu(desc->offset_bytes) + 2924 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2925 2926 switch (desc->fw_type) { 2927 case PSP_FW_TYPE_PSP_SOS: 2928 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2929 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2930 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2931 psp->sos.start_addr = ucode_start_addr; 2932 break; 2933 case PSP_FW_TYPE_PSP_SYS_DRV: 2934 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2935 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2936 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2937 psp->sys.start_addr = ucode_start_addr; 2938 break; 2939 case PSP_FW_TYPE_PSP_KDB: 2940 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2941 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2942 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2943 psp->kdb.start_addr = ucode_start_addr; 2944 break; 2945 case PSP_FW_TYPE_PSP_TOC: 2946 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2947 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2948 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2949 psp->toc.start_addr = ucode_start_addr; 2950 break; 2951 case PSP_FW_TYPE_PSP_SPL: 2952 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2953 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2954 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2955 psp->spl.start_addr = ucode_start_addr; 2956 break; 2957 case PSP_FW_TYPE_PSP_RL: 2958 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 2959 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 2960 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 2961 psp->rl.start_addr = ucode_start_addr; 2962 break; 2963 case PSP_FW_TYPE_PSP_SOC_DRV: 2964 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 2965 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 2966 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2967 psp->soc_drv.start_addr = ucode_start_addr; 2968 break; 2969 case PSP_FW_TYPE_PSP_INTF_DRV: 2970 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 2971 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 2972 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2973 psp->intf_drv.start_addr = ucode_start_addr; 2974 break; 2975 case PSP_FW_TYPE_PSP_DBG_DRV: 2976 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 2977 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 2978 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 2979 psp->dbg_drv.start_addr = ucode_start_addr; 2980 break; 2981 default: 2982 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 2983 break; 2984 } 2985 2986 return 0; 2987 } 2988 2989 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 2990 { 2991 const struct psp_firmware_header_v1_0 *sos_hdr; 2992 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 2993 uint8_t *ucode_array_start_addr; 2994 2995 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 2996 ucode_array_start_addr = (uint8_t *)sos_hdr + 2997 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2998 2999 if (adev->gmc.xgmi.connected_to_cpu || 3000 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3001 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3002 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3003 3004 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3005 adev->psp.sys.start_addr = ucode_array_start_addr; 3006 3007 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3008 adev->psp.sos.start_addr = ucode_array_start_addr + 3009 le32_to_cpu(sos_hdr->sos.offset_bytes); 3010 adev->psp.xgmi_context.supports_extended_data = false; 3011 } else { 3012 /* Load alternate PSP SOS FW */ 3013 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3014 3015 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3016 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3017 3018 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3019 adev->psp.sys.start_addr = ucode_array_start_addr + 3020 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3021 3022 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3023 adev->psp.sos.start_addr = ucode_array_start_addr + 3024 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3025 adev->psp.xgmi_context.supports_extended_data = true; 3026 } 3027 3028 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3029 dev_warn(adev->dev, "PSP SOS FW not available"); 3030 return -EINVAL; 3031 } 3032 3033 return 0; 3034 } 3035 3036 int psp_init_sos_microcode(struct psp_context *psp, 3037 const char *chip_name) 3038 { 3039 struct amdgpu_device *adev = psp->adev; 3040 char fw_name[PSP_FW_NAME_LEN]; 3041 const struct psp_firmware_header_v1_0 *sos_hdr; 3042 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3043 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3044 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3045 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3046 int err = 0; 3047 uint8_t *ucode_array_start_addr; 3048 int fw_index = 0; 3049 3050 if (!chip_name) { 3051 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3052 return -EINVAL; 3053 } 3054 3055 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3056 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3057 if (err) 3058 goto out; 3059 3060 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3061 if (err) 3062 goto out; 3063 3064 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3065 ucode_array_start_addr = (uint8_t *)sos_hdr + 3066 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3067 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3068 3069 switch (sos_hdr->header.header_version_major) { 3070 case 1: 3071 err = psp_init_sos_base_fw(adev); 3072 if (err) 3073 goto out; 3074 3075 if (sos_hdr->header.header_version_minor == 1) { 3076 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3077 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3078 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3079 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3080 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3081 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3082 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3083 } 3084 if (sos_hdr->header.header_version_minor == 2) { 3085 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3086 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3087 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3088 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3089 } 3090 if (sos_hdr->header.header_version_minor == 3) { 3091 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3092 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3093 adev->psp.toc.start_addr = ucode_array_start_addr + 3094 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3095 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3096 adev->psp.kdb.start_addr = ucode_array_start_addr + 3097 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3098 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3099 adev->psp.spl.start_addr = ucode_array_start_addr + 3100 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3101 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3102 adev->psp.rl.start_addr = ucode_array_start_addr + 3103 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3104 } 3105 break; 3106 case 2: 3107 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3108 3109 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3110 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3111 err = -EINVAL; 3112 goto out; 3113 } 3114 3115 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3116 err = parse_sos_bin_descriptor(psp, 3117 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3118 sos_hdr_v2_0); 3119 if (err) 3120 goto out; 3121 } 3122 break; 3123 default: 3124 dev_err(adev->dev, 3125 "unsupported psp sos firmware\n"); 3126 err = -EINVAL; 3127 goto out; 3128 } 3129 3130 return 0; 3131 out: 3132 dev_err(adev->dev, 3133 "failed to init sos firmware\n"); 3134 release_firmware(adev->psp.sos_fw); 3135 adev->psp.sos_fw = NULL; 3136 3137 return err; 3138 } 3139 3140 static int parse_ta_bin_descriptor(struct psp_context *psp, 3141 const struct psp_fw_bin_desc *desc, 3142 const struct ta_firmware_header_v2_0 *ta_hdr) 3143 { 3144 uint8_t *ucode_start_addr = NULL; 3145 3146 if (!psp || !desc || !ta_hdr) 3147 return -EINVAL; 3148 3149 ucode_start_addr = (uint8_t *)ta_hdr + 3150 le32_to_cpu(desc->offset_bytes) + 3151 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3152 3153 switch (desc->fw_type) { 3154 case TA_FW_TYPE_PSP_ASD: 3155 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3156 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3157 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3158 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3159 break; 3160 case TA_FW_TYPE_PSP_XGMI: 3161 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3162 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3163 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3164 break; 3165 case TA_FW_TYPE_PSP_RAS: 3166 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3167 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3168 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3169 break; 3170 case TA_FW_TYPE_PSP_HDCP: 3171 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3172 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3173 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3174 break; 3175 case TA_FW_TYPE_PSP_DTM: 3176 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3177 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3178 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3179 break; 3180 case TA_FW_TYPE_PSP_RAP: 3181 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3182 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3183 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3184 break; 3185 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3186 psp->securedisplay_context.context.bin_desc.fw_version = 3187 le32_to_cpu(desc->fw_version); 3188 psp->securedisplay_context.context.bin_desc.size_bytes = 3189 le32_to_cpu(desc->size_bytes); 3190 psp->securedisplay_context.context.bin_desc.start_addr = 3191 ucode_start_addr; 3192 break; 3193 default: 3194 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3195 break; 3196 } 3197 3198 return 0; 3199 } 3200 3201 int psp_init_ta_microcode(struct psp_context *psp, 3202 const char *chip_name) 3203 { 3204 struct amdgpu_device *adev = psp->adev; 3205 char fw_name[PSP_FW_NAME_LEN]; 3206 const struct ta_firmware_header_v2_0 *ta_hdr; 3207 int err = 0; 3208 int ta_index = 0; 3209 3210 if (!chip_name) { 3211 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3212 return -EINVAL; 3213 } 3214 3215 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3216 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3217 if (err) 3218 goto out; 3219 3220 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3221 if (err) 3222 goto out; 3223 3224 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3225 3226 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3227 dev_err(adev->dev, "unsupported TA header version\n"); 3228 err = -EINVAL; 3229 goto out; 3230 } 3231 3232 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3233 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3234 err = -EINVAL; 3235 goto out; 3236 } 3237 3238 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3239 err = parse_ta_bin_descriptor(psp, 3240 &ta_hdr->ta_fw_bin[ta_index], 3241 ta_hdr); 3242 if (err) 3243 goto out; 3244 } 3245 3246 return 0; 3247 out: 3248 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3249 release_firmware(adev->psp.ta_fw); 3250 adev->psp.ta_fw = NULL; 3251 return err; 3252 } 3253 3254 int psp_init_cap_microcode(struct psp_context *psp, 3255 const char *chip_name) 3256 { 3257 struct amdgpu_device *adev = psp->adev; 3258 char fw_name[PSP_FW_NAME_LEN]; 3259 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3260 struct amdgpu_firmware_info *info = NULL; 3261 int err = 0; 3262 3263 if (!chip_name) { 3264 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3265 return -EINVAL; 3266 } 3267 3268 if (!amdgpu_sriov_vf(adev)) { 3269 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3270 return -EINVAL; 3271 } 3272 3273 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3274 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3275 if (err) { 3276 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3277 err = 0; 3278 goto out; 3279 } 3280 3281 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3282 if (err) { 3283 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3284 goto out; 3285 } 3286 3287 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3288 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3289 info->fw = adev->psp.cap_fw; 3290 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3291 adev->psp.cap_fw->data; 3292 adev->firmware.fw_size += ALIGN( 3293 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3294 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3295 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3296 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3297 3298 return 0; 3299 3300 out: 3301 release_firmware(adev->psp.cap_fw); 3302 adev->psp.cap_fw = NULL; 3303 return err; 3304 } 3305 3306 static int psp_set_clockgating_state(void *handle, 3307 enum amd_clockgating_state state) 3308 { 3309 return 0; 3310 } 3311 3312 static int psp_set_powergating_state(void *handle, 3313 enum amd_powergating_state state) 3314 { 3315 return 0; 3316 } 3317 3318 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3319 struct device_attribute *attr, 3320 char *buf) 3321 { 3322 struct drm_device *ddev = dev_get_drvdata(dev); 3323 struct amdgpu_device *adev = drm_to_adev(ddev); 3324 uint32_t fw_ver; 3325 int ret; 3326 3327 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3328 DRM_INFO("PSP block is not ready yet."); 3329 return -EBUSY; 3330 } 3331 3332 mutex_lock(&adev->psp.mutex); 3333 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3334 mutex_unlock(&adev->psp.mutex); 3335 3336 if (ret) { 3337 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3338 return ret; 3339 } 3340 3341 return sysfs_emit(buf, "%x\n", fw_ver); 3342 } 3343 3344 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3345 struct device_attribute *attr, 3346 const char *buf, 3347 size_t count) 3348 { 3349 struct drm_device *ddev = dev_get_drvdata(dev); 3350 struct amdgpu_device *adev = drm_to_adev(ddev); 3351 int ret, idx; 3352 char fw_name[100]; 3353 const struct firmware *usbc_pd_fw; 3354 struct amdgpu_bo *fw_buf_bo = NULL; 3355 uint64_t fw_pri_mc_addr; 3356 void *fw_pri_cpu_addr; 3357 3358 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3359 DRM_INFO("PSP block is not ready yet."); 3360 return -EBUSY; 3361 } 3362 3363 if (!drm_dev_enter(ddev, &idx)) 3364 return -ENODEV; 3365 3366 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3367 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3368 if (ret) 3369 goto fail; 3370 3371 /* LFB address which is aligned to 1MB boundary per PSP request */ 3372 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3373 AMDGPU_GEM_DOMAIN_VRAM, 3374 &fw_buf_bo, 3375 &fw_pri_mc_addr, 3376 &fw_pri_cpu_addr); 3377 if (ret) 3378 goto rel_buf; 3379 3380 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3381 3382 mutex_lock(&adev->psp.mutex); 3383 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3384 mutex_unlock(&adev->psp.mutex); 3385 3386 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3387 3388 rel_buf: 3389 release_firmware(usbc_pd_fw); 3390 fail: 3391 if (ret) { 3392 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3393 count = ret; 3394 } 3395 3396 drm_dev_exit(idx); 3397 return count; 3398 } 3399 3400 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3401 { 3402 int idx; 3403 3404 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3405 return; 3406 3407 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3408 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3409 3410 drm_dev_exit(idx); 3411 } 3412 3413 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3414 psp_usbc_pd_fw_sysfs_read, 3415 psp_usbc_pd_fw_sysfs_write); 3416 3417 int is_psp_fw_valid(struct psp_bin_desc bin) 3418 { 3419 return bin.size_bytes; 3420 } 3421 3422 const struct amd_ip_funcs psp_ip_funcs = { 3423 .name = "psp", 3424 .early_init = psp_early_init, 3425 .late_init = NULL, 3426 .sw_init = psp_sw_init, 3427 .sw_fini = psp_sw_fini, 3428 .hw_init = psp_hw_init, 3429 .hw_fini = psp_hw_fini, 3430 .suspend = psp_suspend, 3431 .resume = psp_resume, 3432 .is_idle = NULL, 3433 .check_soft_reset = NULL, 3434 .wait_for_idle = NULL, 3435 .soft_reset = NULL, 3436 .set_clockgating_state = psp_set_clockgating_state, 3437 .set_powergating_state = psp_set_powergating_state, 3438 }; 3439 3440 static int psp_sysfs_init(struct amdgpu_device *adev) 3441 { 3442 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3443 3444 if (ret) 3445 DRM_ERROR("Failed to create USBC PD FW control file!"); 3446 3447 return ret; 3448 } 3449 3450 static void psp_sysfs_fini(struct amdgpu_device *adev) 3451 { 3452 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3453 } 3454 3455 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3456 { 3457 .type = AMD_IP_BLOCK_TYPE_PSP, 3458 .major = 3, 3459 .minor = 1, 3460 .rev = 0, 3461 .funcs = &psp_ip_funcs, 3462 }; 3463 3464 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3465 { 3466 .type = AMD_IP_BLOCK_TYPE_PSP, 3467 .major = 10, 3468 .minor = 0, 3469 .rev = 0, 3470 .funcs = &psp_ip_funcs, 3471 }; 3472 3473 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3474 { 3475 .type = AMD_IP_BLOCK_TYPE_PSP, 3476 .major = 11, 3477 .minor = 0, 3478 .rev = 0, 3479 .funcs = &psp_ip_funcs, 3480 }; 3481 3482 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3483 .type = AMD_IP_BLOCK_TYPE_PSP, 3484 .major = 11, 3485 .minor = 0, 3486 .rev = 8, 3487 .funcs = &psp_ip_funcs, 3488 }; 3489 3490 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3491 { 3492 .type = AMD_IP_BLOCK_TYPE_PSP, 3493 .major = 12, 3494 .minor = 0, 3495 .rev = 0, 3496 .funcs = &psp_ip_funcs, 3497 }; 3498 3499 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3500 .type = AMD_IP_BLOCK_TYPE_PSP, 3501 .major = 13, 3502 .minor = 0, 3503 .rev = 0, 3504 .funcs = &psp_ip_funcs, 3505 }; 3506