1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 case IP_VERSION(15, 0, 5): 279 case IP_VERSION(15, 0, 9): 280 psp_v15_0_0_set_psp_funcs(psp); 281 psp->boot_time_tmr = false; 282 break; 283 case IP_VERSION(15, 0, 8): 284 psp_v15_0_8_set_psp_funcs(psp); 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 psp->adev = adev; 291 292 adev->psp_timeout = 20000; 293 294 psp_check_pmfw_centralized_cstate_management(psp); 295 296 if (amdgpu_sriov_vf(adev)) 297 return psp_init_sriov_microcode(psp); 298 else 299 return psp_init_microcode(psp); 300 } 301 302 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 303 { 304 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 305 &mem_ctx->shared_buf); 306 mem_ctx->shared_bo = NULL; 307 } 308 309 static void psp_free_shared_bufs(struct psp_context *psp) 310 { 311 void *tmr_buf; 312 void **pptr; 313 314 /* free TMR memory buffer */ 315 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 316 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 317 psp->tmr_bo = NULL; 318 319 /* free xgmi shared memory */ 320 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 321 322 /* free ras shared memory */ 323 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 324 325 /* free hdcp shared memory */ 326 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 327 328 /* free dtm shared memory */ 329 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 330 331 /* free rap shared memory */ 332 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 333 334 /* free securedisplay shared memory */ 335 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 336 337 338 } 339 340 static void psp_memory_training_fini(struct psp_context *psp) 341 { 342 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 343 344 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 345 kfree(ctx->sys_cache); 346 ctx->sys_cache = NULL; 347 } 348 349 static int psp_memory_training_init(struct psp_context *psp) 350 { 351 int ret; 352 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 353 354 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 355 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 356 return 0; 357 } 358 359 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 360 if (ctx->sys_cache == NULL) { 361 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 362 ret = -ENOMEM; 363 goto Err_out; 364 } 365 366 dev_dbg(psp->adev->dev, 367 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 368 ctx->train_data_size, 369 ctx->p2c_train_data_offset, 370 ctx->c2p_train_data_offset); 371 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 372 return 0; 373 374 Err_out: 375 psp_memory_training_fini(psp); 376 return ret; 377 } 378 379 /* 380 * Helper funciton to query psp runtime database entry 381 * 382 * @adev: amdgpu_device pointer 383 * @entry_type: the type of psp runtime database entry 384 * @db_entry: runtime database entry pointer 385 * 386 * Return false if runtime database doesn't exit or entry is invalid 387 * or true if the specific database entry is found, and copy to @db_entry 388 */ 389 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 390 enum psp_runtime_entry_type entry_type, 391 void *db_entry) 392 { 393 uint64_t db_header_pos, db_dir_pos; 394 struct psp_runtime_data_header db_header = {0}; 395 struct psp_runtime_data_directory db_dir = {0}; 396 bool ret = false; 397 int i; 398 399 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 401 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 402 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 403 return false; 404 405 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 406 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 407 408 /* read runtime db header from vram */ 409 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 410 sizeof(struct psp_runtime_data_header), false); 411 412 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 413 /* runtime db doesn't exist, exit */ 414 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 415 return false; 416 } 417 418 /* read runtime database entry from vram */ 419 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 420 sizeof(struct psp_runtime_data_directory), false); 421 422 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 423 /* invalid db entry count, exit */ 424 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 425 return false; 426 } 427 428 /* look up for requested entry type */ 429 for (i = 0; i < db_dir.entry_count && !ret; i++) { 430 if (db_dir.entry_list[i].entry_type == entry_type) { 431 switch (entry_type) { 432 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 433 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 434 /* invalid db entry size */ 435 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 436 return false; 437 } 438 /* read runtime database entry */ 439 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 440 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 441 ret = true; 442 break; 443 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 444 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 445 /* invalid db entry size */ 446 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 447 return false; 448 } 449 /* read runtime database entry */ 450 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 451 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 452 ret = true; 453 break; 454 default: 455 ret = false; 456 break; 457 } 458 } 459 } 460 461 return ret; 462 } 463 464 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 465 { 466 struct amdgpu_device *adev = ip_block->adev; 467 struct psp_context *psp = &adev->psp; 468 int ret; 469 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 470 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 471 struct psp_runtime_scpm_entry scpm_entry; 472 473 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 474 if (!psp->cmd) { 475 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 476 return -ENOMEM; 477 } 478 479 adev->psp.xgmi_context.supports_extended_data = 480 !adev->gmc.xgmi.connected_to_cpu && 481 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 482 483 memset(&scpm_entry, 0, sizeof(scpm_entry)); 484 if ((psp_get_runtime_db_entry(adev, 485 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 486 &scpm_entry)) && 487 (scpm_entry.scpm_status != SCPM_DISABLE)) { 488 adev->scpm_enabled = true; 489 adev->scpm_status = scpm_entry.scpm_status; 490 } else { 491 adev->scpm_enabled = false; 492 adev->scpm_status = SCPM_DISABLE; 493 } 494 495 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 496 497 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 498 if (psp_get_runtime_db_entry(adev, 499 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 500 &boot_cfg_entry)) { 501 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 502 if ((psp->boot_cfg_bitmask) & 503 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 504 /* If psp runtime database exists, then 505 * only enable two stage memory training 506 * when TWO_STAGE_DRAM_TRAINING bit is set 507 * in runtime database 508 */ 509 mem_training_ctx->enable_mem_training = true; 510 } 511 512 } else { 513 /* If psp runtime database doesn't exist or is 514 * invalid, force enable two stage memory training 515 */ 516 mem_training_ctx->enable_mem_training = true; 517 } 518 519 if (mem_training_ctx->enable_mem_training) { 520 ret = psp_memory_training_init(psp); 521 if (ret) { 522 dev_err(adev->dev, "Failed to initialize memory training!\n"); 523 return ret; 524 } 525 526 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 527 if (ret) { 528 dev_err(adev->dev, "Failed to process memory training!\n"); 529 return ret; 530 } 531 } 532 533 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 534 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 535 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 536 &psp->fw_pri_bo, 537 &psp->fw_pri_mc_addr, 538 &psp->fw_pri_buf); 539 if (ret) 540 return ret; 541 542 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 543 AMDGPU_GEM_DOMAIN_VRAM | 544 AMDGPU_GEM_DOMAIN_GTT, 545 &psp->fence_buf_bo, 546 &psp->fence_buf_mc_addr, 547 &psp->fence_buf); 548 if (ret) 549 goto failed1; 550 551 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 552 AMDGPU_GEM_DOMAIN_VRAM | 553 AMDGPU_GEM_DOMAIN_GTT, 554 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 555 (void **)&psp->cmd_buf_mem); 556 if (ret) 557 goto failed2; 558 559 return 0; 560 561 failed2: 562 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 563 &psp->fence_buf_mc_addr, &psp->fence_buf); 564 failed1: 565 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 566 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 567 return ret; 568 } 569 570 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 571 { 572 struct amdgpu_device *adev = ip_block->adev; 573 struct psp_context *psp = &adev->psp; 574 575 psp_memory_training_fini(psp); 576 577 amdgpu_ucode_release(&psp->sos_fw); 578 amdgpu_ucode_release(&psp->asd_fw); 579 amdgpu_ucode_release(&psp->ta_fw); 580 amdgpu_ucode_release(&psp->cap_fw); 581 amdgpu_ucode_release(&psp->toc_fw); 582 583 kfree(psp->cmd); 584 psp->cmd = NULL; 585 586 psp_free_shared_bufs(psp); 587 588 if (psp->km_ring.ring_mem) 589 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 590 &psp->km_ring.ring_mem_mc_addr, 591 (void **)&psp->km_ring.ring_mem); 592 593 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 594 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 595 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 596 &psp->fence_buf_mc_addr, &psp->fence_buf); 597 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 598 (void **)&psp->cmd_buf_mem); 599 600 return 0; 601 } 602 603 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 604 uint32_t mask, uint32_t flags) 605 { 606 bool check_changed = flags & PSP_WAITREG_CHANGED; 607 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 608 uint32_t val; 609 int i; 610 struct amdgpu_device *adev = psp->adev; 611 612 if (psp->adev->no_hw_access) 613 return 0; 614 615 for (i = 0; i < adev->usec_timeout; i++) { 616 val = RREG32(reg_index); 617 if (check_changed) { 618 if (val != reg_val) 619 return 0; 620 } else { 621 if ((val & mask) == reg_val) 622 return 0; 623 } 624 udelay(1); 625 } 626 627 if (verbose) 628 dev_err(adev->dev, 629 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 630 reg_index, mask, val, reg_val); 631 632 return -ETIME; 633 } 634 635 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 636 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 637 { 638 uint32_t val; 639 int i; 640 struct amdgpu_device *adev = psp->adev; 641 642 if (psp->adev->no_hw_access) 643 return 0; 644 645 for (i = 0; i < msec_timeout; i++) { 646 val = RREG32(reg_index); 647 if ((val & mask) == reg_val) 648 return 0; 649 msleep(1); 650 } 651 652 return -ETIME; 653 } 654 655 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 656 { 657 switch (cmd_id) { 658 case GFX_CMD_ID_LOAD_TA: 659 return "LOAD_TA"; 660 case GFX_CMD_ID_UNLOAD_TA: 661 return "UNLOAD_TA"; 662 case GFX_CMD_ID_INVOKE_CMD: 663 return "INVOKE_CMD"; 664 case GFX_CMD_ID_LOAD_ASD: 665 return "LOAD_ASD"; 666 case GFX_CMD_ID_SETUP_TMR: 667 return "SETUP_TMR"; 668 case GFX_CMD_ID_LOAD_IP_FW: 669 return "LOAD_IP_FW"; 670 case GFX_CMD_ID_DESTROY_TMR: 671 return "DESTROY_TMR"; 672 case GFX_CMD_ID_SAVE_RESTORE: 673 return "SAVE_RESTORE_IP_FW"; 674 case GFX_CMD_ID_SETUP_VMR: 675 return "SETUP_VMR"; 676 case GFX_CMD_ID_DESTROY_VMR: 677 return "DESTROY_VMR"; 678 case GFX_CMD_ID_PROG_REG: 679 return "PROG_REG"; 680 case GFX_CMD_ID_GET_FW_ATTESTATION: 681 return "GET_FW_ATTESTATION"; 682 case GFX_CMD_ID_LOAD_TOC: 683 return "ID_LOAD_TOC"; 684 case GFX_CMD_ID_AUTOLOAD_RLC: 685 return "AUTOLOAD_RLC"; 686 case GFX_CMD_ID_BOOT_CFG: 687 return "BOOT_CFG"; 688 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 689 return "CONFIG_SQ_PERFMON"; 690 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 691 return "FB_FW_RESERV_ADDR"; 692 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 693 return "FB_FW_RESERV_EXT_ADDR"; 694 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 695 return "SPATIAL_PARTITION"; 696 case GFX_CMD_ID_FB_NPS_MODE: 697 return "NPS_MODE_CHANGE"; 698 case GFX_CMD_ID_PERF_HW: 699 return "PERF MONITORING HW"; 700 default: 701 return "UNKNOWN CMD"; 702 } 703 } 704 705 static bool psp_err_warn(struct psp_context *psp) 706 { 707 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 708 709 /* This response indicates reg list is already loaded */ 710 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 711 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 712 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 713 cmd->resp.status == TEE_ERROR_CANCEL) 714 return false; 715 716 return true; 717 } 718 719 static int 720 psp_cmd_submit_buf(struct psp_context *psp, 721 struct amdgpu_firmware_info *ucode, 722 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 723 { 724 int ret; 725 int index; 726 int timeout = psp->adev->psp_timeout; 727 bool ras_intr = false; 728 bool skip_unsupport = false; 729 730 if (psp->adev->no_hw_access) 731 return 0; 732 733 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 734 735 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 736 737 index = atomic_inc_return(&psp->fence_value); 738 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 739 if (ret) { 740 atomic_dec(&psp->fence_value); 741 goto exit; 742 } 743 744 amdgpu_device_invalidate_hdp(psp->adev, NULL); 745 while (*((unsigned int *)psp->fence_buf) != index) { 746 if (--timeout == 0) 747 break; 748 /* 749 * Shouldn't wait for timeout when err_event_athub occurs, 750 * because gpu reset thread triggered and lock resource should 751 * be released for psp resume sequence. 752 */ 753 ras_intr = amdgpu_ras_intr_triggered(); 754 if (ras_intr) 755 break; 756 usleep_range(60, 100); 757 amdgpu_device_invalidate_hdp(psp->adev, NULL); 758 } 759 760 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 761 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 762 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 763 764 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 765 766 /* In some cases, psp response status is not 0 even there is no 767 * problem while the command is submitted. Some version of PSP FW 768 * doesn't write 0 to that field. 769 * So here we would like to only print a warning instead of an error 770 * during psp initialization to avoid breaking hw_init and it doesn't 771 * return -EINVAL. 772 */ 773 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 774 if (ucode) 775 dev_warn(psp->adev->dev, 776 "failed to load ucode %s(0x%X) ", 777 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 778 if (psp_err_warn(psp)) 779 dev_warn( 780 psp->adev->dev, 781 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 782 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 783 psp->cmd_buf_mem->cmd_id, 784 psp->cmd_buf_mem->resp.status); 785 /* If any firmware (including CAP) load fails under SRIOV, it should 786 * return failure to stop the VF from initializing. 787 * Also return failure in case of timeout 788 */ 789 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 790 ret = -EINVAL; 791 goto exit; 792 } 793 } 794 795 if (ucode) { 796 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 797 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 798 } 799 800 exit: 801 return ret; 802 } 803 804 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 805 { 806 struct psp_gfx_cmd_resp *cmd = psp->cmd; 807 808 mutex_lock(&psp->mutex); 809 810 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 811 812 return cmd; 813 } 814 815 static void release_psp_cmd_buf(struct psp_context *psp) 816 { 817 mutex_unlock(&psp->mutex); 818 } 819 820 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 821 struct psp_gfx_cmd_resp *cmd, 822 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 823 { 824 struct amdgpu_device *adev = psp->adev; 825 uint32_t size = 0; 826 uint64_t tmr_pa = 0; 827 828 if (tmr_bo) { 829 size = amdgpu_bo_size(tmr_bo); 830 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 831 } 832 833 if (amdgpu_sriov_vf(psp->adev)) 834 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 835 else 836 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 837 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 838 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 839 cmd->cmd.cmd_setup_tmr.buf_size = size; 840 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 841 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 842 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 843 } 844 845 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 846 uint64_t pri_buf_mc, uint32_t size) 847 { 848 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 849 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 850 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 851 cmd->cmd.cmd_load_toc.toc_size = size; 852 } 853 854 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 855 static int psp_load_toc(struct psp_context *psp, 856 uint32_t *tmr_size) 857 { 858 int ret; 859 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 860 861 /* Copy toc to psp firmware private buffer */ 862 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 863 if (ret) { 864 release_psp_cmd_buf(psp); 865 return ret; 866 } 867 868 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 869 870 ret = psp_cmd_submit_buf(psp, NULL, cmd, 871 psp->fence_buf_mc_addr); 872 if (!ret) 873 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 874 875 release_psp_cmd_buf(psp); 876 877 return ret; 878 } 879 880 /* Set up Trusted Memory Region */ 881 static int psp_tmr_init(struct psp_context *psp) 882 { 883 int ret = 0; 884 int tmr_size; 885 void *tmr_buf; 886 void **pptr; 887 888 /* 889 * According to HW engineer, they prefer the TMR address be "naturally 890 * aligned" , e.g. the start address be an integer divide of TMR size. 891 * 892 * Note: this memory need be reserved till the driver 893 * uninitializes. 894 */ 895 tmr_size = PSP_TMR_SIZE(psp->adev); 896 897 /* For ASICs support RLC autoload, psp will parse the toc 898 * and calculate the total size of TMR needed 899 */ 900 if (!amdgpu_sriov_vf(psp->adev) && 901 psp->toc.start_addr && 902 psp->toc.size_bytes && 903 psp->fw_pri_buf) { 904 ret = psp_load_toc(psp, &tmr_size); 905 if (ret) { 906 dev_err(psp->adev->dev, "Failed to load toc\n"); 907 return ret; 908 } 909 } 910 911 if (!psp->tmr_bo && !psp->boot_time_tmr) { 912 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 913 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 914 PSP_TMR_ALIGNMENT, 915 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 916 &psp->tmr_bo, &psp->tmr_mc_addr, 917 pptr); 918 } 919 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 920 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 921 922 return ret; 923 } 924 925 static bool psp_skip_tmr(struct psp_context *psp) 926 { 927 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 928 929 if (amdgpu_sriov_vf(psp->adev)) 930 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 931 else 932 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 933 } 934 935 static int psp_tmr_load(struct psp_context *psp) 936 { 937 int ret; 938 struct psp_gfx_cmd_resp *cmd; 939 940 if (psp_skip_tmr(psp)) 941 return 0; 942 943 cmd = acquire_psp_cmd_buf(psp); 944 945 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 946 if (psp->tmr_bo) 947 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 948 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 949 950 ret = psp_cmd_submit_buf(psp, NULL, cmd, 951 psp->fence_buf_mc_addr); 952 953 release_psp_cmd_buf(psp); 954 955 return ret; 956 } 957 958 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 959 struct psp_gfx_cmd_resp *cmd) 960 { 961 if (amdgpu_sriov_vf(psp->adev)) 962 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 963 else 964 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 965 } 966 967 static int psp_tmr_unload(struct psp_context *psp) 968 { 969 int ret; 970 struct psp_gfx_cmd_resp *cmd; 971 972 if (psp_skip_tmr(psp)) 973 return 0; 974 975 cmd = acquire_psp_cmd_buf(psp); 976 977 psp_prep_tmr_unload_cmd_buf(psp, cmd); 978 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 979 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, 981 psp->fence_buf_mc_addr); 982 983 release_psp_cmd_buf(psp); 984 985 return ret; 986 } 987 988 static int psp_tmr_terminate(struct psp_context *psp) 989 { 990 return psp_tmr_unload(psp); 991 } 992 993 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 994 uint64_t *output_ptr) 995 { 996 int ret; 997 struct psp_gfx_cmd_resp *cmd; 998 999 if (!output_ptr) 1000 return -EINVAL; 1001 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 cmd = acquire_psp_cmd_buf(psp); 1006 1007 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1008 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1010 psp->fence_buf_mc_addr); 1011 1012 if (!ret) { 1013 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1014 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1015 } 1016 1017 release_psp_cmd_buf(psp); 1018 1019 return ret; 1020 } 1021 1022 static int psp_get_fw_reservation_info(struct psp_context *psp, 1023 uint32_t cmd_id, 1024 uint64_t *addr, 1025 uint32_t *size) 1026 { 1027 int ret; 1028 uint32_t status; 1029 struct psp_gfx_cmd_resp *cmd; 1030 1031 cmd = acquire_psp_cmd_buf(psp); 1032 1033 cmd->cmd_id = cmd_id; 1034 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1036 psp->fence_buf_mc_addr); 1037 if (ret) { 1038 release_psp_cmd_buf(psp); 1039 return ret; 1040 } 1041 1042 status = cmd->resp.status; 1043 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1044 release_psp_cmd_buf(psp); 1045 *addr = 0; 1046 *size = 0; 1047 return 0; 1048 } 1049 1050 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1051 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1052 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1053 1054 release_psp_cmd_buf(psp); 1055 1056 return 0; 1057 } 1058 1059 int psp_update_fw_reservation(struct psp_context *psp) 1060 { 1061 int ret; 1062 uint64_t reserv_addr, reserv_addr_ext; 1063 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1064 struct amdgpu_device *adev = psp->adev; 1065 1066 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1067 1068 if (amdgpu_sriov_vf(psp->adev)) 1069 return 0; 1070 1071 switch (mp0_ip_ver) { 1072 case IP_VERSION(14, 0, 2): 1073 if (adev->psp.sos.fw_version < 0x3b0e0d) 1074 return 0; 1075 break; 1076 1077 case IP_VERSION(14, 0, 3): 1078 if (adev->psp.sos.fw_version < 0x3a0e14) 1079 return 0; 1080 break; 1081 1082 default: 1083 return 0; 1084 } 1085 1086 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1087 if (ret) 1088 return ret; 1089 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1090 if (ret) 1091 return ret; 1092 1093 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1094 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1095 return 0; 1096 } 1097 1098 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1099 1100 reserv_size = roundup(reserv_size, SZ_1M); 1101 1102 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1103 reserv_addr, reserv_size, false); 1104 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1105 if (ret) { 1106 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1107 return ret; 1108 } 1109 1110 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1111 1112 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1113 reserv_addr_ext, reserv_size_ext, false); 1114 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1115 if (ret) { 1116 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1124 { 1125 struct psp_context *psp = &adev->psp; 1126 struct psp_gfx_cmd_resp *cmd; 1127 int ret; 1128 1129 if (amdgpu_sriov_vf(adev)) 1130 return 0; 1131 1132 cmd = acquire_psp_cmd_buf(psp); 1133 1134 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1135 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1136 1137 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1138 if (!ret) { 1139 *boot_cfg = 1140 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1141 } 1142 1143 release_psp_cmd_buf(psp); 1144 1145 return ret; 1146 } 1147 1148 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1149 { 1150 int ret; 1151 struct psp_context *psp = &adev->psp; 1152 struct psp_gfx_cmd_resp *cmd; 1153 1154 if (amdgpu_sriov_vf(adev)) 1155 return 0; 1156 1157 cmd = acquire_psp_cmd_buf(psp); 1158 1159 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1160 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1161 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1162 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1163 1164 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1165 1166 release_psp_cmd_buf(psp); 1167 1168 return ret; 1169 } 1170 1171 static int psp_rl_load(struct amdgpu_device *adev) 1172 { 1173 int ret; 1174 struct psp_context *psp = &adev->psp; 1175 struct psp_gfx_cmd_resp *cmd; 1176 1177 if (!is_psp_fw_valid(psp->rl)) 1178 return 0; 1179 1180 cmd = acquire_psp_cmd_buf(psp); 1181 1182 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1183 if (ret) { 1184 release_psp_cmd_buf(psp); 1185 return ret; 1186 } 1187 1188 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1189 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1190 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1191 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1192 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1195 1196 release_psp_cmd_buf(psp); 1197 1198 return ret; 1199 } 1200 1201 int psp_memory_partition(struct psp_context *psp, int mode) 1202 { 1203 struct psp_gfx_cmd_resp *cmd; 1204 int ret; 1205 1206 if (amdgpu_sriov_vf(psp->adev)) 1207 return 0; 1208 1209 cmd = acquire_psp_cmd_buf(psp); 1210 1211 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1212 cmd->cmd.cmd_memory_part.mode = mode; 1213 1214 dev_info(psp->adev->dev, 1215 "Requesting %d memory partition change through PSP", mode); 1216 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1217 if (ret) 1218 dev_err(psp->adev->dev, 1219 "PSP request failed to change to NPS%d mode\n", mode); 1220 1221 release_psp_cmd_buf(psp); 1222 1223 return ret; 1224 } 1225 1226 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 1227 { 1228 int ret; 1229 struct psp_context *psp = &adev->psp; 1230 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1231 1232 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL; 1233 1234 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1235 if (ret) { 1236 dev_err(psp->adev->dev, 1237 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret); 1238 release_psp_cmd_buf(psp); 1239 return ret; 1240 } 1241 1242 if (cmd->resp.status) { 1243 dev_err(psp->adev->dev, 1244 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n", 1245 cmd->cmd_id, cmd->resp.status); 1246 ret = -EIO; 1247 } 1248 release_psp_cmd_buf(psp); 1249 1250 return ret; 1251 } 1252 1253 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1254 uint32_t *ptl_fmt) 1255 { 1256 struct amdgpu_device *adev = psp->adev; 1257 1258 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1259 return -EINVAL; 1260 1261 switch (fmt) { 1262 case AMDGPU_PTL_FMT_I8: 1263 *ptl_fmt = GFX_FTYPE_I8; 1264 break; 1265 case AMDGPU_PTL_FMT_F16: 1266 *ptl_fmt = GFX_FTYPE_F16; 1267 break; 1268 case AMDGPU_PTL_FMT_BF16: 1269 *ptl_fmt = GFX_FTYPE_BF16; 1270 break; 1271 case AMDGPU_PTL_FMT_F32: 1272 *ptl_fmt = GFX_FTYPE_F32; 1273 break; 1274 case AMDGPU_PTL_FMT_F64: 1275 *ptl_fmt = GFX_FTYPE_F64; 1276 break; 1277 case AMDGPU_PTL_FMT_F8: 1278 *ptl_fmt = GFX_FTYPE_F8; 1279 break; 1280 case AMDGPU_PTL_FMT_VECTOR: 1281 *ptl_fmt = GFX_FTYPE_VECTOR; 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1291 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1292 { 1293 struct psp_gfx_cmd_resp *cmd; 1294 struct amdgpu_ptl *ptl = &psp->ptl; 1295 struct amdgpu_device *adev = psp->adev; 1296 int ret; 1297 1298 if (amdgpu_sriov_vf(adev)) { 1299 ret = amdgpu_virt_ptl_request(adev, req_code, ptl_state, fmt1, fmt2); 1300 if (!ret) { 1301 ptl->enabled = *ptl_state; 1302 ptl->fmt1 = *fmt1; 1303 ptl->fmt2 = *fmt2; 1304 } 1305 return ret; 1306 } 1307 1308 cmd = acquire_psp_cmd_buf(psp); 1309 1310 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1311 cmd->cmd.cmd_req_perf_hw.req = req_code; 1312 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1313 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1314 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1315 1316 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1317 if (ret) 1318 goto out; 1319 1320 /* 1321 * Check response status explicitly to avoid 1322 * updating cached PTL state with invalid data. 1323 */ 1324 if (cmd->resp.status) { 1325 dev_err(psp->adev->dev, 1326 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1327 req_code, cmd->resp.status, 1328 cmd->resp.uresp.perf_hw_info.resp); 1329 ret = -EIO; 1330 goto out; 1331 } 1332 1333 /* Parse response */ 1334 switch (req_code) { 1335 case PSP_PTL_PERF_MON_QUERY: 1336 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1337 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1338 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1339 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1340 *ptl_state, *fmt1, *fmt2); 1341 break; 1342 case PSP_PTL_PERF_MON_SET: 1343 /* Update cached state only on success */ 1344 ptl->enabled = *ptl_state; 1345 ptl->fmt1 = *fmt1; 1346 ptl->fmt2 = *fmt2; 1347 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1348 *ptl_state, *fmt1, *fmt2); 1349 break; 1350 } 1351 1352 out: 1353 release_psp_cmd_buf(psp); 1354 return ret; 1355 } 1356 1357 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1358 uint32_t *ptl_state, 1359 enum amdgpu_ptl_fmt *fmt1, 1360 enum amdgpu_ptl_fmt *fmt2) 1361 { 1362 uint32_t ptl_fmt1, ptl_fmt2; 1363 struct psp_context *psp; 1364 struct amdgpu_ptl *ptl; 1365 int ret; 1366 1367 if (!adev || !ptl_state || !fmt1 || !fmt2) 1368 return -EINVAL; 1369 1370 psp = &adev->psp; 1371 ptl = &psp->ptl; 1372 1373 if (ptl->permanently_disabled && *ptl_state == 1) 1374 return 0; 1375 1376 if (amdgpu_sriov_vf(adev)) { 1377 ptl_fmt1 = *fmt1; 1378 ptl_fmt2 = *fmt2; 1379 return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1380 } 1381 1382 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1383 psp->sos.fw_version < 0x0036081a) 1384 return -EOPNOTSUPP; 1385 1386 /* Verify formats */ 1387 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1388 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1389 return -EINVAL; 1390 1391 /* 1392 * Add check to skip if state and formats are identical to current ones 1393 */ 1394 if (req_code == PSP_PTL_PERF_MON_SET && 1395 ptl->enabled == *ptl_state && 1396 ptl->fmt1 == ptl_fmt1 && 1397 ptl->fmt2 == ptl_fmt2) 1398 return 0; 1399 1400 /* If enabling PTL, check disable bitmap */ 1401 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1402 if (!bitmap_empty(ptl->disable_bitmap, 1403 AMDGPU_PTL_DISABLE_MAX)) { 1404 dev_dbg(adev->dev, 1405 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1406 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1407 ptl->disable_bitmap), 1408 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1409 ptl->disable_bitmap), 1410 atomic_read(&ptl->disable_ref)); 1411 return 0; 1412 } 1413 } 1414 1415 if (req_code == PSP_PTL_PERF_MON_SET) { 1416 amdgpu_amdkfd_stop_sched_all(adev); 1417 /* Wait for GFX engine idle before PTL state transition */ 1418 ret = amdgpu_device_ip_wait_for_idle(adev, 1419 AMD_IP_BLOCK_TYPE_GFX); 1420 if (ret) { 1421 amdgpu_amdkfd_start_sched_all(adev); 1422 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1423 return ret; 1424 } 1425 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1426 amdgpu_amdkfd_start_sched_all(adev); 1427 } else { 1428 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1429 } 1430 1431 return ret; 1432 } 1433 1434 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1435 { 1436 int i; 1437 1438 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1439 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1440 return (enum amdgpu_ptl_fmt)i; 1441 } 1442 1443 return AMDGPU_PTL_FMT_INVALID; 1444 } 1445 1446 static ssize_t ptl_supported_formats_show(struct device *dev, 1447 struct device_attribute *attr, char *buf) 1448 { 1449 ssize_t len = 0; 1450 1451 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1452 const char *fmt = amdgpu_ptl_fmt_str[i]; 1453 1454 len += sysfs_emit_at(buf, len, "%s%s", 1455 fmt ? fmt : "UNKNOWN", 1456 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1457 } 1458 1459 return len; 1460 } 1461 1462 static ssize_t ptl_enable_store(struct device *dev, 1463 struct device_attribute *attr, 1464 const char *buf, size_t count) 1465 { 1466 struct drm_device *ddev = dev_get_drvdata(dev); 1467 struct amdgpu_device *adev = drm_to_adev(ddev); 1468 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1469 uint32_t ptl_state, fmt1, fmt2; 1470 int ret; 1471 bool enable; 1472 bool bit_changed = false; 1473 1474 mutex_lock(&ptl->mutex); 1475 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1476 enable = true; 1477 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1478 enable = false; 1479 } else { 1480 mutex_unlock(&ptl->mutex); 1481 return -EINVAL; 1482 } 1483 1484 /* Block enable when permanently disabled */ 1485 if (ptl->permanently_disabled) { 1486 mutex_unlock(&ptl->mutex); 1487 return -EPERM; 1488 } 1489 1490 fmt1 = ptl->fmt1; 1491 fmt2 = ptl->fmt2; 1492 ptl_state = enable ? 1 : 0; 1493 1494 if (enable) 1495 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1496 ptl->disable_bitmap); 1497 1498 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1499 if (ret) { 1500 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1501 if (enable && bit_changed) 1502 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1503 mutex_unlock(&ptl->mutex); 1504 return ret; 1505 } 1506 1507 if (!enable) 1508 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1509 1510 mutex_unlock(&ptl->mutex); 1511 1512 return count; 1513 } 1514 1515 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1516 { 1517 struct drm_device *ddev = dev_get_drvdata(dev); 1518 struct amdgpu_device *adev = drm_to_adev(ddev); 1519 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1520 uint32_t ptl_state, fmt1, fmt2; 1521 int ret; 1522 1523 if (amdgpu_sriov_vf(adev)) { 1524 ptl_state = ptl->enabled; 1525 fmt1 = ptl->fmt1; 1526 fmt2 = ptl->fmt2; 1527 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, 1528 &ptl_state, &fmt1, &fmt2); 1529 if (ret) 1530 return ret; 1531 } 1532 1533 if (ptl->permanently_disabled) 1534 return sysfs_emit(buf, "permanently disabled\n"); 1535 1536 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1537 } 1538 1539 static ssize_t ptl_format_store(struct device *dev, 1540 struct device_attribute *attr, 1541 const char *buf, size_t count) 1542 { 1543 struct drm_device *ddev = dev_get_drvdata(dev); 1544 struct amdgpu_device *adev = drm_to_adev(ddev); 1545 char fmt1_str[8], fmt2_str[8]; 1546 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1547 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1548 uint32_t ptl_state, fmt1, fmt2; 1549 int ret; 1550 1551 /* Only allow format update when PTL is enabled */ 1552 if (!ptl->enabled) 1553 return -EPERM; 1554 1555 mutex_lock(&ptl->mutex); 1556 /* Parse input, expecting "FMT1,FMT2" */ 1557 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1558 mutex_unlock(&ptl->mutex); 1559 return -EINVAL; 1560 } 1561 1562 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1563 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1564 1565 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1566 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1567 fmt1_enum == fmt2_enum) { 1568 mutex_unlock(&ptl->mutex); 1569 return -EINVAL; 1570 } 1571 1572 ptl_state = ptl->enabled; 1573 fmt1 = fmt1_enum; 1574 fmt2 = fmt2_enum; 1575 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1576 if (ret) { 1577 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1578 mutex_unlock(&ptl->mutex); 1579 return ret; 1580 } 1581 mutex_unlock(&ptl->mutex); 1582 1583 return count; 1584 } 1585 1586 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1587 { 1588 struct drm_device *ddev = dev_get_drvdata(dev); 1589 struct amdgpu_device *adev = drm_to_adev(ddev); 1590 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1591 uint32_t ptl_state, fmt1, fmt2; 1592 int ret; 1593 1594 if (amdgpu_sriov_vf(adev)) { 1595 ptl_state = ptl->enabled; 1596 fmt1 = ptl->fmt1; 1597 fmt2 = ptl->fmt2; 1598 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, 1599 &ptl_state, &fmt1, &fmt2); 1600 if (ret) 1601 return ret; 1602 } 1603 1604 return sysfs_emit(buf, "%s,%s\n", 1605 amdgpu_ptl_fmt_str[ptl->fmt1], 1606 amdgpu_ptl_fmt_str[ptl->fmt2]); 1607 } 1608 1609 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1610 { 1611 struct device *dev = kobj_to_dev(kobj); 1612 struct drm_device *ddev = dev_get_drvdata(dev); 1613 struct amdgpu_device *adev = drm_to_adev(ddev); 1614 1615 /* Only show PTL sysfs files if PTL hardware is supported */ 1616 if (adev->psp.ptl.hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1617 return 0; 1618 1619 return attr->mode; 1620 } 1621 1622 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1623 { 1624 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1625 int ret; 1626 1627 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1628 return 0; 1629 1630 if (ptl->ptl_sysfs_created) 1631 return 0; 1632 1633 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1634 if (!ret) 1635 ptl->ptl_sysfs_created = true; 1636 1637 return ret; 1638 } 1639 1640 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1641 { 1642 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1643 1644 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 1645 return; 1646 1647 if (!ptl->ptl_sysfs_created) 1648 return; 1649 1650 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1651 ptl->ptl_sysfs_created = false; 1652 } 1653 1654 int psp_spatial_partition(struct psp_context *psp, int mode) 1655 { 1656 struct psp_gfx_cmd_resp *cmd; 1657 int ret; 1658 1659 if (amdgpu_sriov_vf(psp->adev)) 1660 return 0; 1661 1662 cmd = acquire_psp_cmd_buf(psp); 1663 1664 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1665 cmd->cmd.cmd_spatial_part.mode = mode; 1666 1667 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1668 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1669 1670 release_psp_cmd_buf(psp); 1671 1672 return ret; 1673 } 1674 1675 static int psp_asd_initialize(struct psp_context *psp) 1676 { 1677 int ret; 1678 1679 /* If PSP version doesn't match ASD version, asd loading will be failed. 1680 * add workaround to bypass it for sriov now. 1681 * TODO: add version check to make it common 1682 */ 1683 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1684 return 0; 1685 1686 /* bypass asd if display hardware is not available */ 1687 if (!amdgpu_device_has_display_hardware(psp->adev) && 1688 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1689 return 0; 1690 1691 psp->asd_context.mem_context.shared_mc_addr = 0; 1692 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1693 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1694 1695 ret = psp_ta_load(psp, &psp->asd_context); 1696 if (!ret) 1697 psp->asd_context.initialized = true; 1698 1699 return ret; 1700 } 1701 1702 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1703 uint32_t session_id) 1704 { 1705 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1706 cmd->cmd.cmd_unload_ta.session_id = session_id; 1707 } 1708 1709 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1710 { 1711 int ret; 1712 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1713 1714 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1715 1716 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1717 1718 context->resp_status = cmd->resp.status; 1719 1720 release_psp_cmd_buf(psp); 1721 1722 return ret; 1723 } 1724 1725 static int psp_asd_terminate(struct psp_context *psp) 1726 { 1727 int ret; 1728 1729 if (amdgpu_sriov_vf(psp->adev)) 1730 return 0; 1731 1732 if (!psp->asd_context.initialized) 1733 return 0; 1734 1735 ret = psp_ta_unload(psp, &psp->asd_context); 1736 if (!ret) 1737 psp->asd_context.initialized = false; 1738 1739 return ret; 1740 } 1741 1742 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1743 uint32_t id, uint32_t value) 1744 { 1745 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1746 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1747 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1748 } 1749 1750 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1751 uint32_t value) 1752 { 1753 struct psp_gfx_cmd_resp *cmd; 1754 int ret = 0; 1755 1756 if (reg >= PSP_REG_LAST) 1757 return -EINVAL; 1758 1759 cmd = acquire_psp_cmd_buf(psp); 1760 1761 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1762 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1763 if (ret) 1764 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1765 1766 release_psp_cmd_buf(psp); 1767 1768 return ret; 1769 } 1770 1771 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1772 uint64_t ta_bin_mc, 1773 struct ta_context *context) 1774 { 1775 cmd->cmd_id = context->ta_load_type; 1776 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1777 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1778 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1779 1780 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1781 lower_32_bits(context->mem_context.shared_mc_addr); 1782 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1783 upper_32_bits(context->mem_context.shared_mc_addr); 1784 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1785 } 1786 1787 int psp_ta_init_shared_buf(struct psp_context *psp, 1788 struct ta_mem_context *mem_ctx) 1789 { 1790 /* 1791 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1792 * physical) for ta to host memory 1793 */ 1794 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1795 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1796 AMDGPU_GEM_DOMAIN_GTT, 1797 &mem_ctx->shared_bo, 1798 &mem_ctx->shared_mc_addr, 1799 &mem_ctx->shared_buf); 1800 } 1801 1802 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1803 uint32_t ta_cmd_id, 1804 uint32_t session_id) 1805 { 1806 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1807 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1808 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1809 } 1810 1811 int psp_ta_invoke(struct psp_context *psp, 1812 uint32_t ta_cmd_id, 1813 struct ta_context *context) 1814 { 1815 int ret; 1816 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1817 1818 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1819 1820 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1821 psp->fence_buf_mc_addr); 1822 1823 context->resp_status = cmd->resp.status; 1824 1825 release_psp_cmd_buf(psp); 1826 1827 return ret; 1828 } 1829 1830 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1831 { 1832 int ret; 1833 struct psp_gfx_cmd_resp *cmd; 1834 1835 cmd = acquire_psp_cmd_buf(psp); 1836 1837 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1838 context->bin_desc.size_bytes); 1839 if (ret) { 1840 release_psp_cmd_buf(psp); 1841 return ret; 1842 } 1843 1844 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1845 context->mem_context.shared_bo) 1846 context->mem_context.shared_mc_addr = 1847 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1848 1849 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1850 1851 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1852 psp->fence_buf_mc_addr); 1853 1854 context->resp_status = cmd->resp.status; 1855 1856 if (!ret) 1857 context->session_id = cmd->resp.session_id; 1858 1859 release_psp_cmd_buf(psp); 1860 1861 return ret; 1862 } 1863 1864 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1865 { 1866 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1867 } 1868 1869 int psp_xgmi_terminate(struct psp_context *psp) 1870 { 1871 int ret; 1872 struct amdgpu_device *adev = psp->adev; 1873 1874 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1875 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1876 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1877 adev->gmc.xgmi.connected_to_cpu)) 1878 return 0; 1879 1880 if (!psp->xgmi_context.context.initialized) 1881 return 0; 1882 1883 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1884 1885 psp->xgmi_context.context.initialized = false; 1886 1887 return ret; 1888 } 1889 1890 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1891 { 1892 struct ta_xgmi_shared_memory *xgmi_cmd; 1893 int ret; 1894 1895 if (!psp->ta_fw || 1896 !psp->xgmi_context.context.bin_desc.size_bytes || 1897 !psp->xgmi_context.context.bin_desc.start_addr) 1898 return -ENOENT; 1899 1900 if (!load_ta) 1901 goto invoke; 1902 1903 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1904 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1905 1906 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1907 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1908 if (ret) 1909 return ret; 1910 } 1911 1912 /* Load XGMI TA */ 1913 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1914 if (!ret) 1915 psp->xgmi_context.context.initialized = true; 1916 else 1917 return ret; 1918 1919 invoke: 1920 /* Initialize XGMI session */ 1921 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1922 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1923 xgmi_cmd->flag_extend_link_record = set_extended_data; 1924 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1925 1926 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1927 /* note down the capbility flag for XGMI TA */ 1928 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1929 1930 if (!amdgpu_sriov_vf(psp->adev)) 1931 psp->xgmi_context.supports_ext_link_info = psp->xgmi_context.xgmi_ta_caps & 1932 EXTEND_PEER_LINK_INFO_CMD_FLAG; 1933 else 1934 psp->xgmi_context.supports_ext_link_info = amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 1935 1936 return ret; 1937 } 1938 1939 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1940 { 1941 struct ta_xgmi_shared_memory *xgmi_cmd; 1942 int ret; 1943 1944 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1945 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1946 1947 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1948 1949 /* Invoke xgmi ta to get hive id */ 1950 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1951 if (ret) 1952 return ret; 1953 1954 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1955 1956 return 0; 1957 } 1958 1959 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1960 { 1961 struct ta_xgmi_shared_memory *xgmi_cmd; 1962 int ret; 1963 1964 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1965 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1966 1967 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1968 1969 /* Invoke xgmi ta to get the node id */ 1970 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1971 if (ret) 1972 return ret; 1973 1974 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1975 1976 return 0; 1977 } 1978 1979 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1980 { 1981 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1982 IP_VERSION(13, 0, 2) && 1983 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1984 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1985 IP_VERSION(13, 0, 6); 1986 } 1987 1988 /* 1989 * Chips that support extended topology information require the driver to 1990 * reflect topology information in the opposite direction. This is 1991 * because the TA has already exceeded its link record limit and if the 1992 * TA holds bi-directional information, the driver would have to do 1993 * multiple fetches instead of just two. 1994 */ 1995 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1996 struct psp_xgmi_node_info node_info) 1997 { 1998 struct amdgpu_device *mirror_adev; 1999 struct amdgpu_hive_info *hive; 2000 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 2001 uint64_t dst_node_id = node_info.node_id; 2002 uint8_t dst_num_hops = node_info.num_hops; 2003 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 2004 uint8_t dst_num_links = node_info.num_links; 2005 2006 hive = amdgpu_get_xgmi_hive(psp->adev); 2007 if (WARN_ON(!hive)) 2008 return; 2009 2010 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 2011 struct psp_xgmi_topology_info *mirror_top_info; 2012 int j; 2013 2014 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 2015 continue; 2016 2017 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 2018 for (j = 0; j < mirror_top_info->num_nodes; j++) { 2019 if (mirror_top_info->nodes[j].node_id != src_node_id) 2020 continue; 2021 2022 mirror_top_info->nodes[j].num_hops = dst_num_hops; 2023 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 2024 /* prevent 0 num_links value re-reflection since reflection 2025 * criteria is based on num_hops (direct or indirect). 2026 */ 2027 if (dst_num_links) { 2028 mirror_top_info->nodes[j].num_links = dst_num_links; 2029 /* swap src and dst due to frame of reference */ 2030 for (int k = 0; k < dst_num_links; k++) { 2031 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 2032 node_info.port_num[k].dst_xgmi_port_num; 2033 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 2034 node_info.port_num[k].src_xgmi_port_num; 2035 } 2036 } 2037 2038 break; 2039 } 2040 2041 break; 2042 } 2043 2044 amdgpu_put_xgmi_hive(hive); 2045 } 2046 2047 int psp_xgmi_get_topology_info(struct psp_context *psp, 2048 int number_devices, 2049 struct psp_xgmi_topology_info *topology, 2050 bool get_extended_data) 2051 { 2052 struct ta_xgmi_shared_memory *xgmi_cmd; 2053 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2054 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 2055 int i; 2056 int ret; 2057 2058 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2059 return -EINVAL; 2060 2061 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2062 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2063 xgmi_cmd->flag_extend_link_record = get_extended_data; 2064 2065 /* Fill in the shared memory with topology information as input */ 2066 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2067 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 2068 topology_info_input->num_nodes = number_devices; 2069 2070 for (i = 0; i < topology_info_input->num_nodes; i++) { 2071 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2072 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2073 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2074 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2075 } 2076 2077 /* Invoke xgmi ta to get the topology information */ 2078 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2079 if (ret) 2080 return ret; 2081 2082 /* Read the output topology information from the shared memory */ 2083 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2084 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2085 for (i = 0; i < topology->num_nodes; i++) { 2086 /* extended data will either be 0 or equal to non-extended data */ 2087 if (topology_info_output->nodes[i].num_hops) 2088 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2089 2090 /* non-extended data gets everything here so no need to update */ 2091 if (!get_extended_data) { 2092 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2093 topology->nodes[i].is_sharing_enabled = 2094 topology_info_output->nodes[i].is_sharing_enabled; 2095 topology->nodes[i].sdma_engine = 2096 topology_info_output->nodes[i].sdma_engine; 2097 } 2098 2099 } 2100 2101 /* Invoke xgmi ta again to get the link information */ 2102 if (psp_xgmi_peer_link_info_supported(psp)) { 2103 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2104 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2105 bool requires_reflection = 2106 (psp->xgmi_context.supports_extended_data && 2107 get_extended_data) || 2108 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2109 IP_VERSION(13, 0, 6) || 2110 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2111 IP_VERSION(13, 0, 14) || 2112 amdgpu_sriov_vf(psp->adev); 2113 2114 /* popluate the shared output buffer rather than the cmd input buffer 2115 * with node_ids as the input for GET_PEER_LINKS command execution. 2116 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2117 * The same requirement for GET_EXTEND_PEER_LINKS command. 2118 */ 2119 if (psp->xgmi_context.supports_ext_link_info) { 2120 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2121 2122 for (i = 0; i < topology->num_nodes; i++) 2123 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2124 2125 link_extend_info_output->num_nodes = topology->num_nodes; 2126 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2127 } else { 2128 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2129 2130 for (i = 0; i < topology->num_nodes; i++) 2131 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2132 2133 link_info_output->num_nodes = topology->num_nodes; 2134 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2135 } 2136 2137 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2138 if (ret) 2139 return ret; 2140 2141 for (i = 0; i < topology->num_nodes; i++) { 2142 uint8_t node_num_links = psp->xgmi_context.supports_ext_link_info ? 2143 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2144 /* accumulate num_links on extended data */ 2145 if (get_extended_data) { 2146 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2147 } else { 2148 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2149 topology->nodes[i].num_links : node_num_links; 2150 } 2151 /* popluate the connected port num info if supported and available */ 2152 if (psp->xgmi_context.supports_ext_link_info && topology->nodes[i].num_links) { 2153 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2154 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2155 } 2156 2157 /* reflect the topology information for bi-directionality */ 2158 if (requires_reflection && topology->nodes[i].num_hops) 2159 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2160 } 2161 } 2162 2163 return 0; 2164 } 2165 2166 int psp_xgmi_set_topology_info(struct psp_context *psp, 2167 int number_devices, 2168 struct psp_xgmi_topology_info *topology) 2169 { 2170 struct ta_xgmi_shared_memory *xgmi_cmd; 2171 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2172 int i; 2173 2174 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2175 return -EINVAL; 2176 2177 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2178 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2179 2180 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2181 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2182 topology_info_input->num_nodes = number_devices; 2183 2184 for (i = 0; i < topology_info_input->num_nodes; i++) { 2185 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2186 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2187 topology_info_input->nodes[i].is_sharing_enabled = 1; 2188 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2189 } 2190 2191 /* Invoke xgmi ta to set topology information */ 2192 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2193 } 2194 2195 // ras begin 2196 static void psp_ras_ta_check_status(struct psp_context *psp) 2197 { 2198 struct ta_ras_shared_memory *ras_cmd = 2199 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2200 2201 switch (ras_cmd->ras_status) { 2202 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2203 dev_warn(psp->adev->dev, 2204 "RAS WARNING: cmd failed due to unsupported ip\n"); 2205 break; 2206 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2207 dev_warn(psp->adev->dev, 2208 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2209 break; 2210 case TA_RAS_STATUS__SUCCESS: 2211 break; 2212 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2213 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2214 dev_warn(psp->adev->dev, 2215 "RAS WARNING: Inject error to critical region is not allowed\n"); 2216 break; 2217 default: 2218 dev_warn(psp->adev->dev, 2219 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2220 break; 2221 } 2222 } 2223 2224 static int psp_ras_send_cmd(struct psp_context *psp, 2225 enum ras_command cmd_id, void *in, void *out) 2226 { 2227 struct ta_ras_shared_memory *ras_cmd; 2228 uint32_t cmd = cmd_id; 2229 int ret = 0; 2230 2231 if (!in) 2232 return -EINVAL; 2233 2234 mutex_lock(&psp->ras_context.mutex); 2235 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2236 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2237 2238 switch (cmd) { 2239 case TA_RAS_COMMAND__ENABLE_FEATURES: 2240 case TA_RAS_COMMAND__DISABLE_FEATURES: 2241 memcpy(&ras_cmd->ras_in_message, 2242 in, sizeof(ras_cmd->ras_in_message)); 2243 break; 2244 case TA_RAS_COMMAND__TRIGGER_ERROR: 2245 memcpy(&ras_cmd->ras_in_message.trigger_error, 2246 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2247 break; 2248 case TA_RAS_COMMAND__QUERY_ADDRESS: 2249 memcpy(&ras_cmd->ras_in_message.address, 2250 in, sizeof(ras_cmd->ras_in_message.address)); 2251 break; 2252 default: 2253 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2254 ret = -EINVAL; 2255 goto err_out; 2256 } 2257 2258 ras_cmd->cmd_id = cmd; 2259 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2260 2261 switch (cmd) { 2262 case TA_RAS_COMMAND__TRIGGER_ERROR: 2263 if (!ret && out) 2264 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2265 break; 2266 case TA_RAS_COMMAND__QUERY_ADDRESS: 2267 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2268 ret = -EINVAL; 2269 else if (out) 2270 memcpy(out, 2271 &ras_cmd->ras_out_message.address, 2272 sizeof(ras_cmd->ras_out_message.address)); 2273 break; 2274 default: 2275 break; 2276 } 2277 2278 err_out: 2279 mutex_unlock(&psp->ras_context.mutex); 2280 2281 return ret; 2282 } 2283 2284 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2285 { 2286 struct ta_ras_shared_memory *ras_cmd; 2287 int ret; 2288 2289 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2290 2291 /* 2292 * TODO: bypass the loading in sriov for now 2293 */ 2294 if (amdgpu_sriov_vf(psp->adev)) 2295 return 0; 2296 2297 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2298 2299 if (amdgpu_ras_intr_triggered()) 2300 return ret; 2301 2302 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2303 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2304 return -EINVAL; 2305 } 2306 2307 if (!ret) { 2308 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2309 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2310 2311 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2312 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2313 dev_warn(psp->adev->dev, 2314 "RAS internal register access blocked\n"); 2315 2316 psp_ras_ta_check_status(psp); 2317 } 2318 2319 return ret; 2320 } 2321 2322 int psp_ras_enable_features(struct psp_context *psp, 2323 union ta_ras_cmd_input *info, bool enable) 2324 { 2325 enum ras_command cmd_id; 2326 int ret; 2327 2328 if (!psp->ras_context.context.initialized || !info) 2329 return -EINVAL; 2330 2331 cmd_id = enable ? 2332 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2333 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2334 if (ret) 2335 return -EINVAL; 2336 2337 return 0; 2338 } 2339 2340 int psp_ras_terminate(struct psp_context *psp) 2341 { 2342 int ret; 2343 2344 /* 2345 * TODO: bypass the terminate in sriov for now 2346 */ 2347 if (amdgpu_sriov_vf(psp->adev)) 2348 return 0; 2349 2350 if (!psp->ras_context.context.initialized) 2351 return 0; 2352 2353 ret = psp_ta_unload(psp, &psp->ras_context.context); 2354 2355 psp->ras_context.context.initialized = false; 2356 2357 mutex_destroy(&psp->ras_context.mutex); 2358 2359 return ret; 2360 } 2361 2362 int psp_ras_initialize(struct psp_context *psp) 2363 { 2364 int ret; 2365 uint32_t boot_cfg = 0xFF; 2366 struct amdgpu_device *adev = psp->adev; 2367 struct ta_ras_shared_memory *ras_cmd; 2368 2369 /* 2370 * TODO: bypass the initialize in sriov for now 2371 */ 2372 if (amdgpu_sriov_vf(adev)) 2373 return 0; 2374 2375 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2376 !adev->psp.ras_context.context.bin_desc.start_addr) { 2377 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2378 return 0; 2379 } 2380 2381 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2382 /* query GECC enablement status from boot config 2383 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2384 */ 2385 ret = psp_boot_config_get(adev, &boot_cfg); 2386 if (ret) 2387 dev_warn(adev->dev, "PSP get boot config failed\n"); 2388 2389 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2390 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2391 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2392 dev_warn(adev->dev, 2393 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2394 } else { 2395 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2396 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2397 if (boot_cfg == 1) { 2398 dev_info(adev->dev, "GECC is enabled\n"); 2399 } else { 2400 /* enable GECC in next boot cycle if it is disabled 2401 * in boot config, or force enable GECC if failed to 2402 * get boot configuration 2403 */ 2404 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2405 if (ret) 2406 dev_warn(adev->dev, "PSP set boot config failed\n"); 2407 else 2408 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2409 } 2410 } else { 2411 if (!boot_cfg) { 2412 if (!adev->ras_default_ecc_enabled && 2413 amdgpu_ras_enable != 1 && 2414 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2415 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2416 else 2417 dev_info(adev->dev, "GECC is disabled\n"); 2418 } else { 2419 /* disable GECC in next boot cycle if ras is 2420 * disabled by module parameter amdgpu_ras_enable 2421 * and/or amdgpu_ras_mask, or boot_config_get call 2422 * is failed 2423 */ 2424 ret = psp_boot_config_set(adev, 0); 2425 if (ret) 2426 dev_warn(adev->dev, "PSP set boot config failed\n"); 2427 else 2428 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2429 } 2430 } 2431 } 2432 } 2433 2434 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2435 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2436 2437 if (!psp->ras_context.context.mem_context.shared_buf) { 2438 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2439 if (ret) 2440 return ret; 2441 } 2442 2443 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2444 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2445 2446 if (amdgpu_ras_is_poison_mode_supported(adev)) 2447 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2448 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2449 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2450 ras_cmd->ras_in_message.init_flags.xcc_mask = 2451 adev->gfx.xcc_mask; 2452 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2453 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2454 ras_cmd->ras_in_message.init_flags.nps_mode = 2455 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2456 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2457 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2458 2459 ret = psp_ta_load(psp, &psp->ras_context.context); 2460 2461 if (!ret && !ras_cmd->ras_status) { 2462 psp->ras_context.context.initialized = true; 2463 mutex_init(&psp->ras_context.mutex); 2464 } else { 2465 if (ras_cmd->ras_status) 2466 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2467 2468 /* fail to load RAS TA */ 2469 psp->ras_context.context.initialized = false; 2470 } 2471 2472 return ret; 2473 } 2474 2475 int psp_ras_trigger_error(struct psp_context *psp, 2476 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2477 { 2478 struct amdgpu_device *adev = psp->adev; 2479 int ret; 2480 uint32_t dev_mask; 2481 uint32_t ras_status = 0; 2482 2483 if (!psp->ras_context.context.initialized || !info) 2484 return -EINVAL; 2485 2486 switch (info->block_id) { 2487 case TA_RAS_BLOCK__GFX: 2488 dev_mask = GET_MASK(GC, instance_mask); 2489 break; 2490 case TA_RAS_BLOCK__SDMA: 2491 dev_mask = GET_MASK(SDMA0, instance_mask); 2492 break; 2493 case TA_RAS_BLOCK__VCN: 2494 case TA_RAS_BLOCK__JPEG: 2495 dev_mask = GET_MASK(VCN, instance_mask); 2496 break; 2497 default: 2498 dev_mask = instance_mask; 2499 break; 2500 } 2501 2502 /* reuse sub_block_index for backward compatibility */ 2503 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2504 dev_mask &= AMDGPU_RAS_INST_MASK; 2505 info->sub_block_index |= dev_mask; 2506 2507 ret = psp_ras_send_cmd(psp, 2508 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2509 if (ret) 2510 return -EINVAL; 2511 2512 /* If err_event_athub occurs error inject was successful, however 2513 * return status from TA is no long reliable 2514 */ 2515 if (amdgpu_ras_intr_triggered()) 2516 return 0; 2517 2518 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2519 return -EACCES; 2520 else if (ras_status) 2521 return -EINVAL; 2522 2523 return 0; 2524 } 2525 2526 int psp_ras_query_address(struct psp_context *psp, 2527 struct ta_ras_query_address_input *addr_in, 2528 struct ta_ras_query_address_output *addr_out) 2529 { 2530 int ret; 2531 2532 if (!psp->ras_context.context.initialized || 2533 !addr_in || !addr_out) 2534 return -EINVAL; 2535 2536 ret = psp_ras_send_cmd(psp, 2537 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2538 2539 return ret; 2540 } 2541 // ras end 2542 2543 // HDCP start 2544 static int psp_hdcp_initialize(struct psp_context *psp) 2545 { 2546 int ret; 2547 2548 /* 2549 * TODO: bypass the initialize in sriov for now 2550 */ 2551 if (amdgpu_sriov_vf(psp->adev)) 2552 return 0; 2553 2554 /* bypass hdcp initialization if dmu is harvested */ 2555 if (!amdgpu_device_has_display_hardware(psp->adev)) 2556 return 0; 2557 2558 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2559 !psp->hdcp_context.context.bin_desc.start_addr) { 2560 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2561 return 0; 2562 } 2563 2564 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2565 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2566 2567 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2568 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2569 if (ret) 2570 return ret; 2571 } 2572 2573 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2574 if (!ret) { 2575 psp->hdcp_context.context.initialized = true; 2576 mutex_init(&psp->hdcp_context.mutex); 2577 } 2578 2579 return ret; 2580 } 2581 2582 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2583 { 2584 /* 2585 * TODO: bypass the loading in sriov for now 2586 */ 2587 if (amdgpu_sriov_vf(psp->adev)) 2588 return 0; 2589 2590 if (!psp->hdcp_context.context.initialized) 2591 return 0; 2592 2593 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2594 } 2595 2596 static int psp_hdcp_terminate(struct psp_context *psp) 2597 { 2598 int ret; 2599 2600 /* 2601 * TODO: bypass the terminate in sriov for now 2602 */ 2603 if (amdgpu_sriov_vf(psp->adev)) 2604 return 0; 2605 2606 if (!psp->hdcp_context.context.initialized) 2607 return 0; 2608 2609 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2610 2611 psp->hdcp_context.context.initialized = false; 2612 2613 return ret; 2614 } 2615 // HDCP end 2616 2617 // DTM start 2618 static int psp_dtm_initialize(struct psp_context *psp) 2619 { 2620 int ret; 2621 2622 /* 2623 * TODO: bypass the initialize in sriov for now 2624 */ 2625 if (amdgpu_sriov_vf(psp->adev)) 2626 return 0; 2627 2628 /* bypass dtm initialization if dmu is harvested */ 2629 if (!amdgpu_device_has_display_hardware(psp->adev)) 2630 return 0; 2631 2632 if (!psp->dtm_context.context.bin_desc.size_bytes || 2633 !psp->dtm_context.context.bin_desc.start_addr) { 2634 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2635 return 0; 2636 } 2637 2638 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2639 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2640 2641 if (!psp->dtm_context.context.mem_context.shared_buf) { 2642 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2643 if (ret) 2644 return ret; 2645 } 2646 2647 ret = psp_ta_load(psp, &psp->dtm_context.context); 2648 if (!ret) { 2649 psp->dtm_context.context.initialized = true; 2650 mutex_init(&psp->dtm_context.mutex); 2651 } 2652 2653 return ret; 2654 } 2655 2656 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2657 { 2658 /* 2659 * TODO: bypass the loading in sriov for now 2660 */ 2661 if (amdgpu_sriov_vf(psp->adev)) 2662 return 0; 2663 2664 if (!psp->dtm_context.context.initialized) 2665 return 0; 2666 2667 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2668 } 2669 2670 static int psp_dtm_terminate(struct psp_context *psp) 2671 { 2672 int ret; 2673 2674 /* 2675 * TODO: bypass the terminate in sriov for now 2676 */ 2677 if (amdgpu_sriov_vf(psp->adev)) 2678 return 0; 2679 2680 if (!psp->dtm_context.context.initialized) 2681 return 0; 2682 2683 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2684 2685 psp->dtm_context.context.initialized = false; 2686 2687 return ret; 2688 } 2689 // DTM end 2690 2691 // RAP start 2692 static int psp_rap_initialize(struct psp_context *psp) 2693 { 2694 int ret; 2695 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2696 2697 /* 2698 * TODO: bypass the initialize in sriov for now 2699 */ 2700 if (amdgpu_sriov_vf(psp->adev)) 2701 return 0; 2702 2703 if (!psp->rap_context.context.bin_desc.size_bytes || 2704 !psp->rap_context.context.bin_desc.start_addr) { 2705 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2706 return 0; 2707 } 2708 2709 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2710 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2711 2712 if (!psp->rap_context.context.mem_context.shared_buf) { 2713 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2714 if (ret) 2715 return ret; 2716 } 2717 2718 ret = psp_ta_load(psp, &psp->rap_context.context); 2719 if (!ret) { 2720 psp->rap_context.context.initialized = true; 2721 mutex_init(&psp->rap_context.mutex); 2722 } else 2723 return ret; 2724 2725 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2726 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2727 psp_rap_terminate(psp); 2728 /* free rap shared memory */ 2729 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2730 2731 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2732 ret, status); 2733 2734 return ret; 2735 } 2736 2737 return 0; 2738 } 2739 2740 static int psp_rap_terminate(struct psp_context *psp) 2741 { 2742 int ret; 2743 2744 if (!psp->rap_context.context.initialized) 2745 return 0; 2746 2747 ret = psp_ta_unload(psp, &psp->rap_context.context); 2748 2749 psp->rap_context.context.initialized = false; 2750 2751 return ret; 2752 } 2753 2754 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2755 { 2756 struct ta_rap_shared_memory *rap_cmd; 2757 int ret = 0; 2758 2759 if (!psp->rap_context.context.initialized) 2760 return 0; 2761 2762 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2763 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2764 return -EINVAL; 2765 2766 mutex_lock(&psp->rap_context.mutex); 2767 2768 rap_cmd = (struct ta_rap_shared_memory *) 2769 psp->rap_context.context.mem_context.shared_buf; 2770 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2771 2772 rap_cmd->cmd_id = ta_cmd_id; 2773 rap_cmd->validation_method_id = METHOD_A; 2774 2775 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2776 if (ret) 2777 goto out_unlock; 2778 2779 if (status) 2780 *status = rap_cmd->rap_status; 2781 2782 out_unlock: 2783 mutex_unlock(&psp->rap_context.mutex); 2784 2785 return ret; 2786 } 2787 // RAP end 2788 2789 /* securedisplay start */ 2790 static int psp_securedisplay_initialize(struct psp_context *psp) 2791 { 2792 int ret; 2793 struct ta_securedisplay_cmd *securedisplay_cmd; 2794 2795 /* 2796 * TODO: bypass the initialize in sriov for now 2797 */ 2798 if (amdgpu_sriov_vf(psp->adev)) 2799 return 0; 2800 2801 /* bypass securedisplay initialization if dmu is harvested */ 2802 if (!amdgpu_device_has_display_hardware(psp->adev)) 2803 return 0; 2804 2805 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2806 !psp->securedisplay_context.context.bin_desc.start_addr) { 2807 dev_info(psp->adev->dev, 2808 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2809 return 0; 2810 } 2811 2812 psp->securedisplay_context.context.mem_context.shared_mem_size = 2813 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2814 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2815 2816 if (!psp->securedisplay_context.context.initialized) { 2817 ret = psp_ta_init_shared_buf(psp, 2818 &psp->securedisplay_context.context.mem_context); 2819 if (ret) 2820 return ret; 2821 } 2822 2823 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2824 if (!ret && !psp->securedisplay_context.context.resp_status) { 2825 psp->securedisplay_context.context.initialized = true; 2826 mutex_init(&psp->securedisplay_context.mutex); 2827 } else { 2828 /* don't try again */ 2829 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2830 return ret; 2831 } 2832 2833 mutex_lock(&psp->securedisplay_context.mutex); 2834 2835 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2836 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2837 2838 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2839 2840 mutex_unlock(&psp->securedisplay_context.mutex); 2841 2842 if (ret) { 2843 psp_securedisplay_terminate(psp); 2844 /* free securedisplay shared memory */ 2845 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2846 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2847 return -EINVAL; 2848 } 2849 2850 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2851 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2852 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2853 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2854 /* don't try again */ 2855 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2856 } 2857 2858 return 0; 2859 } 2860 2861 static int psp_securedisplay_terminate(struct psp_context *psp) 2862 { 2863 int ret; 2864 2865 /* 2866 * TODO:bypass the terminate in sriov for now 2867 */ 2868 if (amdgpu_sriov_vf(psp->adev)) 2869 return 0; 2870 2871 if (!psp->securedisplay_context.context.initialized) 2872 return 0; 2873 2874 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2875 2876 psp->securedisplay_context.context.initialized = false; 2877 2878 return ret; 2879 } 2880 2881 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2882 { 2883 int ret; 2884 2885 if (!psp->securedisplay_context.context.initialized) 2886 return -EINVAL; 2887 2888 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2889 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2890 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2891 return -EINVAL; 2892 2893 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2894 2895 return ret; 2896 } 2897 /* SECUREDISPLAY end */ 2898 2899 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2900 { 2901 struct psp_context *psp = &adev->psp; 2902 int ret = 0; 2903 2904 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2905 ret = psp->funcs->wait_for_bootloader(psp); 2906 2907 return ret; 2908 } 2909 2910 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2911 { 2912 if (psp->funcs && 2913 psp->funcs->get_ras_capability) { 2914 return psp->funcs->get_ras_capability(psp); 2915 } else { 2916 return false; 2917 } 2918 } 2919 2920 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2921 { 2922 struct psp_context *psp = &adev->psp; 2923 2924 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2925 return false; 2926 2927 if (psp->funcs && psp->funcs->is_reload_needed) 2928 return psp->funcs->is_reload_needed(psp); 2929 2930 return false; 2931 } 2932 2933 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2934 { 2935 struct psp_context *psp = &adev->psp; 2936 2937 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2938 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2939 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2940 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2941 } 2942 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2943 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2944 } 2945 2946 static int psp_hw_start(struct psp_context *psp) 2947 { 2948 struct amdgpu_device *adev = psp->adev; 2949 int ret; 2950 2951 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2952 psp_update_gpu_addresses(adev); 2953 2954 if (!amdgpu_sriov_vf(adev)) { 2955 if ((is_psp_fw_valid(psp->kdb)) && 2956 (psp->funcs->bootloader_load_kdb != NULL)) { 2957 ret = psp_bootloader_load_kdb(psp); 2958 if (ret) { 2959 dev_err(adev->dev, "PSP load kdb failed!\n"); 2960 return ret; 2961 } 2962 } 2963 2964 if ((is_psp_fw_valid(psp->spl)) && 2965 (psp->funcs->bootloader_load_spl != NULL)) { 2966 ret = psp_bootloader_load_spl(psp); 2967 if (ret) { 2968 dev_err(adev->dev, "PSP load spl failed!\n"); 2969 return ret; 2970 } 2971 } 2972 2973 if ((is_psp_fw_valid(psp->sys)) && 2974 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2975 ret = psp_bootloader_load_sysdrv(psp); 2976 if (ret) { 2977 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2978 return ret; 2979 } 2980 } 2981 2982 if ((is_psp_fw_valid(psp->soc_drv)) && 2983 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2984 ret = psp_bootloader_load_soc_drv(psp); 2985 if (ret) { 2986 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2987 return ret; 2988 } 2989 } 2990 2991 if ((is_psp_fw_valid(psp->intf_drv)) && 2992 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2993 ret = psp_bootloader_load_intf_drv(psp); 2994 if (ret) { 2995 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2996 return ret; 2997 } 2998 } 2999 3000 if ((is_psp_fw_valid(psp->dbg_drv)) && 3001 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 3002 ret = psp_bootloader_load_dbg_drv(psp); 3003 if (ret) { 3004 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 3005 return ret; 3006 } 3007 } 3008 3009 if ((is_psp_fw_valid(psp->ras_drv)) && 3010 (psp->funcs->bootloader_load_ras_drv != NULL)) { 3011 ret = psp_bootloader_load_ras_drv(psp); 3012 if (ret) { 3013 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 3014 return ret; 3015 } 3016 } 3017 3018 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 3019 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 3020 ret = psp_bootloader_load_ipkeymgr_drv(psp); 3021 if (ret) { 3022 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 3023 return ret; 3024 } 3025 } 3026 3027 if ((is_psp_fw_valid(psp->spdm_drv)) && 3028 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 3029 ret = psp_bootloader_load_spdm_drv(psp); 3030 if (ret) { 3031 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 3032 return ret; 3033 } 3034 } 3035 3036 if ((is_psp_fw_valid(psp->sos)) && 3037 (psp->funcs->bootloader_load_sos != NULL)) { 3038 ret = psp_bootloader_load_sos(psp); 3039 if (ret) { 3040 dev_err(adev->dev, "PSP load sos failed!\n"); 3041 return ret; 3042 } 3043 } 3044 } 3045 3046 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 3047 if (ret) { 3048 dev_err(adev->dev, "PSP create ring failed!\n"); 3049 return ret; 3050 } 3051 3052 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3053 ret = psp_update_fw_reservation(psp); 3054 if (ret) { 3055 dev_err(adev->dev, "update fw reservation failed!\n"); 3056 return ret; 3057 } 3058 } 3059 3060 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 3061 goto skip_pin_bo; 3062 3063 if (!psp->boot_time_tmr || psp->autoload_supported) { 3064 ret = psp_tmr_init(psp); 3065 if (ret) { 3066 dev_err(adev->dev, "PSP tmr init failed!\n"); 3067 return ret; 3068 } 3069 } 3070 3071 skip_pin_bo: 3072 /* 3073 * For ASICs with DF Cstate management centralized 3074 * to PMFW, TMR setup should be performed after PMFW 3075 * loaded and before other non-psp firmware loaded. 3076 */ 3077 if (psp->pmfw_centralized_cstate_management) { 3078 ret = psp_load_smu_fw(psp); 3079 if (ret) 3080 return ret; 3081 } 3082 3083 ret = psp_tmr_load(psp); 3084 if (ret) { 3085 dev_err(adev->dev, "PSP load tmr failed!\n"); 3086 return ret; 3087 } 3088 3089 return 0; 3090 } 3091 3092 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3093 enum psp_gfx_fw_type *type) 3094 { 3095 switch (ucode->ucode_id) { 3096 case AMDGPU_UCODE_ID_CAP: 3097 *type = GFX_FW_TYPE_CAP; 3098 break; 3099 case AMDGPU_UCODE_ID_SDMA0: 3100 *type = GFX_FW_TYPE_SDMA0; 3101 break; 3102 case AMDGPU_UCODE_ID_SDMA1: 3103 *type = GFX_FW_TYPE_SDMA1; 3104 break; 3105 case AMDGPU_UCODE_ID_SDMA2: 3106 *type = GFX_FW_TYPE_SDMA2; 3107 break; 3108 case AMDGPU_UCODE_ID_SDMA3: 3109 *type = GFX_FW_TYPE_SDMA3; 3110 break; 3111 case AMDGPU_UCODE_ID_SDMA4: 3112 *type = GFX_FW_TYPE_SDMA4; 3113 break; 3114 case AMDGPU_UCODE_ID_SDMA5: 3115 *type = GFX_FW_TYPE_SDMA5; 3116 break; 3117 case AMDGPU_UCODE_ID_SDMA6: 3118 *type = GFX_FW_TYPE_SDMA6; 3119 break; 3120 case AMDGPU_UCODE_ID_SDMA7: 3121 *type = GFX_FW_TYPE_SDMA7; 3122 break; 3123 case AMDGPU_UCODE_ID_CP_MES: 3124 *type = GFX_FW_TYPE_CP_MES; 3125 break; 3126 case AMDGPU_UCODE_ID_CP_MES_DATA: 3127 *type = GFX_FW_TYPE_MES_STACK; 3128 break; 3129 case AMDGPU_UCODE_ID_CP_MES1: 3130 *type = GFX_FW_TYPE_CP_MES_KIQ; 3131 break; 3132 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3133 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3134 break; 3135 case AMDGPU_UCODE_ID_CP_CE: 3136 *type = GFX_FW_TYPE_CP_CE; 3137 break; 3138 case AMDGPU_UCODE_ID_CP_PFP: 3139 *type = GFX_FW_TYPE_CP_PFP; 3140 break; 3141 case AMDGPU_UCODE_ID_CP_ME: 3142 *type = GFX_FW_TYPE_CP_ME; 3143 break; 3144 case AMDGPU_UCODE_ID_CP_MEC1: 3145 *type = GFX_FW_TYPE_CP_MEC; 3146 break; 3147 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3148 *type = GFX_FW_TYPE_CP_MEC_ME1; 3149 break; 3150 case AMDGPU_UCODE_ID_CP_MEC2: 3151 *type = GFX_FW_TYPE_CP_MEC; 3152 break; 3153 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3154 *type = GFX_FW_TYPE_CP_MEC_ME2; 3155 break; 3156 case AMDGPU_UCODE_ID_RLC_P: 3157 *type = GFX_FW_TYPE_RLC_P; 3158 break; 3159 case AMDGPU_UCODE_ID_RLC_V: 3160 *type = GFX_FW_TYPE_RLC_V; 3161 break; 3162 case AMDGPU_UCODE_ID_RLC_G: 3163 *type = GFX_FW_TYPE_RLC_G; 3164 break; 3165 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3166 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3167 break; 3168 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3169 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3170 break; 3171 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3172 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3173 break; 3174 case AMDGPU_UCODE_ID_RLC_IRAM: 3175 *type = GFX_FW_TYPE_RLC_IRAM; 3176 break; 3177 case AMDGPU_UCODE_ID_RLC_DRAM: 3178 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3179 break; 3180 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3181 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3182 break; 3183 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3184 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3185 break; 3186 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3187 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3188 break; 3189 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3190 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3191 break; 3192 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3193 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3194 break; 3195 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3196 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3197 break; 3198 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3199 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3200 break; 3201 case AMDGPU_UCODE_ID_SMC: 3202 *type = GFX_FW_TYPE_SMU; 3203 break; 3204 case AMDGPU_UCODE_ID_PPTABLE: 3205 *type = GFX_FW_TYPE_PPTABLE; 3206 break; 3207 case AMDGPU_UCODE_ID_UVD: 3208 *type = GFX_FW_TYPE_UVD; 3209 break; 3210 case AMDGPU_UCODE_ID_UVD1: 3211 *type = GFX_FW_TYPE_UVD1; 3212 break; 3213 case AMDGPU_UCODE_ID_VCE: 3214 *type = GFX_FW_TYPE_VCE; 3215 break; 3216 case AMDGPU_UCODE_ID_VCN: 3217 *type = GFX_FW_TYPE_VCN; 3218 break; 3219 case AMDGPU_UCODE_ID_VCN1: 3220 *type = GFX_FW_TYPE_VCN1; 3221 break; 3222 case AMDGPU_UCODE_ID_DMCU_ERAM: 3223 *type = GFX_FW_TYPE_DMCU_ERAM; 3224 break; 3225 case AMDGPU_UCODE_ID_DMCU_INTV: 3226 *type = GFX_FW_TYPE_DMCU_ISR; 3227 break; 3228 case AMDGPU_UCODE_ID_VCN0_RAM: 3229 *type = GFX_FW_TYPE_VCN0_RAM; 3230 break; 3231 case AMDGPU_UCODE_ID_VCN1_RAM: 3232 *type = GFX_FW_TYPE_VCN1_RAM; 3233 break; 3234 case AMDGPU_UCODE_ID_DMCUB: 3235 *type = GFX_FW_TYPE_DMUB; 3236 break; 3237 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3238 case AMDGPU_UCODE_ID_SDMA_RS64: 3239 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3240 break; 3241 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3242 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3243 break; 3244 case AMDGPU_UCODE_ID_IMU_I: 3245 *type = GFX_FW_TYPE_IMU_I; 3246 break; 3247 case AMDGPU_UCODE_ID_IMU_D: 3248 *type = GFX_FW_TYPE_IMU_D; 3249 break; 3250 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3251 *type = GFX_FW_TYPE_RS64_PFP; 3252 break; 3253 case AMDGPU_UCODE_ID_CP_RS64_ME: 3254 *type = GFX_FW_TYPE_RS64_ME; 3255 break; 3256 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3257 *type = GFX_FW_TYPE_RS64_MEC; 3258 break; 3259 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3260 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3261 break; 3262 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3263 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3264 break; 3265 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3266 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3267 break; 3268 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3269 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3270 break; 3271 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3272 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3273 break; 3274 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3275 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3276 break; 3277 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3278 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3279 break; 3280 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3281 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3282 break; 3283 case AMDGPU_UCODE_ID_VPE_CTX: 3284 *type = GFX_FW_TYPE_VPEC_FW1; 3285 break; 3286 case AMDGPU_UCODE_ID_VPE_CTL: 3287 *type = GFX_FW_TYPE_VPEC_FW2; 3288 break; 3289 case AMDGPU_UCODE_ID_VPE: 3290 *type = GFX_FW_TYPE_VPE; 3291 break; 3292 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3293 *type = GFX_FW_TYPE_UMSCH_UCODE; 3294 break; 3295 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3296 *type = GFX_FW_TYPE_UMSCH_DATA; 3297 break; 3298 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3299 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3300 break; 3301 case AMDGPU_UCODE_ID_P2S_TABLE: 3302 *type = GFX_FW_TYPE_P2S_TABLE; 3303 break; 3304 case AMDGPU_UCODE_ID_JPEG_RAM: 3305 *type = GFX_FW_TYPE_JPEG_RAM; 3306 break; 3307 case AMDGPU_UCODE_ID_ISP: 3308 *type = GFX_FW_TYPE_ISP; 3309 break; 3310 case AMDGPU_UCODE_ID_MAXIMUM: 3311 default: 3312 return -EINVAL; 3313 } 3314 3315 return 0; 3316 } 3317 3318 static void psp_print_fw_hdr(struct psp_context *psp, 3319 struct amdgpu_firmware_info *ucode) 3320 { 3321 struct amdgpu_device *adev = psp->adev; 3322 struct common_firmware_header *hdr; 3323 3324 switch (ucode->ucode_id) { 3325 case AMDGPU_UCODE_ID_SDMA0: 3326 case AMDGPU_UCODE_ID_SDMA1: 3327 case AMDGPU_UCODE_ID_SDMA2: 3328 case AMDGPU_UCODE_ID_SDMA3: 3329 case AMDGPU_UCODE_ID_SDMA4: 3330 case AMDGPU_UCODE_ID_SDMA5: 3331 case AMDGPU_UCODE_ID_SDMA6: 3332 case AMDGPU_UCODE_ID_SDMA7: 3333 hdr = (struct common_firmware_header *) 3334 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3335 amdgpu_ucode_print_sdma_hdr(hdr); 3336 break; 3337 case AMDGPU_UCODE_ID_CP_CE: 3338 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3339 amdgpu_ucode_print_gfx_hdr(hdr); 3340 break; 3341 case AMDGPU_UCODE_ID_CP_PFP: 3342 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3343 amdgpu_ucode_print_gfx_hdr(hdr); 3344 break; 3345 case AMDGPU_UCODE_ID_CP_ME: 3346 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3347 amdgpu_ucode_print_gfx_hdr(hdr); 3348 break; 3349 case AMDGPU_UCODE_ID_CP_MEC1: 3350 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3351 amdgpu_ucode_print_gfx_hdr(hdr); 3352 break; 3353 case AMDGPU_UCODE_ID_RLC_G: 3354 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3355 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3356 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3357 amdgpu_ucode_print_rlc_hdr(hdr); 3358 break; 3359 case AMDGPU_UCODE_ID_SMC: 3360 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3361 amdgpu_ucode_print_smc_hdr(hdr); 3362 break; 3363 default: 3364 break; 3365 } 3366 } 3367 3368 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3369 struct amdgpu_firmware_info *ucode, 3370 struct psp_gfx_cmd_resp *cmd) 3371 { 3372 int ret; 3373 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3374 3375 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3376 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3377 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3378 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3379 3380 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3381 if (ret) 3382 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3383 return ret; 3384 } 3385 3386 int psp_execute_ip_fw_load(struct psp_context *psp, 3387 struct amdgpu_firmware_info *ucode) 3388 { 3389 int ret = 0; 3390 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3391 3392 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3393 if (!ret) { 3394 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3395 psp->fence_buf_mc_addr); 3396 } 3397 3398 release_psp_cmd_buf(psp); 3399 3400 return ret; 3401 } 3402 3403 static int psp_load_p2s_table(struct psp_context *psp) 3404 { 3405 int ret; 3406 struct amdgpu_device *adev = psp->adev; 3407 struct amdgpu_firmware_info *ucode = 3408 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3409 3410 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3411 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3412 return 0; 3413 3414 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3415 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3416 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3417 0x0036003C; 3418 if (psp->sos.fw_version < supp_vers) 3419 return 0; 3420 } 3421 3422 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3423 return 0; 3424 3425 ret = psp_execute_ip_fw_load(psp, ucode); 3426 3427 return ret; 3428 } 3429 3430 static int psp_load_smu_fw(struct psp_context *psp) 3431 { 3432 int ret; 3433 struct amdgpu_device *adev = psp->adev; 3434 struct amdgpu_firmware_info *ucode = 3435 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3436 struct amdgpu_ras *ras = psp->ras_context.ras; 3437 3438 /* 3439 * Skip SMU FW reloading in case of using BACO for runpm only, 3440 * as SMU is always alive. 3441 */ 3442 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3443 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3444 return 0; 3445 3446 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3447 return 0; 3448 3449 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3450 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3451 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3452 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3453 if (ret) 3454 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3455 } 3456 3457 ret = psp_execute_ip_fw_load(psp, ucode); 3458 3459 if (ret) 3460 dev_err(adev->dev, "PSP load smu failed!\n"); 3461 3462 return ret; 3463 } 3464 3465 static bool fw_load_skip_check(struct psp_context *psp, 3466 struct amdgpu_firmware_info *ucode) 3467 { 3468 if (!ucode->fw || !ucode->ucode_size) 3469 return true; 3470 3471 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3472 return true; 3473 3474 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3475 (psp_smu_reload_quirk(psp) || 3476 psp->autoload_supported || 3477 psp->pmfw_centralized_cstate_management)) 3478 return true; 3479 3480 if (amdgpu_sriov_vf(psp->adev) && 3481 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3482 return true; 3483 3484 if (psp->autoload_supported && 3485 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3486 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3487 /* skip mec JT when autoload is enabled */ 3488 return true; 3489 3490 return false; 3491 } 3492 3493 int psp_load_fw_list(struct psp_context *psp, 3494 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3495 { 3496 int ret = 0, i; 3497 struct amdgpu_firmware_info *ucode; 3498 3499 for (i = 0; i < ucode_count; ++i) { 3500 ucode = ucode_list[i]; 3501 psp_print_fw_hdr(psp, ucode); 3502 ret = psp_execute_ip_fw_load(psp, ucode); 3503 if (ret) 3504 return ret; 3505 } 3506 return ret; 3507 } 3508 3509 static int psp_load_non_psp_fw(struct psp_context *psp) 3510 { 3511 int i, ret; 3512 struct amdgpu_firmware_info *ucode; 3513 struct amdgpu_device *adev = psp->adev; 3514 3515 if (psp->autoload_supported && 3516 !psp->pmfw_centralized_cstate_management) { 3517 ret = psp_load_smu_fw(psp); 3518 if (ret) 3519 return ret; 3520 } 3521 3522 /* Load P2S table first if it's available */ 3523 psp_load_p2s_table(psp); 3524 3525 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3526 ucode = &adev->firmware.ucode[i]; 3527 3528 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3529 !fw_load_skip_check(psp, ucode)) { 3530 ret = psp_load_smu_fw(psp); 3531 if (ret) 3532 return ret; 3533 continue; 3534 } 3535 3536 if (fw_load_skip_check(psp, ucode)) 3537 continue; 3538 3539 if (psp->autoload_supported && 3540 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3541 IP_VERSION(11, 0, 7) || 3542 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3543 IP_VERSION(11, 0, 11) || 3544 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3545 IP_VERSION(11, 0, 12) || 3546 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3547 IP_VERSION(15, 0, 0) || 3548 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3549 IP_VERSION(15, 0, 5) || 3550 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3551 IP_VERSION(15, 0, 8) || 3552 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3553 IP_VERSION(15, 0, 9)) && 3554 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3555 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3556 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3557 /* PSP only receive one SDMA fw for sienna_cichlid, 3558 * as all four sdma fw are same 3559 */ 3560 continue; 3561 3562 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3563 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3564 IP_VERSION(15, 0, 8) && 3565 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3566 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3567 continue; 3568 3569 psp_print_fw_hdr(psp, ucode); 3570 3571 ret = psp_execute_ip_fw_load(psp, ucode); 3572 if (ret) 3573 return ret; 3574 3575 /* Start rlc autoload after psp received all the gfx firmware */ 3576 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3577 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3578 ret = psp_rlc_autoload_start(psp); 3579 if (ret) { 3580 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3581 return ret; 3582 } 3583 } 3584 } 3585 3586 return 0; 3587 } 3588 3589 static int psp_load_fw(struct amdgpu_device *adev) 3590 { 3591 int ret; 3592 struct psp_context *psp = &adev->psp; 3593 3594 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3595 /* should not destroy ring, only stop */ 3596 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3597 } else { 3598 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3599 3600 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3601 if (ret) { 3602 dev_err(adev->dev, "PSP ring init failed!\n"); 3603 goto failed; 3604 } 3605 } 3606 3607 ret = psp_hw_start(psp); 3608 if (ret) 3609 goto failed; 3610 3611 ret = psp_load_non_psp_fw(psp); 3612 if (ret) 3613 goto failed1; 3614 3615 ret = psp_asd_initialize(psp); 3616 if (ret) { 3617 dev_err(adev->dev, "PSP load asd failed!\n"); 3618 goto failed1; 3619 } 3620 3621 ret = psp_rl_load(adev); 3622 if (ret) { 3623 dev_err(adev->dev, "PSP load RL failed!\n"); 3624 goto failed1; 3625 } 3626 3627 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3628 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3629 ret = psp_xgmi_initialize(psp, false, true); 3630 /* Warning the XGMI seesion initialize failure 3631 * Instead of stop driver initialization 3632 */ 3633 if (ret) 3634 dev_err(psp->adev->dev, 3635 "XGMI: Failed to initialize XGMI session\n"); 3636 } 3637 } 3638 3639 if (psp->ta_fw) { 3640 ret = psp_ras_initialize(psp); 3641 if (ret) 3642 dev_err(psp->adev->dev, 3643 "RAS: Failed to initialize RAS\n"); 3644 3645 ret = psp_hdcp_initialize(psp); 3646 if (ret) 3647 dev_err(psp->adev->dev, 3648 "HDCP: Failed to initialize HDCP\n"); 3649 3650 ret = psp_dtm_initialize(psp); 3651 if (ret) 3652 dev_err(psp->adev->dev, 3653 "DTM: Failed to initialize DTM\n"); 3654 3655 ret = psp_rap_initialize(psp); 3656 if (ret) 3657 dev_err(psp->adev->dev, 3658 "RAP: Failed to initialize RAP\n"); 3659 3660 ret = psp_securedisplay_initialize(psp); 3661 if (ret) 3662 dev_err(psp->adev->dev, 3663 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3664 } 3665 3666 return 0; 3667 3668 failed1: 3669 psp_free_shared_bufs(psp); 3670 failed: 3671 /* 3672 * all cleanup jobs (xgmi terminate, ras terminate, 3673 * ring destroy, cmd/fence/fw buffers destory, 3674 * psp->cmd destory) are delayed to psp_hw_fini 3675 */ 3676 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3677 return ret; 3678 } 3679 3680 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3681 { 3682 int ret; 3683 struct amdgpu_device *adev = ip_block->adev; 3684 3685 mutex_lock(&adev->firmware.mutex); 3686 3687 ret = amdgpu_ucode_init_bo(adev); 3688 if (ret) 3689 goto failed; 3690 3691 ret = psp_load_fw(adev); 3692 if (ret) { 3693 dev_err(adev->dev, "PSP firmware loading failed\n"); 3694 goto failed; 3695 } 3696 3697 mutex_unlock(&adev->firmware.mutex); 3698 return 0; 3699 3700 failed: 3701 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3702 mutex_unlock(&adev->firmware.mutex); 3703 return -EINVAL; 3704 } 3705 3706 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3707 { 3708 struct amdgpu_device *adev = ip_block->adev; 3709 struct psp_context *psp = &adev->psp; 3710 3711 if (psp->ta_fw) { 3712 psp_ras_terminate(psp); 3713 psp_securedisplay_terminate(psp); 3714 psp_rap_terminate(psp); 3715 psp_dtm_terminate(psp); 3716 psp_hdcp_terminate(psp); 3717 3718 if (adev->gmc.xgmi.num_physical_nodes > 1) 3719 psp_xgmi_terminate(psp); 3720 } 3721 3722 psp_asd_terminate(psp); 3723 psp_tmr_terminate(psp); 3724 3725 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3726 3727 return 0; 3728 } 3729 3730 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3731 { 3732 int ret = 0; 3733 struct amdgpu_device *adev = ip_block->adev; 3734 struct psp_context *psp = &adev->psp; 3735 3736 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3737 psp->xgmi_context.context.initialized) { 3738 ret = psp_xgmi_terminate(psp); 3739 if (ret) { 3740 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3741 goto out; 3742 } 3743 } 3744 3745 if (psp->ta_fw) { 3746 ret = psp_ras_terminate(psp); 3747 if (ret) { 3748 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3749 goto out; 3750 } 3751 ret = psp_hdcp_terminate(psp); 3752 if (ret) { 3753 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3754 goto out; 3755 } 3756 ret = psp_dtm_terminate(psp); 3757 if (ret) { 3758 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3759 goto out; 3760 } 3761 ret = psp_rap_terminate(psp); 3762 if (ret) { 3763 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3764 goto out; 3765 } 3766 ret = psp_securedisplay_terminate(psp); 3767 if (ret) { 3768 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3769 goto out; 3770 } 3771 } 3772 3773 ret = psp_asd_terminate(psp); 3774 if (ret) { 3775 dev_err(adev->dev, "Failed to terminate asd\n"); 3776 goto out; 3777 } 3778 3779 ret = psp_tmr_terminate(psp); 3780 if (ret) { 3781 dev_err(adev->dev, "Failed to terminate tmr\n"); 3782 goto out; 3783 } 3784 3785 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3786 if (ret) 3787 dev_err(adev->dev, "PSP ring stop failed\n"); 3788 3789 out: 3790 return ret; 3791 } 3792 3793 static int psp_resume(struct amdgpu_ip_block *ip_block) 3794 { 3795 int ret; 3796 struct amdgpu_device *adev = ip_block->adev; 3797 struct psp_context *psp = &adev->psp; 3798 3799 dev_info(adev->dev, "PSP is resuming...\n"); 3800 3801 if (psp->mem_train_ctx.enable_mem_training) { 3802 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3803 if (ret) { 3804 dev_err(adev->dev, "Failed to process memory training!\n"); 3805 return ret; 3806 } 3807 } 3808 3809 mutex_lock(&adev->firmware.mutex); 3810 3811 ret = amdgpu_ucode_init_bo(adev); 3812 if (ret) 3813 goto failed; 3814 3815 ret = psp_hw_start(psp); 3816 if (ret) 3817 goto failed; 3818 3819 ret = psp_load_non_psp_fw(psp); 3820 if (ret) 3821 goto failed; 3822 3823 ret = psp_asd_initialize(psp); 3824 if (ret) { 3825 dev_err(adev->dev, "PSP load asd failed!\n"); 3826 goto failed; 3827 } 3828 3829 ret = psp_rl_load(adev); 3830 if (ret) { 3831 dev_err(adev->dev, "PSP load RL failed!\n"); 3832 goto failed; 3833 } 3834 3835 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3836 ret = psp_xgmi_initialize(psp, false, true); 3837 /* Warning the XGMI seesion initialize failure 3838 * Instead of stop driver initialization 3839 */ 3840 if (ret) 3841 dev_err(psp->adev->dev, 3842 "XGMI: Failed to initialize XGMI session\n"); 3843 } 3844 3845 if (psp->ta_fw) { 3846 ret = psp_ras_initialize(psp); 3847 if (ret) 3848 dev_err(psp->adev->dev, 3849 "RAS: Failed to initialize RAS\n"); 3850 3851 ret = psp_hdcp_initialize(psp); 3852 if (ret) 3853 dev_err(psp->adev->dev, 3854 "HDCP: Failed to initialize HDCP\n"); 3855 3856 ret = psp_dtm_initialize(psp); 3857 if (ret) 3858 dev_err(psp->adev->dev, 3859 "DTM: Failed to initialize DTM\n"); 3860 3861 ret = psp_rap_initialize(psp); 3862 if (ret) 3863 dev_err(psp->adev->dev, 3864 "RAP: Failed to initialize RAP\n"); 3865 3866 ret = psp_securedisplay_initialize(psp); 3867 if (ret) 3868 dev_err(psp->adev->dev, 3869 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3870 } 3871 3872 mutex_unlock(&adev->firmware.mutex); 3873 3874 return 0; 3875 3876 failed: 3877 dev_err(adev->dev, "PSP resume failed\n"); 3878 mutex_unlock(&adev->firmware.mutex); 3879 return ret; 3880 } 3881 3882 int psp_gpu_reset(struct amdgpu_device *adev) 3883 { 3884 int ret; 3885 3886 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3887 return 0; 3888 3889 mutex_lock(&adev->psp.mutex); 3890 ret = psp_mode1_reset(&adev->psp); 3891 mutex_unlock(&adev->psp.mutex); 3892 3893 return ret; 3894 } 3895 3896 int psp_rlc_autoload_start(struct psp_context *psp) 3897 { 3898 int ret; 3899 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3900 3901 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3902 3903 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3904 psp->fence_buf_mc_addr); 3905 3906 release_psp_cmd_buf(psp); 3907 3908 return ret; 3909 } 3910 3911 int psp_ring_cmd_submit(struct psp_context *psp, 3912 uint64_t cmd_buf_mc_addr, 3913 uint64_t fence_mc_addr, 3914 int index) 3915 { 3916 unsigned int psp_write_ptr_reg = 0; 3917 struct psp_gfx_rb_frame *write_frame; 3918 struct psp_ring *ring = &psp->km_ring; 3919 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3920 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3921 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3922 struct amdgpu_device *adev = psp->adev; 3923 uint32_t ring_size_dw = ring->ring_size / 4; 3924 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3925 3926 /* KM (GPCOM) prepare write pointer */ 3927 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3928 3929 /* Update KM RB frame pointer to new frame */ 3930 /* write_frame ptr increments by size of rb_frame in bytes */ 3931 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3932 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3933 write_frame = ring_buffer_start; 3934 else 3935 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3936 /* Check invalid write_frame ptr address */ 3937 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3938 dev_err(adev->dev, 3939 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3940 ring_buffer_start, ring_buffer_end, write_frame); 3941 dev_err(adev->dev, 3942 "write_frame is pointing to address out of bounds\n"); 3943 return -EINVAL; 3944 } 3945 3946 /* Initialize KM RB frame */ 3947 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3948 3949 /* Update KM RB frame */ 3950 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3951 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3952 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3953 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3954 write_frame->fence_value = index; 3955 amdgpu_device_flush_hdp(adev, NULL); 3956 3957 /* Update the write Pointer in DWORDs */ 3958 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3959 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3960 return 0; 3961 } 3962 3963 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3964 { 3965 struct amdgpu_device *adev = psp->adev; 3966 const struct psp_firmware_header_v1_0 *asd_hdr; 3967 int err = 0; 3968 3969 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3970 "amdgpu/%s_asd.bin", chip_name); 3971 if (err) 3972 goto out; 3973 3974 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3975 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3976 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3977 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3978 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3979 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3980 return 0; 3981 out: 3982 amdgpu_ucode_release(&adev->psp.asd_fw); 3983 return err; 3984 } 3985 3986 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3987 { 3988 struct amdgpu_device *adev = psp->adev; 3989 const struct psp_firmware_header_v1_0 *toc_hdr; 3990 int err = 0; 3991 3992 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3993 adev->rev_id == 0) 3994 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3995 "amdgpu/%s_toc_1.bin", chip_name); 3996 else 3997 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3998 "amdgpu/%s_toc.bin", chip_name); 3999 if (err) 4000 goto out; 4001 4002 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 4003 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 4004 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 4005 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 4006 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 4007 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 4008 return 0; 4009 out: 4010 amdgpu_ucode_release(&adev->psp.toc_fw); 4011 return err; 4012 } 4013 4014 static int parse_sos_bin_descriptor(struct psp_context *psp, 4015 const struct psp_fw_bin_desc *desc, 4016 const struct psp_firmware_header_v2_0 *sos_hdr) 4017 { 4018 uint8_t *ucode_start_addr = NULL; 4019 4020 if (!psp || !desc || !sos_hdr) 4021 return -EINVAL; 4022 4023 ucode_start_addr = (uint8_t *)sos_hdr + 4024 le32_to_cpu(desc->offset_bytes) + 4025 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4026 4027 switch (desc->fw_type) { 4028 case PSP_FW_TYPE_PSP_SOS: 4029 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 4030 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 4031 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 4032 psp->sos.start_addr = ucode_start_addr; 4033 break; 4034 case PSP_FW_TYPE_PSP_SYS_DRV: 4035 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 4036 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 4037 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 4038 psp->sys.start_addr = ucode_start_addr; 4039 break; 4040 case PSP_FW_TYPE_PSP_KDB: 4041 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 4042 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 4043 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 4044 psp->kdb.start_addr = ucode_start_addr; 4045 break; 4046 case PSP_FW_TYPE_PSP_TOC: 4047 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 4048 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 4049 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 4050 psp->toc.start_addr = ucode_start_addr; 4051 break; 4052 case PSP_FW_TYPE_PSP_SPL: 4053 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 4054 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 4055 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 4056 psp->spl.start_addr = ucode_start_addr; 4057 break; 4058 case PSP_FW_TYPE_PSP_RL: 4059 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 4060 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 4061 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 4062 psp->rl.start_addr = ucode_start_addr; 4063 break; 4064 case PSP_FW_TYPE_PSP_SOC_DRV: 4065 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 4066 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 4067 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4068 psp->soc_drv.start_addr = ucode_start_addr; 4069 break; 4070 case PSP_FW_TYPE_PSP_INTF_DRV: 4071 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4072 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4073 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4074 psp->intf_drv.start_addr = ucode_start_addr; 4075 break; 4076 case PSP_FW_TYPE_PSP_DBG_DRV: 4077 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4078 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4079 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4080 psp->dbg_drv.start_addr = ucode_start_addr; 4081 break; 4082 case PSP_FW_TYPE_PSP_RAS_DRV: 4083 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4084 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4085 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4086 psp->ras_drv.start_addr = ucode_start_addr; 4087 break; 4088 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4089 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4090 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4091 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4092 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4093 break; 4094 case PSP_FW_TYPE_PSP_SPDM_DRV: 4095 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4096 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4097 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4098 psp->spdm_drv.start_addr = ucode_start_addr; 4099 break; 4100 default: 4101 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4102 break; 4103 } 4104 4105 return 0; 4106 } 4107 4108 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4109 { 4110 const struct psp_firmware_header_v1_0 *sos_hdr; 4111 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4112 uint8_t *ucode_array_start_addr; 4113 4114 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4115 ucode_array_start_addr = (uint8_t *)sos_hdr + 4116 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4117 4118 if (adev->gmc.xgmi.connected_to_cpu || 4119 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4120 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4121 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4122 4123 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4124 adev->psp.sys.start_addr = ucode_array_start_addr; 4125 4126 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4127 adev->psp.sos.start_addr = ucode_array_start_addr + 4128 le32_to_cpu(sos_hdr->sos.offset_bytes); 4129 } else { 4130 /* Load alternate PSP SOS FW */ 4131 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4132 4133 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4134 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4135 4136 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4137 adev->psp.sys.start_addr = ucode_array_start_addr + 4138 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4139 4140 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4141 adev->psp.sos.start_addr = ucode_array_start_addr + 4142 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4143 } 4144 4145 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4146 dev_warn(adev->dev, "PSP SOS FW not available"); 4147 return -EINVAL; 4148 } 4149 4150 return 0; 4151 } 4152 4153 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4154 { 4155 struct amdgpu_device *adev = psp->adev; 4156 const struct psp_firmware_header_v1_0 *sos_hdr; 4157 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4158 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4159 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4160 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4161 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4162 int fw_index, fw_bin_count, start_index = 0; 4163 const struct psp_fw_bin_desc *fw_bin; 4164 uint8_t *ucode_array_start_addr; 4165 int err = 0; 4166 4167 if (amdgpu_is_kicker_fw(adev)) 4168 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4169 "amdgpu/%s_sos_kicker.bin", chip_name); 4170 else 4171 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4172 "amdgpu/%s_sos.bin", chip_name); 4173 if (err) 4174 goto out; 4175 4176 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4177 ucode_array_start_addr = (uint8_t *)sos_hdr + 4178 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4179 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4180 4181 switch (sos_hdr->header.header_version_major) { 4182 case 1: 4183 err = psp_init_sos_base_fw(adev); 4184 if (err) 4185 goto out; 4186 4187 if (sos_hdr->header.header_version_minor == 1) { 4188 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4189 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4190 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4191 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4192 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4193 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4194 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4195 } 4196 if (sos_hdr->header.header_version_minor == 2) { 4197 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4198 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4199 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4200 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4201 } 4202 if (sos_hdr->header.header_version_minor == 3) { 4203 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4204 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4205 adev->psp.toc.start_addr = ucode_array_start_addr + 4206 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4207 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4208 adev->psp.kdb.start_addr = ucode_array_start_addr + 4209 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4210 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4211 adev->psp.spl.start_addr = ucode_array_start_addr + 4212 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4213 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4214 adev->psp.rl.start_addr = ucode_array_start_addr + 4215 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4216 } 4217 break; 4218 case 2: 4219 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4220 4221 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4222 4223 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4224 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4225 err = -EINVAL; 4226 goto out; 4227 } 4228 4229 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4230 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4231 4232 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4233 4234 if (psp_is_aux_sos_load_required(psp)) 4235 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4236 else 4237 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4238 4239 } else { 4240 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4241 } 4242 4243 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4244 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4245 sos_hdr_v2_0); 4246 if (err) 4247 goto out; 4248 } 4249 break; 4250 default: 4251 dev_err(adev->dev, 4252 "unsupported psp sos firmware\n"); 4253 err = -EINVAL; 4254 goto out; 4255 } 4256 4257 return 0; 4258 out: 4259 amdgpu_ucode_release(&adev->psp.sos_fw); 4260 4261 return err; 4262 } 4263 4264 static bool is_ta_fw_applicable(struct psp_context *psp, 4265 const struct psp_fw_bin_desc *desc) 4266 { 4267 struct amdgpu_device *adev = psp->adev; 4268 uint32_t fw_version; 4269 4270 switch (desc->fw_type) { 4271 case TA_FW_TYPE_PSP_XGMI: 4272 case TA_FW_TYPE_PSP_XGMI_AUX: 4273 /* for now, AUX TA only exists on 13.0.6 ta bin, 4274 * from v20.00.0x.14 4275 */ 4276 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4277 IP_VERSION(13, 0, 6)) { 4278 fw_version = le32_to_cpu(desc->fw_version); 4279 4280 if (adev->flags & AMD_IS_APU && 4281 (fw_version & 0xff) >= 0x14) 4282 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4283 else 4284 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4285 } 4286 break; 4287 default: 4288 break; 4289 } 4290 4291 return true; 4292 } 4293 4294 static int parse_ta_bin_descriptor(struct psp_context *psp, 4295 const struct psp_fw_bin_desc *desc, 4296 const struct ta_firmware_header_v2_0 *ta_hdr) 4297 { 4298 uint8_t *ucode_start_addr = NULL; 4299 4300 if (!psp || !desc || !ta_hdr) 4301 return -EINVAL; 4302 4303 if (!is_ta_fw_applicable(psp, desc)) 4304 return 0; 4305 4306 ucode_start_addr = (uint8_t *)ta_hdr + 4307 le32_to_cpu(desc->offset_bytes) + 4308 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4309 4310 switch (desc->fw_type) { 4311 case TA_FW_TYPE_PSP_ASD: 4312 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4313 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4314 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4315 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4316 break; 4317 case TA_FW_TYPE_PSP_XGMI: 4318 case TA_FW_TYPE_PSP_XGMI_AUX: 4319 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4320 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4321 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4322 break; 4323 case TA_FW_TYPE_PSP_RAS: 4324 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4325 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4326 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4327 break; 4328 case TA_FW_TYPE_PSP_HDCP: 4329 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4330 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4331 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4332 break; 4333 case TA_FW_TYPE_PSP_DTM: 4334 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4335 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4336 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4337 break; 4338 case TA_FW_TYPE_PSP_RAP: 4339 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4340 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4341 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4342 break; 4343 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4344 psp->securedisplay_context.context.bin_desc.fw_version = 4345 le32_to_cpu(desc->fw_version); 4346 psp->securedisplay_context.context.bin_desc.size_bytes = 4347 le32_to_cpu(desc->size_bytes); 4348 psp->securedisplay_context.context.bin_desc.start_addr = 4349 ucode_start_addr; 4350 break; 4351 default: 4352 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4353 break; 4354 } 4355 4356 return 0; 4357 } 4358 4359 static int parse_ta_v1_microcode(struct psp_context *psp) 4360 { 4361 const struct ta_firmware_header_v1_0 *ta_hdr; 4362 struct amdgpu_device *adev = psp->adev; 4363 4364 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4365 4366 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4367 return -EINVAL; 4368 4369 adev->psp.xgmi_context.context.bin_desc.fw_version = 4370 le32_to_cpu(ta_hdr->xgmi.fw_version); 4371 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4372 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4373 adev->psp.xgmi_context.context.bin_desc.start_addr = 4374 (uint8_t *)ta_hdr + 4375 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4376 4377 adev->psp.ras_context.context.bin_desc.fw_version = 4378 le32_to_cpu(ta_hdr->ras.fw_version); 4379 adev->psp.ras_context.context.bin_desc.size_bytes = 4380 le32_to_cpu(ta_hdr->ras.size_bytes); 4381 adev->psp.ras_context.context.bin_desc.start_addr = 4382 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4383 le32_to_cpu(ta_hdr->ras.offset_bytes); 4384 4385 adev->psp.hdcp_context.context.bin_desc.fw_version = 4386 le32_to_cpu(ta_hdr->hdcp.fw_version); 4387 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4388 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4389 adev->psp.hdcp_context.context.bin_desc.start_addr = 4390 (uint8_t *)ta_hdr + 4391 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4392 4393 adev->psp.dtm_context.context.bin_desc.fw_version = 4394 le32_to_cpu(ta_hdr->dtm.fw_version); 4395 adev->psp.dtm_context.context.bin_desc.size_bytes = 4396 le32_to_cpu(ta_hdr->dtm.size_bytes); 4397 adev->psp.dtm_context.context.bin_desc.start_addr = 4398 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4399 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4400 4401 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4402 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4403 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4404 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4405 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4406 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4407 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4408 4409 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4410 4411 return 0; 4412 } 4413 4414 static int parse_ta_v2_microcode(struct psp_context *psp) 4415 { 4416 const struct ta_firmware_header_v2_0 *ta_hdr; 4417 struct amdgpu_device *adev = psp->adev; 4418 int err = 0; 4419 int ta_index = 0; 4420 4421 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4422 4423 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4424 return -EINVAL; 4425 4426 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4427 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4428 return -EINVAL; 4429 } 4430 4431 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4432 err = parse_ta_bin_descriptor(psp, 4433 &ta_hdr->ta_fw_bin[ta_index], 4434 ta_hdr); 4435 if (err) 4436 return err; 4437 } 4438 4439 return 0; 4440 } 4441 4442 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4443 { 4444 const struct common_firmware_header *hdr; 4445 struct amdgpu_device *adev = psp->adev; 4446 int err; 4447 4448 if (amdgpu_is_kicker_fw(adev)) 4449 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4450 "amdgpu/%s_ta_kicker.bin", chip_name); 4451 else 4452 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4453 "amdgpu/%s_ta.bin", chip_name); 4454 if (err) 4455 return err; 4456 4457 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4458 switch (le16_to_cpu(hdr->header_version_major)) { 4459 case 1: 4460 err = parse_ta_v1_microcode(psp); 4461 break; 4462 case 2: 4463 err = parse_ta_v2_microcode(psp); 4464 break; 4465 default: 4466 dev_err(adev->dev, "unsupported TA header version\n"); 4467 err = -EINVAL; 4468 } 4469 4470 if (err) 4471 amdgpu_ucode_release(&adev->psp.ta_fw); 4472 4473 return err; 4474 } 4475 4476 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4477 { 4478 struct amdgpu_device *adev = psp->adev; 4479 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4480 struct amdgpu_firmware_info *info = NULL; 4481 int err = 0; 4482 4483 if (!amdgpu_sriov_vf(adev)) { 4484 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4485 return -EINVAL; 4486 } 4487 4488 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4489 "amdgpu/%s_cap.bin", chip_name); 4490 if (err) { 4491 if (err == -ENODEV) { 4492 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4493 err = 0; 4494 } else { 4495 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4496 } 4497 goto out; 4498 } 4499 4500 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4501 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4502 info->fw = adev->psp.cap_fw; 4503 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4504 adev->psp.cap_fw->data; 4505 adev->firmware.fw_size += ALIGN( 4506 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4507 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4508 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4509 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4510 4511 return 0; 4512 4513 out: 4514 amdgpu_ucode_release(&adev->psp.cap_fw); 4515 return err; 4516 } 4517 4518 int psp_config_sq_perfmon(struct psp_context *psp, 4519 uint32_t xcp_id, bool core_override_enable, 4520 bool reg_override_enable, bool perfmon_override_enable) 4521 { 4522 int ret; 4523 4524 if (amdgpu_sriov_vf(psp->adev)) 4525 return 0; 4526 4527 if (xcp_id > MAX_XCP) { 4528 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4529 return -EINVAL; 4530 } 4531 4532 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4533 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4534 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4535 return -EINVAL; 4536 } 4537 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4538 4539 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4540 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4541 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4542 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4543 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4544 4545 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4546 if (ret) 4547 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4548 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4549 4550 release_psp_cmd_buf(psp); 4551 return ret; 4552 } 4553 4554 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4555 enum amd_clockgating_state state) 4556 { 4557 return 0; 4558 } 4559 4560 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4561 enum amd_powergating_state state) 4562 { 4563 return 0; 4564 } 4565 4566 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4567 struct device_attribute *attr, 4568 char *buf) 4569 { 4570 struct drm_device *ddev = dev_get_drvdata(dev); 4571 struct amdgpu_device *adev = drm_to_adev(ddev); 4572 struct amdgpu_ip_block *ip_block; 4573 uint32_t fw_ver; 4574 int ret; 4575 4576 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4577 if (!ip_block || !ip_block->status.late_initialized) { 4578 dev_info(adev->dev, "PSP block is not ready yet\n."); 4579 return -EBUSY; 4580 } 4581 4582 mutex_lock(&adev->psp.mutex); 4583 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4584 mutex_unlock(&adev->psp.mutex); 4585 4586 if (ret) { 4587 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4588 return ret; 4589 } 4590 4591 return sysfs_emit(buf, "%x\n", fw_ver); 4592 } 4593 4594 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4595 struct device_attribute *attr, 4596 const char *buf, 4597 size_t count) 4598 { 4599 struct drm_device *ddev = dev_get_drvdata(dev); 4600 struct amdgpu_device *adev = drm_to_adev(ddev); 4601 int ret, idx; 4602 const struct firmware *usbc_pd_fw; 4603 struct amdgpu_bo *fw_buf_bo = NULL; 4604 uint64_t fw_pri_mc_addr; 4605 void *fw_pri_cpu_addr; 4606 struct amdgpu_ip_block *ip_block; 4607 4608 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4609 if (!ip_block || !ip_block->status.late_initialized) { 4610 dev_err(adev->dev, "PSP block is not ready yet."); 4611 return -EBUSY; 4612 } 4613 4614 if (!drm_dev_enter(ddev, &idx)) 4615 return -ENODEV; 4616 4617 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4618 "amdgpu/%s", buf); 4619 if (ret) 4620 goto fail; 4621 4622 /* LFB address which is aligned to 1MB boundary per PSP request */ 4623 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4624 AMDGPU_GEM_DOMAIN_VRAM | 4625 AMDGPU_GEM_DOMAIN_GTT, 4626 &fw_buf_bo, &fw_pri_mc_addr, 4627 &fw_pri_cpu_addr); 4628 if (ret) 4629 goto rel_buf; 4630 4631 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4632 4633 mutex_lock(&adev->psp.mutex); 4634 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4635 mutex_unlock(&adev->psp.mutex); 4636 4637 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4638 4639 rel_buf: 4640 amdgpu_ucode_release(&usbc_pd_fw); 4641 fail: 4642 if (ret) { 4643 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4644 count = ret; 4645 } 4646 4647 drm_dev_exit(idx); 4648 return count; 4649 } 4650 4651 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4652 { 4653 int idx; 4654 4655 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4656 return -ENODEV; 4657 4658 if (!bin_size || bin_size > PSP_1_MEG) { 4659 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4660 drm_dev_exit(idx); 4661 return -EINVAL; 4662 } 4663 4664 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4665 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4666 4667 drm_dev_exit(idx); 4668 return 0; 4669 } 4670 4671 /** 4672 * DOC: usbc_pd_fw 4673 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4674 * this file will trigger the update process. 4675 */ 4676 static DEVICE_ATTR(usbc_pd_fw, 0644, 4677 psp_usbc_pd_fw_sysfs_read, 4678 psp_usbc_pd_fw_sysfs_write); 4679 /** 4680 * DOC: PTL sysfs attributes 4681 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4682 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4683 * formats for each GPU. 4684 */ 4685 static DEVICE_ATTR(ptl_enable, 0644, 4686 ptl_enable_show, ptl_enable_store); 4687 static DEVICE_ATTR(ptl_format, 0644, 4688 ptl_format_show, ptl_format_store); 4689 static DEVICE_ATTR(ptl_supported_formats, 0444, 4690 ptl_supported_formats_show, NULL); 4691 4692 static struct attribute *ptl_attrs[] = { 4693 &dev_attr_ptl_enable.attr, 4694 &dev_attr_ptl_format.attr, 4695 &dev_attr_ptl_supported_formats.attr, 4696 NULL, 4697 }; 4698 4699 const struct attribute_group amdgpu_ptl_attr_group = { 4700 .name = "ptl", 4701 .attrs = ptl_attrs, 4702 .is_visible = amdgpu_ptl_is_visible, 4703 }; 4704 4705 int is_psp_fw_valid(struct psp_bin_desc bin) 4706 { 4707 return bin.size_bytes; 4708 } 4709 4710 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4711 const struct bin_attribute *bin_attr, 4712 char *buffer, loff_t pos, size_t count) 4713 { 4714 struct device *dev = kobj_to_dev(kobj); 4715 struct drm_device *ddev = dev_get_drvdata(dev); 4716 struct amdgpu_device *adev = drm_to_adev(ddev); 4717 4718 adev->psp.vbflash_done = false; 4719 4720 /* Safeguard against memory drain */ 4721 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4722 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4723 kvfree(adev->psp.vbflash_tmp_buf); 4724 adev->psp.vbflash_tmp_buf = NULL; 4725 adev->psp.vbflash_image_size = 0; 4726 return -ENOMEM; 4727 } 4728 4729 mutex_lock(&adev->psp.mutex); 4730 4731 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4732 if (!adev->psp.vbflash_tmp_buf) { 4733 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4734 if (!adev->psp.vbflash_tmp_buf) { 4735 mutex_unlock(&adev->psp.mutex); 4736 return -ENOMEM; 4737 } 4738 } 4739 4740 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4741 adev->psp.vbflash_image_size += count; 4742 mutex_unlock(&adev->psp.mutex); 4743 4744 dev_dbg(adev->dev, "IFWI staged for update\n"); 4745 4746 return count; 4747 } 4748 4749 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4750 const struct bin_attribute *bin_attr, char *buffer, 4751 loff_t pos, size_t count) 4752 { 4753 struct device *dev = kobj_to_dev(kobj); 4754 struct drm_device *ddev = dev_get_drvdata(dev); 4755 struct amdgpu_device *adev = drm_to_adev(ddev); 4756 struct amdgpu_bo *fw_buf_bo = NULL; 4757 uint64_t fw_pri_mc_addr; 4758 void *fw_pri_cpu_addr; 4759 int ret; 4760 4761 if (adev->psp.vbflash_image_size == 0) 4762 return -EINVAL; 4763 4764 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4765 4766 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4767 AMDGPU_GPU_PAGE_SIZE, 4768 AMDGPU_GEM_DOMAIN_VRAM, 4769 &fw_buf_bo, 4770 &fw_pri_mc_addr, 4771 &fw_pri_cpu_addr); 4772 if (ret) 4773 goto rel_buf; 4774 4775 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4776 4777 mutex_lock(&adev->psp.mutex); 4778 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4779 mutex_unlock(&adev->psp.mutex); 4780 4781 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4782 4783 rel_buf: 4784 kvfree(adev->psp.vbflash_tmp_buf); 4785 adev->psp.vbflash_tmp_buf = NULL; 4786 adev->psp.vbflash_image_size = 0; 4787 4788 if (ret) { 4789 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4790 return ret; 4791 } 4792 4793 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4794 return 0; 4795 } 4796 4797 /** 4798 * DOC: psp_vbflash 4799 * Writing to this file will stage an IFWI for update. Reading from this file 4800 * will trigger the update process. 4801 */ 4802 static const struct bin_attribute psp_vbflash_bin_attr = { 4803 .attr = {.name = "psp_vbflash", .mode = 0660}, 4804 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4805 .write = amdgpu_psp_vbflash_write, 4806 .read = amdgpu_psp_vbflash_read, 4807 }; 4808 4809 /** 4810 * DOC: psp_vbflash_status 4811 * The status of the flash process. 4812 * 0: IFWI flash not complete. 4813 * 1: IFWI flash complete. 4814 */ 4815 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4816 struct device_attribute *attr, 4817 char *buf) 4818 { 4819 struct drm_device *ddev = dev_get_drvdata(dev); 4820 struct amdgpu_device *adev = drm_to_adev(ddev); 4821 uint32_t vbflash_status; 4822 4823 vbflash_status = psp_vbflash_status(&adev->psp); 4824 if (!adev->psp.vbflash_done) 4825 vbflash_status = 0; 4826 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4827 vbflash_status = 1; 4828 4829 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4830 } 4831 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4832 4833 static const struct bin_attribute *const bin_flash_attrs[] = { 4834 &psp_vbflash_bin_attr, 4835 NULL 4836 }; 4837 4838 static struct attribute *flash_attrs[] = { 4839 &dev_attr_psp_vbflash_status.attr, 4840 &dev_attr_usbc_pd_fw.attr, 4841 NULL 4842 }; 4843 4844 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4845 { 4846 struct device *dev = kobj_to_dev(kobj); 4847 struct drm_device *ddev = dev_get_drvdata(dev); 4848 struct amdgpu_device *adev = drm_to_adev(ddev); 4849 4850 if (attr == &dev_attr_usbc_pd_fw.attr) 4851 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4852 4853 return adev->psp.sup_ifwi_up ? 0440 : 0; 4854 } 4855 4856 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4857 const struct bin_attribute *attr, 4858 int idx) 4859 { 4860 struct device *dev = kobj_to_dev(kobj); 4861 struct drm_device *ddev = dev_get_drvdata(dev); 4862 struct amdgpu_device *adev = drm_to_adev(ddev); 4863 4864 return adev->psp.sup_ifwi_up ? 0660 : 0; 4865 } 4866 4867 const struct attribute_group amdgpu_flash_attr_group = { 4868 .attrs = flash_attrs, 4869 .bin_attrs = bin_flash_attrs, 4870 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4871 .is_visible = amdgpu_flash_attr_is_visible, 4872 }; 4873 4874 #if defined(CONFIG_DEBUG_FS) 4875 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4876 { 4877 struct amdgpu_device *adev = filp->f_inode->i_private; 4878 struct spirom_bo *bo_triplet; 4879 int ret; 4880 4881 /* serialize the open() file calling */ 4882 if (!mutex_trylock(&adev->psp.mutex)) 4883 return -EBUSY; 4884 4885 /* 4886 * make sure only one userpace process is alive for dumping so that 4887 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4888 * let's say the case where one process try opening the file while 4889 * another one has proceeded to read or release. In this way, eliminate 4890 * the use of mutex for read() or release() callback as well. 4891 */ 4892 if (adev->psp.spirom_dump_trip) { 4893 mutex_unlock(&adev->psp.mutex); 4894 return -EBUSY; 4895 } 4896 4897 bo_triplet = kzalloc_obj(struct spirom_bo); 4898 if (!bo_triplet) { 4899 mutex_unlock(&adev->psp.mutex); 4900 return -ENOMEM; 4901 } 4902 4903 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4904 AMDGPU_GPU_PAGE_SIZE, 4905 AMDGPU_GEM_DOMAIN_GTT, 4906 &bo_triplet->bo, 4907 &bo_triplet->mc_addr, 4908 &bo_triplet->cpu_addr); 4909 if (ret) 4910 goto rel_trip; 4911 4912 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4913 if (ret) 4914 goto rel_bo; 4915 4916 adev->psp.spirom_dump_trip = bo_triplet; 4917 mutex_unlock(&adev->psp.mutex); 4918 return 0; 4919 rel_bo: 4920 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4921 &bo_triplet->cpu_addr); 4922 rel_trip: 4923 kfree(bo_triplet); 4924 mutex_unlock(&adev->psp.mutex); 4925 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4926 return ret; 4927 } 4928 4929 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4930 loff_t *pos) 4931 { 4932 struct amdgpu_device *adev = filp->f_inode->i_private; 4933 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4934 4935 if (!bo_triplet) 4936 return -EINVAL; 4937 4938 return simple_read_from_buffer(buf, 4939 size, 4940 pos, bo_triplet->cpu_addr, 4941 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4942 } 4943 4944 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4945 { 4946 struct amdgpu_device *adev = filp->f_inode->i_private; 4947 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4948 4949 if (bo_triplet) { 4950 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4951 &bo_triplet->cpu_addr); 4952 kfree(bo_triplet); 4953 } 4954 4955 adev->psp.spirom_dump_trip = NULL; 4956 return 0; 4957 } 4958 4959 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4960 .owner = THIS_MODULE, 4961 .open = psp_read_spirom_debugfs_open, 4962 .read = psp_read_spirom_debugfs_read, 4963 .release = psp_read_spirom_debugfs_release, 4964 .llseek = default_llseek, 4965 }; 4966 #endif 4967 4968 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4969 { 4970 #if defined(CONFIG_DEBUG_FS) 4971 struct drm_minor *minor = adev_to_drm(adev)->primary; 4972 4973 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4974 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4975 #endif 4976 } 4977 4978 const struct amd_ip_funcs psp_ip_funcs = { 4979 .name = "psp", 4980 .early_init = psp_early_init, 4981 .sw_init = psp_sw_init, 4982 .sw_fini = psp_sw_fini, 4983 .hw_init = psp_hw_init, 4984 .hw_fini = psp_hw_fini, 4985 .suspend = psp_suspend, 4986 .resume = psp_resume, 4987 .set_clockgating_state = psp_set_clockgating_state, 4988 .set_powergating_state = psp_set_powergating_state, 4989 }; 4990 4991 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4992 .type = AMD_IP_BLOCK_TYPE_PSP, 4993 .major = 3, 4994 .minor = 1, 4995 .rev = 0, 4996 .funcs = &psp_ip_funcs, 4997 }; 4998 4999 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 5000 .type = AMD_IP_BLOCK_TYPE_PSP, 5001 .major = 10, 5002 .minor = 0, 5003 .rev = 0, 5004 .funcs = &psp_ip_funcs, 5005 }; 5006 5007 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 5008 .type = AMD_IP_BLOCK_TYPE_PSP, 5009 .major = 11, 5010 .minor = 0, 5011 .rev = 0, 5012 .funcs = &psp_ip_funcs, 5013 }; 5014 5015 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 5016 .type = AMD_IP_BLOCK_TYPE_PSP, 5017 .major = 11, 5018 .minor = 0, 5019 .rev = 8, 5020 .funcs = &psp_ip_funcs, 5021 }; 5022 5023 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 5024 .type = AMD_IP_BLOCK_TYPE_PSP, 5025 .major = 12, 5026 .minor = 0, 5027 .rev = 0, 5028 .funcs = &psp_ip_funcs, 5029 }; 5030 5031 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 5032 .type = AMD_IP_BLOCK_TYPE_PSP, 5033 .major = 13, 5034 .minor = 0, 5035 .rev = 0, 5036 .funcs = &psp_ip_funcs, 5037 }; 5038 5039 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 5040 .type = AMD_IP_BLOCK_TYPE_PSP, 5041 .major = 13, 5042 .minor = 0, 5043 .rev = 4, 5044 .funcs = &psp_ip_funcs, 5045 }; 5046 5047 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 5048 .type = AMD_IP_BLOCK_TYPE_PSP, 5049 .major = 14, 5050 .minor = 0, 5051 .rev = 0, 5052 .funcs = &psp_ip_funcs, 5053 }; 5054 5055 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 5056 .type = AMD_IP_BLOCK_TYPE_PSP, 5057 .major = 15, 5058 .minor = 0, 5059 .rev = 0, 5060 .funcs = &psp_ip_funcs, 5061 }; 5062 5063 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 5064 .type = AMD_IP_BLOCK_TYPE_PSP, 5065 .major = 15, 5066 .minor = 0, 5067 .rev = 8, 5068 .funcs = &psp_ip_funcs, 5069 }; 5070