1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 #include "psp_v11_0.h" 35 #include "psp_v12_0.h" 36 37 static void psp_set_funcs(struct amdgpu_device *adev); 38 39 static int psp_early_init(void *handle) 40 { 41 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 42 struct psp_context *psp = &adev->psp; 43 44 psp_set_funcs(adev); 45 46 switch (adev->asic_type) { 47 case CHIP_VEGA10: 48 case CHIP_VEGA12: 49 psp_v3_1_set_psp_funcs(psp); 50 psp->autoload_supported = false; 51 break; 52 case CHIP_RAVEN: 53 psp_v10_0_set_psp_funcs(psp); 54 psp->autoload_supported = false; 55 break; 56 case CHIP_VEGA20: 57 case CHIP_ARCTURUS: 58 psp_v11_0_set_psp_funcs(psp); 59 psp->autoload_supported = false; 60 break; 61 case CHIP_NAVI10: 62 case CHIP_NAVI14: 63 case CHIP_NAVI12: 64 psp_v11_0_set_psp_funcs(psp); 65 psp->autoload_supported = true; 66 break; 67 case CHIP_RENOIR: 68 psp_v12_0_set_psp_funcs(psp); 69 break; 70 default: 71 return -EINVAL; 72 } 73 74 psp->adev = adev; 75 76 return 0; 77 } 78 79 static int psp_sw_init(void *handle) 80 { 81 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 82 struct psp_context *psp = &adev->psp; 83 int ret; 84 85 ret = psp_init_microcode(psp); 86 if (ret) { 87 DRM_ERROR("Failed to load psp firmware!\n"); 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int psp_sw_fini(void *handle) 95 { 96 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 97 98 release_firmware(adev->psp.sos_fw); 99 adev->psp.sos_fw = NULL; 100 release_firmware(adev->psp.asd_fw); 101 adev->psp.asd_fw = NULL; 102 if (adev->psp.ta_fw) { 103 release_firmware(adev->psp.ta_fw); 104 adev->psp.ta_fw = NULL; 105 } 106 return 0; 107 } 108 109 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 110 uint32_t reg_val, uint32_t mask, bool check_changed) 111 { 112 uint32_t val; 113 int i; 114 struct amdgpu_device *adev = psp->adev; 115 116 for (i = 0; i < adev->usec_timeout; i++) { 117 val = RREG32(reg_index); 118 if (check_changed) { 119 if (val != reg_val) 120 return 0; 121 } else { 122 if ((val & mask) == reg_val) 123 return 0; 124 } 125 udelay(1); 126 } 127 128 return -ETIME; 129 } 130 131 static int 132 psp_cmd_submit_buf(struct psp_context *psp, 133 struct amdgpu_firmware_info *ucode, 134 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 135 { 136 int ret; 137 int index; 138 int timeout = 2000; 139 140 mutex_lock(&psp->mutex); 141 142 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 143 144 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 145 146 index = atomic_inc_return(&psp->fence_value); 147 ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 148 if (ret) { 149 atomic_dec(&psp->fence_value); 150 mutex_unlock(&psp->mutex); 151 return ret; 152 } 153 154 while (*((unsigned int *)psp->fence_buf) != index) { 155 if (--timeout == 0) 156 break; 157 msleep(1); 158 } 159 160 /* In some cases, psp response status is not 0 even there is no 161 * problem while the command is submitted. Some version of PSP FW 162 * doesn't write 0 to that field. 163 * So here we would like to only print a warning instead of an error 164 * during psp initialization to avoid breaking hw_init and it doesn't 165 * return -EINVAL. 166 */ 167 if (psp->cmd_buf_mem->resp.status || !timeout) { 168 if (ucode) 169 DRM_WARN("failed to load ucode id (%d) ", 170 ucode->ucode_id); 171 DRM_WARN("psp command failed and response status is (0x%X)\n", 172 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK); 173 if (!timeout) { 174 mutex_unlock(&psp->mutex); 175 return -EINVAL; 176 } 177 } 178 179 /* get xGMI session id from response buffer */ 180 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id; 181 182 if (ucode) { 183 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 184 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 185 } 186 mutex_unlock(&psp->mutex); 187 188 return ret; 189 } 190 191 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 192 struct psp_gfx_cmd_resp *cmd, 193 uint64_t tmr_mc, uint32_t size) 194 { 195 if (psp_support_vmr_ring(psp)) 196 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 197 else 198 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 199 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 200 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 201 cmd->cmd.cmd_setup_tmr.buf_size = size; 202 } 203 204 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 205 uint64_t pri_buf_mc, uint32_t size) 206 { 207 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 208 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 209 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 210 cmd->cmd.cmd_load_toc.toc_size = size; 211 } 212 213 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 214 static int psp_load_toc(struct psp_context *psp, 215 uint32_t *tmr_size) 216 { 217 int ret; 218 struct psp_gfx_cmd_resp *cmd; 219 220 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 221 if (!cmd) 222 return -ENOMEM; 223 /* Copy toc to psp firmware private buffer */ 224 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 225 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size); 226 227 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size); 228 229 ret = psp_cmd_submit_buf(psp, NULL, cmd, 230 psp->fence_buf_mc_addr); 231 if (!ret) 232 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 233 kfree(cmd); 234 return ret; 235 } 236 237 /* Set up Trusted Memory Region */ 238 static int psp_tmr_init(struct psp_context *psp) 239 { 240 int ret; 241 int tmr_size; 242 void *tmr_buf; 243 void **pptr; 244 245 /* 246 * According to HW engineer, they prefer the TMR address be "naturally 247 * aligned" , e.g. the start address be an integer divide of TMR size. 248 * 249 * Note: this memory need be reserved till the driver 250 * uninitializes. 251 */ 252 tmr_size = PSP_TMR_SIZE; 253 254 /* For ASICs support RLC autoload, psp will parse the toc 255 * and calculate the total size of TMR needed */ 256 if (!amdgpu_sriov_vf(psp->adev) && 257 psp->toc_start_addr && 258 psp->toc_bin_size && 259 psp->fw_pri_buf) { 260 ret = psp_load_toc(psp, &tmr_size); 261 if (ret) { 262 DRM_ERROR("Failed to load toc\n"); 263 return ret; 264 } 265 } 266 267 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 268 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE, 269 AMDGPU_GEM_DOMAIN_VRAM, 270 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 271 272 return ret; 273 } 274 275 static int psp_tmr_load(struct psp_context *psp) 276 { 277 int ret; 278 struct psp_gfx_cmd_resp *cmd; 279 280 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 281 if (!cmd) 282 return -ENOMEM; 283 284 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, 285 amdgpu_bo_size(psp->tmr_bo)); 286 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 287 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 288 289 ret = psp_cmd_submit_buf(psp, NULL, cmd, 290 psp->fence_buf_mc_addr); 291 292 kfree(cmd); 293 294 return ret; 295 } 296 297 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 298 uint64_t asd_mc, uint64_t asd_mc_shared, 299 uint32_t size, uint32_t shared_size) 300 { 301 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 302 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 303 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 304 cmd->cmd.cmd_load_ta.app_len = size; 305 306 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 307 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 308 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 309 } 310 311 static int psp_asd_init(struct psp_context *psp) 312 { 313 int ret; 314 315 /* 316 * Allocate 16k memory aligned to 4k from Frame Buffer (local 317 * physical) for shared ASD <-> Driver 318 */ 319 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 320 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 321 &psp->asd_shared_bo, 322 &psp->asd_shared_mc_addr, 323 &psp->asd_shared_buf); 324 325 return ret; 326 } 327 328 static int psp_asd_load(struct psp_context *psp) 329 { 330 int ret; 331 struct psp_gfx_cmd_resp *cmd; 332 333 /* If PSP version doesn't match ASD version, asd loading will be failed. 334 * add workaround to bypass it for sriov now. 335 * TODO: add version check to make it common 336 */ 337 if (amdgpu_sriov_vf(psp->adev)) 338 return 0; 339 340 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 341 if (!cmd) 342 return -ENOMEM; 343 344 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 345 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 346 347 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 348 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 349 350 ret = psp_cmd_submit_buf(psp, NULL, cmd, 351 psp->fence_buf_mc_addr); 352 353 kfree(cmd); 354 355 return ret; 356 } 357 358 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 359 uint32_t id, uint32_t value) 360 { 361 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 362 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 363 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 364 } 365 366 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 367 uint32_t value) 368 { 369 struct psp_gfx_cmd_resp *cmd = NULL; 370 int ret = 0; 371 372 if (reg >= PSP_REG_LAST) 373 return -EINVAL; 374 375 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 376 if (!cmd) 377 return -ENOMEM; 378 379 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 380 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 381 382 kfree(cmd); 383 return ret; 384 } 385 386 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 387 uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared, 388 uint32_t xgmi_ta_size, uint32_t shared_size) 389 { 390 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 391 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc); 392 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc); 393 cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size; 394 395 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared); 396 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared); 397 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 398 } 399 400 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 401 { 402 int ret; 403 404 /* 405 * Allocate 16k memory aligned to 4k from Frame Buffer (local 406 * physical) for xgmi ta <-> Driver 407 */ 408 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 409 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 410 &psp->xgmi_context.xgmi_shared_bo, 411 &psp->xgmi_context.xgmi_shared_mc_addr, 412 &psp->xgmi_context.xgmi_shared_buf); 413 414 return ret; 415 } 416 417 static int psp_xgmi_load(struct psp_context *psp) 418 { 419 int ret; 420 struct psp_gfx_cmd_resp *cmd; 421 422 /* 423 * TODO: bypass the loading in sriov for now 424 */ 425 if (amdgpu_sriov_vf(psp->adev)) 426 return 0; 427 428 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 429 if (!cmd) 430 return -ENOMEM; 431 432 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 433 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 434 435 psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 436 psp->xgmi_context.xgmi_shared_mc_addr, 437 psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE); 438 439 ret = psp_cmd_submit_buf(psp, NULL, cmd, 440 psp->fence_buf_mc_addr); 441 442 if (!ret) { 443 psp->xgmi_context.initialized = 1; 444 psp->xgmi_context.session_id = cmd->resp.session_id; 445 } 446 447 kfree(cmd); 448 449 return ret; 450 } 451 452 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 453 uint32_t xgmi_session_id) 454 { 455 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 456 cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id; 457 } 458 459 static int psp_xgmi_unload(struct psp_context *psp) 460 { 461 int ret; 462 struct psp_gfx_cmd_resp *cmd; 463 464 /* 465 * TODO: bypass the unloading in sriov for now 466 */ 467 if (amdgpu_sriov_vf(psp->adev)) 468 return 0; 469 470 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 471 if (!cmd) 472 return -ENOMEM; 473 474 psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 475 476 ret = psp_cmd_submit_buf(psp, NULL, cmd, 477 psp->fence_buf_mc_addr); 478 479 kfree(cmd); 480 481 return ret; 482 } 483 484 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 485 uint32_t ta_cmd_id, 486 uint32_t xgmi_session_id) 487 { 488 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 489 cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id; 490 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 491 /* Note: cmd_invoke_cmd.buf is not used for now */ 492 } 493 494 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 495 { 496 int ret; 497 struct psp_gfx_cmd_resp *cmd; 498 499 /* 500 * TODO: bypass the loading in sriov for now 501 */ 502 if (amdgpu_sriov_vf(psp->adev)) 503 return 0; 504 505 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 506 if (!cmd) 507 return -ENOMEM; 508 509 psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id, 510 psp->xgmi_context.session_id); 511 512 ret = psp_cmd_submit_buf(psp, NULL, cmd, 513 psp->fence_buf_mc_addr); 514 515 kfree(cmd); 516 517 return ret; 518 } 519 520 static int psp_xgmi_terminate(struct psp_context *psp) 521 { 522 int ret; 523 524 if (!psp->xgmi_context.initialized) 525 return 0; 526 527 ret = psp_xgmi_unload(psp); 528 if (ret) 529 return ret; 530 531 psp->xgmi_context.initialized = 0; 532 533 /* free xgmi shared memory */ 534 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 535 &psp->xgmi_context.xgmi_shared_mc_addr, 536 &psp->xgmi_context.xgmi_shared_buf); 537 538 return 0; 539 } 540 541 static int psp_xgmi_initialize(struct psp_context *psp) 542 { 543 struct ta_xgmi_shared_memory *xgmi_cmd; 544 int ret; 545 546 if (!psp->adev->psp.ta_fw) 547 return -ENOENT; 548 549 if (!psp->xgmi_context.initialized) { 550 ret = psp_xgmi_init_shared_buf(psp); 551 if (ret) 552 return ret; 553 } 554 555 /* Load XGMI TA */ 556 ret = psp_xgmi_load(psp); 557 if (ret) 558 return ret; 559 560 /* Initialize XGMI session */ 561 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 562 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 563 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 564 565 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 566 567 return ret; 568 } 569 570 // ras begin 571 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 572 uint64_t ras_ta_mc, uint64_t ras_mc_shared, 573 uint32_t ras_ta_size, uint32_t shared_size) 574 { 575 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 576 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc); 577 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc); 578 cmd->cmd.cmd_load_ta.app_len = ras_ta_size; 579 580 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared); 581 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared); 582 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 583 } 584 585 static int psp_ras_init_shared_buf(struct psp_context *psp) 586 { 587 int ret; 588 589 /* 590 * Allocate 16k memory aligned to 4k from Frame Buffer (local 591 * physical) for ras ta <-> Driver 592 */ 593 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 594 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 595 &psp->ras.ras_shared_bo, 596 &psp->ras.ras_shared_mc_addr, 597 &psp->ras.ras_shared_buf); 598 599 return ret; 600 } 601 602 static int psp_ras_load(struct psp_context *psp) 603 { 604 int ret; 605 struct psp_gfx_cmd_resp *cmd; 606 607 /* 608 * TODO: bypass the loading in sriov for now 609 */ 610 if (amdgpu_sriov_vf(psp->adev)) 611 return 0; 612 613 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 614 if (!cmd) 615 return -ENOMEM; 616 617 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 618 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 619 620 psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 621 psp->ras.ras_shared_mc_addr, 622 psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE); 623 624 ret = psp_cmd_submit_buf(psp, NULL, cmd, 625 psp->fence_buf_mc_addr); 626 627 if (!ret) { 628 psp->ras.ras_initialized = 1; 629 psp->ras.session_id = cmd->resp.session_id; 630 } 631 632 kfree(cmd); 633 634 return ret; 635 } 636 637 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 638 uint32_t ras_session_id) 639 { 640 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 641 cmd->cmd.cmd_unload_ta.session_id = ras_session_id; 642 } 643 644 static int psp_ras_unload(struct psp_context *psp) 645 { 646 int ret; 647 struct psp_gfx_cmd_resp *cmd; 648 649 /* 650 * TODO: bypass the unloading in sriov for now 651 */ 652 if (amdgpu_sriov_vf(psp->adev)) 653 return 0; 654 655 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 656 if (!cmd) 657 return -ENOMEM; 658 659 psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id); 660 661 ret = psp_cmd_submit_buf(psp, NULL, cmd, 662 psp->fence_buf_mc_addr); 663 664 kfree(cmd); 665 666 return ret; 667 } 668 669 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 670 uint32_t ta_cmd_id, 671 uint32_t ras_session_id) 672 { 673 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 674 cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id; 675 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 676 /* Note: cmd_invoke_cmd.buf is not used for now */ 677 } 678 679 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 680 { 681 int ret; 682 struct psp_gfx_cmd_resp *cmd; 683 684 /* 685 * TODO: bypass the loading in sriov for now 686 */ 687 if (amdgpu_sriov_vf(psp->adev)) 688 return 0; 689 690 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 691 if (!cmd) 692 return -ENOMEM; 693 694 psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id, 695 psp->ras.session_id); 696 697 ret = psp_cmd_submit_buf(psp, NULL, cmd, 698 psp->fence_buf_mc_addr); 699 700 kfree(cmd); 701 702 return ret; 703 } 704 705 int psp_ras_enable_features(struct psp_context *psp, 706 union ta_ras_cmd_input *info, bool enable) 707 { 708 struct ta_ras_shared_memory *ras_cmd; 709 int ret; 710 711 if (!psp->ras.ras_initialized) 712 return -EINVAL; 713 714 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 715 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 716 717 if (enable) 718 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 719 else 720 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 721 722 ras_cmd->ras_in_message = *info; 723 724 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 725 if (ret) 726 return -EINVAL; 727 728 return ras_cmd->ras_status; 729 } 730 731 static int psp_ras_terminate(struct psp_context *psp) 732 { 733 int ret; 734 735 if (!psp->ras.ras_initialized) 736 return 0; 737 738 ret = psp_ras_unload(psp); 739 if (ret) 740 return ret; 741 742 psp->ras.ras_initialized = 0; 743 744 /* free ras shared memory */ 745 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 746 &psp->ras.ras_shared_mc_addr, 747 &psp->ras.ras_shared_buf); 748 749 return 0; 750 } 751 752 static int psp_ras_initialize(struct psp_context *psp) 753 { 754 int ret; 755 756 if (!psp->ras.ras_initialized) { 757 ret = psp_ras_init_shared_buf(psp); 758 if (ret) 759 return ret; 760 } 761 762 ret = psp_ras_load(psp); 763 if (ret) 764 return ret; 765 766 return 0; 767 } 768 // ras end 769 770 // HDCP start 771 static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 772 uint64_t hdcp_ta_mc, 773 uint64_t hdcp_mc_shared, 774 uint32_t hdcp_ta_size, 775 uint32_t shared_size) 776 { 777 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 778 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc); 779 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc); 780 cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size; 781 782 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 783 lower_32_bits(hdcp_mc_shared); 784 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 785 upper_32_bits(hdcp_mc_shared); 786 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 787 } 788 789 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 790 { 791 int ret; 792 793 /* 794 * Allocate 16k memory aligned to 4k from Frame Buffer (local 795 * physical) for hdcp ta <-> Driver 796 */ 797 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 798 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 799 &psp->hdcp_context.hdcp_shared_bo, 800 &psp->hdcp_context.hdcp_shared_mc_addr, 801 &psp->hdcp_context.hdcp_shared_buf); 802 803 return ret; 804 } 805 806 static int psp_hdcp_load(struct psp_context *psp) 807 { 808 int ret; 809 struct psp_gfx_cmd_resp *cmd; 810 811 /* 812 * TODO: bypass the loading in sriov for now 813 */ 814 if (amdgpu_sriov_vf(psp->adev)) 815 return 0; 816 817 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 818 if (!cmd) 819 return -ENOMEM; 820 821 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 822 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr, 823 psp->ta_hdcp_ucode_size); 824 825 psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 826 psp->hdcp_context.hdcp_shared_mc_addr, 827 psp->ta_hdcp_ucode_size, 828 PSP_HDCP_SHARED_MEM_SIZE); 829 830 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 831 832 if (!ret) { 833 psp->hdcp_context.hdcp_initialized = 1; 834 psp->hdcp_context.session_id = cmd->resp.session_id; 835 } 836 837 kfree(cmd); 838 839 return ret; 840 } 841 static int psp_hdcp_initialize(struct psp_context *psp) 842 { 843 int ret; 844 845 if (!psp->hdcp_context.hdcp_initialized) { 846 ret = psp_hdcp_init_shared_buf(psp); 847 if (ret) 848 return ret; 849 } 850 851 ret = psp_hdcp_load(psp); 852 if (ret) 853 return ret; 854 855 return 0; 856 } 857 static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 858 uint32_t hdcp_session_id) 859 { 860 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 861 cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id; 862 } 863 864 static int psp_hdcp_unload(struct psp_context *psp) 865 { 866 int ret; 867 struct psp_gfx_cmd_resp *cmd; 868 869 /* 870 * TODO: bypass the unloading in sriov for now 871 */ 872 if (amdgpu_sriov_vf(psp->adev)) 873 return 0; 874 875 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 876 if (!cmd) 877 return -ENOMEM; 878 879 psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 880 881 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 882 883 kfree(cmd); 884 885 return ret; 886 } 887 888 static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 889 uint32_t ta_cmd_id, 890 uint32_t hdcp_session_id) 891 { 892 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 893 cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id; 894 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 895 /* Note: cmd_invoke_cmd.buf is not used for now */ 896 } 897 898 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 899 { 900 int ret; 901 struct psp_gfx_cmd_resp *cmd; 902 903 /* 904 * TODO: bypass the loading in sriov for now 905 */ 906 if (amdgpu_sriov_vf(psp->adev)) 907 return 0; 908 909 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 910 if (!cmd) 911 return -ENOMEM; 912 913 psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id, 914 psp->hdcp_context.session_id); 915 916 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 917 918 kfree(cmd); 919 920 return ret; 921 } 922 923 static int psp_hdcp_terminate(struct psp_context *psp) 924 { 925 int ret; 926 927 if (!psp->hdcp_context.hdcp_initialized) 928 return 0; 929 930 ret = psp_hdcp_unload(psp); 931 if (ret) 932 return ret; 933 934 psp->hdcp_context.hdcp_initialized = 0; 935 936 /* free hdcp shared memory */ 937 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 938 &psp->hdcp_context.hdcp_shared_mc_addr, 939 &psp->hdcp_context.hdcp_shared_buf); 940 941 return 0; 942 } 943 // HDCP end 944 945 // DTM start 946 static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 947 uint64_t dtm_ta_mc, 948 uint64_t dtm_mc_shared, 949 uint32_t dtm_ta_size, 950 uint32_t shared_size) 951 { 952 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 953 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc); 954 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc); 955 cmd->cmd.cmd_load_ta.app_len = dtm_ta_size; 956 957 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared); 958 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared); 959 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 960 } 961 962 static int psp_dtm_init_shared_buf(struct psp_context *psp) 963 { 964 int ret; 965 966 /* 967 * Allocate 16k memory aligned to 4k from Frame Buffer (local 968 * physical) for dtm ta <-> Driver 969 */ 970 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 971 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 972 &psp->dtm_context.dtm_shared_bo, 973 &psp->dtm_context.dtm_shared_mc_addr, 974 &psp->dtm_context.dtm_shared_buf); 975 976 return ret; 977 } 978 979 static int psp_dtm_load(struct psp_context *psp) 980 { 981 int ret; 982 struct psp_gfx_cmd_resp *cmd; 983 984 /* 985 * TODO: bypass the loading in sriov for now 986 */ 987 if (amdgpu_sriov_vf(psp->adev)) 988 return 0; 989 990 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 991 if (!cmd) 992 return -ENOMEM; 993 994 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 995 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 996 997 psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 998 psp->dtm_context.dtm_shared_mc_addr, 999 psp->ta_dtm_ucode_size, 1000 PSP_DTM_SHARED_MEM_SIZE); 1001 1002 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1003 1004 if (!ret) { 1005 psp->dtm_context.dtm_initialized = 1; 1006 psp->dtm_context.session_id = cmd->resp.session_id; 1007 } 1008 1009 kfree(cmd); 1010 1011 return ret; 1012 } 1013 1014 static int psp_dtm_initialize(struct psp_context *psp) 1015 { 1016 int ret; 1017 1018 if (!psp->dtm_context.dtm_initialized) { 1019 ret = psp_dtm_init_shared_buf(psp); 1020 if (ret) 1021 return ret; 1022 } 1023 1024 ret = psp_dtm_load(psp); 1025 if (ret) 1026 return ret; 1027 1028 return 0; 1029 } 1030 1031 static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1032 uint32_t ta_cmd_id, 1033 uint32_t dtm_session_id) 1034 { 1035 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1036 cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id; 1037 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1038 /* Note: cmd_invoke_cmd.buf is not used for now */ 1039 } 1040 1041 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1042 { 1043 int ret; 1044 struct psp_gfx_cmd_resp *cmd; 1045 1046 /* 1047 * TODO: bypass the loading in sriov for now 1048 */ 1049 if (amdgpu_sriov_vf(psp->adev)) 1050 return 0; 1051 1052 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1053 if (!cmd) 1054 return -ENOMEM; 1055 1056 psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id, 1057 psp->dtm_context.session_id); 1058 1059 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1060 1061 kfree(cmd); 1062 1063 return ret; 1064 } 1065 1066 static int psp_dtm_terminate(struct psp_context *psp) 1067 { 1068 int ret; 1069 1070 if (!psp->dtm_context.dtm_initialized) 1071 return 0; 1072 1073 ret = psp_hdcp_unload(psp); 1074 if (ret) 1075 return ret; 1076 1077 psp->dtm_context.dtm_initialized = 0; 1078 1079 /* free hdcp shared memory */ 1080 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1081 &psp->dtm_context.dtm_shared_mc_addr, 1082 &psp->dtm_context.dtm_shared_buf); 1083 1084 return 0; 1085 } 1086 // DTM end 1087 1088 static int psp_hw_start(struct psp_context *psp) 1089 { 1090 struct amdgpu_device *adev = psp->adev; 1091 int ret; 1092 1093 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { 1094 if (psp->kdb_bin_size && 1095 (psp->funcs->bootloader_load_kdb != NULL)) { 1096 ret = psp_bootloader_load_kdb(psp); 1097 if (ret) { 1098 DRM_ERROR("PSP load kdb failed!\n"); 1099 return ret; 1100 } 1101 } 1102 1103 ret = psp_bootloader_load_sysdrv(psp); 1104 if (ret) { 1105 DRM_ERROR("PSP load sysdrv failed!\n"); 1106 return ret; 1107 } 1108 1109 ret = psp_bootloader_load_sos(psp); 1110 if (ret) { 1111 DRM_ERROR("PSP load sos failed!\n"); 1112 return ret; 1113 } 1114 } 1115 1116 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 1117 if (ret) { 1118 DRM_ERROR("PSP create ring failed!\n"); 1119 return ret; 1120 } 1121 1122 ret = psp_tmr_init(psp); 1123 if (ret) { 1124 DRM_ERROR("PSP tmr init failed!\n"); 1125 return ret; 1126 } 1127 1128 ret = psp_tmr_load(psp); 1129 if (ret) { 1130 DRM_ERROR("PSP load tmr failed!\n"); 1131 return ret; 1132 } 1133 1134 ret = psp_asd_init(psp); 1135 if (ret) { 1136 DRM_ERROR("PSP asd init failed!\n"); 1137 return ret; 1138 } 1139 1140 ret = psp_asd_load(psp); 1141 if (ret) { 1142 DRM_ERROR("PSP load asd failed!\n"); 1143 return ret; 1144 } 1145 1146 if (adev->gmc.xgmi.num_physical_nodes > 1) { 1147 ret = psp_xgmi_initialize(psp); 1148 /* Warning the XGMI seesion initialize failure 1149 * Instead of stop driver initialization 1150 */ 1151 if (ret) 1152 dev_err(psp->adev->dev, 1153 "XGMI: Failed to initialize XGMI session\n"); 1154 } 1155 1156 if (psp->adev->psp.ta_fw) { 1157 ret = psp_ras_initialize(psp); 1158 if (ret) 1159 dev_err(psp->adev->dev, 1160 "RAS: Failed to initialize RAS\n"); 1161 1162 ret = psp_hdcp_initialize(psp); 1163 if (ret) 1164 dev_err(psp->adev->dev, 1165 "HDCP: Failed to initialize HDCP\n"); 1166 1167 ret = psp_dtm_initialize(psp); 1168 if (ret) 1169 dev_err(psp->adev->dev, 1170 "DTM: Failed to initialize DTM\n"); 1171 } 1172 1173 return 0; 1174 } 1175 1176 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 1177 enum psp_gfx_fw_type *type) 1178 { 1179 switch (ucode->ucode_id) { 1180 case AMDGPU_UCODE_ID_SDMA0: 1181 *type = GFX_FW_TYPE_SDMA0; 1182 break; 1183 case AMDGPU_UCODE_ID_SDMA1: 1184 *type = GFX_FW_TYPE_SDMA1; 1185 break; 1186 case AMDGPU_UCODE_ID_SDMA2: 1187 *type = GFX_FW_TYPE_SDMA2; 1188 break; 1189 case AMDGPU_UCODE_ID_SDMA3: 1190 *type = GFX_FW_TYPE_SDMA3; 1191 break; 1192 case AMDGPU_UCODE_ID_SDMA4: 1193 *type = GFX_FW_TYPE_SDMA4; 1194 break; 1195 case AMDGPU_UCODE_ID_SDMA5: 1196 *type = GFX_FW_TYPE_SDMA5; 1197 break; 1198 case AMDGPU_UCODE_ID_SDMA6: 1199 *type = GFX_FW_TYPE_SDMA6; 1200 break; 1201 case AMDGPU_UCODE_ID_SDMA7: 1202 *type = GFX_FW_TYPE_SDMA7; 1203 break; 1204 case AMDGPU_UCODE_ID_CP_CE: 1205 *type = GFX_FW_TYPE_CP_CE; 1206 break; 1207 case AMDGPU_UCODE_ID_CP_PFP: 1208 *type = GFX_FW_TYPE_CP_PFP; 1209 break; 1210 case AMDGPU_UCODE_ID_CP_ME: 1211 *type = GFX_FW_TYPE_CP_ME; 1212 break; 1213 case AMDGPU_UCODE_ID_CP_MEC1: 1214 *type = GFX_FW_TYPE_CP_MEC; 1215 break; 1216 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1217 *type = GFX_FW_TYPE_CP_MEC_ME1; 1218 break; 1219 case AMDGPU_UCODE_ID_CP_MEC2: 1220 *type = GFX_FW_TYPE_CP_MEC; 1221 break; 1222 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1223 *type = GFX_FW_TYPE_CP_MEC_ME2; 1224 break; 1225 case AMDGPU_UCODE_ID_RLC_G: 1226 *type = GFX_FW_TYPE_RLC_G; 1227 break; 1228 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 1229 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 1230 break; 1231 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 1232 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 1233 break; 1234 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 1235 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 1236 break; 1237 case AMDGPU_UCODE_ID_SMC: 1238 *type = GFX_FW_TYPE_SMU; 1239 break; 1240 case AMDGPU_UCODE_ID_UVD: 1241 *type = GFX_FW_TYPE_UVD; 1242 break; 1243 case AMDGPU_UCODE_ID_UVD1: 1244 *type = GFX_FW_TYPE_UVD1; 1245 break; 1246 case AMDGPU_UCODE_ID_VCE: 1247 *type = GFX_FW_TYPE_VCE; 1248 break; 1249 case AMDGPU_UCODE_ID_VCN: 1250 *type = GFX_FW_TYPE_VCN; 1251 break; 1252 case AMDGPU_UCODE_ID_DMCU_ERAM: 1253 *type = GFX_FW_TYPE_DMCU_ERAM; 1254 break; 1255 case AMDGPU_UCODE_ID_DMCU_INTV: 1256 *type = GFX_FW_TYPE_DMCU_ISR; 1257 break; 1258 case AMDGPU_UCODE_ID_VCN0_RAM: 1259 *type = GFX_FW_TYPE_VCN0_RAM; 1260 break; 1261 case AMDGPU_UCODE_ID_VCN1_RAM: 1262 *type = GFX_FW_TYPE_VCN1_RAM; 1263 break; 1264 case AMDGPU_UCODE_ID_MAXIMUM: 1265 default: 1266 return -EINVAL; 1267 } 1268 1269 return 0; 1270 } 1271 1272 static void psp_print_fw_hdr(struct psp_context *psp, 1273 struct amdgpu_firmware_info *ucode) 1274 { 1275 struct amdgpu_device *adev = psp->adev; 1276 struct common_firmware_header *hdr; 1277 1278 switch (ucode->ucode_id) { 1279 case AMDGPU_UCODE_ID_SDMA0: 1280 case AMDGPU_UCODE_ID_SDMA1: 1281 case AMDGPU_UCODE_ID_SDMA2: 1282 case AMDGPU_UCODE_ID_SDMA3: 1283 case AMDGPU_UCODE_ID_SDMA4: 1284 case AMDGPU_UCODE_ID_SDMA5: 1285 case AMDGPU_UCODE_ID_SDMA6: 1286 case AMDGPU_UCODE_ID_SDMA7: 1287 hdr = (struct common_firmware_header *) 1288 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 1289 amdgpu_ucode_print_sdma_hdr(hdr); 1290 break; 1291 case AMDGPU_UCODE_ID_CP_CE: 1292 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 1293 amdgpu_ucode_print_gfx_hdr(hdr); 1294 break; 1295 case AMDGPU_UCODE_ID_CP_PFP: 1296 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 1297 amdgpu_ucode_print_gfx_hdr(hdr); 1298 break; 1299 case AMDGPU_UCODE_ID_CP_ME: 1300 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 1301 amdgpu_ucode_print_gfx_hdr(hdr); 1302 break; 1303 case AMDGPU_UCODE_ID_CP_MEC1: 1304 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 1305 amdgpu_ucode_print_gfx_hdr(hdr); 1306 break; 1307 case AMDGPU_UCODE_ID_RLC_G: 1308 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 1309 amdgpu_ucode_print_rlc_hdr(hdr); 1310 break; 1311 case AMDGPU_UCODE_ID_SMC: 1312 hdr = (struct common_firmware_header *)adev->pm.fw->data; 1313 amdgpu_ucode_print_smc_hdr(hdr); 1314 break; 1315 default: 1316 break; 1317 } 1318 } 1319 1320 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 1321 struct psp_gfx_cmd_resp *cmd) 1322 { 1323 int ret; 1324 uint64_t fw_mem_mc_addr = ucode->mc_addr; 1325 1326 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 1327 1328 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1329 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 1330 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 1331 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 1332 1333 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 1334 if (ret) 1335 DRM_ERROR("Unknown firmware type\n"); 1336 1337 return ret; 1338 } 1339 1340 static int psp_execute_np_fw_load(struct psp_context *psp, 1341 struct amdgpu_firmware_info *ucode) 1342 { 1343 int ret = 0; 1344 1345 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 1346 if (ret) 1347 return ret; 1348 1349 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 1350 psp->fence_buf_mc_addr); 1351 1352 return ret; 1353 } 1354 1355 static int psp_np_fw_load(struct psp_context *psp) 1356 { 1357 int i, ret; 1358 struct amdgpu_firmware_info *ucode; 1359 struct amdgpu_device* adev = psp->adev; 1360 1361 if (psp->autoload_supported) { 1362 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 1363 if (!ucode->fw) 1364 goto out; 1365 1366 ret = psp_execute_np_fw_load(psp, ucode); 1367 if (ret) 1368 return ret; 1369 } 1370 1371 out: 1372 for (i = 0; i < adev->firmware.max_ucodes; i++) { 1373 ucode = &adev->firmware.ucode[i]; 1374 if (!ucode->fw) 1375 continue; 1376 1377 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 1378 (psp_smu_reload_quirk(psp) || psp->autoload_supported)) 1379 continue; 1380 1381 if (amdgpu_sriov_vf(adev) && 1382 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 1383 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 1384 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 1385 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 1386 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 1387 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 1388 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 1389 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 1390 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 1391 /*skip ucode loading in SRIOV VF */ 1392 continue; 1393 1394 if (psp->autoload_supported && 1395 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 1396 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 1397 /* skip mec JT when autoload is enabled */ 1398 continue; 1399 /* Renoir only needs to load mec jump table one time */ 1400 if (adev->asic_type == CHIP_RENOIR && 1401 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) 1402 continue; 1403 1404 psp_print_fw_hdr(psp, ucode); 1405 1406 ret = psp_execute_np_fw_load(psp, ucode); 1407 if (ret) 1408 return ret; 1409 1410 /* Start rlc autoload after psp recieved all the gfx firmware */ 1411 if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 1412 ret = psp_rlc_autoload(psp); 1413 if (ret) { 1414 DRM_ERROR("Failed to start rlc autoload\n"); 1415 return ret; 1416 } 1417 } 1418 #if 0 1419 /* check if firmware loaded sucessfully */ 1420 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 1421 return -EINVAL; 1422 #endif 1423 } 1424 1425 return 0; 1426 } 1427 1428 static int psp_load_fw(struct amdgpu_device *adev) 1429 { 1430 int ret; 1431 struct psp_context *psp = &adev->psp; 1432 1433 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) { 1434 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 1435 goto skip_memalloc; 1436 } 1437 1438 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1439 if (!psp->cmd) 1440 return -ENOMEM; 1441 1442 /* this fw pri bo is not used under SRIOV */ 1443 if (!amdgpu_sriov_vf(psp->adev)) { 1444 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 1445 AMDGPU_GEM_DOMAIN_GTT, 1446 &psp->fw_pri_bo, 1447 &psp->fw_pri_mc_addr, 1448 &psp->fw_pri_buf); 1449 if (ret) 1450 goto failed; 1451 } 1452 1453 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 1454 AMDGPU_GEM_DOMAIN_VRAM, 1455 &psp->fence_buf_bo, 1456 &psp->fence_buf_mc_addr, 1457 &psp->fence_buf); 1458 if (ret) 1459 goto failed; 1460 1461 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 1462 AMDGPU_GEM_DOMAIN_VRAM, 1463 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1464 (void **)&psp->cmd_buf_mem); 1465 if (ret) 1466 goto failed; 1467 1468 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 1469 1470 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 1471 if (ret) { 1472 DRM_ERROR("PSP ring init failed!\n"); 1473 goto failed; 1474 } 1475 1476 skip_memalloc: 1477 ret = psp_hw_start(psp); 1478 if (ret) 1479 goto failed; 1480 1481 ret = psp_np_fw_load(psp); 1482 if (ret) 1483 goto failed; 1484 1485 return 0; 1486 1487 failed: 1488 /* 1489 * all cleanup jobs (xgmi terminate, ras terminate, 1490 * ring destroy, cmd/fence/fw buffers destory, 1491 * psp->cmd destory) are delayed to psp_hw_fini 1492 */ 1493 return ret; 1494 } 1495 1496 static int psp_hw_init(void *handle) 1497 { 1498 int ret; 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 1501 mutex_lock(&adev->firmware.mutex); 1502 /* 1503 * This sequence is just used on hw_init only once, no need on 1504 * resume. 1505 */ 1506 ret = amdgpu_ucode_init_bo(adev); 1507 if (ret) 1508 goto failed; 1509 1510 ret = psp_load_fw(adev); 1511 if (ret) { 1512 DRM_ERROR("PSP firmware loading failed\n"); 1513 goto failed; 1514 } 1515 1516 mutex_unlock(&adev->firmware.mutex); 1517 return 0; 1518 1519 failed: 1520 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 1521 mutex_unlock(&adev->firmware.mutex); 1522 return -EINVAL; 1523 } 1524 1525 static int psp_hw_fini(void *handle) 1526 { 1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1528 struct psp_context *psp = &adev->psp; 1529 void *tmr_buf; 1530 void **pptr; 1531 1532 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1533 psp->xgmi_context.initialized == 1) 1534 psp_xgmi_terminate(psp); 1535 1536 if (psp->adev->psp.ta_fw) { 1537 psp_ras_terminate(psp); 1538 psp_dtm_terminate(psp); 1539 psp_hdcp_terminate(psp); 1540 } 1541 1542 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 1543 1544 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1545 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 1546 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 1547 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 1548 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 1549 &psp->fence_buf_mc_addr, &psp->fence_buf); 1550 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 1551 &psp->asd_shared_buf); 1552 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 1553 (void **)&psp->cmd_buf_mem); 1554 1555 kfree(psp->cmd); 1556 psp->cmd = NULL; 1557 1558 return 0; 1559 } 1560 1561 static int psp_suspend(void *handle) 1562 { 1563 int ret; 1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1565 struct psp_context *psp = &adev->psp; 1566 1567 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1568 psp->xgmi_context.initialized == 1) { 1569 ret = psp_xgmi_terminate(psp); 1570 if (ret) { 1571 DRM_ERROR("Failed to terminate xgmi ta\n"); 1572 return ret; 1573 } 1574 } 1575 1576 if (psp->adev->psp.ta_fw) { 1577 ret = psp_ras_terminate(psp); 1578 if (ret) { 1579 DRM_ERROR("Failed to terminate ras ta\n"); 1580 return ret; 1581 } 1582 ret = psp_hdcp_terminate(psp); 1583 if (ret) { 1584 DRM_ERROR("Failed to terminate hdcp ta\n"); 1585 return ret; 1586 } 1587 ret = psp_dtm_terminate(psp); 1588 if (ret) { 1589 DRM_ERROR("Failed to terminate dtm ta\n"); 1590 return ret; 1591 } 1592 } 1593 1594 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 1595 if (ret) { 1596 DRM_ERROR("PSP ring stop failed\n"); 1597 return ret; 1598 } 1599 1600 return 0; 1601 } 1602 1603 static int psp_resume(void *handle) 1604 { 1605 int ret; 1606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1607 struct psp_context *psp = &adev->psp; 1608 1609 DRM_INFO("PSP is resuming...\n"); 1610 1611 mutex_lock(&adev->firmware.mutex); 1612 1613 ret = psp_hw_start(psp); 1614 if (ret) 1615 goto failed; 1616 1617 ret = psp_np_fw_load(psp); 1618 if (ret) 1619 goto failed; 1620 1621 mutex_unlock(&adev->firmware.mutex); 1622 1623 return 0; 1624 1625 failed: 1626 DRM_ERROR("PSP resume failed\n"); 1627 mutex_unlock(&adev->firmware.mutex); 1628 return ret; 1629 } 1630 1631 int psp_gpu_reset(struct amdgpu_device *adev) 1632 { 1633 int ret; 1634 1635 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1636 return 0; 1637 1638 mutex_lock(&adev->psp.mutex); 1639 ret = psp_mode1_reset(&adev->psp); 1640 mutex_unlock(&adev->psp.mutex); 1641 1642 return ret; 1643 } 1644 1645 int psp_rlc_autoload_start(struct psp_context *psp) 1646 { 1647 int ret; 1648 struct psp_gfx_cmd_resp *cmd; 1649 1650 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1651 if (!cmd) 1652 return -ENOMEM; 1653 1654 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 1655 1656 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1657 psp->fence_buf_mc_addr); 1658 kfree(cmd); 1659 return ret; 1660 } 1661 1662 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 1663 uint64_t cmd_gpu_addr, int cmd_size) 1664 { 1665 struct amdgpu_firmware_info ucode = {0}; 1666 1667 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 1668 AMDGPU_UCODE_ID_VCN0_RAM; 1669 ucode.mc_addr = cmd_gpu_addr; 1670 ucode.ucode_size = cmd_size; 1671 1672 return psp_execute_np_fw_load(&adev->psp, &ucode); 1673 } 1674 1675 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 1676 enum AMDGPU_UCODE_ID ucode_type) 1677 { 1678 struct amdgpu_firmware_info *ucode = NULL; 1679 1680 if (!adev->firmware.fw_size) 1681 return false; 1682 1683 ucode = &adev->firmware.ucode[ucode_type]; 1684 if (!ucode->fw || !ucode->ucode_size) 1685 return false; 1686 1687 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 1688 } 1689 1690 static int psp_set_clockgating_state(void *handle, 1691 enum amd_clockgating_state state) 1692 { 1693 return 0; 1694 } 1695 1696 static int psp_set_powergating_state(void *handle, 1697 enum amd_powergating_state state) 1698 { 1699 return 0; 1700 } 1701 1702 const struct amd_ip_funcs psp_ip_funcs = { 1703 .name = "psp", 1704 .early_init = psp_early_init, 1705 .late_init = NULL, 1706 .sw_init = psp_sw_init, 1707 .sw_fini = psp_sw_fini, 1708 .hw_init = psp_hw_init, 1709 .hw_fini = psp_hw_fini, 1710 .suspend = psp_suspend, 1711 .resume = psp_resume, 1712 .is_idle = NULL, 1713 .check_soft_reset = NULL, 1714 .wait_for_idle = NULL, 1715 .soft_reset = NULL, 1716 .set_clockgating_state = psp_set_clockgating_state, 1717 .set_powergating_state = psp_set_powergating_state, 1718 }; 1719 1720 static const struct amdgpu_psp_funcs psp_funcs = { 1721 .check_fw_loading_status = psp_check_fw_loading_status, 1722 }; 1723 1724 static void psp_set_funcs(struct amdgpu_device *adev) 1725 { 1726 if (NULL == adev->firmware.funcs) 1727 adev->firmware.funcs = &psp_funcs; 1728 } 1729 1730 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 1731 { 1732 .type = AMD_IP_BLOCK_TYPE_PSP, 1733 .major = 3, 1734 .minor = 1, 1735 .rev = 0, 1736 .funcs = &psp_ip_funcs, 1737 }; 1738 1739 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 1740 { 1741 .type = AMD_IP_BLOCK_TYPE_PSP, 1742 .major = 10, 1743 .minor = 0, 1744 .rev = 0, 1745 .funcs = &psp_ip_funcs, 1746 }; 1747 1748 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 1749 { 1750 .type = AMD_IP_BLOCK_TYPE_PSP, 1751 .major = 11, 1752 .minor = 0, 1753 .rev = 0, 1754 .funcs = &psp_ip_funcs, 1755 }; 1756 1757 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 1758 { 1759 .type = AMD_IP_BLOCK_TYPE_PSP, 1760 .major = 12, 1761 .minor = 0, 1762 .rev = 0, 1763 .funcs = &psp_ip_funcs, 1764 }; 1765