1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 46 47 static int psp_sysfs_init(struct amdgpu_device *adev); 48 static void psp_sysfs_fini(struct amdgpu_device *adev); 49 50 static int psp_load_smu_fw(struct psp_context *psp); 51 static int psp_rap_terminate(struct psp_context *psp); 52 static int psp_securedisplay_terminate(struct psp_context *psp); 53 54 /* 55 * Due to DF Cstate management centralized to PMFW, the firmware 56 * loading sequence will be updated as below: 57 * - Load KDB 58 * - Load SYS_DRV 59 * - Load tOS 60 * - Load PMFW 61 * - Setup TMR 62 * - Load other non-psp fw 63 * - Load ASD 64 * - Load XGMI/RAS/HDCP/DTM TA if any 65 * 66 * This new sequence is required for 67 * - Arcturus and onwards 68 */ 69 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 if (amdgpu_sriov_vf(adev)) { 74 psp->pmfw_centralized_cstate_management = false; 75 return; 76 } 77 78 switch (adev->ip_versions[MP0_HWIP][0]) { 79 case IP_VERSION(11, 0, 0): 80 case IP_VERSION(11, 0, 4): 81 case IP_VERSION(11, 0, 5): 82 case IP_VERSION(11, 0, 7): 83 case IP_VERSION(11, 0, 9): 84 case IP_VERSION(11, 0, 11): 85 case IP_VERSION(11, 0, 12): 86 case IP_VERSION(11, 0, 13): 87 case IP_VERSION(13, 0, 0): 88 case IP_VERSION(13, 0, 2): 89 case IP_VERSION(13, 0, 7): 90 psp->pmfw_centralized_cstate_management = true; 91 break; 92 default: 93 psp->pmfw_centralized_cstate_management = false; 94 break; 95 } 96 } 97 98 static int psp_early_init(void *handle) 99 { 100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 101 struct psp_context *psp = &adev->psp; 102 103 switch (adev->ip_versions[MP0_HWIP][0]) { 104 case IP_VERSION(9, 0, 0): 105 psp_v3_1_set_psp_funcs(psp); 106 psp->autoload_supported = false; 107 break; 108 case IP_VERSION(10, 0, 0): 109 case IP_VERSION(10, 0, 1): 110 psp_v10_0_set_psp_funcs(psp); 111 psp->autoload_supported = false; 112 break; 113 case IP_VERSION(11, 0, 2): 114 case IP_VERSION(11, 0, 4): 115 psp_v11_0_set_psp_funcs(psp); 116 psp->autoload_supported = false; 117 break; 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 5): 120 case IP_VERSION(11, 0, 9): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 11): 123 case IP_VERSION(11, 5, 0): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 psp_v11_0_set_psp_funcs(psp); 127 psp->autoload_supported = true; 128 break; 129 case IP_VERSION(11, 0, 3): 130 case IP_VERSION(12, 0, 1): 131 psp_v12_0_set_psp_funcs(psp); 132 break; 133 case IP_VERSION(13, 0, 2): 134 psp_v13_0_set_psp_funcs(psp); 135 break; 136 case IP_VERSION(13, 0, 1): 137 case IP_VERSION(13, 0, 3): 138 case IP_VERSION(13, 0, 5): 139 case IP_VERSION(13, 0, 8): 140 psp_v13_0_set_psp_funcs(psp); 141 psp->autoload_supported = true; 142 break; 143 case IP_VERSION(11, 0, 8): 144 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 145 psp_v11_0_8_set_psp_funcs(psp); 146 psp->autoload_supported = false; 147 } 148 break; 149 case IP_VERSION(13, 0, 0): 150 case IP_VERSION(13, 0, 7): 151 psp_v13_0_set_psp_funcs(psp); 152 psp->autoload_supported = true; 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 psp->adev = adev; 159 160 psp_check_pmfw_centralized_cstate_management(psp); 161 162 return 0; 163 } 164 165 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 166 { 167 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 168 &mem_ctx->shared_buf); 169 } 170 171 static void psp_free_shared_bufs(struct psp_context *psp) 172 { 173 void *tmr_buf; 174 void **pptr; 175 176 /* free TMR memory buffer */ 177 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 178 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 179 180 /* free xgmi shared memory */ 181 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 182 183 /* free ras shared memory */ 184 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 185 186 /* free hdcp shared memory */ 187 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 188 189 /* free dtm shared memory */ 190 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 191 192 /* free rap shared memory */ 193 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 194 195 /* free securedisplay shared memory */ 196 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 197 198 199 } 200 201 static void psp_memory_training_fini(struct psp_context *psp) 202 { 203 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 204 205 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 206 kfree(ctx->sys_cache); 207 ctx->sys_cache = NULL; 208 } 209 210 static int psp_memory_training_init(struct psp_context *psp) 211 { 212 int ret; 213 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 214 215 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 216 DRM_DEBUG("memory training is not supported!\n"); 217 return 0; 218 } 219 220 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 221 if (ctx->sys_cache == NULL) { 222 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 223 ret = -ENOMEM; 224 goto Err_out; 225 } 226 227 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 228 ctx->train_data_size, 229 ctx->p2c_train_data_offset, 230 ctx->c2p_train_data_offset); 231 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 232 return 0; 233 234 Err_out: 235 psp_memory_training_fini(psp); 236 return ret; 237 } 238 239 /* 240 * Helper funciton to query psp runtime database entry 241 * 242 * @adev: amdgpu_device pointer 243 * @entry_type: the type of psp runtime database entry 244 * @db_entry: runtime database entry pointer 245 * 246 * Return false if runtime database doesn't exit or entry is invalid 247 * or true if the specific database entry is found, and copy to @db_entry 248 */ 249 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 250 enum psp_runtime_entry_type entry_type, 251 void *db_entry) 252 { 253 uint64_t db_header_pos, db_dir_pos; 254 struct psp_runtime_data_header db_header = {0}; 255 struct psp_runtime_data_directory db_dir = {0}; 256 bool ret = false; 257 int i; 258 259 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 260 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 261 262 /* read runtime db header from vram */ 263 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 264 sizeof(struct psp_runtime_data_header), false); 265 266 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 267 /* runtime db doesn't exist, exit */ 268 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 269 return false; 270 } 271 272 /* read runtime database entry from vram */ 273 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 274 sizeof(struct psp_runtime_data_directory), false); 275 276 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 277 /* invalid db entry count, exit */ 278 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 279 return false; 280 } 281 282 /* look up for requested entry type */ 283 for (i = 0; i < db_dir.entry_count && !ret; i++) { 284 if (db_dir.entry_list[i].entry_type == entry_type) { 285 switch (entry_type) { 286 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 287 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 288 /* invalid db entry size */ 289 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 290 return false; 291 } 292 /* read runtime database entry */ 293 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 294 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 295 ret = true; 296 break; 297 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 298 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 299 /* invalid db entry size */ 300 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 301 return false; 302 } 303 /* read runtime database entry */ 304 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 305 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 306 ret = true; 307 break; 308 default: 309 ret = false; 310 break; 311 } 312 } 313 } 314 315 return ret; 316 } 317 318 static int psp_init_sriov_microcode(struct psp_context *psp) 319 { 320 struct amdgpu_device *adev = psp->adev; 321 int ret = 0; 322 323 switch (adev->ip_versions[MP0_HWIP][0]) { 324 case IP_VERSION(9, 0, 0): 325 ret = psp_init_cap_microcode(psp, "vega10"); 326 break; 327 case IP_VERSION(11, 0, 9): 328 ret = psp_init_cap_microcode(psp, "navi12"); 329 break; 330 case IP_VERSION(11, 0, 7): 331 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 332 break; 333 case IP_VERSION(13, 0, 2): 334 ret = psp_init_cap_microcode(psp, "aldebaran"); 335 ret &= psp_init_ta_microcode(psp, "aldebaran"); 336 break; 337 default: 338 BUG(); 339 break; 340 } 341 342 return ret; 343 } 344 345 static int psp_sw_init(void *handle) 346 { 347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 348 struct psp_context *psp = &adev->psp; 349 int ret; 350 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 351 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 352 struct psp_runtime_scpm_entry scpm_entry; 353 354 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 355 if (!psp->cmd) { 356 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 357 ret = -ENOMEM; 358 } 359 360 if (amdgpu_sriov_vf(adev)) 361 ret = psp_init_sriov_microcode(psp); 362 else 363 ret = psp_init_microcode(psp); 364 if (ret) { 365 DRM_ERROR("Failed to load psp firmware!\n"); 366 return ret; 367 } 368 369 adev->psp.xgmi_context.supports_extended_data = 370 !adev->gmc.xgmi.connected_to_cpu && 371 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 372 373 memset(&scpm_entry, 0, sizeof(scpm_entry)); 374 if ((psp_get_runtime_db_entry(adev, 375 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 376 &scpm_entry)) && 377 (SCPM_DISABLE != scpm_entry.scpm_status)) { 378 adev->scpm_enabled = true; 379 adev->scpm_status = scpm_entry.scpm_status; 380 } else { 381 adev->scpm_enabled = false; 382 adev->scpm_status = SCPM_DISABLE; 383 } 384 385 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 386 387 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 388 if (psp_get_runtime_db_entry(adev, 389 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 390 &boot_cfg_entry)) { 391 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 392 if ((psp->boot_cfg_bitmask) & 393 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 394 /* If psp runtime database exists, then 395 * only enable two stage memory training 396 * when TWO_STAGE_DRAM_TRAINING bit is set 397 * in runtime database */ 398 mem_training_ctx->enable_mem_training = true; 399 } 400 401 } else { 402 /* If psp runtime database doesn't exist or 403 * is invalid, force enable two stage memory 404 * training */ 405 mem_training_ctx->enable_mem_training = true; 406 } 407 408 if (mem_training_ctx->enable_mem_training) { 409 ret = psp_memory_training_init(psp); 410 if (ret) { 411 DRM_ERROR("Failed to initialize memory training!\n"); 412 return ret; 413 } 414 415 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 416 if (ret) { 417 DRM_ERROR("Failed to process memory training!\n"); 418 return ret; 419 } 420 } 421 422 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 423 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 424 ret= psp_sysfs_init(adev); 425 if (ret) { 426 return ret; 427 } 428 } 429 430 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 431 amdgpu_sriov_vf(adev) ? 432 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 433 &psp->fw_pri_bo, 434 &psp->fw_pri_mc_addr, 435 &psp->fw_pri_buf); 436 if (ret) 437 return ret; 438 439 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 440 AMDGPU_GEM_DOMAIN_VRAM, 441 &psp->fence_buf_bo, 442 &psp->fence_buf_mc_addr, 443 &psp->fence_buf); 444 if (ret) 445 goto failed1; 446 447 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 448 AMDGPU_GEM_DOMAIN_VRAM, 449 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 450 (void **)&psp->cmd_buf_mem); 451 if (ret) 452 goto failed2; 453 454 return 0; 455 456 failed2: 457 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 458 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 459 failed1: 460 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 461 &psp->fence_buf_mc_addr, &psp->fence_buf); 462 return ret; 463 } 464 465 static int psp_sw_fini(void *handle) 466 { 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 struct psp_context *psp = &adev->psp; 469 struct psp_gfx_cmd_resp *cmd = psp->cmd; 470 471 psp_memory_training_fini(psp); 472 if (psp->sos_fw) { 473 release_firmware(psp->sos_fw); 474 psp->sos_fw = NULL; 475 } 476 if (psp->asd_fw) { 477 release_firmware(psp->asd_fw); 478 psp->asd_fw = NULL; 479 } 480 if (psp->ta_fw) { 481 release_firmware(psp->ta_fw); 482 psp->ta_fw = NULL; 483 } 484 if (adev->psp.cap_fw) { 485 release_firmware(psp->cap_fw); 486 psp->cap_fw = NULL; 487 } 488 489 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 490 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 491 psp_sysfs_fini(adev); 492 493 kfree(cmd); 494 cmd = NULL; 495 496 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 497 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 498 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 499 &psp->fence_buf_mc_addr, &psp->fence_buf); 500 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 501 (void **)&psp->cmd_buf_mem); 502 503 return 0; 504 } 505 506 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 507 uint32_t reg_val, uint32_t mask, bool check_changed) 508 { 509 uint32_t val; 510 int i; 511 struct amdgpu_device *adev = psp->adev; 512 513 if (psp->adev->no_hw_access) 514 return 0; 515 516 for (i = 0; i < adev->usec_timeout; i++) { 517 val = RREG32(reg_index); 518 if (check_changed) { 519 if (val != reg_val) 520 return 0; 521 } else { 522 if ((val & mask) == reg_val) 523 return 0; 524 } 525 udelay(1); 526 } 527 528 return -ETIME; 529 } 530 531 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 532 { 533 switch (cmd_id) { 534 case GFX_CMD_ID_LOAD_TA: 535 return "LOAD_TA"; 536 case GFX_CMD_ID_UNLOAD_TA: 537 return "UNLOAD_TA"; 538 case GFX_CMD_ID_INVOKE_CMD: 539 return "INVOKE_CMD"; 540 case GFX_CMD_ID_LOAD_ASD: 541 return "LOAD_ASD"; 542 case GFX_CMD_ID_SETUP_TMR: 543 return "SETUP_TMR"; 544 case GFX_CMD_ID_LOAD_IP_FW: 545 return "LOAD_IP_FW"; 546 case GFX_CMD_ID_DESTROY_TMR: 547 return "DESTROY_TMR"; 548 case GFX_CMD_ID_SAVE_RESTORE: 549 return "SAVE_RESTORE_IP_FW"; 550 case GFX_CMD_ID_SETUP_VMR: 551 return "SETUP_VMR"; 552 case GFX_CMD_ID_DESTROY_VMR: 553 return "DESTROY_VMR"; 554 case GFX_CMD_ID_PROG_REG: 555 return "PROG_REG"; 556 case GFX_CMD_ID_GET_FW_ATTESTATION: 557 return "GET_FW_ATTESTATION"; 558 case GFX_CMD_ID_LOAD_TOC: 559 return "ID_LOAD_TOC"; 560 case GFX_CMD_ID_AUTOLOAD_RLC: 561 return "AUTOLOAD_RLC"; 562 case GFX_CMD_ID_BOOT_CFG: 563 return "BOOT_CFG"; 564 default: 565 return "UNKNOWN CMD"; 566 } 567 } 568 569 static int 570 psp_cmd_submit_buf(struct psp_context *psp, 571 struct amdgpu_firmware_info *ucode, 572 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 573 { 574 int ret; 575 int index, idx; 576 int timeout = 20000; 577 bool ras_intr = false; 578 bool skip_unsupport = false; 579 580 if (psp->adev->no_hw_access) 581 return 0; 582 583 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 584 return 0; 585 586 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 587 588 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 589 590 index = atomic_inc_return(&psp->fence_value); 591 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 592 if (ret) { 593 atomic_dec(&psp->fence_value); 594 goto exit; 595 } 596 597 amdgpu_device_invalidate_hdp(psp->adev, NULL); 598 while (*((unsigned int *)psp->fence_buf) != index) { 599 if (--timeout == 0) 600 break; 601 /* 602 * Shouldn't wait for timeout when err_event_athub occurs, 603 * because gpu reset thread triggered and lock resource should 604 * be released for psp resume sequence. 605 */ 606 ras_intr = amdgpu_ras_intr_triggered(); 607 if (ras_intr) 608 break; 609 usleep_range(10, 100); 610 amdgpu_device_invalidate_hdp(psp->adev, NULL); 611 } 612 613 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 614 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 615 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 616 617 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 618 619 /* In some cases, psp response status is not 0 even there is no 620 * problem while the command is submitted. Some version of PSP FW 621 * doesn't write 0 to that field. 622 * So here we would like to only print a warning instead of an error 623 * during psp initialization to avoid breaking hw_init and it doesn't 624 * return -EINVAL. 625 */ 626 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 627 if (ucode) 628 DRM_WARN("failed to load ucode %s(0x%X) ", 629 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 630 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 631 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 632 psp->cmd_buf_mem->resp.status); 633 /* If any firmware (including CAP) load fails under SRIOV, it should 634 * return failure to stop the VF from initializing. 635 * Also return failure in case of timeout 636 */ 637 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 638 ret = -EINVAL; 639 goto exit; 640 } 641 } 642 643 if (ucode) { 644 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 645 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 646 } 647 648 exit: 649 drm_dev_exit(idx); 650 return ret; 651 } 652 653 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 654 { 655 struct psp_gfx_cmd_resp *cmd = psp->cmd; 656 657 mutex_lock(&psp->mutex); 658 659 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 660 661 return cmd; 662 } 663 664 static void release_psp_cmd_buf(struct psp_context *psp) 665 { 666 mutex_unlock(&psp->mutex); 667 } 668 669 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 670 struct psp_gfx_cmd_resp *cmd, 671 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 672 { 673 struct amdgpu_device *adev = psp->adev; 674 uint32_t size = amdgpu_bo_size(tmr_bo); 675 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 676 677 if (amdgpu_sriov_vf(psp->adev)) 678 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 679 else 680 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 681 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 682 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 683 cmd->cmd.cmd_setup_tmr.buf_size = size; 684 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 685 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 686 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 687 } 688 689 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 690 uint64_t pri_buf_mc, uint32_t size) 691 { 692 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 693 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 694 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 695 cmd->cmd.cmd_load_toc.toc_size = size; 696 } 697 698 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 699 static int psp_load_toc(struct psp_context *psp, 700 uint32_t *tmr_size) 701 { 702 int ret; 703 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 704 705 /* Copy toc to psp firmware private buffer */ 706 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 707 708 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 709 710 ret = psp_cmd_submit_buf(psp, NULL, cmd, 711 psp->fence_buf_mc_addr); 712 if (!ret) 713 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 714 715 release_psp_cmd_buf(psp); 716 717 return ret; 718 } 719 720 /* Set up Trusted Memory Region */ 721 static int psp_tmr_init(struct psp_context *psp) 722 { 723 int ret; 724 int tmr_size; 725 void *tmr_buf; 726 void **pptr; 727 728 /* 729 * According to HW engineer, they prefer the TMR address be "naturally 730 * aligned" , e.g. the start address be an integer divide of TMR size. 731 * 732 * Note: this memory need be reserved till the driver 733 * uninitializes. 734 */ 735 tmr_size = PSP_TMR_SIZE(psp->adev); 736 737 /* For ASICs support RLC autoload, psp will parse the toc 738 * and calculate the total size of TMR needed */ 739 if (!amdgpu_sriov_vf(psp->adev) && 740 psp->toc.start_addr && 741 psp->toc.size_bytes && 742 psp->fw_pri_buf) { 743 ret = psp_load_toc(psp, &tmr_size); 744 if (ret) { 745 DRM_ERROR("Failed to load toc\n"); 746 return ret; 747 } 748 } 749 750 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 751 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 752 AMDGPU_GEM_DOMAIN_VRAM, 753 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 754 755 return ret; 756 } 757 758 static bool psp_skip_tmr(struct psp_context *psp) 759 { 760 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 761 case IP_VERSION(11, 0, 9): 762 case IP_VERSION(11, 0, 7): 763 case IP_VERSION(13, 0, 2): 764 return true; 765 default: 766 return false; 767 } 768 } 769 770 static int psp_tmr_load(struct psp_context *psp) 771 { 772 int ret; 773 struct psp_gfx_cmd_resp *cmd; 774 775 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 776 * Already set up by host driver. 777 */ 778 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 779 return 0; 780 781 cmd = acquire_psp_cmd_buf(psp); 782 783 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 784 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 785 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 786 787 ret = psp_cmd_submit_buf(psp, NULL, cmd, 788 psp->fence_buf_mc_addr); 789 790 release_psp_cmd_buf(psp); 791 792 return ret; 793 } 794 795 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 796 struct psp_gfx_cmd_resp *cmd) 797 { 798 if (amdgpu_sriov_vf(psp->adev)) 799 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 800 else 801 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 802 } 803 804 static int psp_tmr_unload(struct psp_context *psp) 805 { 806 int ret; 807 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 808 809 psp_prep_tmr_unload_cmd_buf(psp, cmd); 810 DRM_INFO("free PSP TMR buffer\n"); 811 812 ret = psp_cmd_submit_buf(psp, NULL, cmd, 813 psp->fence_buf_mc_addr); 814 815 release_psp_cmd_buf(psp); 816 817 return ret; 818 } 819 820 static int psp_tmr_terminate(struct psp_context *psp) 821 { 822 return psp_tmr_unload(psp); 823 } 824 825 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 826 uint64_t *output_ptr) 827 { 828 int ret; 829 struct psp_gfx_cmd_resp *cmd; 830 831 if (!output_ptr) 832 return -EINVAL; 833 834 if (amdgpu_sriov_vf(psp->adev)) 835 return 0; 836 837 cmd = acquire_psp_cmd_buf(psp); 838 839 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 840 841 ret = psp_cmd_submit_buf(psp, NULL, cmd, 842 psp->fence_buf_mc_addr); 843 844 if (!ret) { 845 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 846 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 847 } 848 849 release_psp_cmd_buf(psp); 850 851 return ret; 852 } 853 854 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 855 { 856 struct psp_context *psp = &adev->psp; 857 struct psp_gfx_cmd_resp *cmd; 858 int ret; 859 860 if (amdgpu_sriov_vf(adev)) 861 return 0; 862 863 cmd = acquire_psp_cmd_buf(psp); 864 865 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 866 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 867 868 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 869 if (!ret) { 870 *boot_cfg = 871 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 872 } 873 874 release_psp_cmd_buf(psp); 875 876 return ret; 877 } 878 879 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 880 { 881 int ret; 882 struct psp_context *psp = &adev->psp; 883 struct psp_gfx_cmd_resp *cmd; 884 885 if (amdgpu_sriov_vf(adev)) 886 return 0; 887 888 cmd = acquire_psp_cmd_buf(psp); 889 890 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 891 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 892 cmd->cmd.boot_cfg.boot_config = boot_cfg; 893 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 894 895 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 896 897 release_psp_cmd_buf(psp); 898 899 return ret; 900 } 901 902 static int psp_rl_load(struct amdgpu_device *adev) 903 { 904 int ret; 905 struct psp_context *psp = &adev->psp; 906 struct psp_gfx_cmd_resp *cmd; 907 908 if (!is_psp_fw_valid(psp->rl)) 909 return 0; 910 911 cmd = acquire_psp_cmd_buf(psp); 912 913 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 914 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 915 916 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 917 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 918 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 919 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 920 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 921 922 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 923 924 release_psp_cmd_buf(psp); 925 926 return ret; 927 } 928 929 static int psp_asd_initialize(struct psp_context *psp) 930 { 931 int ret; 932 933 /* If PSP version doesn't match ASD version, asd loading will be failed. 934 * add workaround to bypass it for sriov now. 935 * TODO: add version check to make it common 936 */ 937 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 938 return 0; 939 940 psp->asd_context.mem_context.shared_mc_addr = 0; 941 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 942 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 943 944 ret = psp_ta_load(psp, &psp->asd_context); 945 if (!ret) 946 psp->asd_context.initialized = true; 947 948 return ret; 949 } 950 951 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 952 uint32_t session_id) 953 { 954 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 955 cmd->cmd.cmd_unload_ta.session_id = session_id; 956 } 957 958 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 959 { 960 int ret; 961 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 962 963 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 964 965 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 966 967 release_psp_cmd_buf(psp); 968 969 return ret; 970 } 971 972 static int psp_asd_terminate(struct psp_context *psp) 973 { 974 int ret; 975 976 if (amdgpu_sriov_vf(psp->adev)) 977 return 0; 978 979 if (!psp->asd_context.initialized) 980 return 0; 981 982 ret = psp_ta_unload(psp, &psp->asd_context); 983 if (!ret) 984 psp->asd_context.initialized = false; 985 986 return ret; 987 } 988 989 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 990 uint32_t id, uint32_t value) 991 { 992 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 993 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 994 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 995 } 996 997 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 998 uint32_t value) 999 { 1000 struct psp_gfx_cmd_resp *cmd; 1001 int ret = 0; 1002 1003 if (reg >= PSP_REG_LAST) 1004 return -EINVAL; 1005 1006 cmd = acquire_psp_cmd_buf(psp); 1007 1008 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1010 if (ret) 1011 DRM_ERROR("PSP failed to program reg id %d", reg); 1012 1013 release_psp_cmd_buf(psp); 1014 1015 return ret; 1016 } 1017 1018 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1019 uint64_t ta_bin_mc, 1020 struct ta_context *context) 1021 { 1022 cmd->cmd_id = context->ta_load_type; 1023 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1024 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1025 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1026 1027 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1028 lower_32_bits(context->mem_context.shared_mc_addr); 1029 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1030 upper_32_bits(context->mem_context.shared_mc_addr); 1031 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1032 } 1033 1034 int psp_ta_init_shared_buf(struct psp_context *psp, 1035 struct ta_mem_context *mem_ctx) 1036 { 1037 /* 1038 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1039 * physical) for ta to host memory 1040 */ 1041 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1042 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1043 &mem_ctx->shared_bo, 1044 &mem_ctx->shared_mc_addr, 1045 &mem_ctx->shared_buf); 1046 } 1047 1048 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1049 uint32_t ta_cmd_id, 1050 struct ta_context *context) 1051 { 1052 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1053 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1054 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1055 1056 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1057 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1058 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1059 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1060 lower_32_bits(context->mem_context.shared_mc_addr); 1061 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1062 upper_32_bits(context->mem_context.shared_mc_addr); 1063 } 1064 1065 int psp_ta_invoke_indirect(struct psp_context *psp, 1066 uint32_t ta_cmd_id, 1067 struct ta_context *context) 1068 { 1069 int ret; 1070 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1071 1072 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1073 1074 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1075 psp->fence_buf_mc_addr); 1076 1077 context->resp_status = cmd->resp.status; 1078 1079 release_psp_cmd_buf(psp); 1080 1081 return ret; 1082 } 1083 1084 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1085 uint32_t ta_cmd_id, 1086 uint32_t session_id) 1087 { 1088 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1089 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1090 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1091 } 1092 1093 int psp_ta_invoke(struct psp_context *psp, 1094 uint32_t ta_cmd_id, 1095 struct ta_context *context) 1096 { 1097 int ret; 1098 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1099 1100 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1101 1102 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1103 psp->fence_buf_mc_addr); 1104 1105 context->resp_status = cmd->resp.status; 1106 1107 release_psp_cmd_buf(psp); 1108 1109 return ret; 1110 } 1111 1112 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1113 { 1114 int ret; 1115 struct psp_gfx_cmd_resp *cmd; 1116 1117 cmd = acquire_psp_cmd_buf(psp); 1118 1119 psp_copy_fw(psp, context->bin_desc.start_addr, 1120 context->bin_desc.size_bytes); 1121 1122 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1123 1124 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1125 psp->fence_buf_mc_addr); 1126 1127 context->resp_status = cmd->resp.status; 1128 1129 if (!ret) { 1130 context->session_id = cmd->resp.session_id; 1131 } 1132 1133 release_psp_cmd_buf(psp); 1134 1135 return ret; 1136 } 1137 1138 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1139 { 1140 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1141 } 1142 1143 int psp_xgmi_terminate(struct psp_context *psp) 1144 { 1145 int ret; 1146 struct amdgpu_device *adev = psp->adev; 1147 1148 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1149 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1150 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1151 adev->gmc.xgmi.connected_to_cpu)) 1152 return 0; 1153 1154 if (!psp->xgmi_context.context.initialized) 1155 return 0; 1156 1157 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1158 1159 psp->xgmi_context.context.initialized = false; 1160 1161 return ret; 1162 } 1163 1164 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1165 { 1166 struct ta_xgmi_shared_memory *xgmi_cmd; 1167 int ret; 1168 1169 if (!psp->ta_fw || 1170 !psp->xgmi_context.context.bin_desc.size_bytes || 1171 !psp->xgmi_context.context.bin_desc.start_addr) 1172 return -ENOENT; 1173 1174 if (!load_ta) 1175 goto invoke; 1176 1177 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1178 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1179 1180 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1181 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1182 if (ret) 1183 return ret; 1184 } 1185 1186 /* Load XGMI TA */ 1187 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1188 if (!ret) 1189 psp->xgmi_context.context.initialized = true; 1190 else 1191 return ret; 1192 1193 invoke: 1194 /* Initialize XGMI session */ 1195 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1196 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1197 xgmi_cmd->flag_extend_link_record = set_extended_data; 1198 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1199 1200 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1201 1202 return ret; 1203 } 1204 1205 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1206 { 1207 struct ta_xgmi_shared_memory *xgmi_cmd; 1208 int ret; 1209 1210 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1211 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1212 1213 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1214 1215 /* Invoke xgmi ta to get hive id */ 1216 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1217 if (ret) 1218 return ret; 1219 1220 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1221 1222 return 0; 1223 } 1224 1225 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1226 { 1227 struct ta_xgmi_shared_memory *xgmi_cmd; 1228 int ret; 1229 1230 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1231 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1232 1233 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1234 1235 /* Invoke xgmi ta to get the node id */ 1236 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1237 if (ret) 1238 return ret; 1239 1240 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1241 1242 return 0; 1243 } 1244 1245 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1246 { 1247 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1248 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1249 } 1250 1251 /* 1252 * Chips that support extended topology information require the driver to 1253 * reflect topology information in the opposite direction. This is 1254 * because the TA has already exceeded its link record limit and if the 1255 * TA holds bi-directional information, the driver would have to do 1256 * multiple fetches instead of just two. 1257 */ 1258 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1259 struct psp_xgmi_node_info node_info) 1260 { 1261 struct amdgpu_device *mirror_adev; 1262 struct amdgpu_hive_info *hive; 1263 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1264 uint64_t dst_node_id = node_info.node_id; 1265 uint8_t dst_num_hops = node_info.num_hops; 1266 uint8_t dst_num_links = node_info.num_links; 1267 1268 hive = amdgpu_get_xgmi_hive(psp->adev); 1269 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1270 struct psp_xgmi_topology_info *mirror_top_info; 1271 int j; 1272 1273 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1274 continue; 1275 1276 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1277 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1278 if (mirror_top_info->nodes[j].node_id != src_node_id) 1279 continue; 1280 1281 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1282 /* 1283 * prevent 0 num_links value re-reflection since reflection 1284 * criteria is based on num_hops (direct or indirect). 1285 * 1286 */ 1287 if (dst_num_links) 1288 mirror_top_info->nodes[j].num_links = dst_num_links; 1289 1290 break; 1291 } 1292 1293 break; 1294 } 1295 1296 amdgpu_put_xgmi_hive(hive); 1297 } 1298 1299 int psp_xgmi_get_topology_info(struct psp_context *psp, 1300 int number_devices, 1301 struct psp_xgmi_topology_info *topology, 1302 bool get_extended_data) 1303 { 1304 struct ta_xgmi_shared_memory *xgmi_cmd; 1305 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1306 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1307 int i; 1308 int ret; 1309 1310 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1311 return -EINVAL; 1312 1313 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1314 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1315 xgmi_cmd->flag_extend_link_record = get_extended_data; 1316 1317 /* Fill in the shared memory with topology information as input */ 1318 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1319 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1320 topology_info_input->num_nodes = number_devices; 1321 1322 for (i = 0; i < topology_info_input->num_nodes; i++) { 1323 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1324 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1325 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1326 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1327 } 1328 1329 /* Invoke xgmi ta to get the topology information */ 1330 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1331 if (ret) 1332 return ret; 1333 1334 /* Read the output topology information from the shared memory */ 1335 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1336 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1337 for (i = 0; i < topology->num_nodes; i++) { 1338 /* extended data will either be 0 or equal to non-extended data */ 1339 if (topology_info_output->nodes[i].num_hops) 1340 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1341 1342 /* non-extended data gets everything here so no need to update */ 1343 if (!get_extended_data) { 1344 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1345 topology->nodes[i].is_sharing_enabled = 1346 topology_info_output->nodes[i].is_sharing_enabled; 1347 topology->nodes[i].sdma_engine = 1348 topology_info_output->nodes[i].sdma_engine; 1349 } 1350 1351 } 1352 1353 /* Invoke xgmi ta again to get the link information */ 1354 if (psp_xgmi_peer_link_info_supported(psp)) { 1355 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1356 1357 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1358 1359 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1360 1361 if (ret) 1362 return ret; 1363 1364 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1365 for (i = 0; i < topology->num_nodes; i++) { 1366 /* accumulate num_links on extended data */ 1367 topology->nodes[i].num_links = get_extended_data ? 1368 topology->nodes[i].num_links + 1369 link_info_output->nodes[i].num_links : 1370 link_info_output->nodes[i].num_links; 1371 1372 /* reflect the topology information for bi-directionality */ 1373 if (psp->xgmi_context.supports_extended_data && 1374 get_extended_data && topology->nodes[i].num_hops) 1375 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1376 } 1377 } 1378 1379 return 0; 1380 } 1381 1382 int psp_xgmi_set_topology_info(struct psp_context *psp, 1383 int number_devices, 1384 struct psp_xgmi_topology_info *topology) 1385 { 1386 struct ta_xgmi_shared_memory *xgmi_cmd; 1387 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1388 int i; 1389 1390 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1391 return -EINVAL; 1392 1393 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1394 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1395 1396 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1397 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1398 topology_info_input->num_nodes = number_devices; 1399 1400 for (i = 0; i < topology_info_input->num_nodes; i++) { 1401 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1402 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1403 topology_info_input->nodes[i].is_sharing_enabled = 1; 1404 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1405 } 1406 1407 /* Invoke xgmi ta to set topology information */ 1408 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1409 } 1410 1411 // ras begin 1412 static void psp_ras_ta_check_status(struct psp_context *psp) 1413 { 1414 struct ta_ras_shared_memory *ras_cmd = 1415 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1416 1417 switch (ras_cmd->ras_status) { 1418 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1419 dev_warn(psp->adev->dev, 1420 "RAS WARNING: cmd failed due to unsupported ip\n"); 1421 break; 1422 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1423 dev_warn(psp->adev->dev, 1424 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1425 break; 1426 case TA_RAS_STATUS__SUCCESS: 1427 break; 1428 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1429 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1430 dev_warn(psp->adev->dev, 1431 "RAS WARNING: Inject error to critical region is not allowed\n"); 1432 break; 1433 default: 1434 dev_warn(psp->adev->dev, 1435 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1436 break; 1437 } 1438 } 1439 1440 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1441 { 1442 struct ta_ras_shared_memory *ras_cmd; 1443 int ret; 1444 1445 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1446 1447 /* 1448 * TODO: bypass the loading in sriov for now 1449 */ 1450 if (amdgpu_sriov_vf(psp->adev)) 1451 return 0; 1452 1453 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1454 1455 if (amdgpu_ras_intr_triggered()) 1456 return ret; 1457 1458 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1459 { 1460 DRM_WARN("RAS: Unsupported Interface"); 1461 return -EINVAL; 1462 } 1463 1464 if (!ret) { 1465 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1466 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1467 1468 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1469 } 1470 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1471 dev_warn(psp->adev->dev, 1472 "RAS internal register access blocked\n"); 1473 1474 psp_ras_ta_check_status(psp); 1475 } 1476 1477 return ret; 1478 } 1479 1480 int psp_ras_enable_features(struct psp_context *psp, 1481 union ta_ras_cmd_input *info, bool enable) 1482 { 1483 struct ta_ras_shared_memory *ras_cmd; 1484 int ret; 1485 1486 if (!psp->ras_context.context.initialized) 1487 return -EINVAL; 1488 1489 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1490 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1491 1492 if (enable) 1493 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1494 else 1495 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1496 1497 ras_cmd->ras_in_message = *info; 1498 1499 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1500 if (ret) 1501 return -EINVAL; 1502 1503 return 0; 1504 } 1505 1506 int psp_ras_terminate(struct psp_context *psp) 1507 { 1508 int ret; 1509 1510 /* 1511 * TODO: bypass the terminate in sriov for now 1512 */ 1513 if (amdgpu_sriov_vf(psp->adev)) 1514 return 0; 1515 1516 if (!psp->ras_context.context.initialized) 1517 return 0; 1518 1519 ret = psp_ta_unload(psp, &psp->ras_context.context); 1520 1521 psp->ras_context.context.initialized = false; 1522 1523 return ret; 1524 } 1525 1526 static int psp_ras_initialize(struct psp_context *psp) 1527 { 1528 int ret; 1529 uint32_t boot_cfg = 0xFF; 1530 struct amdgpu_device *adev = psp->adev; 1531 struct ta_ras_shared_memory *ras_cmd; 1532 1533 /* 1534 * TODO: bypass the initialize in sriov for now 1535 */ 1536 if (amdgpu_sriov_vf(adev)) 1537 return 0; 1538 1539 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1540 !adev->psp.ras_context.context.bin_desc.start_addr) { 1541 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1542 return 0; 1543 } 1544 1545 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1546 /* query GECC enablement status from boot config 1547 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1548 */ 1549 ret = psp_boot_config_get(adev, &boot_cfg); 1550 if (ret) 1551 dev_warn(adev->dev, "PSP get boot config failed\n"); 1552 1553 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1554 if (!boot_cfg) { 1555 dev_info(adev->dev, "GECC is disabled\n"); 1556 } else { 1557 /* disable GECC in next boot cycle if ras is 1558 * disabled by module parameter amdgpu_ras_enable 1559 * and/or amdgpu_ras_mask, or boot_config_get call 1560 * is failed 1561 */ 1562 ret = psp_boot_config_set(adev, 0); 1563 if (ret) 1564 dev_warn(adev->dev, "PSP set boot config failed\n"); 1565 else 1566 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1567 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1568 } 1569 } else { 1570 if (1 == boot_cfg) { 1571 dev_info(adev->dev, "GECC is enabled\n"); 1572 } else { 1573 /* enable GECC in next boot cycle if it is disabled 1574 * in boot config, or force enable GECC if failed to 1575 * get boot configuration 1576 */ 1577 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1578 if (ret) 1579 dev_warn(adev->dev, "PSP set boot config failed\n"); 1580 else 1581 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1582 } 1583 } 1584 } 1585 1586 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1587 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1588 1589 if (!psp->ras_context.context.initialized) { 1590 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1591 if (ret) 1592 return ret; 1593 } 1594 1595 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1596 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1597 1598 if (amdgpu_ras_is_poison_mode_supported(adev)) 1599 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1600 if (!adev->gmc.xgmi.connected_to_cpu) 1601 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1602 1603 ret = psp_ta_load(psp, &psp->ras_context.context); 1604 1605 if (!ret && !ras_cmd->ras_status) 1606 psp->ras_context.context.initialized = true; 1607 else { 1608 if (ras_cmd->ras_status) 1609 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1610 amdgpu_ras_fini(psp->adev); 1611 } 1612 1613 return ret; 1614 } 1615 1616 int psp_ras_trigger_error(struct psp_context *psp, 1617 struct ta_ras_trigger_error_input *info) 1618 { 1619 struct ta_ras_shared_memory *ras_cmd; 1620 int ret; 1621 1622 if (!psp->ras_context.context.initialized) 1623 return -EINVAL; 1624 1625 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1626 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1627 1628 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1629 ras_cmd->ras_in_message.trigger_error = *info; 1630 1631 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1632 if (ret) 1633 return -EINVAL; 1634 1635 /* If err_event_athub occurs error inject was successful, however 1636 return status from TA is no long reliable */ 1637 if (amdgpu_ras_intr_triggered()) 1638 return 0; 1639 1640 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1641 return -EACCES; 1642 else if (ras_cmd->ras_status) 1643 return -EINVAL; 1644 1645 return 0; 1646 } 1647 // ras end 1648 1649 // HDCP start 1650 static int psp_hdcp_initialize(struct psp_context *psp) 1651 { 1652 int ret; 1653 1654 /* 1655 * TODO: bypass the initialize in sriov for now 1656 */ 1657 if (amdgpu_sriov_vf(psp->adev)) 1658 return 0; 1659 1660 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1661 !psp->hdcp_context.context.bin_desc.start_addr) { 1662 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1663 return 0; 1664 } 1665 1666 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1667 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1668 1669 if (!psp->hdcp_context.context.initialized) { 1670 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1671 if (ret) 1672 return ret; 1673 } 1674 1675 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1676 if (!ret) { 1677 psp->hdcp_context.context.initialized = true; 1678 mutex_init(&psp->hdcp_context.mutex); 1679 } 1680 1681 return ret; 1682 } 1683 1684 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1685 { 1686 /* 1687 * TODO: bypass the loading in sriov for now 1688 */ 1689 if (amdgpu_sriov_vf(psp->adev)) 1690 return 0; 1691 1692 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1693 } 1694 1695 static int psp_hdcp_terminate(struct psp_context *psp) 1696 { 1697 int ret; 1698 1699 /* 1700 * TODO: bypass the terminate in sriov for now 1701 */ 1702 if (amdgpu_sriov_vf(psp->adev)) 1703 return 0; 1704 1705 if (!psp->hdcp_context.context.initialized) 1706 return 0; 1707 1708 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1709 1710 psp->hdcp_context.context.initialized = false; 1711 1712 return ret; 1713 } 1714 // HDCP end 1715 1716 // DTM start 1717 static int psp_dtm_initialize(struct psp_context *psp) 1718 { 1719 int ret; 1720 1721 /* 1722 * TODO: bypass the initialize in sriov for now 1723 */ 1724 if (amdgpu_sriov_vf(psp->adev)) 1725 return 0; 1726 1727 if (!psp->dtm_context.context.bin_desc.size_bytes || 1728 !psp->dtm_context.context.bin_desc.start_addr) { 1729 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1730 return 0; 1731 } 1732 1733 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1734 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1735 1736 if (!psp->dtm_context.context.initialized) { 1737 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1738 if (ret) 1739 return ret; 1740 } 1741 1742 ret = psp_ta_load(psp, &psp->dtm_context.context); 1743 if (!ret) { 1744 psp->dtm_context.context.initialized = true; 1745 mutex_init(&psp->dtm_context.mutex); 1746 } 1747 1748 return ret; 1749 } 1750 1751 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1752 { 1753 /* 1754 * TODO: bypass the loading in sriov for now 1755 */ 1756 if (amdgpu_sriov_vf(psp->adev)) 1757 return 0; 1758 1759 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1760 } 1761 1762 static int psp_dtm_terminate(struct psp_context *psp) 1763 { 1764 int ret; 1765 1766 /* 1767 * TODO: bypass the terminate in sriov for now 1768 */ 1769 if (amdgpu_sriov_vf(psp->adev)) 1770 return 0; 1771 1772 if (!psp->dtm_context.context.initialized) 1773 return 0; 1774 1775 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1776 1777 psp->dtm_context.context.initialized = false; 1778 1779 return ret; 1780 } 1781 // DTM end 1782 1783 // RAP start 1784 static int psp_rap_initialize(struct psp_context *psp) 1785 { 1786 int ret; 1787 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1788 1789 /* 1790 * TODO: bypass the initialize in sriov for now 1791 */ 1792 if (amdgpu_sriov_vf(psp->adev)) 1793 return 0; 1794 1795 if (!psp->rap_context.context.bin_desc.size_bytes || 1796 !psp->rap_context.context.bin_desc.start_addr) { 1797 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1798 return 0; 1799 } 1800 1801 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1802 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1803 1804 if (!psp->rap_context.context.initialized) { 1805 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1806 if (ret) 1807 return ret; 1808 } 1809 1810 ret = psp_ta_load(psp, &psp->rap_context.context); 1811 if (!ret) { 1812 psp->rap_context.context.initialized = true; 1813 mutex_init(&psp->rap_context.mutex); 1814 } else 1815 return ret; 1816 1817 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1818 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1819 psp_rap_terminate(psp); 1820 /* free rap shared memory */ 1821 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1822 1823 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1824 ret, status); 1825 1826 return ret; 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int psp_rap_terminate(struct psp_context *psp) 1833 { 1834 int ret; 1835 1836 if (!psp->rap_context.context.initialized) 1837 return 0; 1838 1839 ret = psp_ta_unload(psp, &psp->rap_context.context); 1840 1841 psp->rap_context.context.initialized = false; 1842 1843 return ret; 1844 } 1845 1846 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1847 { 1848 struct ta_rap_shared_memory *rap_cmd; 1849 int ret = 0; 1850 1851 if (!psp->rap_context.context.initialized) 1852 return 0; 1853 1854 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1855 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1856 return -EINVAL; 1857 1858 mutex_lock(&psp->rap_context.mutex); 1859 1860 rap_cmd = (struct ta_rap_shared_memory *) 1861 psp->rap_context.context.mem_context.shared_buf; 1862 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1863 1864 rap_cmd->cmd_id = ta_cmd_id; 1865 rap_cmd->validation_method_id = METHOD_A; 1866 1867 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1868 if (ret) 1869 goto out_unlock; 1870 1871 if (status) 1872 *status = rap_cmd->rap_status; 1873 1874 out_unlock: 1875 mutex_unlock(&psp->rap_context.mutex); 1876 1877 return ret; 1878 } 1879 // RAP end 1880 1881 /* securedisplay start */ 1882 static int psp_securedisplay_initialize(struct psp_context *psp) 1883 { 1884 int ret; 1885 struct securedisplay_cmd *securedisplay_cmd; 1886 1887 /* 1888 * TODO: bypass the initialize in sriov for now 1889 */ 1890 if (amdgpu_sriov_vf(psp->adev)) 1891 return 0; 1892 1893 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1894 !psp->securedisplay_context.context.bin_desc.start_addr) { 1895 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1896 return 0; 1897 } 1898 1899 psp->securedisplay_context.context.mem_context.shared_mem_size = 1900 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1901 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1902 1903 if (!psp->securedisplay_context.context.initialized) { 1904 ret = psp_ta_init_shared_buf(psp, 1905 &psp->securedisplay_context.context.mem_context); 1906 if (ret) 1907 return ret; 1908 } 1909 1910 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1911 if (!ret) { 1912 psp->securedisplay_context.context.initialized = true; 1913 mutex_init(&psp->securedisplay_context.mutex); 1914 } else 1915 return ret; 1916 1917 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1918 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1919 1920 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1921 if (ret) { 1922 psp_securedisplay_terminate(psp); 1923 /* free securedisplay shared memory */ 1924 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1925 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1926 return -EINVAL; 1927 } 1928 1929 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1930 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1931 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1932 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1933 } 1934 1935 return 0; 1936 } 1937 1938 static int psp_securedisplay_terminate(struct psp_context *psp) 1939 { 1940 int ret; 1941 1942 /* 1943 * TODO:bypass the terminate in sriov for now 1944 */ 1945 if (amdgpu_sriov_vf(psp->adev)) 1946 return 0; 1947 1948 if (!psp->securedisplay_context.context.initialized) 1949 return 0; 1950 1951 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1952 1953 psp->securedisplay_context.context.initialized = false; 1954 1955 return ret; 1956 } 1957 1958 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1959 { 1960 int ret; 1961 1962 if (!psp->securedisplay_context.context.initialized) 1963 return -EINVAL; 1964 1965 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1966 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1967 return -EINVAL; 1968 1969 mutex_lock(&psp->securedisplay_context.mutex); 1970 1971 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 1972 1973 mutex_unlock(&psp->securedisplay_context.mutex); 1974 1975 return ret; 1976 } 1977 /* SECUREDISPLAY end */ 1978 1979 static int psp_hw_start(struct psp_context *psp) 1980 { 1981 struct amdgpu_device *adev = psp->adev; 1982 int ret; 1983 1984 if (!amdgpu_sriov_vf(adev)) { 1985 if ((is_psp_fw_valid(psp->kdb)) && 1986 (psp->funcs->bootloader_load_kdb != NULL)) { 1987 ret = psp_bootloader_load_kdb(psp); 1988 if (ret) { 1989 DRM_ERROR("PSP load kdb failed!\n"); 1990 return ret; 1991 } 1992 } 1993 1994 if ((is_psp_fw_valid(psp->spl)) && 1995 (psp->funcs->bootloader_load_spl != NULL)) { 1996 ret = psp_bootloader_load_spl(psp); 1997 if (ret) { 1998 DRM_ERROR("PSP load spl failed!\n"); 1999 return ret; 2000 } 2001 } 2002 2003 if ((is_psp_fw_valid(psp->sys)) && 2004 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2005 ret = psp_bootloader_load_sysdrv(psp); 2006 if (ret) { 2007 DRM_ERROR("PSP load sys drv failed!\n"); 2008 return ret; 2009 } 2010 } 2011 2012 if ((is_psp_fw_valid(psp->soc_drv)) && 2013 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2014 ret = psp_bootloader_load_soc_drv(psp); 2015 if (ret) { 2016 DRM_ERROR("PSP load soc drv failed!\n"); 2017 return ret; 2018 } 2019 } 2020 2021 if ((is_psp_fw_valid(psp->intf_drv)) && 2022 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2023 ret = psp_bootloader_load_intf_drv(psp); 2024 if (ret) { 2025 DRM_ERROR("PSP load intf drv failed!\n"); 2026 return ret; 2027 } 2028 } 2029 2030 if ((is_psp_fw_valid(psp->dbg_drv)) && 2031 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2032 ret = psp_bootloader_load_dbg_drv(psp); 2033 if (ret) { 2034 DRM_ERROR("PSP load dbg drv failed!\n"); 2035 return ret; 2036 } 2037 } 2038 2039 if ((is_psp_fw_valid(psp->sos)) && 2040 (psp->funcs->bootloader_load_sos != NULL)) { 2041 ret = psp_bootloader_load_sos(psp); 2042 if (ret) { 2043 DRM_ERROR("PSP load sos failed!\n"); 2044 return ret; 2045 } 2046 } 2047 } 2048 2049 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2050 if (ret) { 2051 DRM_ERROR("PSP create ring failed!\n"); 2052 return ret; 2053 } 2054 2055 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2056 goto skip_pin_bo; 2057 2058 ret = psp_tmr_init(psp); 2059 if (ret) { 2060 DRM_ERROR("PSP tmr init failed!\n"); 2061 return ret; 2062 } 2063 2064 skip_pin_bo: 2065 /* 2066 * For ASICs with DF Cstate management centralized 2067 * to PMFW, TMR setup should be performed after PMFW 2068 * loaded and before other non-psp firmware loaded. 2069 */ 2070 if (psp->pmfw_centralized_cstate_management) { 2071 ret = psp_load_smu_fw(psp); 2072 if (ret) 2073 return ret; 2074 } 2075 2076 ret = psp_tmr_load(psp); 2077 if (ret) { 2078 DRM_ERROR("PSP load tmr failed!\n"); 2079 return ret; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2086 enum psp_gfx_fw_type *type) 2087 { 2088 switch (ucode->ucode_id) { 2089 case AMDGPU_UCODE_ID_CAP: 2090 *type = GFX_FW_TYPE_CAP; 2091 break; 2092 case AMDGPU_UCODE_ID_SDMA0: 2093 *type = GFX_FW_TYPE_SDMA0; 2094 break; 2095 case AMDGPU_UCODE_ID_SDMA1: 2096 *type = GFX_FW_TYPE_SDMA1; 2097 break; 2098 case AMDGPU_UCODE_ID_SDMA2: 2099 *type = GFX_FW_TYPE_SDMA2; 2100 break; 2101 case AMDGPU_UCODE_ID_SDMA3: 2102 *type = GFX_FW_TYPE_SDMA3; 2103 break; 2104 case AMDGPU_UCODE_ID_SDMA4: 2105 *type = GFX_FW_TYPE_SDMA4; 2106 break; 2107 case AMDGPU_UCODE_ID_SDMA5: 2108 *type = GFX_FW_TYPE_SDMA5; 2109 break; 2110 case AMDGPU_UCODE_ID_SDMA6: 2111 *type = GFX_FW_TYPE_SDMA6; 2112 break; 2113 case AMDGPU_UCODE_ID_SDMA7: 2114 *type = GFX_FW_TYPE_SDMA7; 2115 break; 2116 case AMDGPU_UCODE_ID_CP_MES: 2117 *type = GFX_FW_TYPE_CP_MES; 2118 break; 2119 case AMDGPU_UCODE_ID_CP_MES_DATA: 2120 *type = GFX_FW_TYPE_MES_STACK; 2121 break; 2122 case AMDGPU_UCODE_ID_CP_MES1: 2123 *type = GFX_FW_TYPE_CP_MES_KIQ; 2124 break; 2125 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2126 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2127 break; 2128 case AMDGPU_UCODE_ID_CP_CE: 2129 *type = GFX_FW_TYPE_CP_CE; 2130 break; 2131 case AMDGPU_UCODE_ID_CP_PFP: 2132 *type = GFX_FW_TYPE_CP_PFP; 2133 break; 2134 case AMDGPU_UCODE_ID_CP_ME: 2135 *type = GFX_FW_TYPE_CP_ME; 2136 break; 2137 case AMDGPU_UCODE_ID_CP_MEC1: 2138 *type = GFX_FW_TYPE_CP_MEC; 2139 break; 2140 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2141 *type = GFX_FW_TYPE_CP_MEC_ME1; 2142 break; 2143 case AMDGPU_UCODE_ID_CP_MEC2: 2144 *type = GFX_FW_TYPE_CP_MEC; 2145 break; 2146 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2147 *type = GFX_FW_TYPE_CP_MEC_ME2; 2148 break; 2149 case AMDGPU_UCODE_ID_RLC_P: 2150 *type = GFX_FW_TYPE_RLC_P; 2151 break; 2152 case AMDGPU_UCODE_ID_RLC_V: 2153 *type = GFX_FW_TYPE_RLC_V; 2154 break; 2155 case AMDGPU_UCODE_ID_RLC_G: 2156 *type = GFX_FW_TYPE_RLC_G; 2157 break; 2158 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2159 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2160 break; 2161 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2162 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2163 break; 2164 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2165 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2166 break; 2167 case AMDGPU_UCODE_ID_RLC_IRAM: 2168 *type = GFX_FW_TYPE_RLC_IRAM; 2169 break; 2170 case AMDGPU_UCODE_ID_RLC_DRAM: 2171 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2172 break; 2173 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2174 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2175 break; 2176 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2177 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2178 break; 2179 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2180 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2181 break; 2182 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2183 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2184 break; 2185 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2186 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2187 break; 2188 case AMDGPU_UCODE_ID_SMC: 2189 *type = GFX_FW_TYPE_SMU; 2190 break; 2191 case AMDGPU_UCODE_ID_PPTABLE: 2192 *type = GFX_FW_TYPE_PPTABLE; 2193 break; 2194 case AMDGPU_UCODE_ID_UVD: 2195 *type = GFX_FW_TYPE_UVD; 2196 break; 2197 case AMDGPU_UCODE_ID_UVD1: 2198 *type = GFX_FW_TYPE_UVD1; 2199 break; 2200 case AMDGPU_UCODE_ID_VCE: 2201 *type = GFX_FW_TYPE_VCE; 2202 break; 2203 case AMDGPU_UCODE_ID_VCN: 2204 *type = GFX_FW_TYPE_VCN; 2205 break; 2206 case AMDGPU_UCODE_ID_VCN1: 2207 *type = GFX_FW_TYPE_VCN1; 2208 break; 2209 case AMDGPU_UCODE_ID_DMCU_ERAM: 2210 *type = GFX_FW_TYPE_DMCU_ERAM; 2211 break; 2212 case AMDGPU_UCODE_ID_DMCU_INTV: 2213 *type = GFX_FW_TYPE_DMCU_ISR; 2214 break; 2215 case AMDGPU_UCODE_ID_VCN0_RAM: 2216 *type = GFX_FW_TYPE_VCN0_RAM; 2217 break; 2218 case AMDGPU_UCODE_ID_VCN1_RAM: 2219 *type = GFX_FW_TYPE_VCN1_RAM; 2220 break; 2221 case AMDGPU_UCODE_ID_DMCUB: 2222 *type = GFX_FW_TYPE_DMUB; 2223 break; 2224 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2225 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2226 break; 2227 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2228 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2229 break; 2230 case AMDGPU_UCODE_ID_IMU_I: 2231 *type = GFX_FW_TYPE_IMU_I; 2232 break; 2233 case AMDGPU_UCODE_ID_IMU_D: 2234 *type = GFX_FW_TYPE_IMU_D; 2235 break; 2236 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2237 *type = GFX_FW_TYPE_RS64_PFP; 2238 break; 2239 case AMDGPU_UCODE_ID_CP_RS64_ME: 2240 *type = GFX_FW_TYPE_RS64_ME; 2241 break; 2242 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2243 *type = GFX_FW_TYPE_RS64_MEC; 2244 break; 2245 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2246 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2247 break; 2248 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2249 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2250 break; 2251 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2252 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2253 break; 2254 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2255 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2256 break; 2257 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2258 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2259 break; 2260 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2261 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2262 break; 2263 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2264 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2265 break; 2266 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2267 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2268 break; 2269 case AMDGPU_UCODE_ID_MAXIMUM: 2270 default: 2271 return -EINVAL; 2272 } 2273 2274 return 0; 2275 } 2276 2277 static void psp_print_fw_hdr(struct psp_context *psp, 2278 struct amdgpu_firmware_info *ucode) 2279 { 2280 struct amdgpu_device *adev = psp->adev; 2281 struct common_firmware_header *hdr; 2282 2283 switch (ucode->ucode_id) { 2284 case AMDGPU_UCODE_ID_SDMA0: 2285 case AMDGPU_UCODE_ID_SDMA1: 2286 case AMDGPU_UCODE_ID_SDMA2: 2287 case AMDGPU_UCODE_ID_SDMA3: 2288 case AMDGPU_UCODE_ID_SDMA4: 2289 case AMDGPU_UCODE_ID_SDMA5: 2290 case AMDGPU_UCODE_ID_SDMA6: 2291 case AMDGPU_UCODE_ID_SDMA7: 2292 hdr = (struct common_firmware_header *) 2293 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2294 amdgpu_ucode_print_sdma_hdr(hdr); 2295 break; 2296 case AMDGPU_UCODE_ID_CP_CE: 2297 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2298 amdgpu_ucode_print_gfx_hdr(hdr); 2299 break; 2300 case AMDGPU_UCODE_ID_CP_PFP: 2301 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2302 amdgpu_ucode_print_gfx_hdr(hdr); 2303 break; 2304 case AMDGPU_UCODE_ID_CP_ME: 2305 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2306 amdgpu_ucode_print_gfx_hdr(hdr); 2307 break; 2308 case AMDGPU_UCODE_ID_CP_MEC1: 2309 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2310 amdgpu_ucode_print_gfx_hdr(hdr); 2311 break; 2312 case AMDGPU_UCODE_ID_RLC_G: 2313 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2314 amdgpu_ucode_print_rlc_hdr(hdr); 2315 break; 2316 case AMDGPU_UCODE_ID_SMC: 2317 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2318 amdgpu_ucode_print_smc_hdr(hdr); 2319 break; 2320 default: 2321 break; 2322 } 2323 } 2324 2325 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2326 struct psp_gfx_cmd_resp *cmd) 2327 { 2328 int ret; 2329 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2330 2331 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2332 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2333 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2334 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2335 2336 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2337 if (ret) 2338 DRM_ERROR("Unknown firmware type\n"); 2339 2340 return ret; 2341 } 2342 2343 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2344 struct amdgpu_firmware_info *ucode) 2345 { 2346 int ret = 0; 2347 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2348 2349 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2350 if (!ret) { 2351 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2352 psp->fence_buf_mc_addr); 2353 } 2354 2355 release_psp_cmd_buf(psp); 2356 2357 return ret; 2358 } 2359 2360 static int psp_load_smu_fw(struct psp_context *psp) 2361 { 2362 int ret; 2363 struct amdgpu_device *adev = psp->adev; 2364 struct amdgpu_firmware_info *ucode = 2365 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2366 struct amdgpu_ras *ras = psp->ras_context.ras; 2367 2368 /* 2369 * Skip SMU FW reloading in case of using BACO for runpm only, 2370 * as SMU is always alive. 2371 */ 2372 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2373 return 0; 2374 2375 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2376 return 0; 2377 2378 if ((amdgpu_in_reset(adev) && 2379 ras && adev->ras_enabled && 2380 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2381 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2382 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2383 if (ret) { 2384 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2385 } 2386 } 2387 2388 ret = psp_execute_non_psp_fw_load(psp, ucode); 2389 2390 if (ret) 2391 DRM_ERROR("PSP load smu failed!\n"); 2392 2393 return ret; 2394 } 2395 2396 static bool fw_load_skip_check(struct psp_context *psp, 2397 struct amdgpu_firmware_info *ucode) 2398 { 2399 if (!ucode->fw) 2400 return true; 2401 2402 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2403 (psp_smu_reload_quirk(psp) || 2404 psp->autoload_supported || 2405 psp->pmfw_centralized_cstate_management)) 2406 return true; 2407 2408 if (amdgpu_sriov_vf(psp->adev) && 2409 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2410 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2411 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2412 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2413 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2414 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2415 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2416 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2417 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2418 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2419 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2420 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2421 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2422 /*skip ucode loading in SRIOV VF */ 2423 return true; 2424 2425 if (psp->autoload_supported && 2426 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2427 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2428 /* skip mec JT when autoload is enabled */ 2429 return true; 2430 2431 return false; 2432 } 2433 2434 int psp_load_fw_list(struct psp_context *psp, 2435 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2436 { 2437 int ret = 0, i; 2438 struct amdgpu_firmware_info *ucode; 2439 2440 for (i = 0; i < ucode_count; ++i) { 2441 ucode = ucode_list[i]; 2442 psp_print_fw_hdr(psp, ucode); 2443 ret = psp_execute_non_psp_fw_load(psp, ucode); 2444 if (ret) 2445 return ret; 2446 } 2447 return ret; 2448 } 2449 2450 static int psp_load_non_psp_fw(struct psp_context *psp) 2451 { 2452 int i, ret; 2453 struct amdgpu_firmware_info *ucode; 2454 struct amdgpu_device *adev = psp->adev; 2455 2456 if (psp->autoload_supported && 2457 !psp->pmfw_centralized_cstate_management) { 2458 ret = psp_load_smu_fw(psp); 2459 if (ret) 2460 return ret; 2461 } 2462 2463 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2464 ucode = &adev->firmware.ucode[i]; 2465 2466 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2467 !fw_load_skip_check(psp, ucode)) { 2468 ret = psp_load_smu_fw(psp); 2469 if (ret) 2470 return ret; 2471 continue; 2472 } 2473 2474 if (fw_load_skip_check(psp, ucode)) 2475 continue; 2476 2477 if (psp->autoload_supported && 2478 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2479 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2480 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2481 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2482 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2483 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2484 /* PSP only receive one SDMA fw for sienna_cichlid, 2485 * as all four sdma fw are same */ 2486 continue; 2487 2488 psp_print_fw_hdr(psp, ucode); 2489 2490 ret = psp_execute_non_psp_fw_load(psp, ucode); 2491 if (ret) 2492 return ret; 2493 2494 /* Start rlc autoload after psp recieved all the gfx firmware */ 2495 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2496 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2497 ret = psp_rlc_autoload_start(psp); 2498 if (ret) { 2499 DRM_ERROR("Failed to start rlc autoload\n"); 2500 return ret; 2501 } 2502 } 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int psp_load_fw(struct amdgpu_device *adev) 2509 { 2510 int ret; 2511 struct psp_context *psp = &adev->psp; 2512 2513 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2514 /* should not destroy ring, only stop */ 2515 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2516 } else { 2517 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2518 2519 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2520 if (ret) { 2521 DRM_ERROR("PSP ring init failed!\n"); 2522 goto failed; 2523 } 2524 } 2525 2526 ret = psp_hw_start(psp); 2527 if (ret) 2528 goto failed; 2529 2530 ret = psp_load_non_psp_fw(psp); 2531 if (ret) 2532 goto failed1; 2533 2534 ret = psp_asd_initialize(psp); 2535 if (ret) { 2536 DRM_ERROR("PSP load asd failed!\n"); 2537 goto failed1; 2538 } 2539 2540 ret = psp_rl_load(adev); 2541 if (ret) { 2542 DRM_ERROR("PSP load RL failed!\n"); 2543 goto failed1; 2544 } 2545 2546 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2547 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2548 ret = psp_xgmi_initialize(psp, false, true); 2549 /* Warning the XGMI seesion initialize failure 2550 * Instead of stop driver initialization 2551 */ 2552 if (ret) 2553 dev_err(psp->adev->dev, 2554 "XGMI: Failed to initialize XGMI session\n"); 2555 } 2556 } 2557 2558 if (psp->ta_fw) { 2559 ret = psp_ras_initialize(psp); 2560 if (ret) 2561 dev_err(psp->adev->dev, 2562 "RAS: Failed to initialize RAS\n"); 2563 2564 ret = psp_hdcp_initialize(psp); 2565 if (ret) 2566 dev_err(psp->adev->dev, 2567 "HDCP: Failed to initialize HDCP\n"); 2568 2569 ret = psp_dtm_initialize(psp); 2570 if (ret) 2571 dev_err(psp->adev->dev, 2572 "DTM: Failed to initialize DTM\n"); 2573 2574 ret = psp_rap_initialize(psp); 2575 if (ret) 2576 dev_err(psp->adev->dev, 2577 "RAP: Failed to initialize RAP\n"); 2578 2579 ret = psp_securedisplay_initialize(psp); 2580 if (ret) 2581 dev_err(psp->adev->dev, 2582 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2583 } 2584 2585 return 0; 2586 2587 failed1: 2588 psp_free_shared_bufs(psp); 2589 failed: 2590 /* 2591 * all cleanup jobs (xgmi terminate, ras terminate, 2592 * ring destroy, cmd/fence/fw buffers destory, 2593 * psp->cmd destory) are delayed to psp_hw_fini 2594 */ 2595 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2596 return ret; 2597 } 2598 2599 static int psp_hw_init(void *handle) 2600 { 2601 int ret; 2602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2603 2604 mutex_lock(&adev->firmware.mutex); 2605 /* 2606 * This sequence is just used on hw_init only once, no need on 2607 * resume. 2608 */ 2609 ret = amdgpu_ucode_init_bo(adev); 2610 if (ret) 2611 goto failed; 2612 2613 ret = psp_load_fw(adev); 2614 if (ret) { 2615 DRM_ERROR("PSP firmware loading failed\n"); 2616 goto failed; 2617 } 2618 2619 mutex_unlock(&adev->firmware.mutex); 2620 return 0; 2621 2622 failed: 2623 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2624 mutex_unlock(&adev->firmware.mutex); 2625 return -EINVAL; 2626 } 2627 2628 static int psp_hw_fini(void *handle) 2629 { 2630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2631 struct psp_context *psp = &adev->psp; 2632 2633 if (psp->ta_fw) { 2634 psp_ras_terminate(psp); 2635 psp_securedisplay_terminate(psp); 2636 psp_rap_terminate(psp); 2637 psp_dtm_terminate(psp); 2638 psp_hdcp_terminate(psp); 2639 } 2640 2641 psp_asd_terminate(psp); 2642 psp_tmr_terminate(psp); 2643 2644 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2645 2646 psp_free_shared_bufs(psp); 2647 2648 return 0; 2649 } 2650 2651 static int psp_suspend(void *handle) 2652 { 2653 int ret = 0; 2654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2655 struct psp_context *psp = &adev->psp; 2656 2657 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2658 psp->xgmi_context.context.initialized) { 2659 ret = psp_xgmi_terminate(psp); 2660 if (ret) { 2661 DRM_ERROR("Failed to terminate xgmi ta\n"); 2662 goto out; 2663 } 2664 } 2665 2666 if (psp->ta_fw) { 2667 ret = psp_ras_terminate(psp); 2668 if (ret) { 2669 DRM_ERROR("Failed to terminate ras ta\n"); 2670 goto out; 2671 } 2672 ret = psp_hdcp_terminate(psp); 2673 if (ret) { 2674 DRM_ERROR("Failed to terminate hdcp ta\n"); 2675 goto out; 2676 } 2677 ret = psp_dtm_terminate(psp); 2678 if (ret) { 2679 DRM_ERROR("Failed to terminate dtm ta\n"); 2680 goto out; 2681 } 2682 ret = psp_rap_terminate(psp); 2683 if (ret) { 2684 DRM_ERROR("Failed to terminate rap ta\n"); 2685 goto out; 2686 } 2687 ret = psp_securedisplay_terminate(psp); 2688 if (ret) { 2689 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2690 goto out; 2691 } 2692 } 2693 2694 ret = psp_asd_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate asd\n"); 2697 goto out; 2698 } 2699 2700 ret = psp_tmr_terminate(psp); 2701 if (ret) { 2702 DRM_ERROR("Failed to terminate tmr\n"); 2703 goto out; 2704 } 2705 2706 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2707 if (ret) { 2708 DRM_ERROR("PSP ring stop failed\n"); 2709 } 2710 2711 out: 2712 psp_free_shared_bufs(psp); 2713 2714 return ret; 2715 } 2716 2717 static int psp_resume(void *handle) 2718 { 2719 int ret; 2720 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2721 struct psp_context *psp = &adev->psp; 2722 2723 DRM_INFO("PSP is resuming...\n"); 2724 2725 if (psp->mem_train_ctx.enable_mem_training) { 2726 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2727 if (ret) { 2728 DRM_ERROR("Failed to process memory training!\n"); 2729 return ret; 2730 } 2731 } 2732 2733 mutex_lock(&adev->firmware.mutex); 2734 2735 ret = psp_hw_start(psp); 2736 if (ret) 2737 goto failed; 2738 2739 ret = psp_load_non_psp_fw(psp); 2740 if (ret) 2741 goto failed; 2742 2743 ret = psp_asd_initialize(psp); 2744 if (ret) { 2745 DRM_ERROR("PSP load asd failed!\n"); 2746 goto failed; 2747 } 2748 2749 ret = psp_rl_load(adev); 2750 if (ret) { 2751 dev_err(adev->dev, "PSP load RL failed!\n"); 2752 goto failed; 2753 } 2754 2755 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2756 ret = psp_xgmi_initialize(psp, false, true); 2757 /* Warning the XGMI seesion initialize failure 2758 * Instead of stop driver initialization 2759 */ 2760 if (ret) 2761 dev_err(psp->adev->dev, 2762 "XGMI: Failed to initialize XGMI session\n"); 2763 } 2764 2765 if (psp->ta_fw) { 2766 ret = psp_ras_initialize(psp); 2767 if (ret) 2768 dev_err(psp->adev->dev, 2769 "RAS: Failed to initialize RAS\n"); 2770 2771 ret = psp_hdcp_initialize(psp); 2772 if (ret) 2773 dev_err(psp->adev->dev, 2774 "HDCP: Failed to initialize HDCP\n"); 2775 2776 ret = psp_dtm_initialize(psp); 2777 if (ret) 2778 dev_err(psp->adev->dev, 2779 "DTM: Failed to initialize DTM\n"); 2780 2781 ret = psp_rap_initialize(psp); 2782 if (ret) 2783 dev_err(psp->adev->dev, 2784 "RAP: Failed to initialize RAP\n"); 2785 2786 ret = psp_securedisplay_initialize(psp); 2787 if (ret) 2788 dev_err(psp->adev->dev, 2789 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2790 } 2791 2792 mutex_unlock(&adev->firmware.mutex); 2793 2794 return 0; 2795 2796 failed: 2797 DRM_ERROR("PSP resume failed\n"); 2798 mutex_unlock(&adev->firmware.mutex); 2799 return ret; 2800 } 2801 2802 int psp_gpu_reset(struct amdgpu_device *adev) 2803 { 2804 int ret; 2805 2806 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2807 return 0; 2808 2809 mutex_lock(&adev->psp.mutex); 2810 ret = psp_mode1_reset(&adev->psp); 2811 mutex_unlock(&adev->psp.mutex); 2812 2813 return ret; 2814 } 2815 2816 int psp_rlc_autoload_start(struct psp_context *psp) 2817 { 2818 int ret; 2819 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2820 2821 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2822 2823 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2824 psp->fence_buf_mc_addr); 2825 2826 release_psp_cmd_buf(psp); 2827 2828 return ret; 2829 } 2830 2831 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2832 uint64_t cmd_gpu_addr, int cmd_size) 2833 { 2834 struct amdgpu_firmware_info ucode = {0}; 2835 2836 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2837 AMDGPU_UCODE_ID_VCN0_RAM; 2838 ucode.mc_addr = cmd_gpu_addr; 2839 ucode.ucode_size = cmd_size; 2840 2841 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2842 } 2843 2844 int psp_ring_cmd_submit(struct psp_context *psp, 2845 uint64_t cmd_buf_mc_addr, 2846 uint64_t fence_mc_addr, 2847 int index) 2848 { 2849 unsigned int psp_write_ptr_reg = 0; 2850 struct psp_gfx_rb_frame *write_frame; 2851 struct psp_ring *ring = &psp->km_ring; 2852 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2853 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2854 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2855 struct amdgpu_device *adev = psp->adev; 2856 uint32_t ring_size_dw = ring->ring_size / 4; 2857 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2858 2859 /* KM (GPCOM) prepare write pointer */ 2860 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2861 2862 /* Update KM RB frame pointer to new frame */ 2863 /* write_frame ptr increments by size of rb_frame in bytes */ 2864 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2865 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2866 write_frame = ring_buffer_start; 2867 else 2868 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2869 /* Check invalid write_frame ptr address */ 2870 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2871 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2872 ring_buffer_start, ring_buffer_end, write_frame); 2873 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2874 return -EINVAL; 2875 } 2876 2877 /* Initialize KM RB frame */ 2878 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2879 2880 /* Update KM RB frame */ 2881 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2882 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2883 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2884 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2885 write_frame->fence_value = index; 2886 amdgpu_device_flush_hdp(adev, NULL); 2887 2888 /* Update the write Pointer in DWORDs */ 2889 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2890 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2891 return 0; 2892 } 2893 2894 int psp_init_asd_microcode(struct psp_context *psp, 2895 const char *chip_name) 2896 { 2897 struct amdgpu_device *adev = psp->adev; 2898 char fw_name[PSP_FW_NAME_LEN]; 2899 const struct psp_firmware_header_v1_0 *asd_hdr; 2900 int err = 0; 2901 2902 if (!chip_name) { 2903 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2904 return -EINVAL; 2905 } 2906 2907 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2908 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2909 if (err) 2910 goto out; 2911 2912 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2913 if (err) 2914 goto out; 2915 2916 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2917 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2918 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2919 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2920 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2921 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2922 return 0; 2923 out: 2924 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2925 release_firmware(adev->psp.asd_fw); 2926 adev->psp.asd_fw = NULL; 2927 return err; 2928 } 2929 2930 int psp_init_toc_microcode(struct psp_context *psp, 2931 const char *chip_name) 2932 { 2933 struct amdgpu_device *adev = psp->adev; 2934 char fw_name[PSP_FW_NAME_LEN]; 2935 const struct psp_firmware_header_v1_0 *toc_hdr; 2936 int err = 0; 2937 2938 if (!chip_name) { 2939 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2940 return -EINVAL; 2941 } 2942 2943 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2944 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2945 if (err) 2946 goto out; 2947 2948 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2949 if (err) 2950 goto out; 2951 2952 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2953 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2954 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2955 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2956 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2957 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2958 return 0; 2959 out: 2960 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2961 release_firmware(adev->psp.toc_fw); 2962 adev->psp.toc_fw = NULL; 2963 return err; 2964 } 2965 2966 static int parse_sos_bin_descriptor(struct psp_context *psp, 2967 const struct psp_fw_bin_desc *desc, 2968 const struct psp_firmware_header_v2_0 *sos_hdr) 2969 { 2970 uint8_t *ucode_start_addr = NULL; 2971 2972 if (!psp || !desc || !sos_hdr) 2973 return -EINVAL; 2974 2975 ucode_start_addr = (uint8_t *)sos_hdr + 2976 le32_to_cpu(desc->offset_bytes) + 2977 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2978 2979 switch (desc->fw_type) { 2980 case PSP_FW_TYPE_PSP_SOS: 2981 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2982 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2983 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2984 psp->sos.start_addr = ucode_start_addr; 2985 break; 2986 case PSP_FW_TYPE_PSP_SYS_DRV: 2987 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2988 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2989 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2990 psp->sys.start_addr = ucode_start_addr; 2991 break; 2992 case PSP_FW_TYPE_PSP_KDB: 2993 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2994 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2995 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2996 psp->kdb.start_addr = ucode_start_addr; 2997 break; 2998 case PSP_FW_TYPE_PSP_TOC: 2999 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3000 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3001 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3002 psp->toc.start_addr = ucode_start_addr; 3003 break; 3004 case PSP_FW_TYPE_PSP_SPL: 3005 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3006 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3007 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3008 psp->spl.start_addr = ucode_start_addr; 3009 break; 3010 case PSP_FW_TYPE_PSP_RL: 3011 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3012 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3013 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3014 psp->rl.start_addr = ucode_start_addr; 3015 break; 3016 case PSP_FW_TYPE_PSP_SOC_DRV: 3017 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3018 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3019 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3020 psp->soc_drv.start_addr = ucode_start_addr; 3021 break; 3022 case PSP_FW_TYPE_PSP_INTF_DRV: 3023 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3024 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3025 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3026 psp->intf_drv.start_addr = ucode_start_addr; 3027 break; 3028 case PSP_FW_TYPE_PSP_DBG_DRV: 3029 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3030 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3031 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3032 psp->dbg_drv.start_addr = ucode_start_addr; 3033 break; 3034 default: 3035 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3036 break; 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3043 { 3044 const struct psp_firmware_header_v1_0 *sos_hdr; 3045 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3046 uint8_t *ucode_array_start_addr; 3047 3048 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3049 ucode_array_start_addr = (uint8_t *)sos_hdr + 3050 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3051 3052 if (adev->gmc.xgmi.connected_to_cpu || 3053 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3054 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3055 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3056 3057 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3058 adev->psp.sys.start_addr = ucode_array_start_addr; 3059 3060 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3061 adev->psp.sos.start_addr = ucode_array_start_addr + 3062 le32_to_cpu(sos_hdr->sos.offset_bytes); 3063 } else { 3064 /* Load alternate PSP SOS FW */ 3065 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3066 3067 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3068 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3069 3070 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3071 adev->psp.sys.start_addr = ucode_array_start_addr + 3072 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3073 3074 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3075 adev->psp.sos.start_addr = ucode_array_start_addr + 3076 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3077 } 3078 3079 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3080 dev_warn(adev->dev, "PSP SOS FW not available"); 3081 return -EINVAL; 3082 } 3083 3084 return 0; 3085 } 3086 3087 int psp_init_sos_microcode(struct psp_context *psp, 3088 const char *chip_name) 3089 { 3090 struct amdgpu_device *adev = psp->adev; 3091 char fw_name[PSP_FW_NAME_LEN]; 3092 const struct psp_firmware_header_v1_0 *sos_hdr; 3093 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3094 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3095 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3096 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3097 int err = 0; 3098 uint8_t *ucode_array_start_addr; 3099 int fw_index = 0; 3100 3101 if (!chip_name) { 3102 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3103 return -EINVAL; 3104 } 3105 3106 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3107 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3108 if (err) 3109 goto out; 3110 3111 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3112 if (err) 3113 goto out; 3114 3115 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3116 ucode_array_start_addr = (uint8_t *)sos_hdr + 3117 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3118 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3119 3120 switch (sos_hdr->header.header_version_major) { 3121 case 1: 3122 err = psp_init_sos_base_fw(adev); 3123 if (err) 3124 goto out; 3125 3126 if (sos_hdr->header.header_version_minor == 1) { 3127 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3128 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3129 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3130 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3131 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3132 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3133 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3134 } 3135 if (sos_hdr->header.header_version_minor == 2) { 3136 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3137 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3138 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3139 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3140 } 3141 if (sos_hdr->header.header_version_minor == 3) { 3142 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3143 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3144 adev->psp.toc.start_addr = ucode_array_start_addr + 3145 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3146 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3147 adev->psp.kdb.start_addr = ucode_array_start_addr + 3148 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3149 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3150 adev->psp.spl.start_addr = ucode_array_start_addr + 3151 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3152 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3153 adev->psp.rl.start_addr = ucode_array_start_addr + 3154 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3155 } 3156 break; 3157 case 2: 3158 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3159 3160 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3161 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3162 err = -EINVAL; 3163 goto out; 3164 } 3165 3166 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3167 err = parse_sos_bin_descriptor(psp, 3168 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3169 sos_hdr_v2_0); 3170 if (err) 3171 goto out; 3172 } 3173 break; 3174 default: 3175 dev_err(adev->dev, 3176 "unsupported psp sos firmware\n"); 3177 err = -EINVAL; 3178 goto out; 3179 } 3180 3181 return 0; 3182 out: 3183 dev_err(adev->dev, 3184 "failed to init sos firmware\n"); 3185 release_firmware(adev->psp.sos_fw); 3186 adev->psp.sos_fw = NULL; 3187 3188 return err; 3189 } 3190 3191 static int parse_ta_bin_descriptor(struct psp_context *psp, 3192 const struct psp_fw_bin_desc *desc, 3193 const struct ta_firmware_header_v2_0 *ta_hdr) 3194 { 3195 uint8_t *ucode_start_addr = NULL; 3196 3197 if (!psp || !desc || !ta_hdr) 3198 return -EINVAL; 3199 3200 ucode_start_addr = (uint8_t *)ta_hdr + 3201 le32_to_cpu(desc->offset_bytes) + 3202 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3203 3204 switch (desc->fw_type) { 3205 case TA_FW_TYPE_PSP_ASD: 3206 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3207 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3208 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3209 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3210 break; 3211 case TA_FW_TYPE_PSP_XGMI: 3212 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3213 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3214 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3215 break; 3216 case TA_FW_TYPE_PSP_RAS: 3217 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3218 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3219 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3220 break; 3221 case TA_FW_TYPE_PSP_HDCP: 3222 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3223 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3224 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3225 break; 3226 case TA_FW_TYPE_PSP_DTM: 3227 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3228 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3229 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3230 break; 3231 case TA_FW_TYPE_PSP_RAP: 3232 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3233 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3234 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3235 break; 3236 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3237 psp->securedisplay_context.context.bin_desc.fw_version = 3238 le32_to_cpu(desc->fw_version); 3239 psp->securedisplay_context.context.bin_desc.size_bytes = 3240 le32_to_cpu(desc->size_bytes); 3241 psp->securedisplay_context.context.bin_desc.start_addr = 3242 ucode_start_addr; 3243 break; 3244 default: 3245 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3246 break; 3247 } 3248 3249 return 0; 3250 } 3251 3252 int psp_init_ta_microcode(struct psp_context *psp, 3253 const char *chip_name) 3254 { 3255 struct amdgpu_device *adev = psp->adev; 3256 char fw_name[PSP_FW_NAME_LEN]; 3257 const struct ta_firmware_header_v2_0 *ta_hdr; 3258 int err = 0; 3259 int ta_index = 0; 3260 3261 if (!chip_name) { 3262 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3263 return -EINVAL; 3264 } 3265 3266 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3267 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3268 if (err) 3269 goto out; 3270 3271 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3272 if (err) 3273 goto out; 3274 3275 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3276 3277 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3278 dev_err(adev->dev, "unsupported TA header version\n"); 3279 err = -EINVAL; 3280 goto out; 3281 } 3282 3283 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3284 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3285 err = -EINVAL; 3286 goto out; 3287 } 3288 3289 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3290 err = parse_ta_bin_descriptor(psp, 3291 &ta_hdr->ta_fw_bin[ta_index], 3292 ta_hdr); 3293 if (err) 3294 goto out; 3295 } 3296 3297 return 0; 3298 out: 3299 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3300 release_firmware(adev->psp.ta_fw); 3301 adev->psp.ta_fw = NULL; 3302 return err; 3303 } 3304 3305 int psp_init_cap_microcode(struct psp_context *psp, 3306 const char *chip_name) 3307 { 3308 struct amdgpu_device *adev = psp->adev; 3309 char fw_name[PSP_FW_NAME_LEN]; 3310 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3311 struct amdgpu_firmware_info *info = NULL; 3312 int err = 0; 3313 3314 if (!chip_name) { 3315 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3316 return -EINVAL; 3317 } 3318 3319 if (!amdgpu_sriov_vf(adev)) { 3320 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3321 return -EINVAL; 3322 } 3323 3324 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3325 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3326 if (err) { 3327 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3328 err = 0; 3329 goto out; 3330 } 3331 3332 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3333 if (err) { 3334 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3335 goto out; 3336 } 3337 3338 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3339 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3340 info->fw = adev->psp.cap_fw; 3341 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3342 adev->psp.cap_fw->data; 3343 adev->firmware.fw_size += ALIGN( 3344 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3345 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3346 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3347 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3348 3349 return 0; 3350 3351 out: 3352 release_firmware(adev->psp.cap_fw); 3353 adev->psp.cap_fw = NULL; 3354 return err; 3355 } 3356 3357 static int psp_set_clockgating_state(void *handle, 3358 enum amd_clockgating_state state) 3359 { 3360 return 0; 3361 } 3362 3363 static int psp_set_powergating_state(void *handle, 3364 enum amd_powergating_state state) 3365 { 3366 return 0; 3367 } 3368 3369 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3370 struct device_attribute *attr, 3371 char *buf) 3372 { 3373 struct drm_device *ddev = dev_get_drvdata(dev); 3374 struct amdgpu_device *adev = drm_to_adev(ddev); 3375 uint32_t fw_ver; 3376 int ret; 3377 3378 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3379 DRM_INFO("PSP block is not ready yet."); 3380 return -EBUSY; 3381 } 3382 3383 mutex_lock(&adev->psp.mutex); 3384 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3385 mutex_unlock(&adev->psp.mutex); 3386 3387 if (ret) { 3388 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3389 return ret; 3390 } 3391 3392 return sysfs_emit(buf, "%x\n", fw_ver); 3393 } 3394 3395 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3396 struct device_attribute *attr, 3397 const char *buf, 3398 size_t count) 3399 { 3400 struct drm_device *ddev = dev_get_drvdata(dev); 3401 struct amdgpu_device *adev = drm_to_adev(ddev); 3402 int ret, idx; 3403 char fw_name[100]; 3404 const struct firmware *usbc_pd_fw; 3405 struct amdgpu_bo *fw_buf_bo = NULL; 3406 uint64_t fw_pri_mc_addr; 3407 void *fw_pri_cpu_addr; 3408 3409 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3410 DRM_INFO("PSP block is not ready yet."); 3411 return -EBUSY; 3412 } 3413 3414 if (!drm_dev_enter(ddev, &idx)) 3415 return -ENODEV; 3416 3417 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3418 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3419 if (ret) 3420 goto fail; 3421 3422 /* LFB address which is aligned to 1MB boundary per PSP request */ 3423 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3424 AMDGPU_GEM_DOMAIN_VRAM, 3425 &fw_buf_bo, 3426 &fw_pri_mc_addr, 3427 &fw_pri_cpu_addr); 3428 if (ret) 3429 goto rel_buf; 3430 3431 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3432 3433 mutex_lock(&adev->psp.mutex); 3434 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3435 mutex_unlock(&adev->psp.mutex); 3436 3437 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3438 3439 rel_buf: 3440 release_firmware(usbc_pd_fw); 3441 fail: 3442 if (ret) { 3443 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3444 count = ret; 3445 } 3446 3447 drm_dev_exit(idx); 3448 return count; 3449 } 3450 3451 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3452 { 3453 int idx; 3454 3455 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3456 return; 3457 3458 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3459 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3460 3461 drm_dev_exit(idx); 3462 } 3463 3464 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3465 psp_usbc_pd_fw_sysfs_read, 3466 psp_usbc_pd_fw_sysfs_write); 3467 3468 int is_psp_fw_valid(struct psp_bin_desc bin) 3469 { 3470 return bin.size_bytes; 3471 } 3472 3473 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3474 struct bin_attribute *bin_attr, 3475 char *buffer, loff_t pos, size_t count) 3476 { 3477 struct device *dev = kobj_to_dev(kobj); 3478 struct drm_device *ddev = dev_get_drvdata(dev); 3479 struct amdgpu_device *adev = drm_to_adev(ddev); 3480 3481 adev->psp.vbflash_done = false; 3482 3483 /* Safeguard against memory drain */ 3484 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3485 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3486 kvfree(adev->psp.vbflash_tmp_buf); 3487 adev->psp.vbflash_tmp_buf = NULL; 3488 adev->psp.vbflash_image_size = 0; 3489 return -ENOMEM; 3490 } 3491 3492 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3493 if (!adev->psp.vbflash_tmp_buf) { 3494 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3495 if (!adev->psp.vbflash_tmp_buf) 3496 return -ENOMEM; 3497 } 3498 3499 mutex_lock(&adev->psp.mutex); 3500 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3501 adev->psp.vbflash_image_size += count; 3502 mutex_unlock(&adev->psp.mutex); 3503 3504 dev_info(adev->dev, "VBIOS flash write PSP done"); 3505 3506 return count; 3507 } 3508 3509 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3510 struct bin_attribute *bin_attr, char *buffer, 3511 loff_t pos, size_t count) 3512 { 3513 struct device *dev = kobj_to_dev(kobj); 3514 struct drm_device *ddev = dev_get_drvdata(dev); 3515 struct amdgpu_device *adev = drm_to_adev(ddev); 3516 struct amdgpu_bo *fw_buf_bo = NULL; 3517 uint64_t fw_pri_mc_addr; 3518 void *fw_pri_cpu_addr; 3519 int ret; 3520 3521 dev_info(adev->dev, "VBIOS flash to PSP started"); 3522 3523 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3524 AMDGPU_GPU_PAGE_SIZE, 3525 AMDGPU_GEM_DOMAIN_VRAM, 3526 &fw_buf_bo, 3527 &fw_pri_mc_addr, 3528 &fw_pri_cpu_addr); 3529 if (ret) 3530 goto rel_buf; 3531 3532 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3533 3534 mutex_lock(&adev->psp.mutex); 3535 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3536 mutex_unlock(&adev->psp.mutex); 3537 3538 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3539 3540 rel_buf: 3541 kvfree(adev->psp.vbflash_tmp_buf); 3542 adev->psp.vbflash_tmp_buf = NULL; 3543 adev->psp.vbflash_image_size = 0; 3544 3545 if (ret) { 3546 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3547 return ret; 3548 } 3549 3550 dev_info(adev->dev, "VBIOS flash to PSP done"); 3551 return 0; 3552 } 3553 3554 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3555 struct device_attribute *attr, 3556 char *buf) 3557 { 3558 struct drm_device *ddev = dev_get_drvdata(dev); 3559 struct amdgpu_device *adev = drm_to_adev(ddev); 3560 uint32_t vbflash_status; 3561 3562 vbflash_status = psp_vbflash_status(&adev->psp); 3563 if (!adev->psp.vbflash_done) 3564 vbflash_status = 0; 3565 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3566 vbflash_status = 1; 3567 3568 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3569 } 3570 3571 static const struct bin_attribute psp_vbflash_bin_attr = { 3572 .attr = {.name = "psp_vbflash", .mode = 0664}, 3573 .size = 0, 3574 .write = amdgpu_psp_vbflash_write, 3575 .read = amdgpu_psp_vbflash_read, 3576 }; 3577 3578 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3579 3580 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3581 { 3582 int ret = 0; 3583 struct psp_context *psp = &adev->psp; 3584 3585 if (amdgpu_sriov_vf(adev)) 3586 return -EINVAL; 3587 3588 switch (adev->ip_versions[MP0_HWIP][0]) { 3589 case IP_VERSION(13, 0, 0): 3590 case IP_VERSION(13, 0, 7): 3591 if (!psp->adev) { 3592 psp->adev = adev; 3593 psp_v13_0_set_psp_funcs(psp); 3594 } 3595 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3596 if (ret) 3597 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3598 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3599 if (ret) 3600 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3601 return ret; 3602 default: 3603 return 0; 3604 } 3605 } 3606 3607 const struct amd_ip_funcs psp_ip_funcs = { 3608 .name = "psp", 3609 .early_init = psp_early_init, 3610 .late_init = NULL, 3611 .sw_init = psp_sw_init, 3612 .sw_fini = psp_sw_fini, 3613 .hw_init = psp_hw_init, 3614 .hw_fini = psp_hw_fini, 3615 .suspend = psp_suspend, 3616 .resume = psp_resume, 3617 .is_idle = NULL, 3618 .check_soft_reset = NULL, 3619 .wait_for_idle = NULL, 3620 .soft_reset = NULL, 3621 .set_clockgating_state = psp_set_clockgating_state, 3622 .set_powergating_state = psp_set_powergating_state, 3623 }; 3624 3625 static int psp_sysfs_init(struct amdgpu_device *adev) 3626 { 3627 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3628 3629 if (ret) 3630 DRM_ERROR("Failed to create USBC PD FW control file!"); 3631 3632 return ret; 3633 } 3634 3635 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3636 { 3637 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3638 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3639 } 3640 3641 static void psp_sysfs_fini(struct amdgpu_device *adev) 3642 { 3643 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3644 } 3645 3646 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3647 { 3648 .type = AMD_IP_BLOCK_TYPE_PSP, 3649 .major = 3, 3650 .minor = 1, 3651 .rev = 0, 3652 .funcs = &psp_ip_funcs, 3653 }; 3654 3655 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3656 { 3657 .type = AMD_IP_BLOCK_TYPE_PSP, 3658 .major = 10, 3659 .minor = 0, 3660 .rev = 0, 3661 .funcs = &psp_ip_funcs, 3662 }; 3663 3664 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3665 { 3666 .type = AMD_IP_BLOCK_TYPE_PSP, 3667 .major = 11, 3668 .minor = 0, 3669 .rev = 0, 3670 .funcs = &psp_ip_funcs, 3671 }; 3672 3673 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3674 .type = AMD_IP_BLOCK_TYPE_PSP, 3675 .major = 11, 3676 .minor = 0, 3677 .rev = 8, 3678 .funcs = &psp_ip_funcs, 3679 }; 3680 3681 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3682 { 3683 .type = AMD_IP_BLOCK_TYPE_PSP, 3684 .major = 12, 3685 .minor = 0, 3686 .rev = 0, 3687 .funcs = &psp_ip_funcs, 3688 }; 3689 3690 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3691 .type = AMD_IP_BLOCK_TYPE_PSP, 3692 .major = 13, 3693 .minor = 0, 3694 .rev = 0, 3695 .funcs = &psp_ip_funcs, 3696 }; 3697