1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 default: 157 return -EINVAL; 158 } 159 return ret; 160 } 161 162 static int psp_early_init(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 struct psp_context *psp = &adev->psp; 166 167 psp->autoload_supported = true; 168 psp->boot_time_tmr = true; 169 170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 171 case IP_VERSION(9, 0, 0): 172 psp_v3_1_set_psp_funcs(psp); 173 psp->autoload_supported = false; 174 psp->boot_time_tmr = false; 175 break; 176 case IP_VERSION(10, 0, 0): 177 case IP_VERSION(10, 0, 1): 178 psp_v10_0_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(11, 0, 2): 183 case IP_VERSION(11, 0, 4): 184 psp_v11_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 0): 189 case IP_VERSION(11, 0, 7): 190 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 191 fallthrough; 192 case IP_VERSION(11, 0, 5): 193 case IP_VERSION(11, 0, 9): 194 case IP_VERSION(11, 0, 11): 195 case IP_VERSION(11, 5, 0): 196 case IP_VERSION(11, 0, 12): 197 case IP_VERSION(11, 0, 13): 198 psp_v11_0_set_psp_funcs(psp); 199 psp->boot_time_tmr = false; 200 break; 201 case IP_VERSION(11, 0, 3): 202 case IP_VERSION(12, 0, 1): 203 psp_v12_0_set_psp_funcs(psp); 204 psp->autoload_supported = false; 205 psp->boot_time_tmr = false; 206 break; 207 case IP_VERSION(13, 0, 2): 208 psp->boot_time_tmr = false; 209 fallthrough; 210 case IP_VERSION(13, 0, 6): 211 case IP_VERSION(13, 0, 14): 212 psp_v13_0_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 break; 215 case IP_VERSION(13, 0, 1): 216 case IP_VERSION(13, 0, 3): 217 case IP_VERSION(13, 0, 5): 218 case IP_VERSION(13, 0, 8): 219 case IP_VERSION(13, 0, 11): 220 case IP_VERSION(14, 0, 0): 221 case IP_VERSION(14, 0, 1): 222 psp_v13_0_set_psp_funcs(psp); 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(11, 0, 8): 226 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 227 psp_v11_0_8_set_psp_funcs(psp); 228 } 229 psp->autoload_supported = false; 230 psp->boot_time_tmr = false; 231 break; 232 case IP_VERSION(13, 0, 0): 233 case IP_VERSION(13, 0, 7): 234 case IP_VERSION(13, 0, 10): 235 psp_v13_0_set_psp_funcs(psp); 236 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 237 psp->boot_time_tmr = false; 238 break; 239 case IP_VERSION(13, 0, 4): 240 psp_v13_0_4_set_psp_funcs(psp); 241 psp->boot_time_tmr = false; 242 break; 243 case IP_VERSION(14, 0, 2): 244 case IP_VERSION(14, 0, 3): 245 psp_v14_0_set_psp_funcs(psp); 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 psp->adev = adev; 252 253 adev->psp_timeout = 20000; 254 255 psp_check_pmfw_centralized_cstate_management(psp); 256 257 if (amdgpu_sriov_vf(adev)) 258 return psp_init_sriov_microcode(psp); 259 else 260 return psp_init_microcode(psp); 261 } 262 263 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 264 { 265 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 266 &mem_ctx->shared_buf); 267 mem_ctx->shared_bo = NULL; 268 } 269 270 static void psp_free_shared_bufs(struct psp_context *psp) 271 { 272 void *tmr_buf; 273 void **pptr; 274 275 /* free TMR memory buffer */ 276 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 277 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 278 psp->tmr_bo = NULL; 279 280 /* free xgmi shared memory */ 281 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 282 283 /* free ras shared memory */ 284 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 285 286 /* free hdcp shared memory */ 287 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 288 289 /* free dtm shared memory */ 290 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 291 292 /* free rap shared memory */ 293 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 294 295 /* free securedisplay shared memory */ 296 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 297 298 299 } 300 301 static void psp_memory_training_fini(struct psp_context *psp) 302 { 303 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 304 305 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 306 kfree(ctx->sys_cache); 307 ctx->sys_cache = NULL; 308 } 309 310 static int psp_memory_training_init(struct psp_context *psp) 311 { 312 int ret; 313 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 314 315 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 316 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 317 return 0; 318 } 319 320 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 321 if (ctx->sys_cache == NULL) { 322 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 323 ret = -ENOMEM; 324 goto Err_out; 325 } 326 327 dev_dbg(psp->adev->dev, 328 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 329 ctx->train_data_size, 330 ctx->p2c_train_data_offset, 331 ctx->c2p_train_data_offset); 332 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 333 return 0; 334 335 Err_out: 336 psp_memory_training_fini(psp); 337 return ret; 338 } 339 340 /* 341 * Helper funciton to query psp runtime database entry 342 * 343 * @adev: amdgpu_device pointer 344 * @entry_type: the type of psp runtime database entry 345 * @db_entry: runtime database entry pointer 346 * 347 * Return false if runtime database doesn't exit or entry is invalid 348 * or true if the specific database entry is found, and copy to @db_entry 349 */ 350 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 351 enum psp_runtime_entry_type entry_type, 352 void *db_entry) 353 { 354 uint64_t db_header_pos, db_dir_pos; 355 struct psp_runtime_data_header db_header = {0}; 356 struct psp_runtime_data_directory db_dir = {0}; 357 bool ret = false; 358 int i; 359 360 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 361 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 362 return false; 363 364 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 365 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 366 367 /* read runtime db header from vram */ 368 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 369 sizeof(struct psp_runtime_data_header), false); 370 371 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 372 /* runtime db doesn't exist, exit */ 373 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 374 return false; 375 } 376 377 /* read runtime database entry from vram */ 378 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 379 sizeof(struct psp_runtime_data_directory), false); 380 381 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 382 /* invalid db entry count, exit */ 383 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 384 return false; 385 } 386 387 /* look up for requested entry type */ 388 for (i = 0; i < db_dir.entry_count && !ret; i++) { 389 if (db_dir.entry_list[i].entry_type == entry_type) { 390 switch (entry_type) { 391 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 392 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 393 /* invalid db entry size */ 394 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 395 return false; 396 } 397 /* read runtime database entry */ 398 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 399 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 400 ret = true; 401 break; 402 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 403 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 404 /* invalid db entry size */ 405 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 406 return false; 407 } 408 /* read runtime database entry */ 409 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 410 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 411 ret = true; 412 break; 413 default: 414 ret = false; 415 break; 416 } 417 } 418 } 419 420 return ret; 421 } 422 423 static int psp_sw_init(void *handle) 424 { 425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 426 struct psp_context *psp = &adev->psp; 427 int ret; 428 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 429 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 430 struct psp_runtime_scpm_entry scpm_entry; 431 432 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 433 if (!psp->cmd) { 434 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 435 ret = -ENOMEM; 436 } 437 438 adev->psp.xgmi_context.supports_extended_data = 439 !adev->gmc.xgmi.connected_to_cpu && 440 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 441 442 memset(&scpm_entry, 0, sizeof(scpm_entry)); 443 if ((psp_get_runtime_db_entry(adev, 444 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 445 &scpm_entry)) && 446 (scpm_entry.scpm_status != SCPM_DISABLE)) { 447 adev->scpm_enabled = true; 448 adev->scpm_status = scpm_entry.scpm_status; 449 } else { 450 adev->scpm_enabled = false; 451 adev->scpm_status = SCPM_DISABLE; 452 } 453 454 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 455 456 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 457 if (psp_get_runtime_db_entry(adev, 458 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 459 &boot_cfg_entry)) { 460 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 461 if ((psp->boot_cfg_bitmask) & 462 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 463 /* If psp runtime database exists, then 464 * only enable two stage memory training 465 * when TWO_STAGE_DRAM_TRAINING bit is set 466 * in runtime database 467 */ 468 mem_training_ctx->enable_mem_training = true; 469 } 470 471 } else { 472 /* If psp runtime database doesn't exist or is 473 * invalid, force enable two stage memory training 474 */ 475 mem_training_ctx->enable_mem_training = true; 476 } 477 478 if (mem_training_ctx->enable_mem_training) { 479 ret = psp_memory_training_init(psp); 480 if (ret) { 481 dev_err(adev->dev, "Failed to initialize memory training!\n"); 482 return ret; 483 } 484 485 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 486 if (ret) { 487 dev_err(adev->dev, "Failed to process memory training!\n"); 488 return ret; 489 } 490 } 491 492 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 493 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 494 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 495 &psp->fw_pri_bo, 496 &psp->fw_pri_mc_addr, 497 &psp->fw_pri_buf); 498 if (ret) 499 return ret; 500 501 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 502 AMDGPU_GEM_DOMAIN_VRAM | 503 AMDGPU_GEM_DOMAIN_GTT, 504 &psp->fence_buf_bo, 505 &psp->fence_buf_mc_addr, 506 &psp->fence_buf); 507 if (ret) 508 goto failed1; 509 510 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 511 AMDGPU_GEM_DOMAIN_VRAM | 512 AMDGPU_GEM_DOMAIN_GTT, 513 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 514 (void **)&psp->cmd_buf_mem); 515 if (ret) 516 goto failed2; 517 518 return 0; 519 520 failed2: 521 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 522 &psp->fence_buf_mc_addr, &psp->fence_buf); 523 failed1: 524 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 525 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 526 return ret; 527 } 528 529 static int psp_sw_fini(void *handle) 530 { 531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 532 struct psp_context *psp = &adev->psp; 533 struct psp_gfx_cmd_resp *cmd = psp->cmd; 534 535 psp_memory_training_fini(psp); 536 537 amdgpu_ucode_release(&psp->sos_fw); 538 amdgpu_ucode_release(&psp->asd_fw); 539 amdgpu_ucode_release(&psp->ta_fw); 540 amdgpu_ucode_release(&psp->cap_fw); 541 amdgpu_ucode_release(&psp->toc_fw); 542 543 kfree(cmd); 544 cmd = NULL; 545 546 psp_free_shared_bufs(psp); 547 548 if (psp->km_ring.ring_mem) 549 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 550 &psp->km_ring.ring_mem_mc_addr, 551 (void **)&psp->km_ring.ring_mem); 552 553 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 554 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 555 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 556 &psp->fence_buf_mc_addr, &psp->fence_buf); 557 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 558 (void **)&psp->cmd_buf_mem); 559 560 return 0; 561 } 562 563 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 564 uint32_t reg_val, uint32_t mask, bool check_changed) 565 { 566 uint32_t val; 567 int i; 568 struct amdgpu_device *adev = psp->adev; 569 570 if (psp->adev->no_hw_access) 571 return 0; 572 573 for (i = 0; i < adev->usec_timeout; i++) { 574 val = RREG32(reg_index); 575 if (check_changed) { 576 if (val != reg_val) 577 return 0; 578 } else { 579 if ((val & mask) == reg_val) 580 return 0; 581 } 582 udelay(1); 583 } 584 585 return -ETIME; 586 } 587 588 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 589 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 590 { 591 uint32_t val; 592 int i; 593 struct amdgpu_device *adev = psp->adev; 594 595 if (psp->adev->no_hw_access) 596 return 0; 597 598 for (i = 0; i < msec_timeout; i++) { 599 val = RREG32(reg_index); 600 if ((val & mask) == reg_val) 601 return 0; 602 msleep(1); 603 } 604 605 return -ETIME; 606 } 607 608 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 609 { 610 switch (cmd_id) { 611 case GFX_CMD_ID_LOAD_TA: 612 return "LOAD_TA"; 613 case GFX_CMD_ID_UNLOAD_TA: 614 return "UNLOAD_TA"; 615 case GFX_CMD_ID_INVOKE_CMD: 616 return "INVOKE_CMD"; 617 case GFX_CMD_ID_LOAD_ASD: 618 return "LOAD_ASD"; 619 case GFX_CMD_ID_SETUP_TMR: 620 return "SETUP_TMR"; 621 case GFX_CMD_ID_LOAD_IP_FW: 622 return "LOAD_IP_FW"; 623 case GFX_CMD_ID_DESTROY_TMR: 624 return "DESTROY_TMR"; 625 case GFX_CMD_ID_SAVE_RESTORE: 626 return "SAVE_RESTORE_IP_FW"; 627 case GFX_CMD_ID_SETUP_VMR: 628 return "SETUP_VMR"; 629 case GFX_CMD_ID_DESTROY_VMR: 630 return "DESTROY_VMR"; 631 case GFX_CMD_ID_PROG_REG: 632 return "PROG_REG"; 633 case GFX_CMD_ID_GET_FW_ATTESTATION: 634 return "GET_FW_ATTESTATION"; 635 case GFX_CMD_ID_LOAD_TOC: 636 return "ID_LOAD_TOC"; 637 case GFX_CMD_ID_AUTOLOAD_RLC: 638 return "AUTOLOAD_RLC"; 639 case GFX_CMD_ID_BOOT_CFG: 640 return "BOOT_CFG"; 641 default: 642 return "UNKNOWN CMD"; 643 } 644 } 645 646 static int 647 psp_cmd_submit_buf(struct psp_context *psp, 648 struct amdgpu_firmware_info *ucode, 649 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 650 { 651 int ret; 652 int index; 653 int timeout = psp->adev->psp_timeout; 654 bool ras_intr = false; 655 bool skip_unsupport = false; 656 657 if (psp->adev->no_hw_access) 658 return 0; 659 660 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 661 662 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 663 664 index = atomic_inc_return(&psp->fence_value); 665 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 666 if (ret) { 667 atomic_dec(&psp->fence_value); 668 goto exit; 669 } 670 671 amdgpu_device_invalidate_hdp(psp->adev, NULL); 672 while (*((unsigned int *)psp->fence_buf) != index) { 673 if (--timeout == 0) 674 break; 675 /* 676 * Shouldn't wait for timeout when err_event_athub occurs, 677 * because gpu reset thread triggered and lock resource should 678 * be released for psp resume sequence. 679 */ 680 ras_intr = amdgpu_ras_intr_triggered(); 681 if (ras_intr) 682 break; 683 usleep_range(10, 100); 684 amdgpu_device_invalidate_hdp(psp->adev, NULL); 685 } 686 687 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 688 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 689 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 690 691 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 692 693 /* In some cases, psp response status is not 0 even there is no 694 * problem while the command is submitted. Some version of PSP FW 695 * doesn't write 0 to that field. 696 * So here we would like to only print a warning instead of an error 697 * during psp initialization to avoid breaking hw_init and it doesn't 698 * return -EINVAL. 699 */ 700 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 701 if (ucode) 702 dev_warn(psp->adev->dev, 703 "failed to load ucode %s(0x%X) ", 704 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 705 dev_warn(psp->adev->dev, 706 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 707 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 708 psp->cmd_buf_mem->resp.status); 709 /* If any firmware (including CAP) load fails under SRIOV, it should 710 * return failure to stop the VF from initializing. 711 * Also return failure in case of timeout 712 */ 713 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 714 ret = -EINVAL; 715 goto exit; 716 } 717 } 718 719 if (ucode) { 720 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 721 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 722 } 723 724 exit: 725 return ret; 726 } 727 728 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 729 { 730 struct psp_gfx_cmd_resp *cmd = psp->cmd; 731 732 mutex_lock(&psp->mutex); 733 734 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 735 736 return cmd; 737 } 738 739 static void release_psp_cmd_buf(struct psp_context *psp) 740 { 741 mutex_unlock(&psp->mutex); 742 } 743 744 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 745 struct psp_gfx_cmd_resp *cmd, 746 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 747 { 748 struct amdgpu_device *adev = psp->adev; 749 uint32_t size = 0; 750 uint64_t tmr_pa = 0; 751 752 if (tmr_bo) { 753 size = amdgpu_bo_size(tmr_bo); 754 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 755 } 756 757 if (amdgpu_sriov_vf(psp->adev)) 758 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 759 else 760 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 761 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 762 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 763 cmd->cmd.cmd_setup_tmr.buf_size = size; 764 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 765 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 766 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 767 } 768 769 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 770 uint64_t pri_buf_mc, uint32_t size) 771 { 772 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 773 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 774 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 775 cmd->cmd.cmd_load_toc.toc_size = size; 776 } 777 778 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 779 static int psp_load_toc(struct psp_context *psp, 780 uint32_t *tmr_size) 781 { 782 int ret; 783 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 784 785 /* Copy toc to psp firmware private buffer */ 786 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 787 788 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 789 790 ret = psp_cmd_submit_buf(psp, NULL, cmd, 791 psp->fence_buf_mc_addr); 792 if (!ret) 793 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 794 795 release_psp_cmd_buf(psp); 796 797 return ret; 798 } 799 800 /* Set up Trusted Memory Region */ 801 static int psp_tmr_init(struct psp_context *psp) 802 { 803 int ret = 0; 804 int tmr_size; 805 void *tmr_buf; 806 void **pptr; 807 808 /* 809 * According to HW engineer, they prefer the TMR address be "naturally 810 * aligned" , e.g. the start address be an integer divide of TMR size. 811 * 812 * Note: this memory need be reserved till the driver 813 * uninitializes. 814 */ 815 tmr_size = PSP_TMR_SIZE(psp->adev); 816 817 /* For ASICs support RLC autoload, psp will parse the toc 818 * and calculate the total size of TMR needed 819 */ 820 if (!amdgpu_sriov_vf(psp->adev) && 821 psp->toc.start_addr && 822 psp->toc.size_bytes && 823 psp->fw_pri_buf) { 824 ret = psp_load_toc(psp, &tmr_size); 825 if (ret) { 826 dev_err(psp->adev->dev, "Failed to load toc\n"); 827 return ret; 828 } 829 } 830 831 if (!psp->tmr_bo && !psp->boot_time_tmr) { 832 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 833 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 834 PSP_TMR_ALIGNMENT, 835 AMDGPU_HAS_VRAM(psp->adev) ? 836 AMDGPU_GEM_DOMAIN_VRAM : 837 AMDGPU_GEM_DOMAIN_GTT, 838 &psp->tmr_bo, &psp->tmr_mc_addr, 839 pptr); 840 } 841 842 return ret; 843 } 844 845 static bool psp_skip_tmr(struct psp_context *psp) 846 { 847 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 848 case IP_VERSION(11, 0, 9): 849 case IP_VERSION(11, 0, 7): 850 case IP_VERSION(13, 0, 2): 851 case IP_VERSION(13, 0, 6): 852 case IP_VERSION(13, 0, 10): 853 case IP_VERSION(13, 0, 14): 854 return true; 855 default: 856 return false; 857 } 858 } 859 860 static int psp_tmr_load(struct psp_context *psp) 861 { 862 int ret; 863 struct psp_gfx_cmd_resp *cmd; 864 865 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 866 * Already set up by host driver. 867 */ 868 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 869 return 0; 870 871 cmd = acquire_psp_cmd_buf(psp); 872 873 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 874 if (psp->tmr_bo) 875 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 876 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 877 878 ret = psp_cmd_submit_buf(psp, NULL, cmd, 879 psp->fence_buf_mc_addr); 880 881 release_psp_cmd_buf(psp); 882 883 return ret; 884 } 885 886 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 887 struct psp_gfx_cmd_resp *cmd) 888 { 889 if (amdgpu_sriov_vf(psp->adev)) 890 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 891 else 892 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 893 } 894 895 static int psp_tmr_unload(struct psp_context *psp) 896 { 897 int ret; 898 struct psp_gfx_cmd_resp *cmd; 899 900 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 901 * as TMR is not loaded at all 902 */ 903 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 904 return 0; 905 906 cmd = acquire_psp_cmd_buf(psp); 907 908 psp_prep_tmr_unload_cmd_buf(psp, cmd); 909 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 910 911 ret = psp_cmd_submit_buf(psp, NULL, cmd, 912 psp->fence_buf_mc_addr); 913 914 release_psp_cmd_buf(psp); 915 916 return ret; 917 } 918 919 static int psp_tmr_terminate(struct psp_context *psp) 920 { 921 return psp_tmr_unload(psp); 922 } 923 924 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 925 uint64_t *output_ptr) 926 { 927 int ret; 928 struct psp_gfx_cmd_resp *cmd; 929 930 if (!output_ptr) 931 return -EINVAL; 932 933 if (amdgpu_sriov_vf(psp->adev)) 934 return 0; 935 936 cmd = acquire_psp_cmd_buf(psp); 937 938 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 939 940 ret = psp_cmd_submit_buf(psp, NULL, cmd, 941 psp->fence_buf_mc_addr); 942 943 if (!ret) { 944 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 945 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 946 } 947 948 release_psp_cmd_buf(psp); 949 950 return ret; 951 } 952 953 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 954 { 955 struct psp_context *psp = &adev->psp; 956 struct psp_gfx_cmd_resp *cmd; 957 int ret; 958 959 if (amdgpu_sriov_vf(adev)) 960 return 0; 961 962 cmd = acquire_psp_cmd_buf(psp); 963 964 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 965 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 966 967 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 968 if (!ret) { 969 *boot_cfg = 970 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 971 } 972 973 release_psp_cmd_buf(psp); 974 975 return ret; 976 } 977 978 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 979 { 980 int ret; 981 struct psp_context *psp = &adev->psp; 982 struct psp_gfx_cmd_resp *cmd; 983 984 if (amdgpu_sriov_vf(adev)) 985 return 0; 986 987 cmd = acquire_psp_cmd_buf(psp); 988 989 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 990 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 991 cmd->cmd.boot_cfg.boot_config = boot_cfg; 992 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 993 994 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 995 996 release_psp_cmd_buf(psp); 997 998 return ret; 999 } 1000 1001 static int psp_rl_load(struct amdgpu_device *adev) 1002 { 1003 int ret; 1004 struct psp_context *psp = &adev->psp; 1005 struct psp_gfx_cmd_resp *cmd; 1006 1007 if (!is_psp_fw_valid(psp->rl)) 1008 return 0; 1009 1010 cmd = acquire_psp_cmd_buf(psp); 1011 1012 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1013 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1014 1015 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1016 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1017 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1018 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1019 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1020 1021 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1022 1023 release_psp_cmd_buf(psp); 1024 1025 return ret; 1026 } 1027 1028 int psp_spatial_partition(struct psp_context *psp, int mode) 1029 { 1030 struct psp_gfx_cmd_resp *cmd; 1031 int ret; 1032 1033 if (amdgpu_sriov_vf(psp->adev)) 1034 return 0; 1035 1036 cmd = acquire_psp_cmd_buf(psp); 1037 1038 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1039 cmd->cmd.cmd_spatial_part.mode = mode; 1040 1041 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1042 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1043 1044 release_psp_cmd_buf(psp); 1045 1046 return ret; 1047 } 1048 1049 static int psp_asd_initialize(struct psp_context *psp) 1050 { 1051 int ret; 1052 1053 /* If PSP version doesn't match ASD version, asd loading will be failed. 1054 * add workaround to bypass it for sriov now. 1055 * TODO: add version check to make it common 1056 */ 1057 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1058 return 0; 1059 1060 /* bypass asd if display hardware is not available */ 1061 if (!amdgpu_device_has_display_hardware(psp->adev) && 1062 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1063 return 0; 1064 1065 psp->asd_context.mem_context.shared_mc_addr = 0; 1066 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1067 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1068 1069 ret = psp_ta_load(psp, &psp->asd_context); 1070 if (!ret) 1071 psp->asd_context.initialized = true; 1072 1073 return ret; 1074 } 1075 1076 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1077 uint32_t session_id) 1078 { 1079 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1080 cmd->cmd.cmd_unload_ta.session_id = session_id; 1081 } 1082 1083 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1084 { 1085 int ret; 1086 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1087 1088 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1089 1090 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1091 1092 context->resp_status = cmd->resp.status; 1093 1094 release_psp_cmd_buf(psp); 1095 1096 return ret; 1097 } 1098 1099 static int psp_asd_terminate(struct psp_context *psp) 1100 { 1101 int ret; 1102 1103 if (amdgpu_sriov_vf(psp->adev)) 1104 return 0; 1105 1106 if (!psp->asd_context.initialized) 1107 return 0; 1108 1109 ret = psp_ta_unload(psp, &psp->asd_context); 1110 if (!ret) 1111 psp->asd_context.initialized = false; 1112 1113 return ret; 1114 } 1115 1116 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1117 uint32_t id, uint32_t value) 1118 { 1119 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1120 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1121 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1122 } 1123 1124 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1125 uint32_t value) 1126 { 1127 struct psp_gfx_cmd_resp *cmd; 1128 int ret = 0; 1129 1130 if (reg >= PSP_REG_LAST) 1131 return -EINVAL; 1132 1133 cmd = acquire_psp_cmd_buf(psp); 1134 1135 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1136 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1137 if (ret) 1138 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1139 1140 release_psp_cmd_buf(psp); 1141 1142 return ret; 1143 } 1144 1145 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1146 uint64_t ta_bin_mc, 1147 struct ta_context *context) 1148 { 1149 cmd->cmd_id = context->ta_load_type; 1150 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1151 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1152 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1153 1154 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1155 lower_32_bits(context->mem_context.shared_mc_addr); 1156 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1157 upper_32_bits(context->mem_context.shared_mc_addr); 1158 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1159 } 1160 1161 int psp_ta_init_shared_buf(struct psp_context *psp, 1162 struct ta_mem_context *mem_ctx) 1163 { 1164 /* 1165 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1166 * physical) for ta to host memory 1167 */ 1168 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1169 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1170 AMDGPU_GEM_DOMAIN_GTT, 1171 &mem_ctx->shared_bo, 1172 &mem_ctx->shared_mc_addr, 1173 &mem_ctx->shared_buf); 1174 } 1175 1176 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1177 uint32_t ta_cmd_id, 1178 uint32_t session_id) 1179 { 1180 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1181 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1182 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1183 } 1184 1185 int psp_ta_invoke(struct psp_context *psp, 1186 uint32_t ta_cmd_id, 1187 struct ta_context *context) 1188 { 1189 int ret; 1190 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1191 1192 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1195 psp->fence_buf_mc_addr); 1196 1197 context->resp_status = cmd->resp.status; 1198 1199 release_psp_cmd_buf(psp); 1200 1201 return ret; 1202 } 1203 1204 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1205 { 1206 int ret; 1207 struct psp_gfx_cmd_resp *cmd; 1208 1209 cmd = acquire_psp_cmd_buf(psp); 1210 1211 psp_copy_fw(psp, context->bin_desc.start_addr, 1212 context->bin_desc.size_bytes); 1213 1214 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1215 1216 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1217 psp->fence_buf_mc_addr); 1218 1219 context->resp_status = cmd->resp.status; 1220 1221 if (!ret) 1222 context->session_id = cmd->resp.session_id; 1223 1224 release_psp_cmd_buf(psp); 1225 1226 return ret; 1227 } 1228 1229 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1230 { 1231 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1232 } 1233 1234 int psp_xgmi_terminate(struct psp_context *psp) 1235 { 1236 int ret; 1237 struct amdgpu_device *adev = psp->adev; 1238 1239 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1240 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1241 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1242 adev->gmc.xgmi.connected_to_cpu)) 1243 return 0; 1244 1245 if (!psp->xgmi_context.context.initialized) 1246 return 0; 1247 1248 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1249 1250 psp->xgmi_context.context.initialized = false; 1251 1252 return ret; 1253 } 1254 1255 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1256 { 1257 struct ta_xgmi_shared_memory *xgmi_cmd; 1258 int ret; 1259 1260 if (!psp->ta_fw || 1261 !psp->xgmi_context.context.bin_desc.size_bytes || 1262 !psp->xgmi_context.context.bin_desc.start_addr) 1263 return -ENOENT; 1264 1265 if (!load_ta) 1266 goto invoke; 1267 1268 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1269 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1270 1271 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1272 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1273 if (ret) 1274 return ret; 1275 } 1276 1277 /* Load XGMI TA */ 1278 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1279 if (!ret) 1280 psp->xgmi_context.context.initialized = true; 1281 else 1282 return ret; 1283 1284 invoke: 1285 /* Initialize XGMI session */ 1286 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1287 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1288 xgmi_cmd->flag_extend_link_record = set_extended_data; 1289 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1290 1291 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1292 /* note down the capbility flag for XGMI TA */ 1293 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1294 1295 return ret; 1296 } 1297 1298 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1299 { 1300 struct ta_xgmi_shared_memory *xgmi_cmd; 1301 int ret; 1302 1303 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1304 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1305 1306 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1307 1308 /* Invoke xgmi ta to get hive id */ 1309 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1310 if (ret) 1311 return ret; 1312 1313 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1314 1315 return 0; 1316 } 1317 1318 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1319 { 1320 struct ta_xgmi_shared_memory *xgmi_cmd; 1321 int ret; 1322 1323 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1324 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1325 1326 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1327 1328 /* Invoke xgmi ta to get the node id */ 1329 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1330 if (ret) 1331 return ret; 1332 1333 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1334 1335 return 0; 1336 } 1337 1338 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1339 { 1340 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1341 IP_VERSION(13, 0, 2) && 1342 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1343 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1344 IP_VERSION(13, 0, 6); 1345 } 1346 1347 /* 1348 * Chips that support extended topology information require the driver to 1349 * reflect topology information in the opposite direction. This is 1350 * because the TA has already exceeded its link record limit and if the 1351 * TA holds bi-directional information, the driver would have to do 1352 * multiple fetches instead of just two. 1353 */ 1354 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1355 struct psp_xgmi_node_info node_info) 1356 { 1357 struct amdgpu_device *mirror_adev; 1358 struct amdgpu_hive_info *hive; 1359 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1360 uint64_t dst_node_id = node_info.node_id; 1361 uint8_t dst_num_hops = node_info.num_hops; 1362 uint8_t dst_num_links = node_info.num_links; 1363 1364 hive = amdgpu_get_xgmi_hive(psp->adev); 1365 if (WARN_ON(!hive)) 1366 return; 1367 1368 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1369 struct psp_xgmi_topology_info *mirror_top_info; 1370 int j; 1371 1372 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1373 continue; 1374 1375 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1376 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1377 if (mirror_top_info->nodes[j].node_id != src_node_id) 1378 continue; 1379 1380 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1381 /* 1382 * prevent 0 num_links value re-reflection since reflection 1383 * criteria is based on num_hops (direct or indirect). 1384 * 1385 */ 1386 if (dst_num_links) 1387 mirror_top_info->nodes[j].num_links = dst_num_links; 1388 1389 break; 1390 } 1391 1392 break; 1393 } 1394 1395 amdgpu_put_xgmi_hive(hive); 1396 } 1397 1398 int psp_xgmi_get_topology_info(struct psp_context *psp, 1399 int number_devices, 1400 struct psp_xgmi_topology_info *topology, 1401 bool get_extended_data) 1402 { 1403 struct ta_xgmi_shared_memory *xgmi_cmd; 1404 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1405 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1406 int i; 1407 int ret; 1408 1409 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1410 return -EINVAL; 1411 1412 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1413 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1414 xgmi_cmd->flag_extend_link_record = get_extended_data; 1415 1416 /* Fill in the shared memory with topology information as input */ 1417 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1418 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1419 topology_info_input->num_nodes = number_devices; 1420 1421 for (i = 0; i < topology_info_input->num_nodes; i++) { 1422 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1423 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1424 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1425 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1426 } 1427 1428 /* Invoke xgmi ta to get the topology information */ 1429 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1430 if (ret) 1431 return ret; 1432 1433 /* Read the output topology information from the shared memory */ 1434 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1435 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1436 for (i = 0; i < topology->num_nodes; i++) { 1437 /* extended data will either be 0 or equal to non-extended data */ 1438 if (topology_info_output->nodes[i].num_hops) 1439 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1440 1441 /* non-extended data gets everything here so no need to update */ 1442 if (!get_extended_data) { 1443 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1444 topology->nodes[i].is_sharing_enabled = 1445 topology_info_output->nodes[i].is_sharing_enabled; 1446 topology->nodes[i].sdma_engine = 1447 topology_info_output->nodes[i].sdma_engine; 1448 } 1449 1450 } 1451 1452 /* Invoke xgmi ta again to get the link information */ 1453 if (psp_xgmi_peer_link_info_supported(psp)) { 1454 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1455 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1456 bool requires_reflection = 1457 (psp->xgmi_context.supports_extended_data && 1458 get_extended_data) || 1459 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1460 IP_VERSION(13, 0, 6) || 1461 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1462 IP_VERSION(13, 0, 14); 1463 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1464 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1465 1466 /* popluate the shared output buffer rather than the cmd input buffer 1467 * with node_ids as the input for GET_PEER_LINKS command execution. 1468 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1469 * The same requirement for GET_EXTEND_PEER_LINKS command. 1470 */ 1471 if (ta_port_num_support) { 1472 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1473 1474 for (i = 0; i < topology->num_nodes; i++) 1475 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1476 1477 link_extend_info_output->num_nodes = topology->num_nodes; 1478 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1479 } else { 1480 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1481 1482 for (i = 0; i < topology->num_nodes; i++) 1483 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1484 1485 link_info_output->num_nodes = topology->num_nodes; 1486 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1487 } 1488 1489 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1490 if (ret) 1491 return ret; 1492 1493 for (i = 0; i < topology->num_nodes; i++) { 1494 uint8_t node_num_links = ta_port_num_support ? 1495 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1496 /* accumulate num_links on extended data */ 1497 if (get_extended_data) { 1498 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1499 } else { 1500 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1501 topology->nodes[i].num_links : node_num_links; 1502 } 1503 /* popluate the connected port num info if supported and available */ 1504 if (ta_port_num_support && topology->nodes[i].num_links) { 1505 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1506 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1507 } 1508 1509 /* reflect the topology information for bi-directionality */ 1510 if (requires_reflection && topology->nodes[i].num_hops) 1511 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1512 } 1513 } 1514 1515 return 0; 1516 } 1517 1518 int psp_xgmi_set_topology_info(struct psp_context *psp, 1519 int number_devices, 1520 struct psp_xgmi_topology_info *topology) 1521 { 1522 struct ta_xgmi_shared_memory *xgmi_cmd; 1523 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1524 int i; 1525 1526 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1527 return -EINVAL; 1528 1529 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1530 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1531 1532 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1533 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1534 topology_info_input->num_nodes = number_devices; 1535 1536 for (i = 0; i < topology_info_input->num_nodes; i++) { 1537 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1538 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1539 topology_info_input->nodes[i].is_sharing_enabled = 1; 1540 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1541 } 1542 1543 /* Invoke xgmi ta to set topology information */ 1544 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1545 } 1546 1547 // ras begin 1548 static void psp_ras_ta_check_status(struct psp_context *psp) 1549 { 1550 struct ta_ras_shared_memory *ras_cmd = 1551 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1552 1553 switch (ras_cmd->ras_status) { 1554 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1555 dev_warn(psp->adev->dev, 1556 "RAS WARNING: cmd failed due to unsupported ip\n"); 1557 break; 1558 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1559 dev_warn(psp->adev->dev, 1560 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1561 break; 1562 case TA_RAS_STATUS__SUCCESS: 1563 break; 1564 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1565 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1566 dev_warn(psp->adev->dev, 1567 "RAS WARNING: Inject error to critical region is not allowed\n"); 1568 break; 1569 default: 1570 dev_warn(psp->adev->dev, 1571 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1572 break; 1573 } 1574 } 1575 1576 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1577 { 1578 struct ta_ras_shared_memory *ras_cmd; 1579 int ret; 1580 1581 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1582 1583 /* 1584 * TODO: bypass the loading in sriov for now 1585 */ 1586 if (amdgpu_sriov_vf(psp->adev)) 1587 return 0; 1588 1589 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1590 1591 if (amdgpu_ras_intr_triggered()) 1592 return ret; 1593 1594 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1595 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1596 return -EINVAL; 1597 } 1598 1599 if (!ret) { 1600 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1601 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1602 1603 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1604 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1605 dev_warn(psp->adev->dev, 1606 "RAS internal register access blocked\n"); 1607 1608 psp_ras_ta_check_status(psp); 1609 } 1610 1611 return ret; 1612 } 1613 1614 int psp_ras_enable_features(struct psp_context *psp, 1615 union ta_ras_cmd_input *info, bool enable) 1616 { 1617 struct ta_ras_shared_memory *ras_cmd; 1618 int ret; 1619 1620 if (!psp->ras_context.context.initialized) 1621 return -EINVAL; 1622 1623 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1624 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1625 1626 if (enable) 1627 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1628 else 1629 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1630 1631 ras_cmd->ras_in_message = *info; 1632 1633 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1634 if (ret) 1635 return -EINVAL; 1636 1637 return 0; 1638 } 1639 1640 int psp_ras_terminate(struct psp_context *psp) 1641 { 1642 int ret; 1643 1644 /* 1645 * TODO: bypass the terminate in sriov for now 1646 */ 1647 if (amdgpu_sriov_vf(psp->adev)) 1648 return 0; 1649 1650 if (!psp->ras_context.context.initialized) 1651 return 0; 1652 1653 ret = psp_ta_unload(psp, &psp->ras_context.context); 1654 1655 psp->ras_context.context.initialized = false; 1656 1657 return ret; 1658 } 1659 1660 int psp_ras_initialize(struct psp_context *psp) 1661 { 1662 int ret; 1663 uint32_t boot_cfg = 0xFF; 1664 struct amdgpu_device *adev = psp->adev; 1665 struct ta_ras_shared_memory *ras_cmd; 1666 1667 /* 1668 * TODO: bypass the initialize in sriov for now 1669 */ 1670 if (amdgpu_sriov_vf(adev)) 1671 return 0; 1672 1673 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1674 !adev->psp.ras_context.context.bin_desc.start_addr) { 1675 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1676 return 0; 1677 } 1678 1679 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1680 /* query GECC enablement status from boot config 1681 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1682 */ 1683 ret = psp_boot_config_get(adev, &boot_cfg); 1684 if (ret) 1685 dev_warn(adev->dev, "PSP get boot config failed\n"); 1686 1687 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1688 if (!boot_cfg) { 1689 dev_info(adev->dev, "GECC is disabled\n"); 1690 } else { 1691 /* disable GECC in next boot cycle if ras is 1692 * disabled by module parameter amdgpu_ras_enable 1693 * and/or amdgpu_ras_mask, or boot_config_get call 1694 * is failed 1695 */ 1696 ret = psp_boot_config_set(adev, 0); 1697 if (ret) 1698 dev_warn(adev->dev, "PSP set boot config failed\n"); 1699 else 1700 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1701 } 1702 } else { 1703 if (boot_cfg == 1) { 1704 dev_info(adev->dev, "GECC is enabled\n"); 1705 } else { 1706 /* enable GECC in next boot cycle if it is disabled 1707 * in boot config, or force enable GECC if failed to 1708 * get boot configuration 1709 */ 1710 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1711 if (ret) 1712 dev_warn(adev->dev, "PSP set boot config failed\n"); 1713 else 1714 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1715 } 1716 } 1717 } 1718 1719 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1720 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1721 1722 if (!psp->ras_context.context.mem_context.shared_buf) { 1723 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1724 if (ret) 1725 return ret; 1726 } 1727 1728 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1729 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1730 1731 if (amdgpu_ras_is_poison_mode_supported(adev)) 1732 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1733 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1734 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1735 ras_cmd->ras_in_message.init_flags.xcc_mask = 1736 adev->gfx.xcc_mask; 1737 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1738 1739 ret = psp_ta_load(psp, &psp->ras_context.context); 1740 1741 if (!ret && !ras_cmd->ras_status) 1742 psp->ras_context.context.initialized = true; 1743 else { 1744 if (ras_cmd->ras_status) 1745 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1746 1747 /* fail to load RAS TA */ 1748 psp->ras_context.context.initialized = false; 1749 } 1750 1751 return ret; 1752 } 1753 1754 int psp_ras_trigger_error(struct psp_context *psp, 1755 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1756 { 1757 struct ta_ras_shared_memory *ras_cmd; 1758 struct amdgpu_device *adev = psp->adev; 1759 int ret; 1760 uint32_t dev_mask; 1761 1762 if (!psp->ras_context.context.initialized) 1763 return -EINVAL; 1764 1765 switch (info->block_id) { 1766 case TA_RAS_BLOCK__GFX: 1767 dev_mask = GET_MASK(GC, instance_mask); 1768 break; 1769 case TA_RAS_BLOCK__SDMA: 1770 dev_mask = GET_MASK(SDMA0, instance_mask); 1771 break; 1772 case TA_RAS_BLOCK__VCN: 1773 case TA_RAS_BLOCK__JPEG: 1774 dev_mask = GET_MASK(VCN, instance_mask); 1775 break; 1776 default: 1777 dev_mask = instance_mask; 1778 break; 1779 } 1780 1781 /* reuse sub_block_index for backward compatibility */ 1782 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1783 dev_mask &= AMDGPU_RAS_INST_MASK; 1784 info->sub_block_index |= dev_mask; 1785 1786 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1787 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1788 1789 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1790 ras_cmd->ras_in_message.trigger_error = *info; 1791 1792 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1793 if (ret) 1794 return -EINVAL; 1795 1796 /* If err_event_athub occurs error inject was successful, however 1797 * return status from TA is no long reliable 1798 */ 1799 if (amdgpu_ras_intr_triggered()) 1800 return 0; 1801 1802 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1803 return -EACCES; 1804 else if (ras_cmd->ras_status) 1805 return -EINVAL; 1806 1807 return 0; 1808 } 1809 1810 int psp_ras_query_address(struct psp_context *psp, 1811 struct ta_ras_query_address_input *addr_in, 1812 struct ta_ras_query_address_output *addr_out) 1813 { 1814 struct ta_ras_shared_memory *ras_cmd; 1815 int ret; 1816 1817 if (!psp->ras_context.context.initialized) 1818 return -EINVAL; 1819 1820 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1821 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1822 1823 ras_cmd->cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS; 1824 ras_cmd->ras_in_message.address = *addr_in; 1825 1826 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1827 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1828 return -EINVAL; 1829 1830 *addr_out = ras_cmd->ras_out_message.address; 1831 1832 return 0; 1833 } 1834 // ras end 1835 1836 // HDCP start 1837 static int psp_hdcp_initialize(struct psp_context *psp) 1838 { 1839 int ret; 1840 1841 /* 1842 * TODO: bypass the initialize in sriov for now 1843 */ 1844 if (amdgpu_sriov_vf(psp->adev)) 1845 return 0; 1846 1847 /* bypass hdcp initialization if dmu is harvested */ 1848 if (!amdgpu_device_has_display_hardware(psp->adev)) 1849 return 0; 1850 1851 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1852 !psp->hdcp_context.context.bin_desc.start_addr) { 1853 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1854 return 0; 1855 } 1856 1857 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1858 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1859 1860 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1861 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1862 if (ret) 1863 return ret; 1864 } 1865 1866 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1867 if (!ret) { 1868 psp->hdcp_context.context.initialized = true; 1869 mutex_init(&psp->hdcp_context.mutex); 1870 } 1871 1872 return ret; 1873 } 1874 1875 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1876 { 1877 /* 1878 * TODO: bypass the loading in sriov for now 1879 */ 1880 if (amdgpu_sriov_vf(psp->adev)) 1881 return 0; 1882 1883 if (!psp->hdcp_context.context.initialized) 1884 return 0; 1885 1886 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1887 } 1888 1889 static int psp_hdcp_terminate(struct psp_context *psp) 1890 { 1891 int ret; 1892 1893 /* 1894 * TODO: bypass the terminate in sriov for now 1895 */ 1896 if (amdgpu_sriov_vf(psp->adev)) 1897 return 0; 1898 1899 if (!psp->hdcp_context.context.initialized) 1900 return 0; 1901 1902 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1903 1904 psp->hdcp_context.context.initialized = false; 1905 1906 return ret; 1907 } 1908 // HDCP end 1909 1910 // DTM start 1911 static int psp_dtm_initialize(struct psp_context *psp) 1912 { 1913 int ret; 1914 1915 /* 1916 * TODO: bypass the initialize in sriov for now 1917 */ 1918 if (amdgpu_sriov_vf(psp->adev)) 1919 return 0; 1920 1921 /* bypass dtm initialization if dmu is harvested */ 1922 if (!amdgpu_device_has_display_hardware(psp->adev)) 1923 return 0; 1924 1925 if (!psp->dtm_context.context.bin_desc.size_bytes || 1926 !psp->dtm_context.context.bin_desc.start_addr) { 1927 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1928 return 0; 1929 } 1930 1931 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1932 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1933 1934 if (!psp->dtm_context.context.mem_context.shared_buf) { 1935 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1936 if (ret) 1937 return ret; 1938 } 1939 1940 ret = psp_ta_load(psp, &psp->dtm_context.context); 1941 if (!ret) { 1942 psp->dtm_context.context.initialized = true; 1943 mutex_init(&psp->dtm_context.mutex); 1944 } 1945 1946 return ret; 1947 } 1948 1949 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1950 { 1951 /* 1952 * TODO: bypass the loading in sriov for now 1953 */ 1954 if (amdgpu_sriov_vf(psp->adev)) 1955 return 0; 1956 1957 if (!psp->dtm_context.context.initialized) 1958 return 0; 1959 1960 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1961 } 1962 1963 static int psp_dtm_terminate(struct psp_context *psp) 1964 { 1965 int ret; 1966 1967 /* 1968 * TODO: bypass the terminate in sriov for now 1969 */ 1970 if (amdgpu_sriov_vf(psp->adev)) 1971 return 0; 1972 1973 if (!psp->dtm_context.context.initialized) 1974 return 0; 1975 1976 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1977 1978 psp->dtm_context.context.initialized = false; 1979 1980 return ret; 1981 } 1982 // DTM end 1983 1984 // RAP start 1985 static int psp_rap_initialize(struct psp_context *psp) 1986 { 1987 int ret; 1988 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1989 1990 /* 1991 * TODO: bypass the initialize in sriov for now 1992 */ 1993 if (amdgpu_sriov_vf(psp->adev)) 1994 return 0; 1995 1996 if (!psp->rap_context.context.bin_desc.size_bytes || 1997 !psp->rap_context.context.bin_desc.start_addr) { 1998 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1999 return 0; 2000 } 2001 2002 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2003 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2004 2005 if (!psp->rap_context.context.mem_context.shared_buf) { 2006 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2007 if (ret) 2008 return ret; 2009 } 2010 2011 ret = psp_ta_load(psp, &psp->rap_context.context); 2012 if (!ret) { 2013 psp->rap_context.context.initialized = true; 2014 mutex_init(&psp->rap_context.mutex); 2015 } else 2016 return ret; 2017 2018 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2019 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2020 psp_rap_terminate(psp); 2021 /* free rap shared memory */ 2022 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2023 2024 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2025 ret, status); 2026 2027 return ret; 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int psp_rap_terminate(struct psp_context *psp) 2034 { 2035 int ret; 2036 2037 if (!psp->rap_context.context.initialized) 2038 return 0; 2039 2040 ret = psp_ta_unload(psp, &psp->rap_context.context); 2041 2042 psp->rap_context.context.initialized = false; 2043 2044 return ret; 2045 } 2046 2047 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2048 { 2049 struct ta_rap_shared_memory *rap_cmd; 2050 int ret = 0; 2051 2052 if (!psp->rap_context.context.initialized) 2053 return 0; 2054 2055 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2056 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2057 return -EINVAL; 2058 2059 mutex_lock(&psp->rap_context.mutex); 2060 2061 rap_cmd = (struct ta_rap_shared_memory *) 2062 psp->rap_context.context.mem_context.shared_buf; 2063 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2064 2065 rap_cmd->cmd_id = ta_cmd_id; 2066 rap_cmd->validation_method_id = METHOD_A; 2067 2068 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2069 if (ret) 2070 goto out_unlock; 2071 2072 if (status) 2073 *status = rap_cmd->rap_status; 2074 2075 out_unlock: 2076 mutex_unlock(&psp->rap_context.mutex); 2077 2078 return ret; 2079 } 2080 // RAP end 2081 2082 /* securedisplay start */ 2083 static int psp_securedisplay_initialize(struct psp_context *psp) 2084 { 2085 int ret; 2086 struct ta_securedisplay_cmd *securedisplay_cmd; 2087 2088 /* 2089 * TODO: bypass the initialize in sriov for now 2090 */ 2091 if (amdgpu_sriov_vf(psp->adev)) 2092 return 0; 2093 2094 /* bypass securedisplay initialization if dmu is harvested */ 2095 if (!amdgpu_device_has_display_hardware(psp->adev)) 2096 return 0; 2097 2098 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2099 !psp->securedisplay_context.context.bin_desc.start_addr) { 2100 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2101 return 0; 2102 } 2103 2104 psp->securedisplay_context.context.mem_context.shared_mem_size = 2105 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2106 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2107 2108 if (!psp->securedisplay_context.context.initialized) { 2109 ret = psp_ta_init_shared_buf(psp, 2110 &psp->securedisplay_context.context.mem_context); 2111 if (ret) 2112 return ret; 2113 } 2114 2115 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2116 if (!ret) { 2117 psp->securedisplay_context.context.initialized = true; 2118 mutex_init(&psp->securedisplay_context.mutex); 2119 } else 2120 return ret; 2121 2122 mutex_lock(&psp->securedisplay_context.mutex); 2123 2124 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2125 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2126 2127 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2128 2129 mutex_unlock(&psp->securedisplay_context.mutex); 2130 2131 if (ret) { 2132 psp_securedisplay_terminate(psp); 2133 /* free securedisplay shared memory */ 2134 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2135 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2136 return -EINVAL; 2137 } 2138 2139 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2140 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2141 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2142 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2143 /* don't try again */ 2144 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int psp_securedisplay_terminate(struct psp_context *psp) 2151 { 2152 int ret; 2153 2154 /* 2155 * TODO:bypass the terminate in sriov for now 2156 */ 2157 if (amdgpu_sriov_vf(psp->adev)) 2158 return 0; 2159 2160 if (!psp->securedisplay_context.context.initialized) 2161 return 0; 2162 2163 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2164 2165 psp->securedisplay_context.context.initialized = false; 2166 2167 return ret; 2168 } 2169 2170 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2171 { 2172 int ret; 2173 2174 if (!psp->securedisplay_context.context.initialized) 2175 return -EINVAL; 2176 2177 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2178 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2179 return -EINVAL; 2180 2181 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2182 2183 return ret; 2184 } 2185 /* SECUREDISPLAY end */ 2186 2187 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2188 { 2189 struct psp_context *psp = &adev->psp; 2190 int ret = 0; 2191 2192 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2193 ret = psp->funcs->wait_for_bootloader(psp); 2194 2195 return ret; 2196 } 2197 2198 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2199 { 2200 if (psp->funcs && 2201 psp->funcs->get_ras_capability) { 2202 return psp->funcs->get_ras_capability(psp); 2203 } else { 2204 return false; 2205 } 2206 } 2207 2208 static int psp_hw_start(struct psp_context *psp) 2209 { 2210 struct amdgpu_device *adev = psp->adev; 2211 int ret; 2212 2213 if (!amdgpu_sriov_vf(adev)) { 2214 if ((is_psp_fw_valid(psp->kdb)) && 2215 (psp->funcs->bootloader_load_kdb != NULL)) { 2216 ret = psp_bootloader_load_kdb(psp); 2217 if (ret) { 2218 dev_err(adev->dev, "PSP load kdb failed!\n"); 2219 return ret; 2220 } 2221 } 2222 2223 if ((is_psp_fw_valid(psp->spl)) && 2224 (psp->funcs->bootloader_load_spl != NULL)) { 2225 ret = psp_bootloader_load_spl(psp); 2226 if (ret) { 2227 dev_err(adev->dev, "PSP load spl failed!\n"); 2228 return ret; 2229 } 2230 } 2231 2232 if ((is_psp_fw_valid(psp->sys)) && 2233 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2234 ret = psp_bootloader_load_sysdrv(psp); 2235 if (ret) { 2236 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2237 return ret; 2238 } 2239 } 2240 2241 if ((is_psp_fw_valid(psp->soc_drv)) && 2242 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2243 ret = psp_bootloader_load_soc_drv(psp); 2244 if (ret) { 2245 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2246 return ret; 2247 } 2248 } 2249 2250 if ((is_psp_fw_valid(psp->intf_drv)) && 2251 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2252 ret = psp_bootloader_load_intf_drv(psp); 2253 if (ret) { 2254 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2255 return ret; 2256 } 2257 } 2258 2259 if ((is_psp_fw_valid(psp->dbg_drv)) && 2260 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2261 ret = psp_bootloader_load_dbg_drv(psp); 2262 if (ret) { 2263 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2264 return ret; 2265 } 2266 } 2267 2268 if ((is_psp_fw_valid(psp->ras_drv)) && 2269 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2270 ret = psp_bootloader_load_ras_drv(psp); 2271 if (ret) { 2272 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2273 return ret; 2274 } 2275 } 2276 2277 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2278 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2279 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2280 if (ret) { 2281 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2282 return ret; 2283 } 2284 } 2285 2286 if ((is_psp_fw_valid(psp->sos)) && 2287 (psp->funcs->bootloader_load_sos != NULL)) { 2288 ret = psp_bootloader_load_sos(psp); 2289 if (ret) { 2290 dev_err(adev->dev, "PSP load sos failed!\n"); 2291 return ret; 2292 } 2293 } 2294 } 2295 2296 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2297 if (ret) { 2298 dev_err(adev->dev, "PSP create ring failed!\n"); 2299 return ret; 2300 } 2301 2302 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2303 goto skip_pin_bo; 2304 2305 if (!psp->boot_time_tmr || psp->autoload_supported) { 2306 ret = psp_tmr_init(psp); 2307 if (ret) { 2308 dev_err(adev->dev, "PSP tmr init failed!\n"); 2309 return ret; 2310 } 2311 } 2312 2313 skip_pin_bo: 2314 /* 2315 * For ASICs with DF Cstate management centralized 2316 * to PMFW, TMR setup should be performed after PMFW 2317 * loaded and before other non-psp firmware loaded. 2318 */ 2319 if (psp->pmfw_centralized_cstate_management) { 2320 ret = psp_load_smu_fw(psp); 2321 if (ret) 2322 return ret; 2323 } 2324 2325 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2326 ret = psp_tmr_load(psp); 2327 if (ret) { 2328 dev_err(adev->dev, "PSP load tmr failed!\n"); 2329 return ret; 2330 } 2331 } 2332 2333 return 0; 2334 } 2335 2336 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2337 enum psp_gfx_fw_type *type) 2338 { 2339 switch (ucode->ucode_id) { 2340 case AMDGPU_UCODE_ID_CAP: 2341 *type = GFX_FW_TYPE_CAP; 2342 break; 2343 case AMDGPU_UCODE_ID_SDMA0: 2344 *type = GFX_FW_TYPE_SDMA0; 2345 break; 2346 case AMDGPU_UCODE_ID_SDMA1: 2347 *type = GFX_FW_TYPE_SDMA1; 2348 break; 2349 case AMDGPU_UCODE_ID_SDMA2: 2350 *type = GFX_FW_TYPE_SDMA2; 2351 break; 2352 case AMDGPU_UCODE_ID_SDMA3: 2353 *type = GFX_FW_TYPE_SDMA3; 2354 break; 2355 case AMDGPU_UCODE_ID_SDMA4: 2356 *type = GFX_FW_TYPE_SDMA4; 2357 break; 2358 case AMDGPU_UCODE_ID_SDMA5: 2359 *type = GFX_FW_TYPE_SDMA5; 2360 break; 2361 case AMDGPU_UCODE_ID_SDMA6: 2362 *type = GFX_FW_TYPE_SDMA6; 2363 break; 2364 case AMDGPU_UCODE_ID_SDMA7: 2365 *type = GFX_FW_TYPE_SDMA7; 2366 break; 2367 case AMDGPU_UCODE_ID_CP_MES: 2368 *type = GFX_FW_TYPE_CP_MES; 2369 break; 2370 case AMDGPU_UCODE_ID_CP_MES_DATA: 2371 *type = GFX_FW_TYPE_MES_STACK; 2372 break; 2373 case AMDGPU_UCODE_ID_CP_MES1: 2374 *type = GFX_FW_TYPE_CP_MES_KIQ; 2375 break; 2376 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2377 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2378 break; 2379 case AMDGPU_UCODE_ID_CP_CE: 2380 *type = GFX_FW_TYPE_CP_CE; 2381 break; 2382 case AMDGPU_UCODE_ID_CP_PFP: 2383 *type = GFX_FW_TYPE_CP_PFP; 2384 break; 2385 case AMDGPU_UCODE_ID_CP_ME: 2386 *type = GFX_FW_TYPE_CP_ME; 2387 break; 2388 case AMDGPU_UCODE_ID_CP_MEC1: 2389 *type = GFX_FW_TYPE_CP_MEC; 2390 break; 2391 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2392 *type = GFX_FW_TYPE_CP_MEC_ME1; 2393 break; 2394 case AMDGPU_UCODE_ID_CP_MEC2: 2395 *type = GFX_FW_TYPE_CP_MEC; 2396 break; 2397 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2398 *type = GFX_FW_TYPE_CP_MEC_ME2; 2399 break; 2400 case AMDGPU_UCODE_ID_RLC_P: 2401 *type = GFX_FW_TYPE_RLC_P; 2402 break; 2403 case AMDGPU_UCODE_ID_RLC_V: 2404 *type = GFX_FW_TYPE_RLC_V; 2405 break; 2406 case AMDGPU_UCODE_ID_RLC_G: 2407 *type = GFX_FW_TYPE_RLC_G; 2408 break; 2409 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2410 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2411 break; 2412 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2413 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2414 break; 2415 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2416 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2417 break; 2418 case AMDGPU_UCODE_ID_RLC_IRAM: 2419 *type = GFX_FW_TYPE_RLC_IRAM; 2420 break; 2421 case AMDGPU_UCODE_ID_RLC_DRAM: 2422 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2423 break; 2424 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2425 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2426 break; 2427 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2428 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2429 break; 2430 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2431 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2432 break; 2433 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2434 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2435 break; 2436 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2437 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2438 break; 2439 case AMDGPU_UCODE_ID_SMC: 2440 *type = GFX_FW_TYPE_SMU; 2441 break; 2442 case AMDGPU_UCODE_ID_PPTABLE: 2443 *type = GFX_FW_TYPE_PPTABLE; 2444 break; 2445 case AMDGPU_UCODE_ID_UVD: 2446 *type = GFX_FW_TYPE_UVD; 2447 break; 2448 case AMDGPU_UCODE_ID_UVD1: 2449 *type = GFX_FW_TYPE_UVD1; 2450 break; 2451 case AMDGPU_UCODE_ID_VCE: 2452 *type = GFX_FW_TYPE_VCE; 2453 break; 2454 case AMDGPU_UCODE_ID_VCN: 2455 *type = GFX_FW_TYPE_VCN; 2456 break; 2457 case AMDGPU_UCODE_ID_VCN1: 2458 *type = GFX_FW_TYPE_VCN1; 2459 break; 2460 case AMDGPU_UCODE_ID_DMCU_ERAM: 2461 *type = GFX_FW_TYPE_DMCU_ERAM; 2462 break; 2463 case AMDGPU_UCODE_ID_DMCU_INTV: 2464 *type = GFX_FW_TYPE_DMCU_ISR; 2465 break; 2466 case AMDGPU_UCODE_ID_VCN0_RAM: 2467 *type = GFX_FW_TYPE_VCN0_RAM; 2468 break; 2469 case AMDGPU_UCODE_ID_VCN1_RAM: 2470 *type = GFX_FW_TYPE_VCN1_RAM; 2471 break; 2472 case AMDGPU_UCODE_ID_DMCUB: 2473 *type = GFX_FW_TYPE_DMUB; 2474 break; 2475 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2476 case AMDGPU_UCODE_ID_SDMA_RS64: 2477 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2478 break; 2479 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2480 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2481 break; 2482 case AMDGPU_UCODE_ID_IMU_I: 2483 *type = GFX_FW_TYPE_IMU_I; 2484 break; 2485 case AMDGPU_UCODE_ID_IMU_D: 2486 *type = GFX_FW_TYPE_IMU_D; 2487 break; 2488 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2489 *type = GFX_FW_TYPE_RS64_PFP; 2490 break; 2491 case AMDGPU_UCODE_ID_CP_RS64_ME: 2492 *type = GFX_FW_TYPE_RS64_ME; 2493 break; 2494 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2495 *type = GFX_FW_TYPE_RS64_MEC; 2496 break; 2497 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2498 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2499 break; 2500 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2501 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2502 break; 2503 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2504 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2505 break; 2506 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2507 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2508 break; 2509 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2510 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2511 break; 2512 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2513 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2514 break; 2515 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2516 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2517 break; 2518 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2519 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2520 break; 2521 case AMDGPU_UCODE_ID_VPE_CTX: 2522 *type = GFX_FW_TYPE_VPEC_FW1; 2523 break; 2524 case AMDGPU_UCODE_ID_VPE_CTL: 2525 *type = GFX_FW_TYPE_VPEC_FW2; 2526 break; 2527 case AMDGPU_UCODE_ID_VPE: 2528 *type = GFX_FW_TYPE_VPE; 2529 break; 2530 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2531 *type = GFX_FW_TYPE_UMSCH_UCODE; 2532 break; 2533 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2534 *type = GFX_FW_TYPE_UMSCH_DATA; 2535 break; 2536 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2537 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2538 break; 2539 case AMDGPU_UCODE_ID_P2S_TABLE: 2540 *type = GFX_FW_TYPE_P2S_TABLE; 2541 break; 2542 case AMDGPU_UCODE_ID_JPEG_RAM: 2543 *type = GFX_FW_TYPE_JPEG_RAM; 2544 break; 2545 case AMDGPU_UCODE_ID_MAXIMUM: 2546 default: 2547 return -EINVAL; 2548 } 2549 2550 return 0; 2551 } 2552 2553 static void psp_print_fw_hdr(struct psp_context *psp, 2554 struct amdgpu_firmware_info *ucode) 2555 { 2556 struct amdgpu_device *adev = psp->adev; 2557 struct common_firmware_header *hdr; 2558 2559 switch (ucode->ucode_id) { 2560 case AMDGPU_UCODE_ID_SDMA0: 2561 case AMDGPU_UCODE_ID_SDMA1: 2562 case AMDGPU_UCODE_ID_SDMA2: 2563 case AMDGPU_UCODE_ID_SDMA3: 2564 case AMDGPU_UCODE_ID_SDMA4: 2565 case AMDGPU_UCODE_ID_SDMA5: 2566 case AMDGPU_UCODE_ID_SDMA6: 2567 case AMDGPU_UCODE_ID_SDMA7: 2568 hdr = (struct common_firmware_header *) 2569 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2570 amdgpu_ucode_print_sdma_hdr(hdr); 2571 break; 2572 case AMDGPU_UCODE_ID_CP_CE: 2573 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2574 amdgpu_ucode_print_gfx_hdr(hdr); 2575 break; 2576 case AMDGPU_UCODE_ID_CP_PFP: 2577 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2578 amdgpu_ucode_print_gfx_hdr(hdr); 2579 break; 2580 case AMDGPU_UCODE_ID_CP_ME: 2581 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2582 amdgpu_ucode_print_gfx_hdr(hdr); 2583 break; 2584 case AMDGPU_UCODE_ID_CP_MEC1: 2585 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2586 amdgpu_ucode_print_gfx_hdr(hdr); 2587 break; 2588 case AMDGPU_UCODE_ID_RLC_G: 2589 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2590 amdgpu_ucode_print_rlc_hdr(hdr); 2591 break; 2592 case AMDGPU_UCODE_ID_SMC: 2593 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2594 amdgpu_ucode_print_smc_hdr(hdr); 2595 break; 2596 default: 2597 break; 2598 } 2599 } 2600 2601 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2602 struct amdgpu_firmware_info *ucode, 2603 struct psp_gfx_cmd_resp *cmd) 2604 { 2605 int ret; 2606 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2607 2608 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2609 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2610 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2611 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2612 2613 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2614 if (ret) 2615 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2616 2617 return ret; 2618 } 2619 2620 int psp_execute_ip_fw_load(struct psp_context *psp, 2621 struct amdgpu_firmware_info *ucode) 2622 { 2623 int ret = 0; 2624 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2625 2626 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2627 if (!ret) { 2628 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2629 psp->fence_buf_mc_addr); 2630 } 2631 2632 release_psp_cmd_buf(psp); 2633 2634 return ret; 2635 } 2636 2637 static int psp_load_p2s_table(struct psp_context *psp) 2638 { 2639 int ret; 2640 struct amdgpu_device *adev = psp->adev; 2641 struct amdgpu_firmware_info *ucode = 2642 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2643 2644 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2645 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2646 return 0; 2647 2648 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2649 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2650 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2651 0x0036003C; 2652 if (psp->sos.fw_version < supp_vers) 2653 return 0; 2654 } 2655 2656 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2657 return 0; 2658 2659 ret = psp_execute_ip_fw_load(psp, ucode); 2660 2661 return ret; 2662 } 2663 2664 static int psp_load_smu_fw(struct psp_context *psp) 2665 { 2666 int ret; 2667 struct amdgpu_device *adev = psp->adev; 2668 struct amdgpu_firmware_info *ucode = 2669 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2670 struct amdgpu_ras *ras = psp->ras_context.ras; 2671 2672 /* 2673 * Skip SMU FW reloading in case of using BACO for runpm only, 2674 * as SMU is always alive. 2675 */ 2676 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2677 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2678 return 0; 2679 2680 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2681 return 0; 2682 2683 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2684 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2685 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2686 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2687 if (ret) 2688 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2689 } 2690 2691 ret = psp_execute_ip_fw_load(psp, ucode); 2692 2693 if (ret) 2694 dev_err(adev->dev, "PSP load smu failed!\n"); 2695 2696 return ret; 2697 } 2698 2699 static bool fw_load_skip_check(struct psp_context *psp, 2700 struct amdgpu_firmware_info *ucode) 2701 { 2702 if (!ucode->fw || !ucode->ucode_size) 2703 return true; 2704 2705 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2706 return true; 2707 2708 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2709 (psp_smu_reload_quirk(psp) || 2710 psp->autoload_supported || 2711 psp->pmfw_centralized_cstate_management)) 2712 return true; 2713 2714 if (amdgpu_sriov_vf(psp->adev) && 2715 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2716 return true; 2717 2718 if (psp->autoload_supported && 2719 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2720 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2721 /* skip mec JT when autoload is enabled */ 2722 return true; 2723 2724 return false; 2725 } 2726 2727 int psp_load_fw_list(struct psp_context *psp, 2728 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2729 { 2730 int ret = 0, i; 2731 struct amdgpu_firmware_info *ucode; 2732 2733 for (i = 0; i < ucode_count; ++i) { 2734 ucode = ucode_list[i]; 2735 psp_print_fw_hdr(psp, ucode); 2736 ret = psp_execute_ip_fw_load(psp, ucode); 2737 if (ret) 2738 return ret; 2739 } 2740 return ret; 2741 } 2742 2743 static int psp_load_non_psp_fw(struct psp_context *psp) 2744 { 2745 int i, ret; 2746 struct amdgpu_firmware_info *ucode; 2747 struct amdgpu_device *adev = psp->adev; 2748 2749 if (psp->autoload_supported && 2750 !psp->pmfw_centralized_cstate_management) { 2751 ret = psp_load_smu_fw(psp); 2752 if (ret) 2753 return ret; 2754 } 2755 2756 /* Load P2S table first if it's available */ 2757 psp_load_p2s_table(psp); 2758 2759 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2760 ucode = &adev->firmware.ucode[i]; 2761 2762 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2763 !fw_load_skip_check(psp, ucode)) { 2764 ret = psp_load_smu_fw(psp); 2765 if (ret) 2766 return ret; 2767 continue; 2768 } 2769 2770 if (fw_load_skip_check(psp, ucode)) 2771 continue; 2772 2773 if (psp->autoload_supported && 2774 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2775 IP_VERSION(11, 0, 7) || 2776 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2777 IP_VERSION(11, 0, 11) || 2778 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2779 IP_VERSION(11, 0, 12)) && 2780 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2781 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2782 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2783 /* PSP only receive one SDMA fw for sienna_cichlid, 2784 * as all four sdma fw are same 2785 */ 2786 continue; 2787 2788 psp_print_fw_hdr(psp, ucode); 2789 2790 ret = psp_execute_ip_fw_load(psp, ucode); 2791 if (ret) 2792 return ret; 2793 2794 /* Start rlc autoload after psp recieved all the gfx firmware */ 2795 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2796 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2797 ret = psp_rlc_autoload_start(psp); 2798 if (ret) { 2799 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2800 return ret; 2801 } 2802 } 2803 } 2804 2805 return 0; 2806 } 2807 2808 static int psp_load_fw(struct amdgpu_device *adev) 2809 { 2810 int ret; 2811 struct psp_context *psp = &adev->psp; 2812 2813 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2814 /* should not destroy ring, only stop */ 2815 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2816 } else { 2817 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2818 2819 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2820 if (ret) { 2821 dev_err(adev->dev, "PSP ring init failed!\n"); 2822 goto failed; 2823 } 2824 } 2825 2826 ret = psp_hw_start(psp); 2827 if (ret) 2828 goto failed; 2829 2830 ret = psp_load_non_psp_fw(psp); 2831 if (ret) 2832 goto failed1; 2833 2834 ret = psp_asd_initialize(psp); 2835 if (ret) { 2836 dev_err(adev->dev, "PSP load asd failed!\n"); 2837 goto failed1; 2838 } 2839 2840 ret = psp_rl_load(adev); 2841 if (ret) { 2842 dev_err(adev->dev, "PSP load RL failed!\n"); 2843 goto failed1; 2844 } 2845 2846 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2847 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2848 ret = psp_xgmi_initialize(psp, false, true); 2849 /* Warning the XGMI seesion initialize failure 2850 * Instead of stop driver initialization 2851 */ 2852 if (ret) 2853 dev_err(psp->adev->dev, 2854 "XGMI: Failed to initialize XGMI session\n"); 2855 } 2856 } 2857 2858 if (psp->ta_fw) { 2859 ret = psp_ras_initialize(psp); 2860 if (ret) 2861 dev_err(psp->adev->dev, 2862 "RAS: Failed to initialize RAS\n"); 2863 2864 ret = psp_hdcp_initialize(psp); 2865 if (ret) 2866 dev_err(psp->adev->dev, 2867 "HDCP: Failed to initialize HDCP\n"); 2868 2869 ret = psp_dtm_initialize(psp); 2870 if (ret) 2871 dev_err(psp->adev->dev, 2872 "DTM: Failed to initialize DTM\n"); 2873 2874 ret = psp_rap_initialize(psp); 2875 if (ret) 2876 dev_err(psp->adev->dev, 2877 "RAP: Failed to initialize RAP\n"); 2878 2879 ret = psp_securedisplay_initialize(psp); 2880 if (ret) 2881 dev_err(psp->adev->dev, 2882 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2883 } 2884 2885 return 0; 2886 2887 failed1: 2888 psp_free_shared_bufs(psp); 2889 failed: 2890 /* 2891 * all cleanup jobs (xgmi terminate, ras terminate, 2892 * ring destroy, cmd/fence/fw buffers destory, 2893 * psp->cmd destory) are delayed to psp_hw_fini 2894 */ 2895 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2896 return ret; 2897 } 2898 2899 static int psp_hw_init(void *handle) 2900 { 2901 int ret; 2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2903 2904 mutex_lock(&adev->firmware.mutex); 2905 /* 2906 * This sequence is just used on hw_init only once, no need on 2907 * resume. 2908 */ 2909 ret = amdgpu_ucode_init_bo(adev); 2910 if (ret) 2911 goto failed; 2912 2913 ret = psp_load_fw(adev); 2914 if (ret) { 2915 dev_err(adev->dev, "PSP firmware loading failed\n"); 2916 goto failed; 2917 } 2918 2919 mutex_unlock(&adev->firmware.mutex); 2920 return 0; 2921 2922 failed: 2923 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2924 mutex_unlock(&adev->firmware.mutex); 2925 return -EINVAL; 2926 } 2927 2928 static int psp_hw_fini(void *handle) 2929 { 2930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2931 struct psp_context *psp = &adev->psp; 2932 2933 if (psp->ta_fw) { 2934 psp_ras_terminate(psp); 2935 psp_securedisplay_terminate(psp); 2936 psp_rap_terminate(psp); 2937 psp_dtm_terminate(psp); 2938 psp_hdcp_terminate(psp); 2939 2940 if (adev->gmc.xgmi.num_physical_nodes > 1) 2941 psp_xgmi_terminate(psp); 2942 } 2943 2944 psp_asd_terminate(psp); 2945 psp_tmr_terminate(psp); 2946 2947 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2948 2949 return 0; 2950 } 2951 2952 static int psp_suspend(void *handle) 2953 { 2954 int ret = 0; 2955 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2956 struct psp_context *psp = &adev->psp; 2957 2958 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2959 psp->xgmi_context.context.initialized) { 2960 ret = psp_xgmi_terminate(psp); 2961 if (ret) { 2962 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 2963 goto out; 2964 } 2965 } 2966 2967 if (psp->ta_fw) { 2968 ret = psp_ras_terminate(psp); 2969 if (ret) { 2970 dev_err(adev->dev, "Failed to terminate ras ta\n"); 2971 goto out; 2972 } 2973 ret = psp_hdcp_terminate(psp); 2974 if (ret) { 2975 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 2976 goto out; 2977 } 2978 ret = psp_dtm_terminate(psp); 2979 if (ret) { 2980 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 2981 goto out; 2982 } 2983 ret = psp_rap_terminate(psp); 2984 if (ret) { 2985 dev_err(adev->dev, "Failed to terminate rap ta\n"); 2986 goto out; 2987 } 2988 ret = psp_securedisplay_terminate(psp); 2989 if (ret) { 2990 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 2991 goto out; 2992 } 2993 } 2994 2995 ret = psp_asd_terminate(psp); 2996 if (ret) { 2997 dev_err(adev->dev, "Failed to terminate asd\n"); 2998 goto out; 2999 } 3000 3001 ret = psp_tmr_terminate(psp); 3002 if (ret) { 3003 dev_err(adev->dev, "Failed to terminate tmr\n"); 3004 goto out; 3005 } 3006 3007 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3008 if (ret) 3009 dev_err(adev->dev, "PSP ring stop failed\n"); 3010 3011 out: 3012 return ret; 3013 } 3014 3015 static int psp_resume(void *handle) 3016 { 3017 int ret; 3018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3019 struct psp_context *psp = &adev->psp; 3020 3021 dev_info(adev->dev, "PSP is resuming...\n"); 3022 3023 if (psp->mem_train_ctx.enable_mem_training) { 3024 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3025 if (ret) { 3026 dev_err(adev->dev, "Failed to process memory training!\n"); 3027 return ret; 3028 } 3029 } 3030 3031 mutex_lock(&adev->firmware.mutex); 3032 3033 ret = psp_hw_start(psp); 3034 if (ret) 3035 goto failed; 3036 3037 ret = psp_load_non_psp_fw(psp); 3038 if (ret) 3039 goto failed; 3040 3041 ret = psp_asd_initialize(psp); 3042 if (ret) { 3043 dev_err(adev->dev, "PSP load asd failed!\n"); 3044 goto failed; 3045 } 3046 3047 ret = psp_rl_load(adev); 3048 if (ret) { 3049 dev_err(adev->dev, "PSP load RL failed!\n"); 3050 goto failed; 3051 } 3052 3053 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3054 ret = psp_xgmi_initialize(psp, false, true); 3055 /* Warning the XGMI seesion initialize failure 3056 * Instead of stop driver initialization 3057 */ 3058 if (ret) 3059 dev_err(psp->adev->dev, 3060 "XGMI: Failed to initialize XGMI session\n"); 3061 } 3062 3063 if (psp->ta_fw) { 3064 ret = psp_ras_initialize(psp); 3065 if (ret) 3066 dev_err(psp->adev->dev, 3067 "RAS: Failed to initialize RAS\n"); 3068 3069 ret = psp_hdcp_initialize(psp); 3070 if (ret) 3071 dev_err(psp->adev->dev, 3072 "HDCP: Failed to initialize HDCP\n"); 3073 3074 ret = psp_dtm_initialize(psp); 3075 if (ret) 3076 dev_err(psp->adev->dev, 3077 "DTM: Failed to initialize DTM\n"); 3078 3079 ret = psp_rap_initialize(psp); 3080 if (ret) 3081 dev_err(psp->adev->dev, 3082 "RAP: Failed to initialize RAP\n"); 3083 3084 ret = psp_securedisplay_initialize(psp); 3085 if (ret) 3086 dev_err(psp->adev->dev, 3087 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3088 } 3089 3090 mutex_unlock(&adev->firmware.mutex); 3091 3092 return 0; 3093 3094 failed: 3095 dev_err(adev->dev, "PSP resume failed\n"); 3096 mutex_unlock(&adev->firmware.mutex); 3097 return ret; 3098 } 3099 3100 int psp_gpu_reset(struct amdgpu_device *adev) 3101 { 3102 int ret; 3103 3104 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3105 return 0; 3106 3107 mutex_lock(&adev->psp.mutex); 3108 ret = psp_mode1_reset(&adev->psp); 3109 mutex_unlock(&adev->psp.mutex); 3110 3111 return ret; 3112 } 3113 3114 int psp_rlc_autoload_start(struct psp_context *psp) 3115 { 3116 int ret; 3117 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3118 3119 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3120 3121 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3122 psp->fence_buf_mc_addr); 3123 3124 release_psp_cmd_buf(psp); 3125 3126 return ret; 3127 } 3128 3129 int psp_ring_cmd_submit(struct psp_context *psp, 3130 uint64_t cmd_buf_mc_addr, 3131 uint64_t fence_mc_addr, 3132 int index) 3133 { 3134 unsigned int psp_write_ptr_reg = 0; 3135 struct psp_gfx_rb_frame *write_frame; 3136 struct psp_ring *ring = &psp->km_ring; 3137 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3138 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3139 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3140 struct amdgpu_device *adev = psp->adev; 3141 uint32_t ring_size_dw = ring->ring_size / 4; 3142 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3143 3144 /* KM (GPCOM) prepare write pointer */ 3145 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3146 3147 /* Update KM RB frame pointer to new frame */ 3148 /* write_frame ptr increments by size of rb_frame in bytes */ 3149 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3150 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3151 write_frame = ring_buffer_start; 3152 else 3153 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3154 /* Check invalid write_frame ptr address */ 3155 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3156 dev_err(adev->dev, 3157 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3158 ring_buffer_start, ring_buffer_end, write_frame); 3159 dev_err(adev->dev, 3160 "write_frame is pointing to address out of bounds\n"); 3161 return -EINVAL; 3162 } 3163 3164 /* Initialize KM RB frame */ 3165 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3166 3167 /* Update KM RB frame */ 3168 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3169 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3170 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3171 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3172 write_frame->fence_value = index; 3173 amdgpu_device_flush_hdp(adev, NULL); 3174 3175 /* Update the write Pointer in DWORDs */ 3176 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3177 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3178 return 0; 3179 } 3180 3181 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3182 { 3183 struct amdgpu_device *adev = psp->adev; 3184 const struct psp_firmware_header_v1_0 *asd_hdr; 3185 int err = 0; 3186 3187 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, "amdgpu/%s_asd.bin", chip_name); 3188 if (err) 3189 goto out; 3190 3191 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3192 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3193 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3194 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3195 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3196 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3197 return 0; 3198 out: 3199 amdgpu_ucode_release(&adev->psp.asd_fw); 3200 return err; 3201 } 3202 3203 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3204 { 3205 struct amdgpu_device *adev = psp->adev; 3206 const struct psp_firmware_header_v1_0 *toc_hdr; 3207 int err = 0; 3208 3209 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, "amdgpu/%s_toc.bin", chip_name); 3210 if (err) 3211 goto out; 3212 3213 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3214 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3215 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3216 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3217 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3218 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3219 return 0; 3220 out: 3221 amdgpu_ucode_release(&adev->psp.toc_fw); 3222 return err; 3223 } 3224 3225 static int parse_sos_bin_descriptor(struct psp_context *psp, 3226 const struct psp_fw_bin_desc *desc, 3227 const struct psp_firmware_header_v2_0 *sos_hdr) 3228 { 3229 uint8_t *ucode_start_addr = NULL; 3230 3231 if (!psp || !desc || !sos_hdr) 3232 return -EINVAL; 3233 3234 ucode_start_addr = (uint8_t *)sos_hdr + 3235 le32_to_cpu(desc->offset_bytes) + 3236 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3237 3238 switch (desc->fw_type) { 3239 case PSP_FW_TYPE_PSP_SOS: 3240 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3241 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3242 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3243 psp->sos.start_addr = ucode_start_addr; 3244 break; 3245 case PSP_FW_TYPE_PSP_SYS_DRV: 3246 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3247 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3248 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3249 psp->sys.start_addr = ucode_start_addr; 3250 break; 3251 case PSP_FW_TYPE_PSP_KDB: 3252 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3253 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3254 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3255 psp->kdb.start_addr = ucode_start_addr; 3256 break; 3257 case PSP_FW_TYPE_PSP_TOC: 3258 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3259 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3260 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3261 psp->toc.start_addr = ucode_start_addr; 3262 break; 3263 case PSP_FW_TYPE_PSP_SPL: 3264 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3265 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3266 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3267 psp->spl.start_addr = ucode_start_addr; 3268 break; 3269 case PSP_FW_TYPE_PSP_RL: 3270 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3271 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3272 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3273 psp->rl.start_addr = ucode_start_addr; 3274 break; 3275 case PSP_FW_TYPE_PSP_SOC_DRV: 3276 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3277 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3278 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3279 psp->soc_drv.start_addr = ucode_start_addr; 3280 break; 3281 case PSP_FW_TYPE_PSP_INTF_DRV: 3282 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3283 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3284 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3285 psp->intf_drv.start_addr = ucode_start_addr; 3286 break; 3287 case PSP_FW_TYPE_PSP_DBG_DRV: 3288 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3289 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3290 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3291 psp->dbg_drv.start_addr = ucode_start_addr; 3292 break; 3293 case PSP_FW_TYPE_PSP_RAS_DRV: 3294 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3295 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3296 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3297 psp->ras_drv.start_addr = ucode_start_addr; 3298 break; 3299 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3300 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3301 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3302 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3303 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3304 break; 3305 default: 3306 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3307 break; 3308 } 3309 3310 return 0; 3311 } 3312 3313 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3314 { 3315 const struct psp_firmware_header_v1_0 *sos_hdr; 3316 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3317 uint8_t *ucode_array_start_addr; 3318 3319 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3320 ucode_array_start_addr = (uint8_t *)sos_hdr + 3321 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3322 3323 if (adev->gmc.xgmi.connected_to_cpu || 3324 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3325 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3326 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3327 3328 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3329 adev->psp.sys.start_addr = ucode_array_start_addr; 3330 3331 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3332 adev->psp.sos.start_addr = ucode_array_start_addr + 3333 le32_to_cpu(sos_hdr->sos.offset_bytes); 3334 } else { 3335 /* Load alternate PSP SOS FW */ 3336 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3337 3338 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3339 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3340 3341 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3342 adev->psp.sys.start_addr = ucode_array_start_addr + 3343 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3344 3345 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3346 adev->psp.sos.start_addr = ucode_array_start_addr + 3347 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3348 } 3349 3350 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3351 dev_warn(adev->dev, "PSP SOS FW not available"); 3352 return -EINVAL; 3353 } 3354 3355 return 0; 3356 } 3357 3358 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3359 { 3360 struct amdgpu_device *adev = psp->adev; 3361 const struct psp_firmware_header_v1_0 *sos_hdr; 3362 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3363 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3364 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3365 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3366 int err = 0; 3367 uint8_t *ucode_array_start_addr; 3368 int fw_index = 0; 3369 3370 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name); 3371 if (err) 3372 goto out; 3373 3374 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3375 ucode_array_start_addr = (uint8_t *)sos_hdr + 3376 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3377 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3378 3379 switch (sos_hdr->header.header_version_major) { 3380 case 1: 3381 err = psp_init_sos_base_fw(adev); 3382 if (err) 3383 goto out; 3384 3385 if (sos_hdr->header.header_version_minor == 1) { 3386 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3387 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3388 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3389 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3390 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3391 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3392 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3393 } 3394 if (sos_hdr->header.header_version_minor == 2) { 3395 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3396 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3397 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3398 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3399 } 3400 if (sos_hdr->header.header_version_minor == 3) { 3401 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3402 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3403 adev->psp.toc.start_addr = ucode_array_start_addr + 3404 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3405 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3406 adev->psp.kdb.start_addr = ucode_array_start_addr + 3407 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3408 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3409 adev->psp.spl.start_addr = ucode_array_start_addr + 3410 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3411 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3412 adev->psp.rl.start_addr = ucode_array_start_addr + 3413 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3414 } 3415 break; 3416 case 2: 3417 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3418 3419 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3420 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3421 err = -EINVAL; 3422 goto out; 3423 } 3424 3425 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3426 err = parse_sos_bin_descriptor(psp, 3427 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3428 sos_hdr_v2_0); 3429 if (err) 3430 goto out; 3431 } 3432 break; 3433 default: 3434 dev_err(adev->dev, 3435 "unsupported psp sos firmware\n"); 3436 err = -EINVAL; 3437 goto out; 3438 } 3439 3440 return 0; 3441 out: 3442 amdgpu_ucode_release(&adev->psp.sos_fw); 3443 3444 return err; 3445 } 3446 3447 static int parse_ta_bin_descriptor(struct psp_context *psp, 3448 const struct psp_fw_bin_desc *desc, 3449 const struct ta_firmware_header_v2_0 *ta_hdr) 3450 { 3451 uint8_t *ucode_start_addr = NULL; 3452 3453 if (!psp || !desc || !ta_hdr) 3454 return -EINVAL; 3455 3456 ucode_start_addr = (uint8_t *)ta_hdr + 3457 le32_to_cpu(desc->offset_bytes) + 3458 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3459 3460 switch (desc->fw_type) { 3461 case TA_FW_TYPE_PSP_ASD: 3462 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3463 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3464 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3465 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3466 break; 3467 case TA_FW_TYPE_PSP_XGMI: 3468 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3469 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3470 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3471 break; 3472 case TA_FW_TYPE_PSP_RAS: 3473 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3474 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3475 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3476 break; 3477 case TA_FW_TYPE_PSP_HDCP: 3478 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3479 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3480 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3481 break; 3482 case TA_FW_TYPE_PSP_DTM: 3483 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3484 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3485 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3486 break; 3487 case TA_FW_TYPE_PSP_RAP: 3488 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3489 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3490 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3491 break; 3492 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3493 psp->securedisplay_context.context.bin_desc.fw_version = 3494 le32_to_cpu(desc->fw_version); 3495 psp->securedisplay_context.context.bin_desc.size_bytes = 3496 le32_to_cpu(desc->size_bytes); 3497 psp->securedisplay_context.context.bin_desc.start_addr = 3498 ucode_start_addr; 3499 break; 3500 default: 3501 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3502 break; 3503 } 3504 3505 return 0; 3506 } 3507 3508 static int parse_ta_v1_microcode(struct psp_context *psp) 3509 { 3510 const struct ta_firmware_header_v1_0 *ta_hdr; 3511 struct amdgpu_device *adev = psp->adev; 3512 3513 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3514 3515 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3516 return -EINVAL; 3517 3518 adev->psp.xgmi_context.context.bin_desc.fw_version = 3519 le32_to_cpu(ta_hdr->xgmi.fw_version); 3520 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3521 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3522 adev->psp.xgmi_context.context.bin_desc.start_addr = 3523 (uint8_t *)ta_hdr + 3524 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3525 3526 adev->psp.ras_context.context.bin_desc.fw_version = 3527 le32_to_cpu(ta_hdr->ras.fw_version); 3528 adev->psp.ras_context.context.bin_desc.size_bytes = 3529 le32_to_cpu(ta_hdr->ras.size_bytes); 3530 adev->psp.ras_context.context.bin_desc.start_addr = 3531 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3532 le32_to_cpu(ta_hdr->ras.offset_bytes); 3533 3534 adev->psp.hdcp_context.context.bin_desc.fw_version = 3535 le32_to_cpu(ta_hdr->hdcp.fw_version); 3536 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3537 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3538 adev->psp.hdcp_context.context.bin_desc.start_addr = 3539 (uint8_t *)ta_hdr + 3540 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3541 3542 adev->psp.dtm_context.context.bin_desc.fw_version = 3543 le32_to_cpu(ta_hdr->dtm.fw_version); 3544 adev->psp.dtm_context.context.bin_desc.size_bytes = 3545 le32_to_cpu(ta_hdr->dtm.size_bytes); 3546 adev->psp.dtm_context.context.bin_desc.start_addr = 3547 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3548 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3549 3550 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3551 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3552 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3553 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3554 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3555 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3556 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3557 3558 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3559 3560 return 0; 3561 } 3562 3563 static int parse_ta_v2_microcode(struct psp_context *psp) 3564 { 3565 const struct ta_firmware_header_v2_0 *ta_hdr; 3566 struct amdgpu_device *adev = psp->adev; 3567 int err = 0; 3568 int ta_index = 0; 3569 3570 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3571 3572 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3573 return -EINVAL; 3574 3575 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3576 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3577 return -EINVAL; 3578 } 3579 3580 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3581 err = parse_ta_bin_descriptor(psp, 3582 &ta_hdr->ta_fw_bin[ta_index], 3583 ta_hdr); 3584 if (err) 3585 return err; 3586 } 3587 3588 return 0; 3589 } 3590 3591 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3592 { 3593 const struct common_firmware_header *hdr; 3594 struct amdgpu_device *adev = psp->adev; 3595 int err; 3596 3597 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, "amdgpu/%s_ta.bin", chip_name); 3598 if (err) 3599 return err; 3600 3601 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3602 switch (le16_to_cpu(hdr->header_version_major)) { 3603 case 1: 3604 err = parse_ta_v1_microcode(psp); 3605 break; 3606 case 2: 3607 err = parse_ta_v2_microcode(psp); 3608 break; 3609 default: 3610 dev_err(adev->dev, "unsupported TA header version\n"); 3611 err = -EINVAL; 3612 } 3613 3614 if (err) 3615 amdgpu_ucode_release(&adev->psp.ta_fw); 3616 3617 return err; 3618 } 3619 3620 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3621 { 3622 struct amdgpu_device *adev = psp->adev; 3623 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3624 struct amdgpu_firmware_info *info = NULL; 3625 int err = 0; 3626 3627 if (!amdgpu_sriov_vf(adev)) { 3628 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3629 return -EINVAL; 3630 } 3631 3632 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, "amdgpu/%s_cap.bin", chip_name); 3633 if (err) { 3634 if (err == -ENODEV) { 3635 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3636 err = 0; 3637 goto out; 3638 } 3639 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3640 } 3641 3642 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3643 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3644 info->fw = adev->psp.cap_fw; 3645 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3646 adev->psp.cap_fw->data; 3647 adev->firmware.fw_size += ALIGN( 3648 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3649 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3650 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3651 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3652 3653 return 0; 3654 3655 out: 3656 amdgpu_ucode_release(&adev->psp.cap_fw); 3657 return err; 3658 } 3659 3660 static int psp_set_clockgating_state(void *handle, 3661 enum amd_clockgating_state state) 3662 { 3663 return 0; 3664 } 3665 3666 static int psp_set_powergating_state(void *handle, 3667 enum amd_powergating_state state) 3668 { 3669 return 0; 3670 } 3671 3672 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3673 struct device_attribute *attr, 3674 char *buf) 3675 { 3676 struct drm_device *ddev = dev_get_drvdata(dev); 3677 struct amdgpu_device *adev = drm_to_adev(ddev); 3678 uint32_t fw_ver; 3679 int ret; 3680 3681 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3682 dev_info(adev->dev, "PSP block is not ready yet\n."); 3683 return -EBUSY; 3684 } 3685 3686 mutex_lock(&adev->psp.mutex); 3687 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3688 mutex_unlock(&adev->psp.mutex); 3689 3690 if (ret) { 3691 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3692 return ret; 3693 } 3694 3695 return sysfs_emit(buf, "%x\n", fw_ver); 3696 } 3697 3698 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3699 struct device_attribute *attr, 3700 const char *buf, 3701 size_t count) 3702 { 3703 struct drm_device *ddev = dev_get_drvdata(dev); 3704 struct amdgpu_device *adev = drm_to_adev(ddev); 3705 int ret, idx; 3706 const struct firmware *usbc_pd_fw; 3707 struct amdgpu_bo *fw_buf_bo = NULL; 3708 uint64_t fw_pri_mc_addr; 3709 void *fw_pri_cpu_addr; 3710 3711 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3712 dev_err(adev->dev, "PSP block is not ready yet."); 3713 return -EBUSY; 3714 } 3715 3716 if (!drm_dev_enter(ddev, &idx)) 3717 return -ENODEV; 3718 3719 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, "amdgpu/%s", buf); 3720 if (ret) 3721 goto fail; 3722 3723 /* LFB address which is aligned to 1MB boundary per PSP request */ 3724 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3725 AMDGPU_GEM_DOMAIN_VRAM | 3726 AMDGPU_GEM_DOMAIN_GTT, 3727 &fw_buf_bo, &fw_pri_mc_addr, 3728 &fw_pri_cpu_addr); 3729 if (ret) 3730 goto rel_buf; 3731 3732 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3733 3734 mutex_lock(&adev->psp.mutex); 3735 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3736 mutex_unlock(&adev->psp.mutex); 3737 3738 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3739 3740 rel_buf: 3741 amdgpu_ucode_release(&usbc_pd_fw); 3742 fail: 3743 if (ret) { 3744 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3745 count = ret; 3746 } 3747 3748 drm_dev_exit(idx); 3749 return count; 3750 } 3751 3752 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3753 { 3754 int idx; 3755 3756 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3757 return; 3758 3759 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3760 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3761 3762 drm_dev_exit(idx); 3763 } 3764 3765 /** 3766 * DOC: usbc_pd_fw 3767 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3768 * this file will trigger the update process. 3769 */ 3770 static DEVICE_ATTR(usbc_pd_fw, 0644, 3771 psp_usbc_pd_fw_sysfs_read, 3772 psp_usbc_pd_fw_sysfs_write); 3773 3774 int is_psp_fw_valid(struct psp_bin_desc bin) 3775 { 3776 return bin.size_bytes; 3777 } 3778 3779 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3780 struct bin_attribute *bin_attr, 3781 char *buffer, loff_t pos, size_t count) 3782 { 3783 struct device *dev = kobj_to_dev(kobj); 3784 struct drm_device *ddev = dev_get_drvdata(dev); 3785 struct amdgpu_device *adev = drm_to_adev(ddev); 3786 3787 adev->psp.vbflash_done = false; 3788 3789 /* Safeguard against memory drain */ 3790 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3791 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 3792 kvfree(adev->psp.vbflash_tmp_buf); 3793 adev->psp.vbflash_tmp_buf = NULL; 3794 adev->psp.vbflash_image_size = 0; 3795 return -ENOMEM; 3796 } 3797 3798 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3799 if (!adev->psp.vbflash_tmp_buf) { 3800 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3801 if (!adev->psp.vbflash_tmp_buf) 3802 return -ENOMEM; 3803 } 3804 3805 mutex_lock(&adev->psp.mutex); 3806 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3807 adev->psp.vbflash_image_size += count; 3808 mutex_unlock(&adev->psp.mutex); 3809 3810 dev_dbg(adev->dev, "IFWI staged for update\n"); 3811 3812 return count; 3813 } 3814 3815 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3816 struct bin_attribute *bin_attr, char *buffer, 3817 loff_t pos, size_t count) 3818 { 3819 struct device *dev = kobj_to_dev(kobj); 3820 struct drm_device *ddev = dev_get_drvdata(dev); 3821 struct amdgpu_device *adev = drm_to_adev(ddev); 3822 struct amdgpu_bo *fw_buf_bo = NULL; 3823 uint64_t fw_pri_mc_addr; 3824 void *fw_pri_cpu_addr; 3825 int ret; 3826 3827 if (adev->psp.vbflash_image_size == 0) 3828 return -EINVAL; 3829 3830 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 3831 3832 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3833 AMDGPU_GPU_PAGE_SIZE, 3834 AMDGPU_GEM_DOMAIN_VRAM, 3835 &fw_buf_bo, 3836 &fw_pri_mc_addr, 3837 &fw_pri_cpu_addr); 3838 if (ret) 3839 goto rel_buf; 3840 3841 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3842 3843 mutex_lock(&adev->psp.mutex); 3844 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3845 mutex_unlock(&adev->psp.mutex); 3846 3847 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3848 3849 rel_buf: 3850 kvfree(adev->psp.vbflash_tmp_buf); 3851 adev->psp.vbflash_tmp_buf = NULL; 3852 adev->psp.vbflash_image_size = 0; 3853 3854 if (ret) { 3855 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 3856 return ret; 3857 } 3858 3859 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 3860 return 0; 3861 } 3862 3863 /** 3864 * DOC: psp_vbflash 3865 * Writing to this file will stage an IFWI for update. Reading from this file 3866 * will trigger the update process. 3867 */ 3868 static struct bin_attribute psp_vbflash_bin_attr = { 3869 .attr = {.name = "psp_vbflash", .mode = 0660}, 3870 .size = 0, 3871 .write = amdgpu_psp_vbflash_write, 3872 .read = amdgpu_psp_vbflash_read, 3873 }; 3874 3875 /** 3876 * DOC: psp_vbflash_status 3877 * The status of the flash process. 3878 * 0: IFWI flash not complete. 3879 * 1: IFWI flash complete. 3880 */ 3881 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3882 struct device_attribute *attr, 3883 char *buf) 3884 { 3885 struct drm_device *ddev = dev_get_drvdata(dev); 3886 struct amdgpu_device *adev = drm_to_adev(ddev); 3887 uint32_t vbflash_status; 3888 3889 vbflash_status = psp_vbflash_status(&adev->psp); 3890 if (!adev->psp.vbflash_done) 3891 vbflash_status = 0; 3892 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3893 vbflash_status = 1; 3894 3895 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3896 } 3897 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3898 3899 static struct bin_attribute *bin_flash_attrs[] = { 3900 &psp_vbflash_bin_attr, 3901 NULL 3902 }; 3903 3904 static struct attribute *flash_attrs[] = { 3905 &dev_attr_psp_vbflash_status.attr, 3906 &dev_attr_usbc_pd_fw.attr, 3907 NULL 3908 }; 3909 3910 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3911 { 3912 struct device *dev = kobj_to_dev(kobj); 3913 struct drm_device *ddev = dev_get_drvdata(dev); 3914 struct amdgpu_device *adev = drm_to_adev(ddev); 3915 3916 if (attr == &dev_attr_usbc_pd_fw.attr) 3917 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3918 3919 return adev->psp.sup_ifwi_up ? 0440 : 0; 3920 } 3921 3922 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3923 struct bin_attribute *attr, 3924 int idx) 3925 { 3926 struct device *dev = kobj_to_dev(kobj); 3927 struct drm_device *ddev = dev_get_drvdata(dev); 3928 struct amdgpu_device *adev = drm_to_adev(ddev); 3929 3930 return adev->psp.sup_ifwi_up ? 0660 : 0; 3931 } 3932 3933 const struct attribute_group amdgpu_flash_attr_group = { 3934 .attrs = flash_attrs, 3935 .bin_attrs = bin_flash_attrs, 3936 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3937 .is_visible = amdgpu_flash_attr_is_visible, 3938 }; 3939 3940 const struct amd_ip_funcs psp_ip_funcs = { 3941 .name = "psp", 3942 .early_init = psp_early_init, 3943 .late_init = NULL, 3944 .sw_init = psp_sw_init, 3945 .sw_fini = psp_sw_fini, 3946 .hw_init = psp_hw_init, 3947 .hw_fini = psp_hw_fini, 3948 .suspend = psp_suspend, 3949 .resume = psp_resume, 3950 .is_idle = NULL, 3951 .check_soft_reset = NULL, 3952 .wait_for_idle = NULL, 3953 .soft_reset = NULL, 3954 .set_clockgating_state = psp_set_clockgating_state, 3955 .set_powergating_state = psp_set_powergating_state, 3956 }; 3957 3958 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3959 .type = AMD_IP_BLOCK_TYPE_PSP, 3960 .major = 3, 3961 .minor = 1, 3962 .rev = 0, 3963 .funcs = &psp_ip_funcs, 3964 }; 3965 3966 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3967 .type = AMD_IP_BLOCK_TYPE_PSP, 3968 .major = 10, 3969 .minor = 0, 3970 .rev = 0, 3971 .funcs = &psp_ip_funcs, 3972 }; 3973 3974 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3975 .type = AMD_IP_BLOCK_TYPE_PSP, 3976 .major = 11, 3977 .minor = 0, 3978 .rev = 0, 3979 .funcs = &psp_ip_funcs, 3980 }; 3981 3982 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3983 .type = AMD_IP_BLOCK_TYPE_PSP, 3984 .major = 11, 3985 .minor = 0, 3986 .rev = 8, 3987 .funcs = &psp_ip_funcs, 3988 }; 3989 3990 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 3991 .type = AMD_IP_BLOCK_TYPE_PSP, 3992 .major = 12, 3993 .minor = 0, 3994 .rev = 0, 3995 .funcs = &psp_ip_funcs, 3996 }; 3997 3998 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3999 .type = AMD_IP_BLOCK_TYPE_PSP, 4000 .major = 13, 4001 .minor = 0, 4002 .rev = 0, 4003 .funcs = &psp_ip_funcs, 4004 }; 4005 4006 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4007 .type = AMD_IP_BLOCK_TYPE_PSP, 4008 .major = 13, 4009 .minor = 0, 4010 .rev = 4, 4011 .funcs = &psp_ip_funcs, 4012 }; 4013 4014 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4015 .type = AMD_IP_BLOCK_TYPE_PSP, 4016 .major = 14, 4017 .minor = 0, 4018 .rev = 0, 4019 .funcs = &psp_ip_funcs, 4020 }; 4021