1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 case IP_VERSION(15, 0, 9): 279 psp_v15_0_0_set_psp_funcs(psp); 280 psp->boot_time_tmr = false; 281 break; 282 case IP_VERSION(15, 0, 8): 283 psp_v15_0_8_set_psp_funcs(psp); 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 psp->adev = adev; 290 291 adev->psp_timeout = 20000; 292 293 psp_check_pmfw_centralized_cstate_management(psp); 294 295 if (amdgpu_sriov_vf(adev)) 296 return psp_init_sriov_microcode(psp); 297 else 298 return psp_init_microcode(psp); 299 } 300 301 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 302 { 303 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 304 &mem_ctx->shared_buf); 305 mem_ctx->shared_bo = NULL; 306 } 307 308 static void psp_free_shared_bufs(struct psp_context *psp) 309 { 310 void *tmr_buf; 311 void **pptr; 312 313 /* free TMR memory buffer */ 314 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 315 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 316 psp->tmr_bo = NULL; 317 318 /* free xgmi shared memory */ 319 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 320 321 /* free ras shared memory */ 322 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 323 324 /* free hdcp shared memory */ 325 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 326 327 /* free dtm shared memory */ 328 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 329 330 /* free rap shared memory */ 331 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 332 333 /* free securedisplay shared memory */ 334 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 335 336 337 } 338 339 static void psp_memory_training_fini(struct psp_context *psp) 340 { 341 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 342 343 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 344 kfree(ctx->sys_cache); 345 ctx->sys_cache = NULL; 346 } 347 348 static int psp_memory_training_init(struct psp_context *psp) 349 { 350 int ret; 351 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 352 353 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 354 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 355 return 0; 356 } 357 358 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 359 if (ctx->sys_cache == NULL) { 360 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 361 ret = -ENOMEM; 362 goto Err_out; 363 } 364 365 dev_dbg(psp->adev->dev, 366 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 367 ctx->train_data_size, 368 ctx->p2c_train_data_offset, 369 ctx->c2p_train_data_offset); 370 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 371 return 0; 372 373 Err_out: 374 psp_memory_training_fini(psp); 375 return ret; 376 } 377 378 /* 379 * Helper funciton to query psp runtime database entry 380 * 381 * @adev: amdgpu_device pointer 382 * @entry_type: the type of psp runtime database entry 383 * @db_entry: runtime database entry pointer 384 * 385 * Return false if runtime database doesn't exit or entry is invalid 386 * or true if the specific database entry is found, and copy to @db_entry 387 */ 388 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 389 enum psp_runtime_entry_type entry_type, 390 void *db_entry) 391 { 392 uint64_t db_header_pos, db_dir_pos; 393 struct psp_runtime_data_header db_header = {0}; 394 struct psp_runtime_data_directory db_dir = {0}; 395 bool ret = false; 396 int i; 397 398 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 399 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 401 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 402 return false; 403 404 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 405 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 406 407 /* read runtime db header from vram */ 408 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 409 sizeof(struct psp_runtime_data_header), false); 410 411 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 412 /* runtime db doesn't exist, exit */ 413 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 414 return false; 415 } 416 417 /* read runtime database entry from vram */ 418 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 419 sizeof(struct psp_runtime_data_directory), false); 420 421 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 422 /* invalid db entry count, exit */ 423 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 424 return false; 425 } 426 427 /* look up for requested entry type */ 428 for (i = 0; i < db_dir.entry_count && !ret; i++) { 429 if (db_dir.entry_list[i].entry_type == entry_type) { 430 switch (entry_type) { 431 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 432 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 433 /* invalid db entry size */ 434 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 435 return false; 436 } 437 /* read runtime database entry */ 438 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 439 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 440 ret = true; 441 break; 442 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 443 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 444 /* invalid db entry size */ 445 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 446 return false; 447 } 448 /* read runtime database entry */ 449 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 450 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 451 ret = true; 452 break; 453 default: 454 ret = false; 455 break; 456 } 457 } 458 } 459 460 return ret; 461 } 462 463 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 464 { 465 struct amdgpu_device *adev = ip_block->adev; 466 struct psp_context *psp = &adev->psp; 467 int ret; 468 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 469 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 470 struct psp_runtime_scpm_entry scpm_entry; 471 472 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 473 if (!psp->cmd) { 474 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 475 return -ENOMEM; 476 } 477 478 adev->psp.xgmi_context.supports_extended_data = 479 !adev->gmc.xgmi.connected_to_cpu && 480 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 481 482 memset(&scpm_entry, 0, sizeof(scpm_entry)); 483 if ((psp_get_runtime_db_entry(adev, 484 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 485 &scpm_entry)) && 486 (scpm_entry.scpm_status != SCPM_DISABLE)) { 487 adev->scpm_enabled = true; 488 adev->scpm_status = scpm_entry.scpm_status; 489 } else { 490 adev->scpm_enabled = false; 491 adev->scpm_status = SCPM_DISABLE; 492 } 493 494 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 495 496 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 497 if (psp_get_runtime_db_entry(adev, 498 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 499 &boot_cfg_entry)) { 500 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 501 if ((psp->boot_cfg_bitmask) & 502 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 503 /* If psp runtime database exists, then 504 * only enable two stage memory training 505 * when TWO_STAGE_DRAM_TRAINING bit is set 506 * in runtime database 507 */ 508 mem_training_ctx->enable_mem_training = true; 509 } 510 511 } else { 512 /* If psp runtime database doesn't exist or is 513 * invalid, force enable two stage memory training 514 */ 515 mem_training_ctx->enable_mem_training = true; 516 } 517 518 if (mem_training_ctx->enable_mem_training) { 519 ret = psp_memory_training_init(psp); 520 if (ret) { 521 dev_err(adev->dev, "Failed to initialize memory training!\n"); 522 return ret; 523 } 524 525 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 526 if (ret) { 527 dev_err(adev->dev, "Failed to process memory training!\n"); 528 return ret; 529 } 530 } 531 532 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 533 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 534 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 535 &psp->fw_pri_bo, 536 &psp->fw_pri_mc_addr, 537 &psp->fw_pri_buf); 538 if (ret) 539 return ret; 540 541 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 542 AMDGPU_GEM_DOMAIN_VRAM | 543 AMDGPU_GEM_DOMAIN_GTT, 544 &psp->fence_buf_bo, 545 &psp->fence_buf_mc_addr, 546 &psp->fence_buf); 547 if (ret) 548 goto failed1; 549 550 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 551 AMDGPU_GEM_DOMAIN_VRAM | 552 AMDGPU_GEM_DOMAIN_GTT, 553 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 554 (void **)&psp->cmd_buf_mem); 555 if (ret) 556 goto failed2; 557 558 return 0; 559 560 failed2: 561 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 562 &psp->fence_buf_mc_addr, &psp->fence_buf); 563 failed1: 564 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 565 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 566 return ret; 567 } 568 569 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 570 { 571 struct amdgpu_device *adev = ip_block->adev; 572 struct psp_context *psp = &adev->psp; 573 574 psp_memory_training_fini(psp); 575 576 amdgpu_ucode_release(&psp->sos_fw); 577 amdgpu_ucode_release(&psp->asd_fw); 578 amdgpu_ucode_release(&psp->ta_fw); 579 amdgpu_ucode_release(&psp->cap_fw); 580 amdgpu_ucode_release(&psp->toc_fw); 581 582 kfree(psp->cmd); 583 psp->cmd = NULL; 584 585 psp_free_shared_bufs(psp); 586 587 if (psp->km_ring.ring_mem) 588 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 589 &psp->km_ring.ring_mem_mc_addr, 590 (void **)&psp->km_ring.ring_mem); 591 592 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 593 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 594 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 595 &psp->fence_buf_mc_addr, &psp->fence_buf); 596 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 597 (void **)&psp->cmd_buf_mem); 598 599 return 0; 600 } 601 602 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 603 uint32_t mask, uint32_t flags) 604 { 605 bool check_changed = flags & PSP_WAITREG_CHANGED; 606 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 607 uint32_t val; 608 int i; 609 struct amdgpu_device *adev = psp->adev; 610 611 if (psp->adev->no_hw_access) 612 return 0; 613 614 for (i = 0; i < adev->usec_timeout; i++) { 615 val = RREG32(reg_index); 616 if (check_changed) { 617 if (val != reg_val) 618 return 0; 619 } else { 620 if ((val & mask) == reg_val) 621 return 0; 622 } 623 udelay(1); 624 } 625 626 if (verbose) 627 dev_err(adev->dev, 628 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 629 reg_index, mask, val, reg_val); 630 631 return -ETIME; 632 } 633 634 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 635 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 636 { 637 uint32_t val; 638 int i; 639 struct amdgpu_device *adev = psp->adev; 640 641 if (psp->adev->no_hw_access) 642 return 0; 643 644 for (i = 0; i < msec_timeout; i++) { 645 val = RREG32(reg_index); 646 if ((val & mask) == reg_val) 647 return 0; 648 msleep(1); 649 } 650 651 return -ETIME; 652 } 653 654 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 655 { 656 switch (cmd_id) { 657 case GFX_CMD_ID_LOAD_TA: 658 return "LOAD_TA"; 659 case GFX_CMD_ID_UNLOAD_TA: 660 return "UNLOAD_TA"; 661 case GFX_CMD_ID_INVOKE_CMD: 662 return "INVOKE_CMD"; 663 case GFX_CMD_ID_LOAD_ASD: 664 return "LOAD_ASD"; 665 case GFX_CMD_ID_SETUP_TMR: 666 return "SETUP_TMR"; 667 case GFX_CMD_ID_LOAD_IP_FW: 668 return "LOAD_IP_FW"; 669 case GFX_CMD_ID_DESTROY_TMR: 670 return "DESTROY_TMR"; 671 case GFX_CMD_ID_SAVE_RESTORE: 672 return "SAVE_RESTORE_IP_FW"; 673 case GFX_CMD_ID_SETUP_VMR: 674 return "SETUP_VMR"; 675 case GFX_CMD_ID_DESTROY_VMR: 676 return "DESTROY_VMR"; 677 case GFX_CMD_ID_PROG_REG: 678 return "PROG_REG"; 679 case GFX_CMD_ID_GET_FW_ATTESTATION: 680 return "GET_FW_ATTESTATION"; 681 case GFX_CMD_ID_LOAD_TOC: 682 return "ID_LOAD_TOC"; 683 case GFX_CMD_ID_AUTOLOAD_RLC: 684 return "AUTOLOAD_RLC"; 685 case GFX_CMD_ID_BOOT_CFG: 686 return "BOOT_CFG"; 687 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 688 return "CONFIG_SQ_PERFMON"; 689 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 690 return "FB_FW_RESERV_ADDR"; 691 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 692 return "FB_FW_RESERV_EXT_ADDR"; 693 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 694 return "SPATIAL_PARTITION"; 695 case GFX_CMD_ID_FB_NPS_MODE: 696 return "NPS_MODE_CHANGE"; 697 case GFX_CMD_ID_PERF_HW: 698 return "PERF MONITORING HW"; 699 default: 700 return "UNKNOWN CMD"; 701 } 702 } 703 704 static bool psp_err_warn(struct psp_context *psp) 705 { 706 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 707 708 /* This response indicates reg list is already loaded */ 709 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 710 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 711 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 712 cmd->resp.status == TEE_ERROR_CANCEL) 713 return false; 714 715 return true; 716 } 717 718 static int 719 psp_cmd_submit_buf(struct psp_context *psp, 720 struct amdgpu_firmware_info *ucode, 721 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 722 { 723 int ret; 724 int index; 725 int timeout = psp->adev->psp_timeout; 726 bool ras_intr = false; 727 bool skip_unsupport = false; 728 729 if (psp->adev->no_hw_access) 730 return 0; 731 732 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 733 734 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 735 736 index = atomic_inc_return(&psp->fence_value); 737 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 738 if (ret) { 739 atomic_dec(&psp->fence_value); 740 goto exit; 741 } 742 743 amdgpu_device_invalidate_hdp(psp->adev, NULL); 744 while (*((unsigned int *)psp->fence_buf) != index) { 745 if (--timeout == 0) 746 break; 747 /* 748 * Shouldn't wait for timeout when err_event_athub occurs, 749 * because gpu reset thread triggered and lock resource should 750 * be released for psp resume sequence. 751 */ 752 ras_intr = amdgpu_ras_intr_triggered(); 753 if (ras_intr) 754 break; 755 usleep_range(60, 100); 756 amdgpu_device_invalidate_hdp(psp->adev, NULL); 757 } 758 759 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 760 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 761 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 762 763 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 764 765 /* In some cases, psp response status is not 0 even there is no 766 * problem while the command is submitted. Some version of PSP FW 767 * doesn't write 0 to that field. 768 * So here we would like to only print a warning instead of an error 769 * during psp initialization to avoid breaking hw_init and it doesn't 770 * return -EINVAL. 771 */ 772 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 773 if (ucode) 774 dev_warn(psp->adev->dev, 775 "failed to load ucode %s(0x%X) ", 776 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 777 if (psp_err_warn(psp)) 778 dev_warn( 779 psp->adev->dev, 780 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 781 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 782 psp->cmd_buf_mem->cmd_id, 783 psp->cmd_buf_mem->resp.status); 784 /* If any firmware (including CAP) load fails under SRIOV, it should 785 * return failure to stop the VF from initializing. 786 * Also return failure in case of timeout 787 */ 788 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 789 ret = -EINVAL; 790 goto exit; 791 } 792 } 793 794 if (ucode) { 795 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 796 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 797 } 798 799 exit: 800 return ret; 801 } 802 803 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 804 { 805 struct psp_gfx_cmd_resp *cmd = psp->cmd; 806 807 mutex_lock(&psp->mutex); 808 809 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 810 811 return cmd; 812 } 813 814 static void release_psp_cmd_buf(struct psp_context *psp) 815 { 816 mutex_unlock(&psp->mutex); 817 } 818 819 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 820 struct psp_gfx_cmd_resp *cmd, 821 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 822 { 823 struct amdgpu_device *adev = psp->adev; 824 uint32_t size = 0; 825 uint64_t tmr_pa = 0; 826 827 if (tmr_bo) { 828 size = amdgpu_bo_size(tmr_bo); 829 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 830 } 831 832 if (amdgpu_sriov_vf(psp->adev)) 833 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 834 else 835 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 836 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 837 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 838 cmd->cmd.cmd_setup_tmr.buf_size = size; 839 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 840 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 841 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 842 } 843 844 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 845 uint64_t pri_buf_mc, uint32_t size) 846 { 847 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 848 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 849 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 850 cmd->cmd.cmd_load_toc.toc_size = size; 851 } 852 853 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 854 static int psp_load_toc(struct psp_context *psp, 855 uint32_t *tmr_size) 856 { 857 int ret; 858 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 859 860 /* Copy toc to psp firmware private buffer */ 861 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 862 if (ret) { 863 release_psp_cmd_buf(psp); 864 return ret; 865 } 866 867 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 868 869 ret = psp_cmd_submit_buf(psp, NULL, cmd, 870 psp->fence_buf_mc_addr); 871 if (!ret) 872 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 873 874 release_psp_cmd_buf(psp); 875 876 return ret; 877 } 878 879 /* Set up Trusted Memory Region */ 880 static int psp_tmr_init(struct psp_context *psp) 881 { 882 int ret = 0; 883 int tmr_size; 884 void *tmr_buf; 885 void **pptr; 886 887 /* 888 * According to HW engineer, they prefer the TMR address be "naturally 889 * aligned" , e.g. the start address be an integer divide of TMR size. 890 * 891 * Note: this memory need be reserved till the driver 892 * uninitializes. 893 */ 894 tmr_size = PSP_TMR_SIZE(psp->adev); 895 896 /* For ASICs support RLC autoload, psp will parse the toc 897 * and calculate the total size of TMR needed 898 */ 899 if (!amdgpu_sriov_vf(psp->adev) && 900 psp->toc.start_addr && 901 psp->toc.size_bytes && 902 psp->fw_pri_buf) { 903 ret = psp_load_toc(psp, &tmr_size); 904 if (ret) { 905 dev_err(psp->adev->dev, "Failed to load toc\n"); 906 return ret; 907 } 908 } 909 910 if (!psp->tmr_bo && !psp->boot_time_tmr) { 911 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 912 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 913 PSP_TMR_ALIGNMENT, 914 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 915 &psp->tmr_bo, &psp->tmr_mc_addr, 916 pptr); 917 } 918 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 919 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 920 921 return ret; 922 } 923 924 static bool psp_skip_tmr(struct psp_context *psp) 925 { 926 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 927 928 if (amdgpu_sriov_vf(psp->adev)) 929 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 930 else 931 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 932 } 933 934 static int psp_tmr_load(struct psp_context *psp) 935 { 936 int ret; 937 struct psp_gfx_cmd_resp *cmd; 938 939 if (psp_skip_tmr(psp)) 940 return 0; 941 942 cmd = acquire_psp_cmd_buf(psp); 943 944 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 945 if (psp->tmr_bo) 946 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 947 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 948 949 ret = psp_cmd_submit_buf(psp, NULL, cmd, 950 psp->fence_buf_mc_addr); 951 952 release_psp_cmd_buf(psp); 953 954 return ret; 955 } 956 957 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 958 struct psp_gfx_cmd_resp *cmd) 959 { 960 if (amdgpu_sriov_vf(psp->adev)) 961 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 962 else 963 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 964 } 965 966 static int psp_tmr_unload(struct psp_context *psp) 967 { 968 int ret; 969 struct psp_gfx_cmd_resp *cmd; 970 971 if (psp_skip_tmr(psp)) 972 return 0; 973 974 cmd = acquire_psp_cmd_buf(psp); 975 976 psp_prep_tmr_unload_cmd_buf(psp, cmd); 977 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 978 979 ret = psp_cmd_submit_buf(psp, NULL, cmd, 980 psp->fence_buf_mc_addr); 981 982 release_psp_cmd_buf(psp); 983 984 return ret; 985 } 986 987 static int psp_tmr_terminate(struct psp_context *psp) 988 { 989 return psp_tmr_unload(psp); 990 } 991 992 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 993 uint64_t *output_ptr) 994 { 995 int ret; 996 struct psp_gfx_cmd_resp *cmd; 997 998 if (!output_ptr) 999 return -EINVAL; 1000 1001 if (amdgpu_sriov_vf(psp->adev)) 1002 return 0; 1003 1004 cmd = acquire_psp_cmd_buf(psp); 1005 1006 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1007 1008 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1009 psp->fence_buf_mc_addr); 1010 1011 if (!ret) { 1012 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1013 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1014 } 1015 1016 release_psp_cmd_buf(psp); 1017 1018 return ret; 1019 } 1020 1021 static int psp_get_fw_reservation_info(struct psp_context *psp, 1022 uint32_t cmd_id, 1023 uint64_t *addr, 1024 uint32_t *size) 1025 { 1026 int ret; 1027 uint32_t status; 1028 struct psp_gfx_cmd_resp *cmd; 1029 1030 cmd = acquire_psp_cmd_buf(psp); 1031 1032 cmd->cmd_id = cmd_id; 1033 1034 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1035 psp->fence_buf_mc_addr); 1036 if (ret) { 1037 release_psp_cmd_buf(psp); 1038 return ret; 1039 } 1040 1041 status = cmd->resp.status; 1042 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1043 release_psp_cmd_buf(psp); 1044 *addr = 0; 1045 *size = 0; 1046 return 0; 1047 } 1048 1049 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1050 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1051 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1052 1053 release_psp_cmd_buf(psp); 1054 1055 return 0; 1056 } 1057 1058 int psp_update_fw_reservation(struct psp_context *psp) 1059 { 1060 int ret; 1061 uint64_t reserv_addr, reserv_addr_ext; 1062 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1063 struct amdgpu_device *adev = psp->adev; 1064 1065 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1066 1067 if (amdgpu_sriov_vf(psp->adev)) 1068 return 0; 1069 1070 switch (mp0_ip_ver) { 1071 case IP_VERSION(14, 0, 2): 1072 if (adev->psp.sos.fw_version < 0x3b0e0d) 1073 return 0; 1074 break; 1075 1076 case IP_VERSION(14, 0, 3): 1077 if (adev->psp.sos.fw_version < 0x3a0e14) 1078 return 0; 1079 break; 1080 1081 default: 1082 return 0; 1083 } 1084 1085 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1086 if (ret) 1087 return ret; 1088 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1089 if (ret) 1090 return ret; 1091 1092 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1093 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1094 return 0; 1095 } 1096 1097 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1098 1099 reserv_size = roundup(reserv_size, SZ_1M); 1100 1101 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1102 reserv_addr, reserv_size, false); 1103 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1104 if (ret) { 1105 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1106 return ret; 1107 } 1108 1109 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1110 1111 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1112 reserv_addr_ext, reserv_size_ext, false); 1113 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1114 if (ret) { 1115 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1116 return ret; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1123 { 1124 struct psp_context *psp = &adev->psp; 1125 struct psp_gfx_cmd_resp *cmd; 1126 int ret; 1127 1128 if (amdgpu_sriov_vf(adev)) 1129 return 0; 1130 1131 cmd = acquire_psp_cmd_buf(psp); 1132 1133 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1134 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1135 1136 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1137 if (!ret) { 1138 *boot_cfg = 1139 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1140 } 1141 1142 release_psp_cmd_buf(psp); 1143 1144 return ret; 1145 } 1146 1147 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1148 { 1149 int ret; 1150 struct psp_context *psp = &adev->psp; 1151 struct psp_gfx_cmd_resp *cmd; 1152 1153 if (amdgpu_sriov_vf(adev)) 1154 return 0; 1155 1156 cmd = acquire_psp_cmd_buf(psp); 1157 1158 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1159 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1160 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1161 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1162 1163 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1164 1165 release_psp_cmd_buf(psp); 1166 1167 return ret; 1168 } 1169 1170 static int psp_rl_load(struct amdgpu_device *adev) 1171 { 1172 int ret; 1173 struct psp_context *psp = &adev->psp; 1174 struct psp_gfx_cmd_resp *cmd; 1175 1176 if (!is_psp_fw_valid(psp->rl)) 1177 return 0; 1178 1179 cmd = acquire_psp_cmd_buf(psp); 1180 1181 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1182 if (ret) { 1183 release_psp_cmd_buf(psp); 1184 return ret; 1185 } 1186 1187 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1188 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1189 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1190 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1191 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1192 1193 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1194 1195 release_psp_cmd_buf(psp); 1196 1197 return ret; 1198 } 1199 1200 int psp_memory_partition(struct psp_context *psp, int mode) 1201 { 1202 struct psp_gfx_cmd_resp *cmd; 1203 int ret; 1204 1205 if (amdgpu_sriov_vf(psp->adev)) 1206 return 0; 1207 1208 cmd = acquire_psp_cmd_buf(psp); 1209 1210 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1211 cmd->cmd.cmd_memory_part.mode = mode; 1212 1213 dev_info(psp->adev->dev, 1214 "Requesting %d memory partition change through PSP", mode); 1215 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1216 if (ret) 1217 dev_err(psp->adev->dev, 1218 "PSP request failed to change to NPS%d mode\n", mode); 1219 1220 release_psp_cmd_buf(psp); 1221 1222 return ret; 1223 } 1224 1225 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1226 uint32_t *ptl_fmt) 1227 { 1228 struct amdgpu_device *adev = psp->adev; 1229 1230 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1231 return -EINVAL; 1232 1233 switch (fmt) { 1234 case AMDGPU_PTL_FMT_I8: 1235 *ptl_fmt = GFX_FTYPE_I8; 1236 break; 1237 case AMDGPU_PTL_FMT_F16: 1238 *ptl_fmt = GFX_FTYPE_F16; 1239 break; 1240 case AMDGPU_PTL_FMT_BF16: 1241 *ptl_fmt = GFX_FTYPE_BF16; 1242 break; 1243 case AMDGPU_PTL_FMT_F32: 1244 *ptl_fmt = GFX_FTYPE_F32; 1245 break; 1246 case AMDGPU_PTL_FMT_F64: 1247 *ptl_fmt = GFX_FTYPE_F64; 1248 break; 1249 case AMDGPU_PTL_FMT_F8: 1250 *ptl_fmt = GFX_FTYPE_F8; 1251 break; 1252 case AMDGPU_PTL_FMT_VECTOR: 1253 *ptl_fmt = GFX_FTYPE_VECTOR; 1254 break; 1255 default: 1256 return -EINVAL; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1263 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1264 { 1265 struct psp_gfx_cmd_resp *cmd; 1266 struct amdgpu_ptl *ptl = &psp->ptl; 1267 int ret; 1268 1269 cmd = acquire_psp_cmd_buf(psp); 1270 1271 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1272 cmd->cmd.cmd_req_perf_hw.req = req_code; 1273 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1274 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1275 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1276 1277 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1278 if (ret) 1279 goto out; 1280 1281 /* 1282 * Check response status explicitly to avoid 1283 * updating cached PTL state with invalid data. 1284 */ 1285 if (cmd->resp.status) { 1286 dev_err(psp->adev->dev, 1287 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1288 req_code, cmd->resp.status, 1289 cmd->resp.uresp.perf_hw_info.resp); 1290 ret = -EIO; 1291 goto out; 1292 } 1293 1294 /* Parse response */ 1295 switch (req_code) { 1296 case PSP_PTL_PERF_MON_QUERY: 1297 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1298 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1299 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1300 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1301 *ptl_state, *fmt1, *fmt2); 1302 break; 1303 case PSP_PTL_PERF_MON_SET: 1304 /* Update cached state only on success */ 1305 ptl->enabled = *ptl_state; 1306 ptl->fmt1 = *fmt1; 1307 ptl->fmt2 = *fmt2; 1308 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1309 *ptl_state, *fmt1, *fmt2); 1310 break; 1311 } 1312 1313 out: 1314 release_psp_cmd_buf(psp); 1315 return ret; 1316 } 1317 1318 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1319 uint32_t *ptl_state, 1320 enum amdgpu_ptl_fmt *fmt1, 1321 enum amdgpu_ptl_fmt *fmt2) 1322 { 1323 uint32_t ptl_fmt1, ptl_fmt2; 1324 struct psp_context *psp; 1325 struct amdgpu_ptl *ptl; 1326 int ret; 1327 1328 if (!adev || !ptl_state || !fmt1 || !fmt2) 1329 return -EINVAL; 1330 1331 if (amdgpu_sriov_vf(adev)) 1332 return 0; 1333 1334 psp = &adev->psp; 1335 ptl = &psp->ptl; 1336 1337 if (ptl->permanently_disabled && *ptl_state == 1) 1338 return 0; 1339 1340 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1341 psp->sos.fw_version < 0x0036081a) 1342 return -EOPNOTSUPP; 1343 1344 /* Verify formats */ 1345 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1346 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1347 return -EINVAL; 1348 1349 /* 1350 * Add check to skip if state and formats are identical to current ones 1351 */ 1352 if (req_code == PSP_PTL_PERF_MON_SET && 1353 ptl->enabled == *ptl_state && 1354 ptl->fmt1 == ptl_fmt1 && 1355 ptl->fmt2 == ptl_fmt2) 1356 return 0; 1357 1358 /* If enabling PTL, check disable bitmap */ 1359 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1360 if (!bitmap_empty(ptl->disable_bitmap, 1361 AMDGPU_PTL_DISABLE_MAX)) { 1362 dev_dbg(adev->dev, 1363 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1364 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1365 ptl->disable_bitmap), 1366 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1367 ptl->disable_bitmap), 1368 atomic_read(&ptl->disable_ref)); 1369 return 0; 1370 } 1371 } 1372 1373 if (req_code == PSP_PTL_PERF_MON_SET) { 1374 amdgpu_amdkfd_stop_sched_all(adev); 1375 /* Wait for GFX engine idle before PTL state transition */ 1376 ret = amdgpu_device_ip_wait_for_idle(adev, 1377 AMD_IP_BLOCK_TYPE_GFX); 1378 if (ret) { 1379 amdgpu_amdkfd_start_sched_all(adev); 1380 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1381 return ret; 1382 } 1383 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1384 amdgpu_amdkfd_start_sched_all(adev); 1385 } else { 1386 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1387 } 1388 1389 return ret; 1390 } 1391 1392 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1393 { 1394 int i; 1395 1396 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1397 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1398 return (enum amdgpu_ptl_fmt)i; 1399 } 1400 1401 return AMDGPU_PTL_FMT_INVALID; 1402 } 1403 1404 static ssize_t ptl_supported_formats_show(struct device *dev, 1405 struct device_attribute *attr, char *buf) 1406 { 1407 ssize_t len = 0; 1408 1409 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1410 const char *fmt = amdgpu_ptl_fmt_str[i]; 1411 1412 len += sysfs_emit_at(buf, len, "%s%s", 1413 fmt ? fmt : "UNKNOWN", 1414 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1415 } 1416 1417 return len; 1418 } 1419 1420 static ssize_t ptl_enable_store(struct device *dev, 1421 struct device_attribute *attr, 1422 const char *buf, size_t count) 1423 { 1424 struct drm_device *ddev = dev_get_drvdata(dev); 1425 struct amdgpu_device *adev = drm_to_adev(ddev); 1426 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1427 uint32_t ptl_state, fmt1, fmt2; 1428 int ret; 1429 bool enable; 1430 bool bit_changed = false; 1431 1432 mutex_lock(&ptl->mutex); 1433 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1434 enable = true; 1435 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1436 enable = false; 1437 } else { 1438 mutex_unlock(&ptl->mutex); 1439 return -EINVAL; 1440 } 1441 1442 /* Block enable when permanently disabled */ 1443 if (ptl->permanently_disabled) { 1444 mutex_unlock(&ptl->mutex); 1445 return -EPERM; 1446 } 1447 1448 fmt1 = ptl->fmt1; 1449 fmt2 = ptl->fmt2; 1450 ptl_state = enable ? 1 : 0; 1451 1452 if (enable) 1453 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1454 ptl->disable_bitmap); 1455 1456 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1457 if (ret) { 1458 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1459 if (enable && bit_changed) 1460 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1461 mutex_unlock(&ptl->mutex); 1462 return ret; 1463 } 1464 1465 if (!enable) 1466 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1467 1468 mutex_unlock(&ptl->mutex); 1469 1470 return count; 1471 } 1472 1473 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1474 { 1475 struct drm_device *ddev = dev_get_drvdata(dev); 1476 struct amdgpu_device *adev = drm_to_adev(ddev); 1477 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1478 1479 if (ptl->permanently_disabled) 1480 return sysfs_emit(buf, "permanently disabled\n"); 1481 1482 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1483 } 1484 1485 static ssize_t ptl_format_store(struct device *dev, 1486 struct device_attribute *attr, 1487 const char *buf, size_t count) 1488 { 1489 struct drm_device *ddev = dev_get_drvdata(dev); 1490 struct amdgpu_device *adev = drm_to_adev(ddev); 1491 char fmt1_str[8], fmt2_str[8]; 1492 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1493 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1494 uint32_t ptl_state, fmt1, fmt2; 1495 int ret; 1496 1497 /* Only allow format update when PTL is enabled */ 1498 if (!ptl->enabled) 1499 return -EPERM; 1500 1501 mutex_lock(&ptl->mutex); 1502 /* Parse input, expecting "FMT1,FMT2" */ 1503 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1504 mutex_unlock(&ptl->mutex); 1505 return -EINVAL; 1506 } 1507 1508 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1509 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1510 1511 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1512 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1513 fmt1_enum == fmt2_enum) { 1514 mutex_unlock(&ptl->mutex); 1515 return -EINVAL; 1516 } 1517 1518 ptl_state = ptl->enabled; 1519 fmt1 = fmt1_enum; 1520 fmt2 = fmt2_enum; 1521 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1522 if (ret) { 1523 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1524 mutex_unlock(&ptl->mutex); 1525 return ret; 1526 } 1527 mutex_unlock(&ptl->mutex); 1528 1529 return count; 1530 } 1531 1532 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1533 { 1534 struct drm_device *ddev = dev_get_drvdata(dev); 1535 struct amdgpu_device *adev = drm_to_adev(ddev); 1536 struct psp_context *psp = &adev->psp; 1537 1538 return sysfs_emit(buf, "%s,%s\n", 1539 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1540 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1541 } 1542 1543 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1544 { 1545 struct device *dev = kobj_to_dev(kobj); 1546 struct drm_device *ddev = dev_get_drvdata(dev); 1547 struct amdgpu_device *adev = drm_to_adev(ddev); 1548 1549 /* Only show PTL sysfs files if PTL hardware is supported */ 1550 if (!adev->psp.ptl.hw_supported) 1551 return 0; 1552 1553 return attr->mode; 1554 } 1555 1556 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1557 { 1558 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1559 int ret; 1560 1561 if (!ptl->hw_supported) 1562 return 0; 1563 1564 if (ptl->ptl_sysfs_created) 1565 return 0; 1566 1567 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1568 if (!ret) 1569 ptl->ptl_sysfs_created = true; 1570 1571 return ret; 1572 } 1573 1574 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1575 { 1576 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1577 1578 if (!ptl->hw_supported) 1579 return; 1580 1581 if (!ptl->ptl_sysfs_created) 1582 return; 1583 1584 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1585 ptl->ptl_sysfs_created = false; 1586 } 1587 1588 int psp_spatial_partition(struct psp_context *psp, int mode) 1589 { 1590 struct psp_gfx_cmd_resp *cmd; 1591 int ret; 1592 1593 if (amdgpu_sriov_vf(psp->adev)) 1594 return 0; 1595 1596 cmd = acquire_psp_cmd_buf(psp); 1597 1598 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1599 cmd->cmd.cmd_spatial_part.mode = mode; 1600 1601 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1602 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1603 1604 release_psp_cmd_buf(psp); 1605 1606 return ret; 1607 } 1608 1609 static int psp_asd_initialize(struct psp_context *psp) 1610 { 1611 int ret; 1612 1613 /* If PSP version doesn't match ASD version, asd loading will be failed. 1614 * add workaround to bypass it for sriov now. 1615 * TODO: add version check to make it common 1616 */ 1617 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1618 return 0; 1619 1620 /* bypass asd if display hardware is not available */ 1621 if (!amdgpu_device_has_display_hardware(psp->adev) && 1622 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1623 return 0; 1624 1625 psp->asd_context.mem_context.shared_mc_addr = 0; 1626 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1627 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1628 1629 ret = psp_ta_load(psp, &psp->asd_context); 1630 if (!ret) 1631 psp->asd_context.initialized = true; 1632 1633 return ret; 1634 } 1635 1636 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1637 uint32_t session_id) 1638 { 1639 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1640 cmd->cmd.cmd_unload_ta.session_id = session_id; 1641 } 1642 1643 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1644 { 1645 int ret; 1646 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1647 1648 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1649 1650 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1651 1652 context->resp_status = cmd->resp.status; 1653 1654 release_psp_cmd_buf(psp); 1655 1656 return ret; 1657 } 1658 1659 static int psp_asd_terminate(struct psp_context *psp) 1660 { 1661 int ret; 1662 1663 if (amdgpu_sriov_vf(psp->adev)) 1664 return 0; 1665 1666 if (!psp->asd_context.initialized) 1667 return 0; 1668 1669 ret = psp_ta_unload(psp, &psp->asd_context); 1670 if (!ret) 1671 psp->asd_context.initialized = false; 1672 1673 return ret; 1674 } 1675 1676 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1677 uint32_t id, uint32_t value) 1678 { 1679 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1680 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1681 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1682 } 1683 1684 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1685 uint32_t value) 1686 { 1687 struct psp_gfx_cmd_resp *cmd; 1688 int ret = 0; 1689 1690 if (reg >= PSP_REG_LAST) 1691 return -EINVAL; 1692 1693 cmd = acquire_psp_cmd_buf(psp); 1694 1695 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1696 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1697 if (ret) 1698 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1699 1700 release_psp_cmd_buf(psp); 1701 1702 return ret; 1703 } 1704 1705 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1706 uint64_t ta_bin_mc, 1707 struct ta_context *context) 1708 { 1709 cmd->cmd_id = context->ta_load_type; 1710 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1711 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1712 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1713 1714 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1715 lower_32_bits(context->mem_context.shared_mc_addr); 1716 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1717 upper_32_bits(context->mem_context.shared_mc_addr); 1718 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1719 } 1720 1721 int psp_ta_init_shared_buf(struct psp_context *psp, 1722 struct ta_mem_context *mem_ctx) 1723 { 1724 /* 1725 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1726 * physical) for ta to host memory 1727 */ 1728 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1729 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1730 AMDGPU_GEM_DOMAIN_GTT, 1731 &mem_ctx->shared_bo, 1732 &mem_ctx->shared_mc_addr, 1733 &mem_ctx->shared_buf); 1734 } 1735 1736 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1737 uint32_t ta_cmd_id, 1738 uint32_t session_id) 1739 { 1740 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1741 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1742 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1743 } 1744 1745 int psp_ta_invoke(struct psp_context *psp, 1746 uint32_t ta_cmd_id, 1747 struct ta_context *context) 1748 { 1749 int ret; 1750 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1751 1752 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1753 1754 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1755 psp->fence_buf_mc_addr); 1756 1757 context->resp_status = cmd->resp.status; 1758 1759 release_psp_cmd_buf(psp); 1760 1761 return ret; 1762 } 1763 1764 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1765 { 1766 int ret; 1767 struct psp_gfx_cmd_resp *cmd; 1768 1769 cmd = acquire_psp_cmd_buf(psp); 1770 1771 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1772 context->bin_desc.size_bytes); 1773 if (ret) { 1774 release_psp_cmd_buf(psp); 1775 return ret; 1776 } 1777 1778 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1779 context->mem_context.shared_bo) 1780 context->mem_context.shared_mc_addr = 1781 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1782 1783 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1784 1785 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1786 psp->fence_buf_mc_addr); 1787 1788 context->resp_status = cmd->resp.status; 1789 1790 if (!ret) 1791 context->session_id = cmd->resp.session_id; 1792 1793 release_psp_cmd_buf(psp); 1794 1795 return ret; 1796 } 1797 1798 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1799 { 1800 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1801 } 1802 1803 int psp_xgmi_terminate(struct psp_context *psp) 1804 { 1805 int ret; 1806 struct amdgpu_device *adev = psp->adev; 1807 1808 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1809 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1810 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1811 adev->gmc.xgmi.connected_to_cpu)) 1812 return 0; 1813 1814 if (!psp->xgmi_context.context.initialized) 1815 return 0; 1816 1817 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1818 1819 psp->xgmi_context.context.initialized = false; 1820 1821 return ret; 1822 } 1823 1824 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1825 { 1826 struct ta_xgmi_shared_memory *xgmi_cmd; 1827 int ret; 1828 1829 if (!psp->ta_fw || 1830 !psp->xgmi_context.context.bin_desc.size_bytes || 1831 !psp->xgmi_context.context.bin_desc.start_addr) 1832 return -ENOENT; 1833 1834 if (!load_ta) 1835 goto invoke; 1836 1837 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1838 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1839 1840 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1841 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1842 if (ret) 1843 return ret; 1844 } 1845 1846 /* Load XGMI TA */ 1847 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1848 if (!ret) 1849 psp->xgmi_context.context.initialized = true; 1850 else 1851 return ret; 1852 1853 invoke: 1854 /* Initialize XGMI session */ 1855 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1856 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1857 xgmi_cmd->flag_extend_link_record = set_extended_data; 1858 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1859 1860 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1861 /* note down the capbility flag for XGMI TA */ 1862 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1863 1864 return ret; 1865 } 1866 1867 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1868 { 1869 struct ta_xgmi_shared_memory *xgmi_cmd; 1870 int ret; 1871 1872 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1873 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1874 1875 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1876 1877 /* Invoke xgmi ta to get hive id */ 1878 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1879 if (ret) 1880 return ret; 1881 1882 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1883 1884 return 0; 1885 } 1886 1887 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1888 { 1889 struct ta_xgmi_shared_memory *xgmi_cmd; 1890 int ret; 1891 1892 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1893 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1894 1895 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1896 1897 /* Invoke xgmi ta to get the node id */ 1898 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1899 if (ret) 1900 return ret; 1901 1902 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1903 1904 return 0; 1905 } 1906 1907 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1908 { 1909 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1910 IP_VERSION(13, 0, 2) && 1911 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1912 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1913 IP_VERSION(13, 0, 6); 1914 } 1915 1916 /* 1917 * Chips that support extended topology information require the driver to 1918 * reflect topology information in the opposite direction. This is 1919 * because the TA has already exceeded its link record limit and if the 1920 * TA holds bi-directional information, the driver would have to do 1921 * multiple fetches instead of just two. 1922 */ 1923 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1924 struct psp_xgmi_node_info node_info) 1925 { 1926 struct amdgpu_device *mirror_adev; 1927 struct amdgpu_hive_info *hive; 1928 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1929 uint64_t dst_node_id = node_info.node_id; 1930 uint8_t dst_num_hops = node_info.num_hops; 1931 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1932 uint8_t dst_num_links = node_info.num_links; 1933 1934 hive = amdgpu_get_xgmi_hive(psp->adev); 1935 if (WARN_ON(!hive)) 1936 return; 1937 1938 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1939 struct psp_xgmi_topology_info *mirror_top_info; 1940 int j; 1941 1942 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1943 continue; 1944 1945 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1946 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1947 if (mirror_top_info->nodes[j].node_id != src_node_id) 1948 continue; 1949 1950 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1951 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1952 /* prevent 0 num_links value re-reflection since reflection 1953 * criteria is based on num_hops (direct or indirect). 1954 */ 1955 if (dst_num_links) { 1956 mirror_top_info->nodes[j].num_links = dst_num_links; 1957 /* swap src and dst due to frame of reference */ 1958 for (int k = 0; k < dst_num_links; k++) { 1959 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1960 node_info.port_num[k].dst_xgmi_port_num; 1961 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1962 node_info.port_num[k].src_xgmi_port_num; 1963 } 1964 } 1965 1966 break; 1967 } 1968 1969 break; 1970 } 1971 1972 amdgpu_put_xgmi_hive(hive); 1973 } 1974 1975 int psp_xgmi_get_topology_info(struct psp_context *psp, 1976 int number_devices, 1977 struct psp_xgmi_topology_info *topology, 1978 bool get_extended_data) 1979 { 1980 struct ta_xgmi_shared_memory *xgmi_cmd; 1981 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1982 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1983 int i; 1984 int ret; 1985 1986 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1987 return -EINVAL; 1988 1989 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1990 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1991 xgmi_cmd->flag_extend_link_record = get_extended_data; 1992 1993 /* Fill in the shared memory with topology information as input */ 1994 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1995 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1996 topology_info_input->num_nodes = number_devices; 1997 1998 for (i = 0; i < topology_info_input->num_nodes; i++) { 1999 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2000 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2001 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2002 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2003 } 2004 2005 /* Invoke xgmi ta to get the topology information */ 2006 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2007 if (ret) 2008 return ret; 2009 2010 /* Read the output topology information from the shared memory */ 2011 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2012 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2013 for (i = 0; i < topology->num_nodes; i++) { 2014 /* extended data will either be 0 or equal to non-extended data */ 2015 if (topology_info_output->nodes[i].num_hops) 2016 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2017 2018 /* non-extended data gets everything here so no need to update */ 2019 if (!get_extended_data) { 2020 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2021 topology->nodes[i].is_sharing_enabled = 2022 topology_info_output->nodes[i].is_sharing_enabled; 2023 topology->nodes[i].sdma_engine = 2024 topology_info_output->nodes[i].sdma_engine; 2025 } 2026 2027 } 2028 2029 /* Invoke xgmi ta again to get the link information */ 2030 if (psp_xgmi_peer_link_info_supported(psp)) { 2031 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2032 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2033 bool requires_reflection = 2034 (psp->xgmi_context.supports_extended_data && 2035 get_extended_data) || 2036 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2037 IP_VERSION(13, 0, 6) || 2038 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2039 IP_VERSION(13, 0, 14) || 2040 amdgpu_sriov_vf(psp->adev); 2041 bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || 2042 amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 2043 2044 /* popluate the shared output buffer rather than the cmd input buffer 2045 * with node_ids as the input for GET_PEER_LINKS command execution. 2046 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2047 * The same requirement for GET_EXTEND_PEER_LINKS command. 2048 */ 2049 if (ta_port_num_support) { 2050 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2051 2052 for (i = 0; i < topology->num_nodes; i++) 2053 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2054 2055 link_extend_info_output->num_nodes = topology->num_nodes; 2056 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2057 } else { 2058 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2059 2060 for (i = 0; i < topology->num_nodes; i++) 2061 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2062 2063 link_info_output->num_nodes = topology->num_nodes; 2064 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2065 } 2066 2067 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2068 if (ret) 2069 return ret; 2070 2071 for (i = 0; i < topology->num_nodes; i++) { 2072 uint8_t node_num_links = ta_port_num_support ? 2073 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2074 /* accumulate num_links on extended data */ 2075 if (get_extended_data) { 2076 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2077 } else { 2078 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2079 topology->nodes[i].num_links : node_num_links; 2080 } 2081 /* popluate the connected port num info if supported and available */ 2082 if (ta_port_num_support && topology->nodes[i].num_links) { 2083 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2084 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2085 } 2086 2087 /* reflect the topology information for bi-directionality */ 2088 if (requires_reflection && topology->nodes[i].num_hops) 2089 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2090 } 2091 } 2092 2093 return 0; 2094 } 2095 2096 int psp_xgmi_set_topology_info(struct psp_context *psp, 2097 int number_devices, 2098 struct psp_xgmi_topology_info *topology) 2099 { 2100 struct ta_xgmi_shared_memory *xgmi_cmd; 2101 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2102 int i; 2103 2104 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2105 return -EINVAL; 2106 2107 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2108 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2109 2110 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2111 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2112 topology_info_input->num_nodes = number_devices; 2113 2114 for (i = 0; i < topology_info_input->num_nodes; i++) { 2115 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2116 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2117 topology_info_input->nodes[i].is_sharing_enabled = 1; 2118 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2119 } 2120 2121 /* Invoke xgmi ta to set topology information */ 2122 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2123 } 2124 2125 // ras begin 2126 static void psp_ras_ta_check_status(struct psp_context *psp) 2127 { 2128 struct ta_ras_shared_memory *ras_cmd = 2129 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2130 2131 switch (ras_cmd->ras_status) { 2132 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2133 dev_warn(psp->adev->dev, 2134 "RAS WARNING: cmd failed due to unsupported ip\n"); 2135 break; 2136 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2137 dev_warn(psp->adev->dev, 2138 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2139 break; 2140 case TA_RAS_STATUS__SUCCESS: 2141 break; 2142 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2143 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2144 dev_warn(psp->adev->dev, 2145 "RAS WARNING: Inject error to critical region is not allowed\n"); 2146 break; 2147 default: 2148 dev_warn(psp->adev->dev, 2149 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2150 break; 2151 } 2152 } 2153 2154 static int psp_ras_send_cmd(struct psp_context *psp, 2155 enum ras_command cmd_id, void *in, void *out) 2156 { 2157 struct ta_ras_shared_memory *ras_cmd; 2158 uint32_t cmd = cmd_id; 2159 int ret = 0; 2160 2161 if (!in) 2162 return -EINVAL; 2163 2164 mutex_lock(&psp->ras_context.mutex); 2165 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2166 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2167 2168 switch (cmd) { 2169 case TA_RAS_COMMAND__ENABLE_FEATURES: 2170 case TA_RAS_COMMAND__DISABLE_FEATURES: 2171 memcpy(&ras_cmd->ras_in_message, 2172 in, sizeof(ras_cmd->ras_in_message)); 2173 break; 2174 case TA_RAS_COMMAND__TRIGGER_ERROR: 2175 memcpy(&ras_cmd->ras_in_message.trigger_error, 2176 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2177 break; 2178 case TA_RAS_COMMAND__QUERY_ADDRESS: 2179 memcpy(&ras_cmd->ras_in_message.address, 2180 in, sizeof(ras_cmd->ras_in_message.address)); 2181 break; 2182 default: 2183 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2184 ret = -EINVAL; 2185 goto err_out; 2186 } 2187 2188 ras_cmd->cmd_id = cmd; 2189 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2190 2191 switch (cmd) { 2192 case TA_RAS_COMMAND__TRIGGER_ERROR: 2193 if (!ret && out) 2194 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2195 break; 2196 case TA_RAS_COMMAND__QUERY_ADDRESS: 2197 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2198 ret = -EINVAL; 2199 else if (out) 2200 memcpy(out, 2201 &ras_cmd->ras_out_message.address, 2202 sizeof(ras_cmd->ras_out_message.address)); 2203 break; 2204 default: 2205 break; 2206 } 2207 2208 err_out: 2209 mutex_unlock(&psp->ras_context.mutex); 2210 2211 return ret; 2212 } 2213 2214 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2215 { 2216 struct ta_ras_shared_memory *ras_cmd; 2217 int ret; 2218 2219 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2220 2221 /* 2222 * TODO: bypass the loading in sriov for now 2223 */ 2224 if (amdgpu_sriov_vf(psp->adev)) 2225 return 0; 2226 2227 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2228 2229 if (amdgpu_ras_intr_triggered()) 2230 return ret; 2231 2232 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2233 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2234 return -EINVAL; 2235 } 2236 2237 if (!ret) { 2238 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2239 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2240 2241 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2242 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2243 dev_warn(psp->adev->dev, 2244 "RAS internal register access blocked\n"); 2245 2246 psp_ras_ta_check_status(psp); 2247 } 2248 2249 return ret; 2250 } 2251 2252 int psp_ras_enable_features(struct psp_context *psp, 2253 union ta_ras_cmd_input *info, bool enable) 2254 { 2255 enum ras_command cmd_id; 2256 int ret; 2257 2258 if (!psp->ras_context.context.initialized || !info) 2259 return -EINVAL; 2260 2261 cmd_id = enable ? 2262 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2263 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2264 if (ret) 2265 return -EINVAL; 2266 2267 return 0; 2268 } 2269 2270 int psp_ras_terminate(struct psp_context *psp) 2271 { 2272 int ret; 2273 2274 /* 2275 * TODO: bypass the terminate in sriov for now 2276 */ 2277 if (amdgpu_sriov_vf(psp->adev)) 2278 return 0; 2279 2280 if (!psp->ras_context.context.initialized) 2281 return 0; 2282 2283 ret = psp_ta_unload(psp, &psp->ras_context.context); 2284 2285 psp->ras_context.context.initialized = false; 2286 2287 mutex_destroy(&psp->ras_context.mutex); 2288 2289 return ret; 2290 } 2291 2292 int psp_ras_initialize(struct psp_context *psp) 2293 { 2294 int ret; 2295 uint32_t boot_cfg = 0xFF; 2296 struct amdgpu_device *adev = psp->adev; 2297 struct ta_ras_shared_memory *ras_cmd; 2298 2299 /* 2300 * TODO: bypass the initialize in sriov for now 2301 */ 2302 if (amdgpu_sriov_vf(adev)) 2303 return 0; 2304 2305 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2306 !adev->psp.ras_context.context.bin_desc.start_addr) { 2307 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2308 return 0; 2309 } 2310 2311 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2312 /* query GECC enablement status from boot config 2313 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2314 */ 2315 ret = psp_boot_config_get(adev, &boot_cfg); 2316 if (ret) 2317 dev_warn(adev->dev, "PSP get boot config failed\n"); 2318 2319 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2320 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2321 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2322 dev_warn(adev->dev, 2323 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2324 } else { 2325 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2326 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2327 if (boot_cfg == 1) { 2328 dev_info(adev->dev, "GECC is enabled\n"); 2329 } else { 2330 /* enable GECC in next boot cycle if it is disabled 2331 * in boot config, or force enable GECC if failed to 2332 * get boot configuration 2333 */ 2334 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2335 if (ret) 2336 dev_warn(adev->dev, "PSP set boot config failed\n"); 2337 else 2338 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2339 } 2340 } else { 2341 if (!boot_cfg) { 2342 if (!adev->ras_default_ecc_enabled && 2343 amdgpu_ras_enable != 1 && 2344 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2345 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2346 else 2347 dev_info(adev->dev, "GECC is disabled\n"); 2348 } else { 2349 /* disable GECC in next boot cycle if ras is 2350 * disabled by module parameter amdgpu_ras_enable 2351 * and/or amdgpu_ras_mask, or boot_config_get call 2352 * is failed 2353 */ 2354 ret = psp_boot_config_set(adev, 0); 2355 if (ret) 2356 dev_warn(adev->dev, "PSP set boot config failed\n"); 2357 else 2358 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2359 } 2360 } 2361 } 2362 } 2363 2364 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2365 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2366 2367 if (!psp->ras_context.context.mem_context.shared_buf) { 2368 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2369 if (ret) 2370 return ret; 2371 } 2372 2373 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2374 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2375 2376 if (amdgpu_ras_is_poison_mode_supported(adev)) 2377 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2378 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2379 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2380 ras_cmd->ras_in_message.init_flags.xcc_mask = 2381 adev->gfx.xcc_mask; 2382 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2383 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2384 ras_cmd->ras_in_message.init_flags.nps_mode = 2385 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2386 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2387 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2388 2389 ret = psp_ta_load(psp, &psp->ras_context.context); 2390 2391 if (!ret && !ras_cmd->ras_status) { 2392 psp->ras_context.context.initialized = true; 2393 mutex_init(&psp->ras_context.mutex); 2394 } else { 2395 if (ras_cmd->ras_status) 2396 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2397 2398 /* fail to load RAS TA */ 2399 psp->ras_context.context.initialized = false; 2400 } 2401 2402 return ret; 2403 } 2404 2405 int psp_ras_trigger_error(struct psp_context *psp, 2406 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2407 { 2408 struct amdgpu_device *adev = psp->adev; 2409 int ret; 2410 uint32_t dev_mask; 2411 uint32_t ras_status = 0; 2412 2413 if (!psp->ras_context.context.initialized || !info) 2414 return -EINVAL; 2415 2416 switch (info->block_id) { 2417 case TA_RAS_BLOCK__GFX: 2418 dev_mask = GET_MASK(GC, instance_mask); 2419 break; 2420 case TA_RAS_BLOCK__SDMA: 2421 dev_mask = GET_MASK(SDMA0, instance_mask); 2422 break; 2423 case TA_RAS_BLOCK__VCN: 2424 case TA_RAS_BLOCK__JPEG: 2425 dev_mask = GET_MASK(VCN, instance_mask); 2426 break; 2427 default: 2428 dev_mask = instance_mask; 2429 break; 2430 } 2431 2432 /* reuse sub_block_index for backward compatibility */ 2433 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2434 dev_mask &= AMDGPU_RAS_INST_MASK; 2435 info->sub_block_index |= dev_mask; 2436 2437 ret = psp_ras_send_cmd(psp, 2438 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2439 if (ret) 2440 return -EINVAL; 2441 2442 /* If err_event_athub occurs error inject was successful, however 2443 * return status from TA is no long reliable 2444 */ 2445 if (amdgpu_ras_intr_triggered()) 2446 return 0; 2447 2448 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2449 return -EACCES; 2450 else if (ras_status) 2451 return -EINVAL; 2452 2453 return 0; 2454 } 2455 2456 int psp_ras_query_address(struct psp_context *psp, 2457 struct ta_ras_query_address_input *addr_in, 2458 struct ta_ras_query_address_output *addr_out) 2459 { 2460 int ret; 2461 2462 if (!psp->ras_context.context.initialized || 2463 !addr_in || !addr_out) 2464 return -EINVAL; 2465 2466 ret = psp_ras_send_cmd(psp, 2467 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2468 2469 return ret; 2470 } 2471 // ras end 2472 2473 // HDCP start 2474 static int psp_hdcp_initialize(struct psp_context *psp) 2475 { 2476 int ret; 2477 2478 /* 2479 * TODO: bypass the initialize in sriov for now 2480 */ 2481 if (amdgpu_sriov_vf(psp->adev)) 2482 return 0; 2483 2484 /* bypass hdcp initialization if dmu is harvested */ 2485 if (!amdgpu_device_has_display_hardware(psp->adev)) 2486 return 0; 2487 2488 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2489 !psp->hdcp_context.context.bin_desc.start_addr) { 2490 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2491 return 0; 2492 } 2493 2494 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2495 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2496 2497 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2498 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2499 if (ret) 2500 return ret; 2501 } 2502 2503 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2504 if (!ret) { 2505 psp->hdcp_context.context.initialized = true; 2506 mutex_init(&psp->hdcp_context.mutex); 2507 } 2508 2509 return ret; 2510 } 2511 2512 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2513 { 2514 /* 2515 * TODO: bypass the loading in sriov for now 2516 */ 2517 if (amdgpu_sriov_vf(psp->adev)) 2518 return 0; 2519 2520 if (!psp->hdcp_context.context.initialized) 2521 return 0; 2522 2523 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2524 } 2525 2526 static int psp_hdcp_terminate(struct psp_context *psp) 2527 { 2528 int ret; 2529 2530 /* 2531 * TODO: bypass the terminate in sriov for now 2532 */ 2533 if (amdgpu_sriov_vf(psp->adev)) 2534 return 0; 2535 2536 if (!psp->hdcp_context.context.initialized) 2537 return 0; 2538 2539 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2540 2541 psp->hdcp_context.context.initialized = false; 2542 2543 return ret; 2544 } 2545 // HDCP end 2546 2547 // DTM start 2548 static int psp_dtm_initialize(struct psp_context *psp) 2549 { 2550 int ret; 2551 2552 /* 2553 * TODO: bypass the initialize in sriov for now 2554 */ 2555 if (amdgpu_sriov_vf(psp->adev)) 2556 return 0; 2557 2558 /* bypass dtm initialization if dmu is harvested */ 2559 if (!amdgpu_device_has_display_hardware(psp->adev)) 2560 return 0; 2561 2562 if (!psp->dtm_context.context.bin_desc.size_bytes || 2563 !psp->dtm_context.context.bin_desc.start_addr) { 2564 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2565 return 0; 2566 } 2567 2568 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2569 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2570 2571 if (!psp->dtm_context.context.mem_context.shared_buf) { 2572 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2573 if (ret) 2574 return ret; 2575 } 2576 2577 ret = psp_ta_load(psp, &psp->dtm_context.context); 2578 if (!ret) { 2579 psp->dtm_context.context.initialized = true; 2580 mutex_init(&psp->dtm_context.mutex); 2581 } 2582 2583 return ret; 2584 } 2585 2586 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2587 { 2588 /* 2589 * TODO: bypass the loading in sriov for now 2590 */ 2591 if (amdgpu_sriov_vf(psp->adev)) 2592 return 0; 2593 2594 if (!psp->dtm_context.context.initialized) 2595 return 0; 2596 2597 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2598 } 2599 2600 static int psp_dtm_terminate(struct psp_context *psp) 2601 { 2602 int ret; 2603 2604 /* 2605 * TODO: bypass the terminate in sriov for now 2606 */ 2607 if (amdgpu_sriov_vf(psp->adev)) 2608 return 0; 2609 2610 if (!psp->dtm_context.context.initialized) 2611 return 0; 2612 2613 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2614 2615 psp->dtm_context.context.initialized = false; 2616 2617 return ret; 2618 } 2619 // DTM end 2620 2621 // RAP start 2622 static int psp_rap_initialize(struct psp_context *psp) 2623 { 2624 int ret; 2625 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2626 2627 /* 2628 * TODO: bypass the initialize in sriov for now 2629 */ 2630 if (amdgpu_sriov_vf(psp->adev)) 2631 return 0; 2632 2633 if (!psp->rap_context.context.bin_desc.size_bytes || 2634 !psp->rap_context.context.bin_desc.start_addr) { 2635 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2636 return 0; 2637 } 2638 2639 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2640 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2641 2642 if (!psp->rap_context.context.mem_context.shared_buf) { 2643 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2644 if (ret) 2645 return ret; 2646 } 2647 2648 ret = psp_ta_load(psp, &psp->rap_context.context); 2649 if (!ret) { 2650 psp->rap_context.context.initialized = true; 2651 mutex_init(&psp->rap_context.mutex); 2652 } else 2653 return ret; 2654 2655 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2656 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2657 psp_rap_terminate(psp); 2658 /* free rap shared memory */ 2659 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2660 2661 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2662 ret, status); 2663 2664 return ret; 2665 } 2666 2667 return 0; 2668 } 2669 2670 static int psp_rap_terminate(struct psp_context *psp) 2671 { 2672 int ret; 2673 2674 if (!psp->rap_context.context.initialized) 2675 return 0; 2676 2677 ret = psp_ta_unload(psp, &psp->rap_context.context); 2678 2679 psp->rap_context.context.initialized = false; 2680 2681 return ret; 2682 } 2683 2684 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2685 { 2686 struct ta_rap_shared_memory *rap_cmd; 2687 int ret = 0; 2688 2689 if (!psp->rap_context.context.initialized) 2690 return 0; 2691 2692 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2693 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2694 return -EINVAL; 2695 2696 mutex_lock(&psp->rap_context.mutex); 2697 2698 rap_cmd = (struct ta_rap_shared_memory *) 2699 psp->rap_context.context.mem_context.shared_buf; 2700 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2701 2702 rap_cmd->cmd_id = ta_cmd_id; 2703 rap_cmd->validation_method_id = METHOD_A; 2704 2705 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2706 if (ret) 2707 goto out_unlock; 2708 2709 if (status) 2710 *status = rap_cmd->rap_status; 2711 2712 out_unlock: 2713 mutex_unlock(&psp->rap_context.mutex); 2714 2715 return ret; 2716 } 2717 // RAP end 2718 2719 /* securedisplay start */ 2720 static int psp_securedisplay_initialize(struct psp_context *psp) 2721 { 2722 int ret; 2723 struct ta_securedisplay_cmd *securedisplay_cmd; 2724 2725 /* 2726 * TODO: bypass the initialize in sriov for now 2727 */ 2728 if (amdgpu_sriov_vf(psp->adev)) 2729 return 0; 2730 2731 /* bypass securedisplay initialization if dmu is harvested */ 2732 if (!amdgpu_device_has_display_hardware(psp->adev)) 2733 return 0; 2734 2735 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2736 !psp->securedisplay_context.context.bin_desc.start_addr) { 2737 dev_info(psp->adev->dev, 2738 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2739 return 0; 2740 } 2741 2742 psp->securedisplay_context.context.mem_context.shared_mem_size = 2743 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2744 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2745 2746 if (!psp->securedisplay_context.context.initialized) { 2747 ret = psp_ta_init_shared_buf(psp, 2748 &psp->securedisplay_context.context.mem_context); 2749 if (ret) 2750 return ret; 2751 } 2752 2753 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2754 if (!ret && !psp->securedisplay_context.context.resp_status) { 2755 psp->securedisplay_context.context.initialized = true; 2756 mutex_init(&psp->securedisplay_context.mutex); 2757 } else { 2758 /* don't try again */ 2759 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2760 return ret; 2761 } 2762 2763 mutex_lock(&psp->securedisplay_context.mutex); 2764 2765 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2766 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2767 2768 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2769 2770 mutex_unlock(&psp->securedisplay_context.mutex); 2771 2772 if (ret) { 2773 psp_securedisplay_terminate(psp); 2774 /* free securedisplay shared memory */ 2775 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2776 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2777 return -EINVAL; 2778 } 2779 2780 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2781 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2782 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2783 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2784 /* don't try again */ 2785 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2786 } 2787 2788 return 0; 2789 } 2790 2791 static int psp_securedisplay_terminate(struct psp_context *psp) 2792 { 2793 int ret; 2794 2795 /* 2796 * TODO:bypass the terminate in sriov for now 2797 */ 2798 if (amdgpu_sriov_vf(psp->adev)) 2799 return 0; 2800 2801 if (!psp->securedisplay_context.context.initialized) 2802 return 0; 2803 2804 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2805 2806 psp->securedisplay_context.context.initialized = false; 2807 2808 return ret; 2809 } 2810 2811 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2812 { 2813 int ret; 2814 2815 if (!psp->securedisplay_context.context.initialized) 2816 return -EINVAL; 2817 2818 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2819 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2820 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2821 return -EINVAL; 2822 2823 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2824 2825 return ret; 2826 } 2827 /* SECUREDISPLAY end */ 2828 2829 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2830 { 2831 struct psp_context *psp = &adev->psp; 2832 int ret = 0; 2833 2834 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2835 ret = psp->funcs->wait_for_bootloader(psp); 2836 2837 return ret; 2838 } 2839 2840 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2841 { 2842 if (psp->funcs && 2843 psp->funcs->get_ras_capability) { 2844 return psp->funcs->get_ras_capability(psp); 2845 } else { 2846 return false; 2847 } 2848 } 2849 2850 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2851 { 2852 struct psp_context *psp = &adev->psp; 2853 2854 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2855 return false; 2856 2857 if (psp->funcs && psp->funcs->is_reload_needed) 2858 return psp->funcs->is_reload_needed(psp); 2859 2860 return false; 2861 } 2862 2863 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2864 { 2865 struct psp_context *psp = &adev->psp; 2866 2867 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2868 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2869 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2870 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2871 } 2872 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2873 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2874 } 2875 2876 static int psp_hw_start(struct psp_context *psp) 2877 { 2878 struct amdgpu_device *adev = psp->adev; 2879 int ret; 2880 2881 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2882 psp_update_gpu_addresses(adev); 2883 2884 if (!amdgpu_sriov_vf(adev)) { 2885 if ((is_psp_fw_valid(psp->kdb)) && 2886 (psp->funcs->bootloader_load_kdb != NULL)) { 2887 ret = psp_bootloader_load_kdb(psp); 2888 if (ret) { 2889 dev_err(adev->dev, "PSP load kdb failed!\n"); 2890 return ret; 2891 } 2892 } 2893 2894 if ((is_psp_fw_valid(psp->spl)) && 2895 (psp->funcs->bootloader_load_spl != NULL)) { 2896 ret = psp_bootloader_load_spl(psp); 2897 if (ret) { 2898 dev_err(adev->dev, "PSP load spl failed!\n"); 2899 return ret; 2900 } 2901 } 2902 2903 if ((is_psp_fw_valid(psp->sys)) && 2904 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2905 ret = psp_bootloader_load_sysdrv(psp); 2906 if (ret) { 2907 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2908 return ret; 2909 } 2910 } 2911 2912 if ((is_psp_fw_valid(psp->soc_drv)) && 2913 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2914 ret = psp_bootloader_load_soc_drv(psp); 2915 if (ret) { 2916 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2917 return ret; 2918 } 2919 } 2920 2921 if ((is_psp_fw_valid(psp->intf_drv)) && 2922 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2923 ret = psp_bootloader_load_intf_drv(psp); 2924 if (ret) { 2925 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2926 return ret; 2927 } 2928 } 2929 2930 if ((is_psp_fw_valid(psp->dbg_drv)) && 2931 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2932 ret = psp_bootloader_load_dbg_drv(psp); 2933 if (ret) { 2934 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2935 return ret; 2936 } 2937 } 2938 2939 if ((is_psp_fw_valid(psp->ras_drv)) && 2940 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2941 ret = psp_bootloader_load_ras_drv(psp); 2942 if (ret) { 2943 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2944 return ret; 2945 } 2946 } 2947 2948 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2949 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2950 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2951 if (ret) { 2952 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2953 return ret; 2954 } 2955 } 2956 2957 if ((is_psp_fw_valid(psp->spdm_drv)) && 2958 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2959 ret = psp_bootloader_load_spdm_drv(psp); 2960 if (ret) { 2961 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2962 return ret; 2963 } 2964 } 2965 2966 if ((is_psp_fw_valid(psp->sos)) && 2967 (psp->funcs->bootloader_load_sos != NULL)) { 2968 ret = psp_bootloader_load_sos(psp); 2969 if (ret) { 2970 dev_err(adev->dev, "PSP load sos failed!\n"); 2971 return ret; 2972 } 2973 } 2974 } 2975 2976 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2977 if (ret) { 2978 dev_err(adev->dev, "PSP create ring failed!\n"); 2979 return ret; 2980 } 2981 2982 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2983 ret = psp_update_fw_reservation(psp); 2984 if (ret) { 2985 dev_err(adev->dev, "update fw reservation failed!\n"); 2986 return ret; 2987 } 2988 } 2989 2990 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2991 goto skip_pin_bo; 2992 2993 if (!psp->boot_time_tmr || psp->autoload_supported) { 2994 ret = psp_tmr_init(psp); 2995 if (ret) { 2996 dev_err(adev->dev, "PSP tmr init failed!\n"); 2997 return ret; 2998 } 2999 } 3000 3001 skip_pin_bo: 3002 /* 3003 * For ASICs with DF Cstate management centralized 3004 * to PMFW, TMR setup should be performed after PMFW 3005 * loaded and before other non-psp firmware loaded. 3006 */ 3007 if (psp->pmfw_centralized_cstate_management) { 3008 ret = psp_load_smu_fw(psp); 3009 if (ret) 3010 return ret; 3011 } 3012 3013 ret = psp_tmr_load(psp); 3014 if (ret) { 3015 dev_err(adev->dev, "PSP load tmr failed!\n"); 3016 return ret; 3017 } 3018 3019 return 0; 3020 } 3021 3022 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3023 enum psp_gfx_fw_type *type) 3024 { 3025 switch (ucode->ucode_id) { 3026 case AMDGPU_UCODE_ID_CAP: 3027 *type = GFX_FW_TYPE_CAP; 3028 break; 3029 case AMDGPU_UCODE_ID_SDMA0: 3030 *type = GFX_FW_TYPE_SDMA0; 3031 break; 3032 case AMDGPU_UCODE_ID_SDMA1: 3033 *type = GFX_FW_TYPE_SDMA1; 3034 break; 3035 case AMDGPU_UCODE_ID_SDMA2: 3036 *type = GFX_FW_TYPE_SDMA2; 3037 break; 3038 case AMDGPU_UCODE_ID_SDMA3: 3039 *type = GFX_FW_TYPE_SDMA3; 3040 break; 3041 case AMDGPU_UCODE_ID_SDMA4: 3042 *type = GFX_FW_TYPE_SDMA4; 3043 break; 3044 case AMDGPU_UCODE_ID_SDMA5: 3045 *type = GFX_FW_TYPE_SDMA5; 3046 break; 3047 case AMDGPU_UCODE_ID_SDMA6: 3048 *type = GFX_FW_TYPE_SDMA6; 3049 break; 3050 case AMDGPU_UCODE_ID_SDMA7: 3051 *type = GFX_FW_TYPE_SDMA7; 3052 break; 3053 case AMDGPU_UCODE_ID_CP_MES: 3054 *type = GFX_FW_TYPE_CP_MES; 3055 break; 3056 case AMDGPU_UCODE_ID_CP_MES_DATA: 3057 *type = GFX_FW_TYPE_MES_STACK; 3058 break; 3059 case AMDGPU_UCODE_ID_CP_MES1: 3060 *type = GFX_FW_TYPE_CP_MES_KIQ; 3061 break; 3062 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3063 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3064 break; 3065 case AMDGPU_UCODE_ID_CP_CE: 3066 *type = GFX_FW_TYPE_CP_CE; 3067 break; 3068 case AMDGPU_UCODE_ID_CP_PFP: 3069 *type = GFX_FW_TYPE_CP_PFP; 3070 break; 3071 case AMDGPU_UCODE_ID_CP_ME: 3072 *type = GFX_FW_TYPE_CP_ME; 3073 break; 3074 case AMDGPU_UCODE_ID_CP_MEC1: 3075 *type = GFX_FW_TYPE_CP_MEC; 3076 break; 3077 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3078 *type = GFX_FW_TYPE_CP_MEC_ME1; 3079 break; 3080 case AMDGPU_UCODE_ID_CP_MEC2: 3081 *type = GFX_FW_TYPE_CP_MEC; 3082 break; 3083 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3084 *type = GFX_FW_TYPE_CP_MEC_ME2; 3085 break; 3086 case AMDGPU_UCODE_ID_RLC_P: 3087 *type = GFX_FW_TYPE_RLC_P; 3088 break; 3089 case AMDGPU_UCODE_ID_RLC_V: 3090 *type = GFX_FW_TYPE_RLC_V; 3091 break; 3092 case AMDGPU_UCODE_ID_RLC_G: 3093 *type = GFX_FW_TYPE_RLC_G; 3094 break; 3095 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3096 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3097 break; 3098 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3099 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3100 break; 3101 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3102 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3103 break; 3104 case AMDGPU_UCODE_ID_RLC_IRAM: 3105 *type = GFX_FW_TYPE_RLC_IRAM; 3106 break; 3107 case AMDGPU_UCODE_ID_RLC_DRAM: 3108 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3109 break; 3110 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3111 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3112 break; 3113 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3114 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3115 break; 3116 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3117 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3118 break; 3119 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3120 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3121 break; 3122 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3123 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3124 break; 3125 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3126 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3127 break; 3128 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3129 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3130 break; 3131 case AMDGPU_UCODE_ID_SMC: 3132 *type = GFX_FW_TYPE_SMU; 3133 break; 3134 case AMDGPU_UCODE_ID_PPTABLE: 3135 *type = GFX_FW_TYPE_PPTABLE; 3136 break; 3137 case AMDGPU_UCODE_ID_UVD: 3138 *type = GFX_FW_TYPE_UVD; 3139 break; 3140 case AMDGPU_UCODE_ID_UVD1: 3141 *type = GFX_FW_TYPE_UVD1; 3142 break; 3143 case AMDGPU_UCODE_ID_VCE: 3144 *type = GFX_FW_TYPE_VCE; 3145 break; 3146 case AMDGPU_UCODE_ID_VCN: 3147 *type = GFX_FW_TYPE_VCN; 3148 break; 3149 case AMDGPU_UCODE_ID_VCN1: 3150 *type = GFX_FW_TYPE_VCN1; 3151 break; 3152 case AMDGPU_UCODE_ID_DMCU_ERAM: 3153 *type = GFX_FW_TYPE_DMCU_ERAM; 3154 break; 3155 case AMDGPU_UCODE_ID_DMCU_INTV: 3156 *type = GFX_FW_TYPE_DMCU_ISR; 3157 break; 3158 case AMDGPU_UCODE_ID_VCN0_RAM: 3159 *type = GFX_FW_TYPE_VCN0_RAM; 3160 break; 3161 case AMDGPU_UCODE_ID_VCN1_RAM: 3162 *type = GFX_FW_TYPE_VCN1_RAM; 3163 break; 3164 case AMDGPU_UCODE_ID_DMCUB: 3165 *type = GFX_FW_TYPE_DMUB; 3166 break; 3167 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3168 case AMDGPU_UCODE_ID_SDMA_RS64: 3169 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3170 break; 3171 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3172 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3173 break; 3174 case AMDGPU_UCODE_ID_IMU_I: 3175 *type = GFX_FW_TYPE_IMU_I; 3176 break; 3177 case AMDGPU_UCODE_ID_IMU_D: 3178 *type = GFX_FW_TYPE_IMU_D; 3179 break; 3180 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3181 *type = GFX_FW_TYPE_RS64_PFP; 3182 break; 3183 case AMDGPU_UCODE_ID_CP_RS64_ME: 3184 *type = GFX_FW_TYPE_RS64_ME; 3185 break; 3186 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3187 *type = GFX_FW_TYPE_RS64_MEC; 3188 break; 3189 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3190 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3191 break; 3192 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3193 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3194 break; 3195 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3196 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3197 break; 3198 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3199 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3200 break; 3201 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3202 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3203 break; 3204 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3205 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3206 break; 3207 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3208 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3209 break; 3210 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3211 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3212 break; 3213 case AMDGPU_UCODE_ID_VPE_CTX: 3214 *type = GFX_FW_TYPE_VPEC_FW1; 3215 break; 3216 case AMDGPU_UCODE_ID_VPE_CTL: 3217 *type = GFX_FW_TYPE_VPEC_FW2; 3218 break; 3219 case AMDGPU_UCODE_ID_VPE: 3220 *type = GFX_FW_TYPE_VPE; 3221 break; 3222 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3223 *type = GFX_FW_TYPE_UMSCH_UCODE; 3224 break; 3225 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3226 *type = GFX_FW_TYPE_UMSCH_DATA; 3227 break; 3228 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3229 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3230 break; 3231 case AMDGPU_UCODE_ID_P2S_TABLE: 3232 *type = GFX_FW_TYPE_P2S_TABLE; 3233 break; 3234 case AMDGPU_UCODE_ID_JPEG_RAM: 3235 *type = GFX_FW_TYPE_JPEG_RAM; 3236 break; 3237 case AMDGPU_UCODE_ID_ISP: 3238 *type = GFX_FW_TYPE_ISP; 3239 break; 3240 case AMDGPU_UCODE_ID_MAXIMUM: 3241 default: 3242 return -EINVAL; 3243 } 3244 3245 return 0; 3246 } 3247 3248 static void psp_print_fw_hdr(struct psp_context *psp, 3249 struct amdgpu_firmware_info *ucode) 3250 { 3251 struct amdgpu_device *adev = psp->adev; 3252 struct common_firmware_header *hdr; 3253 3254 switch (ucode->ucode_id) { 3255 case AMDGPU_UCODE_ID_SDMA0: 3256 case AMDGPU_UCODE_ID_SDMA1: 3257 case AMDGPU_UCODE_ID_SDMA2: 3258 case AMDGPU_UCODE_ID_SDMA3: 3259 case AMDGPU_UCODE_ID_SDMA4: 3260 case AMDGPU_UCODE_ID_SDMA5: 3261 case AMDGPU_UCODE_ID_SDMA6: 3262 case AMDGPU_UCODE_ID_SDMA7: 3263 hdr = (struct common_firmware_header *) 3264 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3265 amdgpu_ucode_print_sdma_hdr(hdr); 3266 break; 3267 case AMDGPU_UCODE_ID_CP_CE: 3268 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3269 amdgpu_ucode_print_gfx_hdr(hdr); 3270 break; 3271 case AMDGPU_UCODE_ID_CP_PFP: 3272 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3273 amdgpu_ucode_print_gfx_hdr(hdr); 3274 break; 3275 case AMDGPU_UCODE_ID_CP_ME: 3276 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3277 amdgpu_ucode_print_gfx_hdr(hdr); 3278 break; 3279 case AMDGPU_UCODE_ID_CP_MEC1: 3280 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3281 amdgpu_ucode_print_gfx_hdr(hdr); 3282 break; 3283 case AMDGPU_UCODE_ID_RLC_G: 3284 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3285 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3286 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3287 amdgpu_ucode_print_rlc_hdr(hdr); 3288 break; 3289 case AMDGPU_UCODE_ID_SMC: 3290 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3291 amdgpu_ucode_print_smc_hdr(hdr); 3292 break; 3293 default: 3294 break; 3295 } 3296 } 3297 3298 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3299 struct amdgpu_firmware_info *ucode, 3300 struct psp_gfx_cmd_resp *cmd) 3301 { 3302 int ret; 3303 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3304 3305 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3306 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3307 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3308 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3309 3310 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3311 if (ret) 3312 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3313 return ret; 3314 } 3315 3316 int psp_execute_ip_fw_load(struct psp_context *psp, 3317 struct amdgpu_firmware_info *ucode) 3318 { 3319 int ret = 0; 3320 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3321 3322 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3323 if (!ret) { 3324 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3325 psp->fence_buf_mc_addr); 3326 } 3327 3328 release_psp_cmd_buf(psp); 3329 3330 return ret; 3331 } 3332 3333 static int psp_load_p2s_table(struct psp_context *psp) 3334 { 3335 int ret; 3336 struct amdgpu_device *adev = psp->adev; 3337 struct amdgpu_firmware_info *ucode = 3338 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3339 3340 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3341 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3342 return 0; 3343 3344 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3345 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3346 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3347 0x0036003C; 3348 if (psp->sos.fw_version < supp_vers) 3349 return 0; 3350 } 3351 3352 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3353 return 0; 3354 3355 ret = psp_execute_ip_fw_load(psp, ucode); 3356 3357 return ret; 3358 } 3359 3360 static int psp_load_smu_fw(struct psp_context *psp) 3361 { 3362 int ret; 3363 struct amdgpu_device *adev = psp->adev; 3364 struct amdgpu_firmware_info *ucode = 3365 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3366 struct amdgpu_ras *ras = psp->ras_context.ras; 3367 3368 /* 3369 * Skip SMU FW reloading in case of using BACO for runpm only, 3370 * as SMU is always alive. 3371 */ 3372 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3373 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3374 return 0; 3375 3376 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3377 return 0; 3378 3379 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3380 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3381 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3382 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3383 if (ret) 3384 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3385 } 3386 3387 ret = psp_execute_ip_fw_load(psp, ucode); 3388 3389 if (ret) 3390 dev_err(adev->dev, "PSP load smu failed!\n"); 3391 3392 return ret; 3393 } 3394 3395 static bool fw_load_skip_check(struct psp_context *psp, 3396 struct amdgpu_firmware_info *ucode) 3397 { 3398 if (!ucode->fw || !ucode->ucode_size) 3399 return true; 3400 3401 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3402 return true; 3403 3404 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3405 (psp_smu_reload_quirk(psp) || 3406 psp->autoload_supported || 3407 psp->pmfw_centralized_cstate_management)) 3408 return true; 3409 3410 if (amdgpu_sriov_vf(psp->adev) && 3411 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3412 return true; 3413 3414 if (psp->autoload_supported && 3415 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3416 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3417 /* skip mec JT when autoload is enabled */ 3418 return true; 3419 3420 return false; 3421 } 3422 3423 int psp_load_fw_list(struct psp_context *psp, 3424 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3425 { 3426 int ret = 0, i; 3427 struct amdgpu_firmware_info *ucode; 3428 3429 for (i = 0; i < ucode_count; ++i) { 3430 ucode = ucode_list[i]; 3431 psp_print_fw_hdr(psp, ucode); 3432 ret = psp_execute_ip_fw_load(psp, ucode); 3433 if (ret) 3434 return ret; 3435 } 3436 return ret; 3437 } 3438 3439 static int psp_load_non_psp_fw(struct psp_context *psp) 3440 { 3441 int i, ret; 3442 struct amdgpu_firmware_info *ucode; 3443 struct amdgpu_device *adev = psp->adev; 3444 3445 if (psp->autoload_supported && 3446 !psp->pmfw_centralized_cstate_management) { 3447 ret = psp_load_smu_fw(psp); 3448 if (ret) 3449 return ret; 3450 } 3451 3452 /* Load P2S table first if it's available */ 3453 psp_load_p2s_table(psp); 3454 3455 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3456 ucode = &adev->firmware.ucode[i]; 3457 3458 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3459 !fw_load_skip_check(psp, ucode)) { 3460 ret = psp_load_smu_fw(psp); 3461 if (ret) 3462 return ret; 3463 continue; 3464 } 3465 3466 if (fw_load_skip_check(psp, ucode)) 3467 continue; 3468 3469 if (psp->autoload_supported && 3470 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3471 IP_VERSION(11, 0, 7) || 3472 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3473 IP_VERSION(11, 0, 11) || 3474 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3475 IP_VERSION(11, 0, 12) || 3476 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3477 IP_VERSION(15, 0, 0) || 3478 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3479 IP_VERSION(15, 0, 8) || 3480 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3481 IP_VERSION(15, 0, 9)) && 3482 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3483 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3484 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3485 /* PSP only receive one SDMA fw for sienna_cichlid, 3486 * as all four sdma fw are same 3487 */ 3488 continue; 3489 3490 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3491 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3492 IP_VERSION(15, 0, 8) && 3493 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3494 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3495 continue; 3496 3497 psp_print_fw_hdr(psp, ucode); 3498 3499 ret = psp_execute_ip_fw_load(psp, ucode); 3500 if (ret) 3501 return ret; 3502 3503 /* Start rlc autoload after psp received all the gfx firmware */ 3504 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3505 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3506 ret = psp_rlc_autoload_start(psp); 3507 if (ret) { 3508 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3509 return ret; 3510 } 3511 } 3512 } 3513 3514 return 0; 3515 } 3516 3517 static int psp_load_fw(struct amdgpu_device *adev) 3518 { 3519 int ret; 3520 struct psp_context *psp = &adev->psp; 3521 3522 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3523 /* should not destroy ring, only stop */ 3524 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3525 } else { 3526 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3527 3528 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3529 if (ret) { 3530 dev_err(adev->dev, "PSP ring init failed!\n"); 3531 goto failed; 3532 } 3533 } 3534 3535 ret = psp_hw_start(psp); 3536 if (ret) 3537 goto failed; 3538 3539 ret = psp_load_non_psp_fw(psp); 3540 if (ret) 3541 goto failed1; 3542 3543 ret = psp_asd_initialize(psp); 3544 if (ret) { 3545 dev_err(adev->dev, "PSP load asd failed!\n"); 3546 goto failed1; 3547 } 3548 3549 ret = psp_rl_load(adev); 3550 if (ret) { 3551 dev_err(adev->dev, "PSP load RL failed!\n"); 3552 goto failed1; 3553 } 3554 3555 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3556 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3557 ret = psp_xgmi_initialize(psp, false, true); 3558 /* Warning the XGMI seesion initialize failure 3559 * Instead of stop driver initialization 3560 */ 3561 if (ret) 3562 dev_err(psp->adev->dev, 3563 "XGMI: Failed to initialize XGMI session\n"); 3564 } 3565 } 3566 3567 if (psp->ta_fw) { 3568 ret = psp_ras_initialize(psp); 3569 if (ret) 3570 dev_err(psp->adev->dev, 3571 "RAS: Failed to initialize RAS\n"); 3572 3573 ret = psp_hdcp_initialize(psp); 3574 if (ret) 3575 dev_err(psp->adev->dev, 3576 "HDCP: Failed to initialize HDCP\n"); 3577 3578 ret = psp_dtm_initialize(psp); 3579 if (ret) 3580 dev_err(psp->adev->dev, 3581 "DTM: Failed to initialize DTM\n"); 3582 3583 ret = psp_rap_initialize(psp); 3584 if (ret) 3585 dev_err(psp->adev->dev, 3586 "RAP: Failed to initialize RAP\n"); 3587 3588 ret = psp_securedisplay_initialize(psp); 3589 if (ret) 3590 dev_err(psp->adev->dev, 3591 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3592 } 3593 3594 return 0; 3595 3596 failed1: 3597 psp_free_shared_bufs(psp); 3598 failed: 3599 /* 3600 * all cleanup jobs (xgmi terminate, ras terminate, 3601 * ring destroy, cmd/fence/fw buffers destory, 3602 * psp->cmd destory) are delayed to psp_hw_fini 3603 */ 3604 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3605 return ret; 3606 } 3607 3608 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3609 { 3610 int ret; 3611 struct amdgpu_device *adev = ip_block->adev; 3612 3613 mutex_lock(&adev->firmware.mutex); 3614 3615 ret = amdgpu_ucode_init_bo(adev); 3616 if (ret) 3617 goto failed; 3618 3619 ret = psp_load_fw(adev); 3620 if (ret) { 3621 dev_err(adev->dev, "PSP firmware loading failed\n"); 3622 goto failed; 3623 } 3624 3625 mutex_unlock(&adev->firmware.mutex); 3626 return 0; 3627 3628 failed: 3629 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3630 mutex_unlock(&adev->firmware.mutex); 3631 return -EINVAL; 3632 } 3633 3634 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3635 { 3636 struct amdgpu_device *adev = ip_block->adev; 3637 struct psp_context *psp = &adev->psp; 3638 3639 if (psp->ta_fw) { 3640 psp_ras_terminate(psp); 3641 psp_securedisplay_terminate(psp); 3642 psp_rap_terminate(psp); 3643 psp_dtm_terminate(psp); 3644 psp_hdcp_terminate(psp); 3645 3646 if (adev->gmc.xgmi.num_physical_nodes > 1) 3647 psp_xgmi_terminate(psp); 3648 } 3649 3650 psp_asd_terminate(psp); 3651 psp_tmr_terminate(psp); 3652 3653 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3654 3655 return 0; 3656 } 3657 3658 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3659 { 3660 int ret = 0; 3661 struct amdgpu_device *adev = ip_block->adev; 3662 struct psp_context *psp = &adev->psp; 3663 3664 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3665 psp->xgmi_context.context.initialized) { 3666 ret = psp_xgmi_terminate(psp); 3667 if (ret) { 3668 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3669 goto out; 3670 } 3671 } 3672 3673 if (psp->ta_fw) { 3674 ret = psp_ras_terminate(psp); 3675 if (ret) { 3676 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3677 goto out; 3678 } 3679 ret = psp_hdcp_terminate(psp); 3680 if (ret) { 3681 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3682 goto out; 3683 } 3684 ret = psp_dtm_terminate(psp); 3685 if (ret) { 3686 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3687 goto out; 3688 } 3689 ret = psp_rap_terminate(psp); 3690 if (ret) { 3691 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3692 goto out; 3693 } 3694 ret = psp_securedisplay_terminate(psp); 3695 if (ret) { 3696 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3697 goto out; 3698 } 3699 } 3700 3701 ret = psp_asd_terminate(psp); 3702 if (ret) { 3703 dev_err(adev->dev, "Failed to terminate asd\n"); 3704 goto out; 3705 } 3706 3707 ret = psp_tmr_terminate(psp); 3708 if (ret) { 3709 dev_err(adev->dev, "Failed to terminate tmr\n"); 3710 goto out; 3711 } 3712 3713 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3714 if (ret) 3715 dev_err(adev->dev, "PSP ring stop failed\n"); 3716 3717 out: 3718 return ret; 3719 } 3720 3721 static int psp_resume(struct amdgpu_ip_block *ip_block) 3722 { 3723 int ret; 3724 struct amdgpu_device *adev = ip_block->adev; 3725 struct psp_context *psp = &adev->psp; 3726 3727 dev_info(adev->dev, "PSP is resuming...\n"); 3728 3729 if (psp->mem_train_ctx.enable_mem_training) { 3730 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3731 if (ret) { 3732 dev_err(adev->dev, "Failed to process memory training!\n"); 3733 return ret; 3734 } 3735 } 3736 3737 mutex_lock(&adev->firmware.mutex); 3738 3739 ret = amdgpu_ucode_init_bo(adev); 3740 if (ret) 3741 goto failed; 3742 3743 ret = psp_hw_start(psp); 3744 if (ret) 3745 goto failed; 3746 3747 ret = psp_load_non_psp_fw(psp); 3748 if (ret) 3749 goto failed; 3750 3751 ret = psp_asd_initialize(psp); 3752 if (ret) { 3753 dev_err(adev->dev, "PSP load asd failed!\n"); 3754 goto failed; 3755 } 3756 3757 ret = psp_rl_load(adev); 3758 if (ret) { 3759 dev_err(adev->dev, "PSP load RL failed!\n"); 3760 goto failed; 3761 } 3762 3763 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3764 ret = psp_xgmi_initialize(psp, false, true); 3765 /* Warning the XGMI seesion initialize failure 3766 * Instead of stop driver initialization 3767 */ 3768 if (ret) 3769 dev_err(psp->adev->dev, 3770 "XGMI: Failed to initialize XGMI session\n"); 3771 } 3772 3773 if (psp->ta_fw) { 3774 ret = psp_ras_initialize(psp); 3775 if (ret) 3776 dev_err(psp->adev->dev, 3777 "RAS: Failed to initialize RAS\n"); 3778 3779 ret = psp_hdcp_initialize(psp); 3780 if (ret) 3781 dev_err(psp->adev->dev, 3782 "HDCP: Failed to initialize HDCP\n"); 3783 3784 ret = psp_dtm_initialize(psp); 3785 if (ret) 3786 dev_err(psp->adev->dev, 3787 "DTM: Failed to initialize DTM\n"); 3788 3789 ret = psp_rap_initialize(psp); 3790 if (ret) 3791 dev_err(psp->adev->dev, 3792 "RAP: Failed to initialize RAP\n"); 3793 3794 ret = psp_securedisplay_initialize(psp); 3795 if (ret) 3796 dev_err(psp->adev->dev, 3797 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3798 } 3799 3800 mutex_unlock(&adev->firmware.mutex); 3801 3802 return 0; 3803 3804 failed: 3805 dev_err(adev->dev, "PSP resume failed\n"); 3806 mutex_unlock(&adev->firmware.mutex); 3807 return ret; 3808 } 3809 3810 int psp_gpu_reset(struct amdgpu_device *adev) 3811 { 3812 int ret; 3813 3814 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3815 return 0; 3816 3817 mutex_lock(&adev->psp.mutex); 3818 ret = psp_mode1_reset(&adev->psp); 3819 mutex_unlock(&adev->psp.mutex); 3820 3821 return ret; 3822 } 3823 3824 int psp_rlc_autoload_start(struct psp_context *psp) 3825 { 3826 int ret; 3827 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3828 3829 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3830 3831 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3832 psp->fence_buf_mc_addr); 3833 3834 release_psp_cmd_buf(psp); 3835 3836 return ret; 3837 } 3838 3839 int psp_ring_cmd_submit(struct psp_context *psp, 3840 uint64_t cmd_buf_mc_addr, 3841 uint64_t fence_mc_addr, 3842 int index) 3843 { 3844 unsigned int psp_write_ptr_reg = 0; 3845 struct psp_gfx_rb_frame *write_frame; 3846 struct psp_ring *ring = &psp->km_ring; 3847 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3848 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3849 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3850 struct amdgpu_device *adev = psp->adev; 3851 uint32_t ring_size_dw = ring->ring_size / 4; 3852 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3853 3854 /* KM (GPCOM) prepare write pointer */ 3855 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3856 3857 /* Update KM RB frame pointer to new frame */ 3858 /* write_frame ptr increments by size of rb_frame in bytes */ 3859 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3860 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3861 write_frame = ring_buffer_start; 3862 else 3863 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3864 /* Check invalid write_frame ptr address */ 3865 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3866 dev_err(adev->dev, 3867 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3868 ring_buffer_start, ring_buffer_end, write_frame); 3869 dev_err(adev->dev, 3870 "write_frame is pointing to address out of bounds\n"); 3871 return -EINVAL; 3872 } 3873 3874 /* Initialize KM RB frame */ 3875 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3876 3877 /* Update KM RB frame */ 3878 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3879 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3880 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3881 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3882 write_frame->fence_value = index; 3883 amdgpu_device_flush_hdp(adev, NULL); 3884 3885 /* Update the write Pointer in DWORDs */ 3886 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3887 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3888 return 0; 3889 } 3890 3891 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3892 { 3893 struct amdgpu_device *adev = psp->adev; 3894 const struct psp_firmware_header_v1_0 *asd_hdr; 3895 int err = 0; 3896 3897 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3898 "amdgpu/%s_asd.bin", chip_name); 3899 if (err) 3900 goto out; 3901 3902 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3903 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3904 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3905 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3906 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3907 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3908 return 0; 3909 out: 3910 amdgpu_ucode_release(&adev->psp.asd_fw); 3911 return err; 3912 } 3913 3914 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3915 { 3916 struct amdgpu_device *adev = psp->adev; 3917 const struct psp_firmware_header_v1_0 *toc_hdr; 3918 int err = 0; 3919 3920 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3921 adev->rev_id == 0) 3922 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3923 "amdgpu/%s_toc_1.bin", chip_name); 3924 else 3925 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3926 "amdgpu/%s_toc.bin", chip_name); 3927 if (err) 3928 goto out; 3929 3930 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3931 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3932 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3933 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3934 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3935 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3936 return 0; 3937 out: 3938 amdgpu_ucode_release(&adev->psp.toc_fw); 3939 return err; 3940 } 3941 3942 static int parse_sos_bin_descriptor(struct psp_context *psp, 3943 const struct psp_fw_bin_desc *desc, 3944 const struct psp_firmware_header_v2_0 *sos_hdr) 3945 { 3946 uint8_t *ucode_start_addr = NULL; 3947 3948 if (!psp || !desc || !sos_hdr) 3949 return -EINVAL; 3950 3951 ucode_start_addr = (uint8_t *)sos_hdr + 3952 le32_to_cpu(desc->offset_bytes) + 3953 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3954 3955 switch (desc->fw_type) { 3956 case PSP_FW_TYPE_PSP_SOS: 3957 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3958 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3959 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3960 psp->sos.start_addr = ucode_start_addr; 3961 break; 3962 case PSP_FW_TYPE_PSP_SYS_DRV: 3963 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3964 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3965 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3966 psp->sys.start_addr = ucode_start_addr; 3967 break; 3968 case PSP_FW_TYPE_PSP_KDB: 3969 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3970 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3971 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3972 psp->kdb.start_addr = ucode_start_addr; 3973 break; 3974 case PSP_FW_TYPE_PSP_TOC: 3975 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3976 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3977 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3978 psp->toc.start_addr = ucode_start_addr; 3979 break; 3980 case PSP_FW_TYPE_PSP_SPL: 3981 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3982 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3983 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3984 psp->spl.start_addr = ucode_start_addr; 3985 break; 3986 case PSP_FW_TYPE_PSP_RL: 3987 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3988 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3989 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3990 psp->rl.start_addr = ucode_start_addr; 3991 break; 3992 case PSP_FW_TYPE_PSP_SOC_DRV: 3993 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3994 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3995 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3996 psp->soc_drv.start_addr = ucode_start_addr; 3997 break; 3998 case PSP_FW_TYPE_PSP_INTF_DRV: 3999 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4000 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4001 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4002 psp->intf_drv.start_addr = ucode_start_addr; 4003 break; 4004 case PSP_FW_TYPE_PSP_DBG_DRV: 4005 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4006 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4007 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4008 psp->dbg_drv.start_addr = ucode_start_addr; 4009 break; 4010 case PSP_FW_TYPE_PSP_RAS_DRV: 4011 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4012 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4013 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4014 psp->ras_drv.start_addr = ucode_start_addr; 4015 break; 4016 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4017 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4018 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4019 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4020 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4021 break; 4022 case PSP_FW_TYPE_PSP_SPDM_DRV: 4023 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4024 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4025 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4026 psp->spdm_drv.start_addr = ucode_start_addr; 4027 break; 4028 default: 4029 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4030 break; 4031 } 4032 4033 return 0; 4034 } 4035 4036 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4037 { 4038 const struct psp_firmware_header_v1_0 *sos_hdr; 4039 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4040 uint8_t *ucode_array_start_addr; 4041 4042 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4043 ucode_array_start_addr = (uint8_t *)sos_hdr + 4044 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4045 4046 if (adev->gmc.xgmi.connected_to_cpu || 4047 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4048 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4049 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4050 4051 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4052 adev->psp.sys.start_addr = ucode_array_start_addr; 4053 4054 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4055 adev->psp.sos.start_addr = ucode_array_start_addr + 4056 le32_to_cpu(sos_hdr->sos.offset_bytes); 4057 } else { 4058 /* Load alternate PSP SOS FW */ 4059 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4060 4061 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4062 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4063 4064 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4065 adev->psp.sys.start_addr = ucode_array_start_addr + 4066 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4067 4068 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4069 adev->psp.sos.start_addr = ucode_array_start_addr + 4070 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4071 } 4072 4073 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4074 dev_warn(adev->dev, "PSP SOS FW not available"); 4075 return -EINVAL; 4076 } 4077 4078 return 0; 4079 } 4080 4081 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4082 { 4083 struct amdgpu_device *adev = psp->adev; 4084 const struct psp_firmware_header_v1_0 *sos_hdr; 4085 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4086 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4087 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4088 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4089 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4090 int fw_index, fw_bin_count, start_index = 0; 4091 const struct psp_fw_bin_desc *fw_bin; 4092 uint8_t *ucode_array_start_addr; 4093 int err = 0; 4094 4095 if (amdgpu_is_kicker_fw(adev)) 4096 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4097 "amdgpu/%s_sos_kicker.bin", chip_name); 4098 else 4099 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4100 "amdgpu/%s_sos.bin", chip_name); 4101 if (err) 4102 goto out; 4103 4104 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4105 ucode_array_start_addr = (uint8_t *)sos_hdr + 4106 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4107 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4108 4109 switch (sos_hdr->header.header_version_major) { 4110 case 1: 4111 err = psp_init_sos_base_fw(adev); 4112 if (err) 4113 goto out; 4114 4115 if (sos_hdr->header.header_version_minor == 1) { 4116 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4117 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4118 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4119 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4120 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4121 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4122 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4123 } 4124 if (sos_hdr->header.header_version_minor == 2) { 4125 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4126 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4127 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4128 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4129 } 4130 if (sos_hdr->header.header_version_minor == 3) { 4131 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4132 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4133 adev->psp.toc.start_addr = ucode_array_start_addr + 4134 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4135 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4136 adev->psp.kdb.start_addr = ucode_array_start_addr + 4137 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4138 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4139 adev->psp.spl.start_addr = ucode_array_start_addr + 4140 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4141 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4142 adev->psp.rl.start_addr = ucode_array_start_addr + 4143 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4144 } 4145 break; 4146 case 2: 4147 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4148 4149 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4150 4151 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4152 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4153 err = -EINVAL; 4154 goto out; 4155 } 4156 4157 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4158 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4159 4160 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4161 4162 if (psp_is_aux_sos_load_required(psp)) 4163 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4164 else 4165 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4166 4167 } else { 4168 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4169 } 4170 4171 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4172 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4173 sos_hdr_v2_0); 4174 if (err) 4175 goto out; 4176 } 4177 break; 4178 default: 4179 dev_err(adev->dev, 4180 "unsupported psp sos firmware\n"); 4181 err = -EINVAL; 4182 goto out; 4183 } 4184 4185 return 0; 4186 out: 4187 amdgpu_ucode_release(&adev->psp.sos_fw); 4188 4189 return err; 4190 } 4191 4192 static bool is_ta_fw_applicable(struct psp_context *psp, 4193 const struct psp_fw_bin_desc *desc) 4194 { 4195 struct amdgpu_device *adev = psp->adev; 4196 uint32_t fw_version; 4197 4198 switch (desc->fw_type) { 4199 case TA_FW_TYPE_PSP_XGMI: 4200 case TA_FW_TYPE_PSP_XGMI_AUX: 4201 /* for now, AUX TA only exists on 13.0.6 ta bin, 4202 * from v20.00.0x.14 4203 */ 4204 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4205 IP_VERSION(13, 0, 6)) { 4206 fw_version = le32_to_cpu(desc->fw_version); 4207 4208 if (adev->flags & AMD_IS_APU && 4209 (fw_version & 0xff) >= 0x14) 4210 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4211 else 4212 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4213 } 4214 break; 4215 default: 4216 break; 4217 } 4218 4219 return true; 4220 } 4221 4222 static int parse_ta_bin_descriptor(struct psp_context *psp, 4223 const struct psp_fw_bin_desc *desc, 4224 const struct ta_firmware_header_v2_0 *ta_hdr) 4225 { 4226 uint8_t *ucode_start_addr = NULL; 4227 4228 if (!psp || !desc || !ta_hdr) 4229 return -EINVAL; 4230 4231 if (!is_ta_fw_applicable(psp, desc)) 4232 return 0; 4233 4234 ucode_start_addr = (uint8_t *)ta_hdr + 4235 le32_to_cpu(desc->offset_bytes) + 4236 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4237 4238 switch (desc->fw_type) { 4239 case TA_FW_TYPE_PSP_ASD: 4240 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4241 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4242 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4243 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4244 break; 4245 case TA_FW_TYPE_PSP_XGMI: 4246 case TA_FW_TYPE_PSP_XGMI_AUX: 4247 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4248 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4249 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4250 break; 4251 case TA_FW_TYPE_PSP_RAS: 4252 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4253 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4254 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4255 break; 4256 case TA_FW_TYPE_PSP_HDCP: 4257 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4258 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4259 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4260 break; 4261 case TA_FW_TYPE_PSP_DTM: 4262 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4263 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4264 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4265 break; 4266 case TA_FW_TYPE_PSP_RAP: 4267 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4268 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4269 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4270 break; 4271 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4272 psp->securedisplay_context.context.bin_desc.fw_version = 4273 le32_to_cpu(desc->fw_version); 4274 psp->securedisplay_context.context.bin_desc.size_bytes = 4275 le32_to_cpu(desc->size_bytes); 4276 psp->securedisplay_context.context.bin_desc.start_addr = 4277 ucode_start_addr; 4278 break; 4279 default: 4280 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4281 break; 4282 } 4283 4284 return 0; 4285 } 4286 4287 static int parse_ta_v1_microcode(struct psp_context *psp) 4288 { 4289 const struct ta_firmware_header_v1_0 *ta_hdr; 4290 struct amdgpu_device *adev = psp->adev; 4291 4292 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4293 4294 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4295 return -EINVAL; 4296 4297 adev->psp.xgmi_context.context.bin_desc.fw_version = 4298 le32_to_cpu(ta_hdr->xgmi.fw_version); 4299 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4300 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4301 adev->psp.xgmi_context.context.bin_desc.start_addr = 4302 (uint8_t *)ta_hdr + 4303 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4304 4305 adev->psp.ras_context.context.bin_desc.fw_version = 4306 le32_to_cpu(ta_hdr->ras.fw_version); 4307 adev->psp.ras_context.context.bin_desc.size_bytes = 4308 le32_to_cpu(ta_hdr->ras.size_bytes); 4309 adev->psp.ras_context.context.bin_desc.start_addr = 4310 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4311 le32_to_cpu(ta_hdr->ras.offset_bytes); 4312 4313 adev->psp.hdcp_context.context.bin_desc.fw_version = 4314 le32_to_cpu(ta_hdr->hdcp.fw_version); 4315 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4316 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4317 adev->psp.hdcp_context.context.bin_desc.start_addr = 4318 (uint8_t *)ta_hdr + 4319 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4320 4321 adev->psp.dtm_context.context.bin_desc.fw_version = 4322 le32_to_cpu(ta_hdr->dtm.fw_version); 4323 adev->psp.dtm_context.context.bin_desc.size_bytes = 4324 le32_to_cpu(ta_hdr->dtm.size_bytes); 4325 adev->psp.dtm_context.context.bin_desc.start_addr = 4326 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4327 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4328 4329 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4330 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4331 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4332 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4333 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4334 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4335 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4336 4337 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4338 4339 return 0; 4340 } 4341 4342 static int parse_ta_v2_microcode(struct psp_context *psp) 4343 { 4344 const struct ta_firmware_header_v2_0 *ta_hdr; 4345 struct amdgpu_device *adev = psp->adev; 4346 int err = 0; 4347 int ta_index = 0; 4348 4349 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4350 4351 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4352 return -EINVAL; 4353 4354 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4355 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4356 return -EINVAL; 4357 } 4358 4359 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4360 err = parse_ta_bin_descriptor(psp, 4361 &ta_hdr->ta_fw_bin[ta_index], 4362 ta_hdr); 4363 if (err) 4364 return err; 4365 } 4366 4367 return 0; 4368 } 4369 4370 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4371 { 4372 const struct common_firmware_header *hdr; 4373 struct amdgpu_device *adev = psp->adev; 4374 int err; 4375 4376 if (amdgpu_is_kicker_fw(adev)) 4377 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4378 "amdgpu/%s_ta_kicker.bin", chip_name); 4379 else 4380 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4381 "amdgpu/%s_ta.bin", chip_name); 4382 if (err) 4383 return err; 4384 4385 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4386 switch (le16_to_cpu(hdr->header_version_major)) { 4387 case 1: 4388 err = parse_ta_v1_microcode(psp); 4389 break; 4390 case 2: 4391 err = parse_ta_v2_microcode(psp); 4392 break; 4393 default: 4394 dev_err(adev->dev, "unsupported TA header version\n"); 4395 err = -EINVAL; 4396 } 4397 4398 if (err) 4399 amdgpu_ucode_release(&adev->psp.ta_fw); 4400 4401 return err; 4402 } 4403 4404 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4405 { 4406 struct amdgpu_device *adev = psp->adev; 4407 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4408 struct amdgpu_firmware_info *info = NULL; 4409 int err = 0; 4410 4411 if (!amdgpu_sriov_vf(adev)) { 4412 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4413 return -EINVAL; 4414 } 4415 4416 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4417 "amdgpu/%s_cap.bin", chip_name); 4418 if (err) { 4419 if (err == -ENODEV) { 4420 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4421 err = 0; 4422 } else { 4423 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4424 } 4425 goto out; 4426 } 4427 4428 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4429 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4430 info->fw = adev->psp.cap_fw; 4431 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4432 adev->psp.cap_fw->data; 4433 adev->firmware.fw_size += ALIGN( 4434 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4435 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4436 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4437 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4438 4439 return 0; 4440 4441 out: 4442 amdgpu_ucode_release(&adev->psp.cap_fw); 4443 return err; 4444 } 4445 4446 int psp_config_sq_perfmon(struct psp_context *psp, 4447 uint32_t xcp_id, bool core_override_enable, 4448 bool reg_override_enable, bool perfmon_override_enable) 4449 { 4450 int ret; 4451 4452 if (amdgpu_sriov_vf(psp->adev)) 4453 return 0; 4454 4455 if (xcp_id > MAX_XCP) { 4456 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4457 return -EINVAL; 4458 } 4459 4460 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4461 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4462 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4463 return -EINVAL; 4464 } 4465 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4466 4467 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4468 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4469 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4470 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4471 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4472 4473 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4474 if (ret) 4475 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4476 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4477 4478 release_psp_cmd_buf(psp); 4479 return ret; 4480 } 4481 4482 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4483 enum amd_clockgating_state state) 4484 { 4485 return 0; 4486 } 4487 4488 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4489 enum amd_powergating_state state) 4490 { 4491 return 0; 4492 } 4493 4494 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4495 struct device_attribute *attr, 4496 char *buf) 4497 { 4498 struct drm_device *ddev = dev_get_drvdata(dev); 4499 struct amdgpu_device *adev = drm_to_adev(ddev); 4500 struct amdgpu_ip_block *ip_block; 4501 uint32_t fw_ver; 4502 int ret; 4503 4504 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4505 if (!ip_block || !ip_block->status.late_initialized) { 4506 dev_info(adev->dev, "PSP block is not ready yet\n."); 4507 return -EBUSY; 4508 } 4509 4510 mutex_lock(&adev->psp.mutex); 4511 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4512 mutex_unlock(&adev->psp.mutex); 4513 4514 if (ret) { 4515 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4516 return ret; 4517 } 4518 4519 return sysfs_emit(buf, "%x\n", fw_ver); 4520 } 4521 4522 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4523 struct device_attribute *attr, 4524 const char *buf, 4525 size_t count) 4526 { 4527 struct drm_device *ddev = dev_get_drvdata(dev); 4528 struct amdgpu_device *adev = drm_to_adev(ddev); 4529 int ret, idx; 4530 const struct firmware *usbc_pd_fw; 4531 struct amdgpu_bo *fw_buf_bo = NULL; 4532 uint64_t fw_pri_mc_addr; 4533 void *fw_pri_cpu_addr; 4534 struct amdgpu_ip_block *ip_block; 4535 4536 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4537 if (!ip_block || !ip_block->status.late_initialized) { 4538 dev_err(adev->dev, "PSP block is not ready yet."); 4539 return -EBUSY; 4540 } 4541 4542 if (!drm_dev_enter(ddev, &idx)) 4543 return -ENODEV; 4544 4545 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4546 "amdgpu/%s", buf); 4547 if (ret) 4548 goto fail; 4549 4550 /* LFB address which is aligned to 1MB boundary per PSP request */ 4551 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4552 AMDGPU_GEM_DOMAIN_VRAM | 4553 AMDGPU_GEM_DOMAIN_GTT, 4554 &fw_buf_bo, &fw_pri_mc_addr, 4555 &fw_pri_cpu_addr); 4556 if (ret) 4557 goto rel_buf; 4558 4559 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4560 4561 mutex_lock(&adev->psp.mutex); 4562 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4563 mutex_unlock(&adev->psp.mutex); 4564 4565 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4566 4567 rel_buf: 4568 amdgpu_ucode_release(&usbc_pd_fw); 4569 fail: 4570 if (ret) { 4571 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4572 count = ret; 4573 } 4574 4575 drm_dev_exit(idx); 4576 return count; 4577 } 4578 4579 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4580 { 4581 int idx; 4582 4583 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4584 return -ENODEV; 4585 4586 if (!bin_size || bin_size > PSP_1_MEG) { 4587 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4588 drm_dev_exit(idx); 4589 return -EINVAL; 4590 } 4591 4592 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4593 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4594 4595 drm_dev_exit(idx); 4596 return 0; 4597 } 4598 4599 /** 4600 * DOC: usbc_pd_fw 4601 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4602 * this file will trigger the update process. 4603 */ 4604 static DEVICE_ATTR(usbc_pd_fw, 0644, 4605 psp_usbc_pd_fw_sysfs_read, 4606 psp_usbc_pd_fw_sysfs_write); 4607 /** 4608 * DOC: PTL sysfs attributes 4609 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4610 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4611 * formats for each GPU. 4612 */ 4613 static DEVICE_ATTR(ptl_enable, 0644, 4614 ptl_enable_show, ptl_enable_store); 4615 static DEVICE_ATTR(ptl_format, 0644, 4616 ptl_format_show, ptl_format_store); 4617 static DEVICE_ATTR(ptl_supported_formats, 0444, 4618 ptl_supported_formats_show, NULL); 4619 4620 static struct attribute *ptl_attrs[] = { 4621 &dev_attr_ptl_enable.attr, 4622 &dev_attr_ptl_format.attr, 4623 &dev_attr_ptl_supported_formats.attr, 4624 NULL, 4625 }; 4626 4627 const struct attribute_group amdgpu_ptl_attr_group = { 4628 .name = "ptl", 4629 .attrs = ptl_attrs, 4630 .is_visible = amdgpu_ptl_is_visible, 4631 }; 4632 4633 int is_psp_fw_valid(struct psp_bin_desc bin) 4634 { 4635 return bin.size_bytes; 4636 } 4637 4638 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4639 const struct bin_attribute *bin_attr, 4640 char *buffer, loff_t pos, size_t count) 4641 { 4642 struct device *dev = kobj_to_dev(kobj); 4643 struct drm_device *ddev = dev_get_drvdata(dev); 4644 struct amdgpu_device *adev = drm_to_adev(ddev); 4645 4646 adev->psp.vbflash_done = false; 4647 4648 /* Safeguard against memory drain */ 4649 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4650 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4651 kvfree(adev->psp.vbflash_tmp_buf); 4652 adev->psp.vbflash_tmp_buf = NULL; 4653 adev->psp.vbflash_image_size = 0; 4654 return -ENOMEM; 4655 } 4656 4657 mutex_lock(&adev->psp.mutex); 4658 4659 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4660 if (!adev->psp.vbflash_tmp_buf) { 4661 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4662 if (!adev->psp.vbflash_tmp_buf) { 4663 mutex_unlock(&adev->psp.mutex); 4664 return -ENOMEM; 4665 } 4666 } 4667 4668 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4669 adev->psp.vbflash_image_size += count; 4670 mutex_unlock(&adev->psp.mutex); 4671 4672 dev_dbg(adev->dev, "IFWI staged for update\n"); 4673 4674 return count; 4675 } 4676 4677 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4678 const struct bin_attribute *bin_attr, char *buffer, 4679 loff_t pos, size_t count) 4680 { 4681 struct device *dev = kobj_to_dev(kobj); 4682 struct drm_device *ddev = dev_get_drvdata(dev); 4683 struct amdgpu_device *adev = drm_to_adev(ddev); 4684 struct amdgpu_bo *fw_buf_bo = NULL; 4685 uint64_t fw_pri_mc_addr; 4686 void *fw_pri_cpu_addr; 4687 int ret; 4688 4689 if (adev->psp.vbflash_image_size == 0) 4690 return -EINVAL; 4691 4692 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4693 4694 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4695 AMDGPU_GPU_PAGE_SIZE, 4696 AMDGPU_GEM_DOMAIN_VRAM, 4697 &fw_buf_bo, 4698 &fw_pri_mc_addr, 4699 &fw_pri_cpu_addr); 4700 if (ret) 4701 goto rel_buf; 4702 4703 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4704 4705 mutex_lock(&adev->psp.mutex); 4706 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4707 mutex_unlock(&adev->psp.mutex); 4708 4709 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4710 4711 rel_buf: 4712 kvfree(adev->psp.vbflash_tmp_buf); 4713 adev->psp.vbflash_tmp_buf = NULL; 4714 adev->psp.vbflash_image_size = 0; 4715 4716 if (ret) { 4717 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4718 return ret; 4719 } 4720 4721 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4722 return 0; 4723 } 4724 4725 /** 4726 * DOC: psp_vbflash 4727 * Writing to this file will stage an IFWI for update. Reading from this file 4728 * will trigger the update process. 4729 */ 4730 static const struct bin_attribute psp_vbflash_bin_attr = { 4731 .attr = {.name = "psp_vbflash", .mode = 0660}, 4732 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4733 .write = amdgpu_psp_vbflash_write, 4734 .read = amdgpu_psp_vbflash_read, 4735 }; 4736 4737 /** 4738 * DOC: psp_vbflash_status 4739 * The status of the flash process. 4740 * 0: IFWI flash not complete. 4741 * 1: IFWI flash complete. 4742 */ 4743 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4744 struct device_attribute *attr, 4745 char *buf) 4746 { 4747 struct drm_device *ddev = dev_get_drvdata(dev); 4748 struct amdgpu_device *adev = drm_to_adev(ddev); 4749 uint32_t vbflash_status; 4750 4751 vbflash_status = psp_vbflash_status(&adev->psp); 4752 if (!adev->psp.vbflash_done) 4753 vbflash_status = 0; 4754 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4755 vbflash_status = 1; 4756 4757 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4758 } 4759 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4760 4761 static const struct bin_attribute *const bin_flash_attrs[] = { 4762 &psp_vbflash_bin_attr, 4763 NULL 4764 }; 4765 4766 static struct attribute *flash_attrs[] = { 4767 &dev_attr_psp_vbflash_status.attr, 4768 &dev_attr_usbc_pd_fw.attr, 4769 NULL 4770 }; 4771 4772 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4773 { 4774 struct device *dev = kobj_to_dev(kobj); 4775 struct drm_device *ddev = dev_get_drvdata(dev); 4776 struct amdgpu_device *adev = drm_to_adev(ddev); 4777 4778 if (attr == &dev_attr_usbc_pd_fw.attr) 4779 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4780 4781 return adev->psp.sup_ifwi_up ? 0440 : 0; 4782 } 4783 4784 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4785 const struct bin_attribute *attr, 4786 int idx) 4787 { 4788 struct device *dev = kobj_to_dev(kobj); 4789 struct drm_device *ddev = dev_get_drvdata(dev); 4790 struct amdgpu_device *adev = drm_to_adev(ddev); 4791 4792 return adev->psp.sup_ifwi_up ? 0660 : 0; 4793 } 4794 4795 const struct attribute_group amdgpu_flash_attr_group = { 4796 .attrs = flash_attrs, 4797 .bin_attrs = bin_flash_attrs, 4798 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4799 .is_visible = amdgpu_flash_attr_is_visible, 4800 }; 4801 4802 #if defined(CONFIG_DEBUG_FS) 4803 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4804 { 4805 struct amdgpu_device *adev = filp->f_inode->i_private; 4806 struct spirom_bo *bo_triplet; 4807 int ret; 4808 4809 /* serialize the open() file calling */ 4810 if (!mutex_trylock(&adev->psp.mutex)) 4811 return -EBUSY; 4812 4813 /* 4814 * make sure only one userpace process is alive for dumping so that 4815 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4816 * let's say the case where one process try opening the file while 4817 * another one has proceeded to read or release. In this way, eliminate 4818 * the use of mutex for read() or release() callback as well. 4819 */ 4820 if (adev->psp.spirom_dump_trip) { 4821 mutex_unlock(&adev->psp.mutex); 4822 return -EBUSY; 4823 } 4824 4825 bo_triplet = kzalloc_obj(struct spirom_bo); 4826 if (!bo_triplet) { 4827 mutex_unlock(&adev->psp.mutex); 4828 return -ENOMEM; 4829 } 4830 4831 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4832 AMDGPU_GPU_PAGE_SIZE, 4833 AMDGPU_GEM_DOMAIN_GTT, 4834 &bo_triplet->bo, 4835 &bo_triplet->mc_addr, 4836 &bo_triplet->cpu_addr); 4837 if (ret) 4838 goto rel_trip; 4839 4840 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4841 if (ret) 4842 goto rel_bo; 4843 4844 adev->psp.spirom_dump_trip = bo_triplet; 4845 mutex_unlock(&adev->psp.mutex); 4846 return 0; 4847 rel_bo: 4848 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4849 &bo_triplet->cpu_addr); 4850 rel_trip: 4851 kfree(bo_triplet); 4852 mutex_unlock(&adev->psp.mutex); 4853 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4854 return ret; 4855 } 4856 4857 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4858 loff_t *pos) 4859 { 4860 struct amdgpu_device *adev = filp->f_inode->i_private; 4861 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4862 4863 if (!bo_triplet) 4864 return -EINVAL; 4865 4866 return simple_read_from_buffer(buf, 4867 size, 4868 pos, bo_triplet->cpu_addr, 4869 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4870 } 4871 4872 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4873 { 4874 struct amdgpu_device *adev = filp->f_inode->i_private; 4875 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4876 4877 if (bo_triplet) { 4878 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4879 &bo_triplet->cpu_addr); 4880 kfree(bo_triplet); 4881 } 4882 4883 adev->psp.spirom_dump_trip = NULL; 4884 return 0; 4885 } 4886 4887 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4888 .owner = THIS_MODULE, 4889 .open = psp_read_spirom_debugfs_open, 4890 .read = psp_read_spirom_debugfs_read, 4891 .release = psp_read_spirom_debugfs_release, 4892 .llseek = default_llseek, 4893 }; 4894 #endif 4895 4896 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4897 { 4898 #if defined(CONFIG_DEBUG_FS) 4899 struct drm_minor *minor = adev_to_drm(adev)->primary; 4900 4901 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4902 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4903 #endif 4904 } 4905 4906 const struct amd_ip_funcs psp_ip_funcs = { 4907 .name = "psp", 4908 .early_init = psp_early_init, 4909 .sw_init = psp_sw_init, 4910 .sw_fini = psp_sw_fini, 4911 .hw_init = psp_hw_init, 4912 .hw_fini = psp_hw_fini, 4913 .suspend = psp_suspend, 4914 .resume = psp_resume, 4915 .set_clockgating_state = psp_set_clockgating_state, 4916 .set_powergating_state = psp_set_powergating_state, 4917 }; 4918 4919 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4920 .type = AMD_IP_BLOCK_TYPE_PSP, 4921 .major = 3, 4922 .minor = 1, 4923 .rev = 0, 4924 .funcs = &psp_ip_funcs, 4925 }; 4926 4927 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4928 .type = AMD_IP_BLOCK_TYPE_PSP, 4929 .major = 10, 4930 .minor = 0, 4931 .rev = 0, 4932 .funcs = &psp_ip_funcs, 4933 }; 4934 4935 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4936 .type = AMD_IP_BLOCK_TYPE_PSP, 4937 .major = 11, 4938 .minor = 0, 4939 .rev = 0, 4940 .funcs = &psp_ip_funcs, 4941 }; 4942 4943 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4944 .type = AMD_IP_BLOCK_TYPE_PSP, 4945 .major = 11, 4946 .minor = 0, 4947 .rev = 8, 4948 .funcs = &psp_ip_funcs, 4949 }; 4950 4951 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4952 .type = AMD_IP_BLOCK_TYPE_PSP, 4953 .major = 12, 4954 .minor = 0, 4955 .rev = 0, 4956 .funcs = &psp_ip_funcs, 4957 }; 4958 4959 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4960 .type = AMD_IP_BLOCK_TYPE_PSP, 4961 .major = 13, 4962 .minor = 0, 4963 .rev = 0, 4964 .funcs = &psp_ip_funcs, 4965 }; 4966 4967 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4968 .type = AMD_IP_BLOCK_TYPE_PSP, 4969 .major = 13, 4970 .minor = 0, 4971 .rev = 4, 4972 .funcs = &psp_ip_funcs, 4973 }; 4974 4975 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4976 .type = AMD_IP_BLOCK_TYPE_PSP, 4977 .major = 14, 4978 .minor = 0, 4979 .rev = 0, 4980 .funcs = &psp_ip_funcs, 4981 }; 4982 4983 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 4984 .type = AMD_IP_BLOCK_TYPE_PSP, 4985 .major = 15, 4986 .minor = 0, 4987 .rev = 0, 4988 .funcs = &psp_ip_funcs, 4989 }; 4990 4991 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 4992 .type = AMD_IP_BLOCK_TYPE_PSP, 4993 .major = 15, 4994 .minor = 0, 4995 .rev = 8, 4996 .funcs = &psp_ip_funcs, 4997 }; 4998