1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v12_0.h" 37 #include "psp_v13_0.h" 38 39 #include "amdgpu_ras.h" 40 #include "amdgpu_securedisplay.h" 41 #include "amdgpu_atomfirmware.h" 42 43 #include <drm/drm_drv.h> 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 50 /* 51 * Due to DF Cstate management centralized to PMFW, the firmware 52 * loading sequence will be updated as below: 53 * - Load KDB 54 * - Load SYS_DRV 55 * - Load tOS 56 * - Load PMFW 57 * - Setup TMR 58 * - Load other non-psp fw 59 * - Load ASD 60 * - Load XGMI/RAS/HDCP/DTM TA if any 61 * 62 * This new sequence is required for 63 * - Arcturus and onwards 64 * - Navi12 and onwards 65 */ 66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 67 { 68 struct amdgpu_device *adev = psp->adev; 69 70 psp->pmfw_centralized_cstate_management = false; 71 72 if (amdgpu_sriov_vf(adev)) 73 return; 74 75 if (adev->flags & AMD_IS_APU) 76 return; 77 78 if ((adev->asic_type >= CHIP_ARCTURUS) || 79 (adev->asic_type >= CHIP_NAVI12)) 80 psp->pmfw_centralized_cstate_management = true; 81 } 82 83 static int psp_early_init(void *handle) 84 { 85 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 86 struct psp_context *psp = &adev->psp; 87 88 switch (adev->asic_type) { 89 case CHIP_VEGA10: 90 case CHIP_VEGA12: 91 psp_v3_1_set_psp_funcs(psp); 92 psp->autoload_supported = false; 93 break; 94 case CHIP_RAVEN: 95 psp_v10_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_VEGA20: 99 case CHIP_ARCTURUS: 100 psp_v11_0_set_psp_funcs(psp); 101 psp->autoload_supported = false; 102 break; 103 case CHIP_NAVI10: 104 case CHIP_NAVI14: 105 case CHIP_NAVI12: 106 case CHIP_SIENNA_CICHLID: 107 case CHIP_NAVY_FLOUNDER: 108 case CHIP_VANGOGH: 109 case CHIP_DIMGREY_CAVEFISH: 110 case CHIP_BEIGE_GOBY: 111 psp_v11_0_set_psp_funcs(psp); 112 psp->autoload_supported = true; 113 break; 114 case CHIP_RENOIR: 115 psp_v12_0_set_psp_funcs(psp); 116 break; 117 case CHIP_ALDEBARAN: 118 psp_v13_0_set_psp_funcs(psp); 119 break; 120 case CHIP_YELLOW_CARP: 121 psp_v13_0_set_psp_funcs(psp); 122 psp->autoload_supported = true; 123 break; 124 default: 125 return -EINVAL; 126 } 127 128 psp->adev = adev; 129 130 psp_check_pmfw_centralized_cstate_management(psp); 131 132 return 0; 133 } 134 135 static void psp_memory_training_fini(struct psp_context *psp) 136 { 137 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 138 139 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 140 kfree(ctx->sys_cache); 141 ctx->sys_cache = NULL; 142 } 143 144 static int psp_memory_training_init(struct psp_context *psp) 145 { 146 int ret; 147 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 148 149 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 150 DRM_DEBUG("memory training is not supported!\n"); 151 return 0; 152 } 153 154 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 155 if (ctx->sys_cache == NULL) { 156 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 157 ret = -ENOMEM; 158 goto Err_out; 159 } 160 161 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 162 ctx->train_data_size, 163 ctx->p2c_train_data_offset, 164 ctx->c2p_train_data_offset); 165 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 166 return 0; 167 168 Err_out: 169 psp_memory_training_fini(psp); 170 return ret; 171 } 172 173 /* 174 * Helper funciton to query psp runtime database entry 175 * 176 * @adev: amdgpu_device pointer 177 * @entry_type: the type of psp runtime database entry 178 * @db_entry: runtime database entry pointer 179 * 180 * Return false if runtime database doesn't exit or entry is invalid 181 * or true if the specific database entry is found, and copy to @db_entry 182 */ 183 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 184 enum psp_runtime_entry_type entry_type, 185 void *db_entry) 186 { 187 uint64_t db_header_pos, db_dir_pos; 188 struct psp_runtime_data_header db_header = {0}; 189 struct psp_runtime_data_directory db_dir = {0}; 190 bool ret = false; 191 int i; 192 193 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 194 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 195 196 /* read runtime db header from vram */ 197 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 198 sizeof(struct psp_runtime_data_header), false); 199 200 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 201 /* runtime db doesn't exist, exit */ 202 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 203 return false; 204 } 205 206 /* read runtime database entry from vram */ 207 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 208 sizeof(struct psp_runtime_data_directory), false); 209 210 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 211 /* invalid db entry count, exit */ 212 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 213 return false; 214 } 215 216 /* look up for requested entry type */ 217 for (i = 0; i < db_dir.entry_count && !ret; i++) { 218 if (db_dir.entry_list[i].entry_type == entry_type) { 219 switch (entry_type) { 220 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 221 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 222 /* invalid db entry size */ 223 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 224 return false; 225 } 226 /* read runtime database entry */ 227 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 228 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 229 ret = true; 230 break; 231 default: 232 ret = false; 233 break; 234 } 235 } 236 } 237 238 return ret; 239 } 240 241 static int psp_sw_init(void *handle) 242 { 243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 244 struct psp_context *psp = &adev->psp; 245 int ret; 246 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 247 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 248 249 if (!amdgpu_sriov_vf(adev)) { 250 ret = psp_init_microcode(psp); 251 if (ret) { 252 DRM_ERROR("Failed to load psp firmware!\n"); 253 return ret; 254 } 255 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 256 ret = psp_init_ta_microcode(psp, "aldebaran"); 257 if (ret) { 258 DRM_ERROR("Failed to initialize ta microcode!\n"); 259 return ret; 260 } 261 } 262 263 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 264 if (psp_get_runtime_db_entry(adev, 265 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 266 &boot_cfg_entry)) { 267 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 268 if ((psp->boot_cfg_bitmask) & 269 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 270 /* If psp runtime database exists, then 271 * only enable two stage memory training 272 * when TWO_STAGE_DRAM_TRAINING bit is set 273 * in runtime database */ 274 mem_training_ctx->enable_mem_training = true; 275 } 276 277 } else { 278 /* If psp runtime database doesn't exist or 279 * is invalid, force enable two stage memory 280 * training */ 281 mem_training_ctx->enable_mem_training = true; 282 } 283 284 if (mem_training_ctx->enable_mem_training) { 285 ret = psp_memory_training_init(psp); 286 if (ret) { 287 DRM_ERROR("Failed to initialize memory training!\n"); 288 return ret; 289 } 290 291 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 292 if (ret) { 293 DRM_ERROR("Failed to process memory training!\n"); 294 return ret; 295 } 296 } 297 298 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 299 ret= psp_sysfs_init(adev); 300 if (ret) { 301 return ret; 302 } 303 } 304 305 return 0; 306 } 307 308 static int psp_sw_fini(void *handle) 309 { 310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 311 312 psp_memory_training_fini(&adev->psp); 313 if (adev->psp.sos_fw) { 314 release_firmware(adev->psp.sos_fw); 315 adev->psp.sos_fw = NULL; 316 } 317 if (adev->psp.asd_fw) { 318 release_firmware(adev->psp.asd_fw); 319 adev->psp.asd_fw = NULL; 320 } 321 if (adev->psp.ta_fw) { 322 release_firmware(adev->psp.ta_fw); 323 adev->psp.ta_fw = NULL; 324 } 325 326 if (adev->asic_type == CHIP_NAVI10 || 327 adev->asic_type == CHIP_SIENNA_CICHLID) 328 psp_sysfs_fini(adev); 329 330 return 0; 331 } 332 333 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 334 uint32_t reg_val, uint32_t mask, bool check_changed) 335 { 336 uint32_t val; 337 int i; 338 struct amdgpu_device *adev = psp->adev; 339 340 if (psp->adev->no_hw_access) 341 return 0; 342 343 for (i = 0; i < adev->usec_timeout; i++) { 344 val = RREG32(reg_index); 345 if (check_changed) { 346 if (val != reg_val) 347 return 0; 348 } else { 349 if ((val & mask) == reg_val) 350 return 0; 351 } 352 udelay(1); 353 } 354 355 return -ETIME; 356 } 357 358 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 359 { 360 switch (cmd_id) { 361 case GFX_CMD_ID_LOAD_TA: 362 return "LOAD_TA"; 363 case GFX_CMD_ID_UNLOAD_TA: 364 return "UNLOAD_TA"; 365 case GFX_CMD_ID_INVOKE_CMD: 366 return "INVOKE_CMD"; 367 case GFX_CMD_ID_LOAD_ASD: 368 return "LOAD_ASD"; 369 case GFX_CMD_ID_SETUP_TMR: 370 return "SETUP_TMR"; 371 case GFX_CMD_ID_LOAD_IP_FW: 372 return "LOAD_IP_FW"; 373 case GFX_CMD_ID_DESTROY_TMR: 374 return "DESTROY_TMR"; 375 case GFX_CMD_ID_SAVE_RESTORE: 376 return "SAVE_RESTORE_IP_FW"; 377 case GFX_CMD_ID_SETUP_VMR: 378 return "SETUP_VMR"; 379 case GFX_CMD_ID_DESTROY_VMR: 380 return "DESTROY_VMR"; 381 case GFX_CMD_ID_PROG_REG: 382 return "PROG_REG"; 383 case GFX_CMD_ID_GET_FW_ATTESTATION: 384 return "GET_FW_ATTESTATION"; 385 case GFX_CMD_ID_LOAD_TOC: 386 return "ID_LOAD_TOC"; 387 case GFX_CMD_ID_AUTOLOAD_RLC: 388 return "AUTOLOAD_RLC"; 389 case GFX_CMD_ID_BOOT_CFG: 390 return "BOOT_CFG"; 391 default: 392 return "UNKNOWN CMD"; 393 } 394 } 395 396 static int 397 psp_cmd_submit_buf(struct psp_context *psp, 398 struct amdgpu_firmware_info *ucode, 399 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 400 { 401 int ret; 402 int index, idx; 403 int timeout = 20000; 404 bool ras_intr = false; 405 bool skip_unsupport = false; 406 407 if (psp->adev->no_hw_access) 408 return 0; 409 410 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 411 return 0; 412 413 mutex_lock(&psp->mutex); 414 415 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 416 417 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 418 419 index = atomic_inc_return(&psp->fence_value); 420 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 421 if (ret) { 422 atomic_dec(&psp->fence_value); 423 goto exit; 424 } 425 426 amdgpu_device_invalidate_hdp(psp->adev, NULL); 427 while (*((unsigned int *)psp->fence_buf) != index) { 428 if (--timeout == 0) 429 break; 430 /* 431 * Shouldn't wait for timeout when err_event_athub occurs, 432 * because gpu reset thread triggered and lock resource should 433 * be released for psp resume sequence. 434 */ 435 ras_intr = amdgpu_ras_intr_triggered(); 436 if (ras_intr) 437 break; 438 usleep_range(10, 100); 439 amdgpu_device_invalidate_hdp(psp->adev, NULL); 440 } 441 442 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 443 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 444 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 445 446 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 447 448 /* In some cases, psp response status is not 0 even there is no 449 * problem while the command is submitted. Some version of PSP FW 450 * doesn't write 0 to that field. 451 * So here we would like to only print a warning instead of an error 452 * during psp initialization to avoid breaking hw_init and it doesn't 453 * return -EINVAL. 454 */ 455 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 456 if (ucode) 457 DRM_WARN("failed to load ucode (%s) ", 458 amdgpu_ucode_name(ucode->ucode_id)); 459 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n", 460 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 461 psp->cmd_buf_mem->resp.status); 462 if (!timeout) { 463 ret = -EINVAL; 464 goto exit; 465 } 466 } 467 468 if (ucode) { 469 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 470 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 471 } 472 473 exit: 474 mutex_unlock(&psp->mutex); 475 drm_dev_exit(idx); 476 return ret; 477 } 478 479 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 480 struct psp_gfx_cmd_resp *cmd, 481 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 482 { 483 struct amdgpu_device *adev = psp->adev; 484 uint32_t size = amdgpu_bo_size(tmr_bo); 485 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 486 487 if (amdgpu_sriov_vf(psp->adev)) 488 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 489 else 490 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 491 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 492 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 493 cmd->cmd.cmd_setup_tmr.buf_size = size; 494 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 495 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 496 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 497 } 498 499 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 500 uint64_t pri_buf_mc, uint32_t size) 501 { 502 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 503 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 504 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 505 cmd->cmd.cmd_load_toc.toc_size = size; 506 } 507 508 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 509 static int psp_load_toc(struct psp_context *psp, 510 uint32_t *tmr_size) 511 { 512 int ret; 513 struct psp_gfx_cmd_resp *cmd; 514 515 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 516 if (!cmd) 517 return -ENOMEM; 518 /* Copy toc to psp firmware private buffer */ 519 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 520 521 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 522 523 ret = psp_cmd_submit_buf(psp, NULL, cmd, 524 psp->fence_buf_mc_addr); 525 if (!ret) 526 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 527 kfree(cmd); 528 return ret; 529 } 530 531 /* Set up Trusted Memory Region */ 532 static int psp_tmr_init(struct psp_context *psp) 533 { 534 int ret; 535 int tmr_size; 536 void *tmr_buf; 537 void **pptr; 538 539 /* 540 * According to HW engineer, they prefer the TMR address be "naturally 541 * aligned" , e.g. the start address be an integer divide of TMR size. 542 * 543 * Note: this memory need be reserved till the driver 544 * uninitializes. 545 */ 546 tmr_size = PSP_TMR_SIZE(psp->adev); 547 548 /* For ASICs support RLC autoload, psp will parse the toc 549 * and calculate the total size of TMR needed */ 550 if (!amdgpu_sriov_vf(psp->adev) && 551 psp->toc.start_addr && 552 psp->toc.size_bytes && 553 psp->fw_pri_buf) { 554 ret = psp_load_toc(psp, &tmr_size); 555 if (ret) { 556 DRM_ERROR("Failed to load toc\n"); 557 return ret; 558 } 559 } 560 561 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 562 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 563 AMDGPU_GEM_DOMAIN_VRAM, 564 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 565 566 return ret; 567 } 568 569 static bool psp_skip_tmr(struct psp_context *psp) 570 { 571 switch (psp->adev->asic_type) { 572 case CHIP_NAVI12: 573 case CHIP_SIENNA_CICHLID: 574 case CHIP_ALDEBARAN: 575 return true; 576 default: 577 return false; 578 } 579 } 580 581 static int psp_tmr_load(struct psp_context *psp) 582 { 583 int ret; 584 struct psp_gfx_cmd_resp *cmd; 585 586 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 587 * Already set up by host driver. 588 */ 589 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 590 return 0; 591 592 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 593 if (!cmd) 594 return -ENOMEM; 595 596 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 597 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 598 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 599 600 ret = psp_cmd_submit_buf(psp, NULL, cmd, 601 psp->fence_buf_mc_addr); 602 603 kfree(cmd); 604 605 return ret; 606 } 607 608 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 609 struct psp_gfx_cmd_resp *cmd) 610 { 611 if (amdgpu_sriov_vf(psp->adev)) 612 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 613 else 614 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 615 } 616 617 static int psp_tmr_unload(struct psp_context *psp) 618 { 619 int ret; 620 struct psp_gfx_cmd_resp *cmd; 621 622 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 623 if (!cmd) 624 return -ENOMEM; 625 626 psp_prep_tmr_unload_cmd_buf(psp, cmd); 627 DRM_INFO("free PSP TMR buffer\n"); 628 629 ret = psp_cmd_submit_buf(psp, NULL, cmd, 630 psp->fence_buf_mc_addr); 631 632 kfree(cmd); 633 634 return ret; 635 } 636 637 static int psp_tmr_terminate(struct psp_context *psp) 638 { 639 int ret; 640 void *tmr_buf; 641 void **pptr; 642 643 ret = psp_tmr_unload(psp); 644 if (ret) 645 return ret; 646 647 /* free TMR memory buffer */ 648 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 649 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 650 651 return 0; 652 } 653 654 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 655 uint64_t *output_ptr) 656 { 657 int ret; 658 struct psp_gfx_cmd_resp *cmd; 659 660 if (!output_ptr) 661 return -EINVAL; 662 663 if (amdgpu_sriov_vf(psp->adev)) 664 return 0; 665 666 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 667 if (!cmd) 668 return -ENOMEM; 669 670 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 671 672 ret = psp_cmd_submit_buf(psp, NULL, cmd, 673 psp->fence_buf_mc_addr); 674 675 if (!ret) { 676 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 677 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 678 } 679 680 kfree(cmd); 681 682 return ret; 683 } 684 685 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 686 { 687 struct psp_context *psp = &adev->psp; 688 struct psp_gfx_cmd_resp *cmd = psp->cmd; 689 int ret; 690 691 if (amdgpu_sriov_vf(adev)) 692 return 0; 693 694 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 695 696 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 697 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 698 699 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 700 if (!ret) { 701 *boot_cfg = 702 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 703 } 704 705 return ret; 706 } 707 708 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 709 { 710 struct psp_context *psp = &adev->psp; 711 struct psp_gfx_cmd_resp *cmd = psp->cmd; 712 713 if (amdgpu_sriov_vf(adev)) 714 return 0; 715 716 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 717 718 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 719 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 720 cmd->cmd.boot_cfg.boot_config = boot_cfg; 721 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 722 723 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 724 } 725 726 static int psp_rl_load(struct amdgpu_device *adev) 727 { 728 struct psp_context *psp = &adev->psp; 729 struct psp_gfx_cmd_resp *cmd = psp->cmd; 730 731 if (!is_psp_fw_valid(psp->rl)) 732 return 0; 733 734 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 735 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 736 737 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 738 739 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 740 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 741 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 742 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 743 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 744 745 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 746 } 747 748 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 749 uint64_t asd_mc, uint32_t size) 750 { 751 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 752 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 753 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 754 cmd->cmd.cmd_load_ta.app_len = size; 755 756 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 757 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 758 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 759 } 760 761 static int psp_asd_load(struct psp_context *psp) 762 { 763 int ret; 764 struct psp_gfx_cmd_resp *cmd; 765 766 /* If PSP version doesn't match ASD version, asd loading will be failed. 767 * add workaround to bypass it for sriov now. 768 * TODO: add version check to make it common 769 */ 770 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 771 return 0; 772 773 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 774 if (!cmd) 775 return -ENOMEM; 776 777 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 778 779 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 780 psp->asd_ucode_size); 781 782 ret = psp_cmd_submit_buf(psp, NULL, cmd, 783 psp->fence_buf_mc_addr); 784 if (!ret) { 785 psp->asd_context.asd_initialized = true; 786 psp->asd_context.session_id = cmd->resp.session_id; 787 } 788 789 kfree(cmd); 790 791 return ret; 792 } 793 794 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 795 uint32_t session_id) 796 { 797 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 798 cmd->cmd.cmd_unload_ta.session_id = session_id; 799 } 800 801 static int psp_asd_unload(struct psp_context *psp) 802 { 803 int ret; 804 struct psp_gfx_cmd_resp *cmd; 805 806 if (amdgpu_sriov_vf(psp->adev)) 807 return 0; 808 809 if (!psp->asd_context.asd_initialized) 810 return 0; 811 812 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 813 if (!cmd) 814 return -ENOMEM; 815 816 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 817 818 ret = psp_cmd_submit_buf(psp, NULL, cmd, 819 psp->fence_buf_mc_addr); 820 if (!ret) 821 psp->asd_context.asd_initialized = false; 822 823 kfree(cmd); 824 825 return ret; 826 } 827 828 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 829 uint32_t id, uint32_t value) 830 { 831 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 832 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 833 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 834 } 835 836 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 837 uint32_t value) 838 { 839 struct psp_gfx_cmd_resp *cmd = NULL; 840 int ret = 0; 841 842 if (reg >= PSP_REG_LAST) 843 return -EINVAL; 844 845 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 846 if (!cmd) 847 return -ENOMEM; 848 849 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 850 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 851 if (ret) 852 DRM_ERROR("PSP failed to program reg id %d", reg); 853 854 kfree(cmd); 855 return ret; 856 } 857 858 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 859 uint64_t ta_bin_mc, 860 uint32_t ta_bin_size, 861 uint64_t ta_shared_mc, 862 uint32_t ta_shared_size) 863 { 864 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 865 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 866 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 867 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 868 869 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 870 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 871 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 872 } 873 874 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 875 { 876 int ret; 877 878 /* 879 * Allocate 16k memory aligned to 4k from Frame Buffer (local 880 * physical) for xgmi ta <-> Driver 881 */ 882 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 883 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 884 &psp->xgmi_context.xgmi_shared_bo, 885 &psp->xgmi_context.xgmi_shared_mc_addr, 886 &psp->xgmi_context.xgmi_shared_buf); 887 888 return ret; 889 } 890 891 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 892 uint32_t ta_cmd_id, 893 uint32_t session_id) 894 { 895 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 896 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 897 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 898 } 899 900 static int psp_ta_invoke(struct psp_context *psp, 901 uint32_t ta_cmd_id, 902 uint32_t session_id) 903 { 904 int ret; 905 struct psp_gfx_cmd_resp *cmd; 906 907 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 908 if (!cmd) 909 return -ENOMEM; 910 911 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 912 913 ret = psp_cmd_submit_buf(psp, NULL, cmd, 914 psp->fence_buf_mc_addr); 915 916 kfree(cmd); 917 918 return ret; 919 } 920 921 static int psp_xgmi_load(struct psp_context *psp) 922 { 923 int ret; 924 struct psp_gfx_cmd_resp *cmd; 925 926 /* 927 * TODO: bypass the loading in sriov for now 928 */ 929 930 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 931 if (!cmd) 932 return -ENOMEM; 933 934 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 935 936 psp_prep_ta_load_cmd_buf(cmd, 937 psp->fw_pri_mc_addr, 938 psp->ta_xgmi_ucode_size, 939 psp->xgmi_context.xgmi_shared_mc_addr, 940 PSP_XGMI_SHARED_MEM_SIZE); 941 942 ret = psp_cmd_submit_buf(psp, NULL, cmd, 943 psp->fence_buf_mc_addr); 944 945 if (!ret) { 946 psp->xgmi_context.initialized = 1; 947 psp->xgmi_context.session_id = cmd->resp.session_id; 948 } 949 950 kfree(cmd); 951 952 return ret; 953 } 954 955 static int psp_xgmi_unload(struct psp_context *psp) 956 { 957 int ret; 958 struct psp_gfx_cmd_resp *cmd; 959 struct amdgpu_device *adev = psp->adev; 960 961 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 962 if (adev->asic_type == CHIP_ARCTURUS || 963 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 964 return 0; 965 966 /* 967 * TODO: bypass the unloading in sriov for now 968 */ 969 970 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 971 if (!cmd) 972 return -ENOMEM; 973 974 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 975 976 ret = psp_cmd_submit_buf(psp, NULL, cmd, 977 psp->fence_buf_mc_addr); 978 979 kfree(cmd); 980 981 return ret; 982 } 983 984 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 985 { 986 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 987 } 988 989 int psp_xgmi_terminate(struct psp_context *psp) 990 { 991 int ret; 992 993 if (!psp->xgmi_context.initialized) 994 return 0; 995 996 ret = psp_xgmi_unload(psp); 997 if (ret) 998 return ret; 999 1000 psp->xgmi_context.initialized = 0; 1001 1002 /* free xgmi shared memory */ 1003 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 1004 &psp->xgmi_context.xgmi_shared_mc_addr, 1005 &psp->xgmi_context.xgmi_shared_buf); 1006 1007 return 0; 1008 } 1009 1010 int psp_xgmi_initialize(struct psp_context *psp) 1011 { 1012 struct ta_xgmi_shared_memory *xgmi_cmd; 1013 int ret; 1014 1015 if (!psp->adev->psp.ta_fw || 1016 !psp->adev->psp.ta_xgmi_ucode_size || 1017 !psp->adev->psp.ta_xgmi_start_addr) 1018 return -ENOENT; 1019 1020 if (!psp->xgmi_context.initialized) { 1021 ret = psp_xgmi_init_shared_buf(psp); 1022 if (ret) 1023 return ret; 1024 } 1025 1026 /* Load XGMI TA */ 1027 ret = psp_xgmi_load(psp); 1028 if (ret) 1029 return ret; 1030 1031 /* Initialize XGMI session */ 1032 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 1033 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1034 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1035 1036 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1037 1038 return ret; 1039 } 1040 1041 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1042 { 1043 struct ta_xgmi_shared_memory *xgmi_cmd; 1044 int ret; 1045 1046 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1047 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1048 1049 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1050 1051 /* Invoke xgmi ta to get hive id */ 1052 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1053 if (ret) 1054 return ret; 1055 1056 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1057 1058 return 0; 1059 } 1060 1061 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1062 { 1063 struct ta_xgmi_shared_memory *xgmi_cmd; 1064 int ret; 1065 1066 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1067 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1068 1069 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1070 1071 /* Invoke xgmi ta to get the node id */ 1072 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1073 if (ret) 1074 return ret; 1075 1076 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1077 1078 return 0; 1079 } 1080 1081 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1082 { 1083 return psp->adev->asic_type == CHIP_ALDEBARAN && 1084 psp->ta_xgmi_ucode_version >= 0x2000000b; 1085 } 1086 1087 int psp_xgmi_get_topology_info(struct psp_context *psp, 1088 int number_devices, 1089 struct psp_xgmi_topology_info *topology) 1090 { 1091 struct ta_xgmi_shared_memory *xgmi_cmd; 1092 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1093 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1094 int i; 1095 int ret; 1096 1097 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1098 return -EINVAL; 1099 1100 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1101 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1102 1103 /* Fill in the shared memory with topology information as input */ 1104 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1105 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1106 topology_info_input->num_nodes = number_devices; 1107 1108 for (i = 0; i < topology_info_input->num_nodes; i++) { 1109 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1110 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1111 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1112 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1113 } 1114 1115 /* Invoke xgmi ta to get the topology information */ 1116 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1117 if (ret) 1118 return ret; 1119 1120 /* Read the output topology information from the shared memory */ 1121 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1122 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1123 for (i = 0; i < topology->num_nodes; i++) { 1124 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1125 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1126 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 1127 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 1128 } 1129 1130 /* Invoke xgmi ta again to get the link information */ 1131 if (psp_xgmi_peer_link_info_supported(psp)) { 1132 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1133 1134 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1135 1136 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1137 1138 if (ret) 1139 return ret; 1140 1141 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1142 for (i = 0; i < topology->num_nodes; i++) 1143 topology->nodes[i].num_links = 1144 link_info_output->nodes[i].num_links; 1145 } 1146 1147 return 0; 1148 } 1149 1150 int psp_xgmi_set_topology_info(struct psp_context *psp, 1151 int number_devices, 1152 struct psp_xgmi_topology_info *topology) 1153 { 1154 struct ta_xgmi_shared_memory *xgmi_cmd; 1155 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1156 int i; 1157 1158 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1159 return -EINVAL; 1160 1161 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1162 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1163 1164 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1165 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1166 topology_info_input->num_nodes = number_devices; 1167 1168 for (i = 0; i < topology_info_input->num_nodes; i++) { 1169 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1170 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1171 topology_info_input->nodes[i].is_sharing_enabled = 1; 1172 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1173 } 1174 1175 /* Invoke xgmi ta to set topology information */ 1176 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1177 } 1178 1179 // ras begin 1180 static int psp_ras_init_shared_buf(struct psp_context *psp) 1181 { 1182 int ret; 1183 1184 /* 1185 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1186 * physical) for ras ta <-> Driver 1187 */ 1188 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1189 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1190 &psp->ras.ras_shared_bo, 1191 &psp->ras.ras_shared_mc_addr, 1192 &psp->ras.ras_shared_buf); 1193 1194 return ret; 1195 } 1196 1197 static int psp_ras_load(struct psp_context *psp) 1198 { 1199 int ret; 1200 struct psp_gfx_cmd_resp *cmd; 1201 struct ta_ras_shared_memory *ras_cmd; 1202 1203 /* 1204 * TODO: bypass the loading in sriov for now 1205 */ 1206 if (amdgpu_sriov_vf(psp->adev)) 1207 return 0; 1208 1209 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1210 if (!cmd) 1211 return -ENOMEM; 1212 1213 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1214 1215 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1216 1217 if (psp->adev->gmc.xgmi.connected_to_cpu) 1218 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1219 else 1220 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1221 1222 psp_prep_ta_load_cmd_buf(cmd, 1223 psp->fw_pri_mc_addr, 1224 psp->ta_ras_ucode_size, 1225 psp->ras.ras_shared_mc_addr, 1226 PSP_RAS_SHARED_MEM_SIZE); 1227 1228 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1229 psp->fence_buf_mc_addr); 1230 1231 if (!ret) { 1232 psp->ras.session_id = cmd->resp.session_id; 1233 1234 if (!ras_cmd->ras_status) 1235 psp->ras.ras_initialized = true; 1236 else 1237 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1238 } 1239 1240 if (ret || ras_cmd->ras_status) 1241 amdgpu_ras_fini(psp->adev); 1242 1243 kfree(cmd); 1244 1245 return ret; 1246 } 1247 1248 static int psp_ras_unload(struct psp_context *psp) 1249 { 1250 int ret; 1251 struct psp_gfx_cmd_resp *cmd; 1252 1253 /* 1254 * TODO: bypass the unloading in sriov for now 1255 */ 1256 if (amdgpu_sriov_vf(psp->adev)) 1257 return 0; 1258 1259 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1260 if (!cmd) 1261 return -ENOMEM; 1262 1263 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1264 1265 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1266 psp->fence_buf_mc_addr); 1267 1268 kfree(cmd); 1269 1270 return ret; 1271 } 1272 1273 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1274 { 1275 struct ta_ras_shared_memory *ras_cmd; 1276 int ret; 1277 1278 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1279 1280 /* 1281 * TODO: bypass the loading in sriov for now 1282 */ 1283 if (amdgpu_sriov_vf(psp->adev)) 1284 return 0; 1285 1286 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1287 1288 if (amdgpu_ras_intr_triggered()) 1289 return ret; 1290 1291 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1292 { 1293 DRM_WARN("RAS: Unsupported Interface"); 1294 return -EINVAL; 1295 } 1296 1297 if (!ret) { 1298 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1299 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1300 1301 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1302 } 1303 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1304 dev_warn(psp->adev->dev, 1305 "RAS internal register access blocked\n"); 1306 } 1307 1308 return ret; 1309 } 1310 1311 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1312 enum ta_ras_status ras_status) 1313 { 1314 int ret = -EINVAL; 1315 1316 switch (ras_status) { 1317 case TA_RAS_STATUS__SUCCESS: 1318 ret = 0; 1319 break; 1320 case TA_RAS_STATUS__RESET_NEEDED: 1321 ret = -EAGAIN; 1322 break; 1323 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1324 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1325 break; 1326 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1327 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1328 break; 1329 default: 1330 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1331 } 1332 1333 return ret; 1334 } 1335 1336 int psp_ras_enable_features(struct psp_context *psp, 1337 union ta_ras_cmd_input *info, bool enable) 1338 { 1339 struct ta_ras_shared_memory *ras_cmd; 1340 int ret; 1341 1342 if (!psp->ras.ras_initialized) 1343 return -EINVAL; 1344 1345 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1346 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1347 1348 if (enable) 1349 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1350 else 1351 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1352 1353 ras_cmd->ras_in_message = *info; 1354 1355 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1356 if (ret) 1357 return -EINVAL; 1358 1359 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1360 } 1361 1362 static int psp_ras_terminate(struct psp_context *psp) 1363 { 1364 int ret; 1365 1366 /* 1367 * TODO: bypass the terminate in sriov for now 1368 */ 1369 if (amdgpu_sriov_vf(psp->adev)) 1370 return 0; 1371 1372 if (!psp->ras.ras_initialized) 1373 return 0; 1374 1375 ret = psp_ras_unload(psp); 1376 if (ret) 1377 return ret; 1378 1379 psp->ras.ras_initialized = false; 1380 1381 /* free ras shared memory */ 1382 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1383 &psp->ras.ras_shared_mc_addr, 1384 &psp->ras.ras_shared_buf); 1385 1386 return 0; 1387 } 1388 1389 static int psp_ras_initialize(struct psp_context *psp) 1390 { 1391 int ret; 1392 uint32_t boot_cfg = 0xFF; 1393 struct amdgpu_device *adev = psp->adev; 1394 1395 /* 1396 * TODO: bypass the initialize in sriov for now 1397 */ 1398 if (amdgpu_sriov_vf(adev)) 1399 return 0; 1400 1401 if (!adev->psp.ta_ras_ucode_size || 1402 !adev->psp.ta_ras_start_addr) { 1403 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1404 return 0; 1405 } 1406 1407 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1408 /* query GECC enablement status from boot config 1409 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1410 */ 1411 ret = psp_boot_config_get(adev, &boot_cfg); 1412 if (ret) 1413 dev_warn(adev->dev, "PSP get boot config failed\n"); 1414 1415 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1416 if (!boot_cfg) { 1417 dev_info(adev->dev, "GECC is disabled\n"); 1418 } else { 1419 /* disable GECC in next boot cycle if ras is 1420 * disabled by module parameter amdgpu_ras_enable 1421 * and/or amdgpu_ras_mask, or boot_config_get call 1422 * is failed 1423 */ 1424 ret = psp_boot_config_set(adev, 0); 1425 if (ret) 1426 dev_warn(adev->dev, "PSP set boot config failed\n"); 1427 else 1428 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1429 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1430 } 1431 } else { 1432 if (1 == boot_cfg) { 1433 dev_info(adev->dev, "GECC is enabled\n"); 1434 } else { 1435 /* enable GECC in next boot cycle if it is disabled 1436 * in boot config, or force enable GECC if failed to 1437 * get boot configuration 1438 */ 1439 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1440 if (ret) 1441 dev_warn(adev->dev, "PSP set boot config failed\n"); 1442 else 1443 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1444 } 1445 } 1446 } 1447 1448 if (!psp->ras.ras_initialized) { 1449 ret = psp_ras_init_shared_buf(psp); 1450 if (ret) 1451 return ret; 1452 } 1453 1454 ret = psp_ras_load(psp); 1455 if (ret) 1456 return ret; 1457 1458 return 0; 1459 } 1460 1461 int psp_ras_trigger_error(struct psp_context *psp, 1462 struct ta_ras_trigger_error_input *info) 1463 { 1464 struct ta_ras_shared_memory *ras_cmd; 1465 int ret; 1466 1467 if (!psp->ras.ras_initialized) 1468 return -EINVAL; 1469 1470 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1471 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1472 1473 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1474 ras_cmd->ras_in_message.trigger_error = *info; 1475 1476 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1477 if (ret) 1478 return -EINVAL; 1479 1480 /* If err_event_athub occurs error inject was successful, however 1481 return status from TA is no long reliable */ 1482 if (amdgpu_ras_intr_triggered()) 1483 return 0; 1484 1485 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1486 } 1487 // ras end 1488 1489 // HDCP start 1490 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1491 { 1492 int ret; 1493 1494 /* 1495 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1496 * physical) for hdcp ta <-> Driver 1497 */ 1498 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1500 &psp->hdcp_context.hdcp_shared_bo, 1501 &psp->hdcp_context.hdcp_shared_mc_addr, 1502 &psp->hdcp_context.hdcp_shared_buf); 1503 1504 return ret; 1505 } 1506 1507 static int psp_hdcp_load(struct psp_context *psp) 1508 { 1509 int ret; 1510 struct psp_gfx_cmd_resp *cmd; 1511 1512 /* 1513 * TODO: bypass the loading in sriov for now 1514 */ 1515 if (amdgpu_sriov_vf(psp->adev)) 1516 return 0; 1517 1518 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1519 if (!cmd) 1520 return -ENOMEM; 1521 1522 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1523 psp->ta_hdcp_ucode_size); 1524 1525 psp_prep_ta_load_cmd_buf(cmd, 1526 psp->fw_pri_mc_addr, 1527 psp->ta_hdcp_ucode_size, 1528 psp->hdcp_context.hdcp_shared_mc_addr, 1529 PSP_HDCP_SHARED_MEM_SIZE); 1530 1531 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1532 1533 if (!ret) { 1534 psp->hdcp_context.hdcp_initialized = true; 1535 psp->hdcp_context.session_id = cmd->resp.session_id; 1536 mutex_init(&psp->hdcp_context.mutex); 1537 } 1538 1539 kfree(cmd); 1540 1541 return ret; 1542 } 1543 static int psp_hdcp_initialize(struct psp_context *psp) 1544 { 1545 int ret; 1546 1547 /* 1548 * TODO: bypass the initialize in sriov for now 1549 */ 1550 if (amdgpu_sriov_vf(psp->adev)) 1551 return 0; 1552 1553 if (!psp->adev->psp.ta_hdcp_ucode_size || 1554 !psp->adev->psp.ta_hdcp_start_addr) { 1555 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1556 return 0; 1557 } 1558 1559 if (!psp->hdcp_context.hdcp_initialized) { 1560 ret = psp_hdcp_init_shared_buf(psp); 1561 if (ret) 1562 return ret; 1563 } 1564 1565 ret = psp_hdcp_load(psp); 1566 if (ret) 1567 return ret; 1568 1569 return 0; 1570 } 1571 1572 static int psp_hdcp_unload(struct psp_context *psp) 1573 { 1574 int ret; 1575 struct psp_gfx_cmd_resp *cmd; 1576 1577 /* 1578 * TODO: bypass the unloading in sriov for now 1579 */ 1580 if (amdgpu_sriov_vf(psp->adev)) 1581 return 0; 1582 1583 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1584 if (!cmd) 1585 return -ENOMEM; 1586 1587 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1588 1589 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1590 1591 kfree(cmd); 1592 1593 return ret; 1594 } 1595 1596 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1597 { 1598 /* 1599 * TODO: bypass the loading in sriov for now 1600 */ 1601 if (amdgpu_sriov_vf(psp->adev)) 1602 return 0; 1603 1604 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1605 } 1606 1607 static int psp_hdcp_terminate(struct psp_context *psp) 1608 { 1609 int ret; 1610 1611 /* 1612 * TODO: bypass the terminate in sriov for now 1613 */ 1614 if (amdgpu_sriov_vf(psp->adev)) 1615 return 0; 1616 1617 if (!psp->hdcp_context.hdcp_initialized) { 1618 if (psp->hdcp_context.hdcp_shared_buf) 1619 goto out; 1620 else 1621 return 0; 1622 } 1623 1624 ret = psp_hdcp_unload(psp); 1625 if (ret) 1626 return ret; 1627 1628 psp->hdcp_context.hdcp_initialized = false; 1629 1630 out: 1631 /* free hdcp shared memory */ 1632 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1633 &psp->hdcp_context.hdcp_shared_mc_addr, 1634 &psp->hdcp_context.hdcp_shared_buf); 1635 1636 return 0; 1637 } 1638 // HDCP end 1639 1640 // DTM start 1641 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1642 { 1643 int ret; 1644 1645 /* 1646 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1647 * physical) for dtm ta <-> Driver 1648 */ 1649 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1650 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1651 &psp->dtm_context.dtm_shared_bo, 1652 &psp->dtm_context.dtm_shared_mc_addr, 1653 &psp->dtm_context.dtm_shared_buf); 1654 1655 return ret; 1656 } 1657 1658 static int psp_dtm_load(struct psp_context *psp) 1659 { 1660 int ret; 1661 struct psp_gfx_cmd_resp *cmd; 1662 1663 /* 1664 * TODO: bypass the loading in sriov for now 1665 */ 1666 if (amdgpu_sriov_vf(psp->adev)) 1667 return 0; 1668 1669 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1670 if (!cmd) 1671 return -ENOMEM; 1672 1673 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1674 1675 psp_prep_ta_load_cmd_buf(cmd, 1676 psp->fw_pri_mc_addr, 1677 psp->ta_dtm_ucode_size, 1678 psp->dtm_context.dtm_shared_mc_addr, 1679 PSP_DTM_SHARED_MEM_SIZE); 1680 1681 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1682 1683 if (!ret) { 1684 psp->dtm_context.dtm_initialized = true; 1685 psp->dtm_context.session_id = cmd->resp.session_id; 1686 mutex_init(&psp->dtm_context.mutex); 1687 } 1688 1689 kfree(cmd); 1690 1691 return ret; 1692 } 1693 1694 static int psp_dtm_initialize(struct psp_context *psp) 1695 { 1696 int ret; 1697 1698 /* 1699 * TODO: bypass the initialize in sriov for now 1700 */ 1701 if (amdgpu_sriov_vf(psp->adev)) 1702 return 0; 1703 1704 if (!psp->adev->psp.ta_dtm_ucode_size || 1705 !psp->adev->psp.ta_dtm_start_addr) { 1706 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1707 return 0; 1708 } 1709 1710 if (!psp->dtm_context.dtm_initialized) { 1711 ret = psp_dtm_init_shared_buf(psp); 1712 if (ret) 1713 return ret; 1714 } 1715 1716 ret = psp_dtm_load(psp); 1717 if (ret) 1718 return ret; 1719 1720 return 0; 1721 } 1722 1723 static int psp_dtm_unload(struct psp_context *psp) 1724 { 1725 int ret; 1726 struct psp_gfx_cmd_resp *cmd; 1727 1728 /* 1729 * TODO: bypass the unloading in sriov for now 1730 */ 1731 if (amdgpu_sriov_vf(psp->adev)) 1732 return 0; 1733 1734 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1735 if (!cmd) 1736 return -ENOMEM; 1737 1738 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1739 1740 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1741 1742 kfree(cmd); 1743 1744 return ret; 1745 } 1746 1747 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1748 { 1749 /* 1750 * TODO: bypass the loading in sriov for now 1751 */ 1752 if (amdgpu_sriov_vf(psp->adev)) 1753 return 0; 1754 1755 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1756 } 1757 1758 static int psp_dtm_terminate(struct psp_context *psp) 1759 { 1760 int ret; 1761 1762 /* 1763 * TODO: bypass the terminate in sriov for now 1764 */ 1765 if (amdgpu_sriov_vf(psp->adev)) 1766 return 0; 1767 1768 if (!psp->dtm_context.dtm_initialized) { 1769 if (psp->dtm_context.dtm_shared_buf) 1770 goto out; 1771 else 1772 return 0; 1773 } 1774 1775 ret = psp_dtm_unload(psp); 1776 if (ret) 1777 return ret; 1778 1779 psp->dtm_context.dtm_initialized = false; 1780 1781 out: 1782 /* free hdcp shared memory */ 1783 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1784 &psp->dtm_context.dtm_shared_mc_addr, 1785 &psp->dtm_context.dtm_shared_buf); 1786 1787 return 0; 1788 } 1789 // DTM end 1790 1791 // RAP start 1792 static int psp_rap_init_shared_buf(struct psp_context *psp) 1793 { 1794 int ret; 1795 1796 /* 1797 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1798 * physical) for rap ta <-> Driver 1799 */ 1800 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1801 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1802 &psp->rap_context.rap_shared_bo, 1803 &psp->rap_context.rap_shared_mc_addr, 1804 &psp->rap_context.rap_shared_buf); 1805 1806 return ret; 1807 } 1808 1809 static int psp_rap_load(struct psp_context *psp) 1810 { 1811 int ret; 1812 struct psp_gfx_cmd_resp *cmd; 1813 1814 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1815 if (!cmd) 1816 return -ENOMEM; 1817 1818 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1819 1820 psp_prep_ta_load_cmd_buf(cmd, 1821 psp->fw_pri_mc_addr, 1822 psp->ta_rap_ucode_size, 1823 psp->rap_context.rap_shared_mc_addr, 1824 PSP_RAP_SHARED_MEM_SIZE); 1825 1826 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1827 1828 if (!ret) { 1829 psp->rap_context.rap_initialized = true; 1830 psp->rap_context.session_id = cmd->resp.session_id; 1831 mutex_init(&psp->rap_context.mutex); 1832 } 1833 1834 kfree(cmd); 1835 1836 return ret; 1837 } 1838 1839 static int psp_rap_unload(struct psp_context *psp) 1840 { 1841 int ret; 1842 struct psp_gfx_cmd_resp *cmd; 1843 1844 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1845 if (!cmd) 1846 return -ENOMEM; 1847 1848 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1849 1850 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1851 1852 kfree(cmd); 1853 1854 return ret; 1855 } 1856 1857 static int psp_rap_initialize(struct psp_context *psp) 1858 { 1859 int ret; 1860 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1861 1862 /* 1863 * TODO: bypass the initialize in sriov for now 1864 */ 1865 if (amdgpu_sriov_vf(psp->adev)) 1866 return 0; 1867 1868 if (!psp->adev->psp.ta_rap_ucode_size || 1869 !psp->adev->psp.ta_rap_start_addr) { 1870 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1871 return 0; 1872 } 1873 1874 if (!psp->rap_context.rap_initialized) { 1875 ret = psp_rap_init_shared_buf(psp); 1876 if (ret) 1877 return ret; 1878 } 1879 1880 ret = psp_rap_load(psp); 1881 if (ret) 1882 return ret; 1883 1884 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1885 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1886 psp_rap_unload(psp); 1887 1888 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1889 &psp->rap_context.rap_shared_mc_addr, 1890 &psp->rap_context.rap_shared_buf); 1891 1892 psp->rap_context.rap_initialized = false; 1893 1894 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1895 ret, status); 1896 1897 return ret; 1898 } 1899 1900 return 0; 1901 } 1902 1903 static int psp_rap_terminate(struct psp_context *psp) 1904 { 1905 int ret; 1906 1907 if (!psp->rap_context.rap_initialized) 1908 return 0; 1909 1910 ret = psp_rap_unload(psp); 1911 1912 psp->rap_context.rap_initialized = false; 1913 1914 /* free rap shared memory */ 1915 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1916 &psp->rap_context.rap_shared_mc_addr, 1917 &psp->rap_context.rap_shared_buf); 1918 1919 return ret; 1920 } 1921 1922 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1923 { 1924 struct ta_rap_shared_memory *rap_cmd; 1925 int ret = 0; 1926 1927 if (!psp->rap_context.rap_initialized) 1928 return 0; 1929 1930 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1931 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1932 return -EINVAL; 1933 1934 mutex_lock(&psp->rap_context.mutex); 1935 1936 rap_cmd = (struct ta_rap_shared_memory *) 1937 psp->rap_context.rap_shared_buf; 1938 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1939 1940 rap_cmd->cmd_id = ta_cmd_id; 1941 rap_cmd->validation_method_id = METHOD_A; 1942 1943 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1944 if (ret) 1945 goto out_unlock; 1946 1947 if (status) 1948 *status = rap_cmd->rap_status; 1949 1950 out_unlock: 1951 mutex_unlock(&psp->rap_context.mutex); 1952 1953 return ret; 1954 } 1955 // RAP end 1956 1957 /* securedisplay start */ 1958 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1959 { 1960 int ret; 1961 1962 /* 1963 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1964 * physical) for sa ta <-> Driver 1965 */ 1966 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1967 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1968 &psp->securedisplay_context.securedisplay_shared_bo, 1969 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1970 &psp->securedisplay_context.securedisplay_shared_buf); 1971 1972 return ret; 1973 } 1974 1975 static int psp_securedisplay_load(struct psp_context *psp) 1976 { 1977 int ret; 1978 struct psp_gfx_cmd_resp *cmd; 1979 1980 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 1981 if (!cmd) 1982 return -ENOMEM; 1983 1984 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1985 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1986 1987 psp_prep_ta_load_cmd_buf(cmd, 1988 psp->fw_pri_mc_addr, 1989 psp->ta_securedisplay_ucode_size, 1990 psp->securedisplay_context.securedisplay_shared_mc_addr, 1991 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1992 1993 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1994 1995 if (ret) 1996 goto failed; 1997 1998 psp->securedisplay_context.securedisplay_initialized = true; 1999 psp->securedisplay_context.session_id = cmd->resp.session_id; 2000 mutex_init(&psp->securedisplay_context.mutex); 2001 2002 failed: 2003 kfree(cmd); 2004 return ret; 2005 } 2006 2007 static int psp_securedisplay_unload(struct psp_context *psp) 2008 { 2009 int ret; 2010 struct psp_gfx_cmd_resp *cmd; 2011 2012 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2013 if (!cmd) 2014 return -ENOMEM; 2015 2016 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 2017 2018 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2019 2020 kfree(cmd); 2021 2022 return ret; 2023 } 2024 2025 static int psp_securedisplay_initialize(struct psp_context *psp) 2026 { 2027 int ret; 2028 struct securedisplay_cmd *securedisplay_cmd; 2029 2030 /* 2031 * TODO: bypass the initialize in sriov for now 2032 */ 2033 if (amdgpu_sriov_vf(psp->adev)) 2034 return 0; 2035 2036 if (!psp->adev->psp.ta_securedisplay_ucode_size || 2037 !psp->adev->psp.ta_securedisplay_start_addr) { 2038 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2039 return 0; 2040 } 2041 2042 if (!psp->securedisplay_context.securedisplay_initialized) { 2043 ret = psp_securedisplay_init_shared_buf(psp); 2044 if (ret) 2045 return ret; 2046 } 2047 2048 ret = psp_securedisplay_load(psp); 2049 if (ret) 2050 return ret; 2051 2052 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2053 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2054 2055 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2056 if (ret) { 2057 psp_securedisplay_unload(psp); 2058 2059 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2060 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2061 &psp->securedisplay_context.securedisplay_shared_buf); 2062 2063 psp->securedisplay_context.securedisplay_initialized = false; 2064 2065 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2066 return -EINVAL; 2067 } 2068 2069 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2070 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2071 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2072 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2073 } 2074 2075 return 0; 2076 } 2077 2078 static int psp_securedisplay_terminate(struct psp_context *psp) 2079 { 2080 int ret; 2081 2082 /* 2083 * TODO:bypass the terminate in sriov for now 2084 */ 2085 if (amdgpu_sriov_vf(psp->adev)) 2086 return 0; 2087 2088 if (!psp->securedisplay_context.securedisplay_initialized) 2089 return 0; 2090 2091 ret = psp_securedisplay_unload(psp); 2092 if (ret) 2093 return ret; 2094 2095 psp->securedisplay_context.securedisplay_initialized = false; 2096 2097 /* free securedisplay shared memory */ 2098 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2099 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2100 &psp->securedisplay_context.securedisplay_shared_buf); 2101 2102 return ret; 2103 } 2104 2105 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2106 { 2107 int ret; 2108 2109 if (!psp->securedisplay_context.securedisplay_initialized) 2110 return -EINVAL; 2111 2112 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2113 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2114 return -EINVAL; 2115 2116 mutex_lock(&psp->securedisplay_context.mutex); 2117 2118 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 2119 2120 mutex_unlock(&psp->securedisplay_context.mutex); 2121 2122 return ret; 2123 } 2124 /* SECUREDISPLAY end */ 2125 2126 static int psp_hw_start(struct psp_context *psp) 2127 { 2128 struct amdgpu_device *adev = psp->adev; 2129 int ret; 2130 2131 if (!amdgpu_sriov_vf(adev)) { 2132 if ((is_psp_fw_valid(psp->kdb)) && 2133 (psp->funcs->bootloader_load_kdb != NULL)) { 2134 ret = psp_bootloader_load_kdb(psp); 2135 if (ret) { 2136 DRM_ERROR("PSP load kdb failed!\n"); 2137 return ret; 2138 } 2139 } 2140 2141 if ((is_psp_fw_valid(psp->spl)) && 2142 (psp->funcs->bootloader_load_spl != NULL)) { 2143 ret = psp_bootloader_load_spl(psp); 2144 if (ret) { 2145 DRM_ERROR("PSP load spl failed!\n"); 2146 return ret; 2147 } 2148 } 2149 2150 if ((is_psp_fw_valid(psp->sys)) && 2151 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2152 ret = psp_bootloader_load_sysdrv(psp); 2153 if (ret) { 2154 DRM_ERROR("PSP load sysdrv failed!\n"); 2155 return ret; 2156 } 2157 } 2158 2159 if ((is_psp_fw_valid(psp->sos)) && 2160 (psp->funcs->bootloader_load_sos != NULL)) { 2161 ret = psp_bootloader_load_sos(psp); 2162 if (ret) { 2163 DRM_ERROR("PSP load sos failed!\n"); 2164 return ret; 2165 } 2166 } 2167 } 2168 2169 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2170 if (ret) { 2171 DRM_ERROR("PSP create ring failed!\n"); 2172 return ret; 2173 } 2174 2175 ret = psp_tmr_init(psp); 2176 if (ret) { 2177 DRM_ERROR("PSP tmr init failed!\n"); 2178 return ret; 2179 } 2180 2181 /* 2182 * For ASICs with DF Cstate management centralized 2183 * to PMFW, TMR setup should be performed after PMFW 2184 * loaded and before other non-psp firmware loaded. 2185 */ 2186 if (psp->pmfw_centralized_cstate_management) { 2187 ret = psp_load_smu_fw(psp); 2188 if (ret) 2189 return ret; 2190 } 2191 2192 ret = psp_tmr_load(psp); 2193 if (ret) { 2194 DRM_ERROR("PSP load tmr failed!\n"); 2195 return ret; 2196 } 2197 2198 return 0; 2199 } 2200 2201 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2202 enum psp_gfx_fw_type *type) 2203 { 2204 switch (ucode->ucode_id) { 2205 case AMDGPU_UCODE_ID_SDMA0: 2206 *type = GFX_FW_TYPE_SDMA0; 2207 break; 2208 case AMDGPU_UCODE_ID_SDMA1: 2209 *type = GFX_FW_TYPE_SDMA1; 2210 break; 2211 case AMDGPU_UCODE_ID_SDMA2: 2212 *type = GFX_FW_TYPE_SDMA2; 2213 break; 2214 case AMDGPU_UCODE_ID_SDMA3: 2215 *type = GFX_FW_TYPE_SDMA3; 2216 break; 2217 case AMDGPU_UCODE_ID_SDMA4: 2218 *type = GFX_FW_TYPE_SDMA4; 2219 break; 2220 case AMDGPU_UCODE_ID_SDMA5: 2221 *type = GFX_FW_TYPE_SDMA5; 2222 break; 2223 case AMDGPU_UCODE_ID_SDMA6: 2224 *type = GFX_FW_TYPE_SDMA6; 2225 break; 2226 case AMDGPU_UCODE_ID_SDMA7: 2227 *type = GFX_FW_TYPE_SDMA7; 2228 break; 2229 case AMDGPU_UCODE_ID_CP_MES: 2230 *type = GFX_FW_TYPE_CP_MES; 2231 break; 2232 case AMDGPU_UCODE_ID_CP_MES_DATA: 2233 *type = GFX_FW_TYPE_MES_STACK; 2234 break; 2235 case AMDGPU_UCODE_ID_CP_CE: 2236 *type = GFX_FW_TYPE_CP_CE; 2237 break; 2238 case AMDGPU_UCODE_ID_CP_PFP: 2239 *type = GFX_FW_TYPE_CP_PFP; 2240 break; 2241 case AMDGPU_UCODE_ID_CP_ME: 2242 *type = GFX_FW_TYPE_CP_ME; 2243 break; 2244 case AMDGPU_UCODE_ID_CP_MEC1: 2245 *type = GFX_FW_TYPE_CP_MEC; 2246 break; 2247 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2248 *type = GFX_FW_TYPE_CP_MEC_ME1; 2249 break; 2250 case AMDGPU_UCODE_ID_CP_MEC2: 2251 *type = GFX_FW_TYPE_CP_MEC; 2252 break; 2253 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2254 *type = GFX_FW_TYPE_CP_MEC_ME2; 2255 break; 2256 case AMDGPU_UCODE_ID_RLC_G: 2257 *type = GFX_FW_TYPE_RLC_G; 2258 break; 2259 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2260 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2261 break; 2262 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2263 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2264 break; 2265 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2266 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2267 break; 2268 case AMDGPU_UCODE_ID_RLC_IRAM: 2269 *type = GFX_FW_TYPE_RLC_IRAM; 2270 break; 2271 case AMDGPU_UCODE_ID_RLC_DRAM: 2272 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2273 break; 2274 case AMDGPU_UCODE_ID_SMC: 2275 *type = GFX_FW_TYPE_SMU; 2276 break; 2277 case AMDGPU_UCODE_ID_UVD: 2278 *type = GFX_FW_TYPE_UVD; 2279 break; 2280 case AMDGPU_UCODE_ID_UVD1: 2281 *type = GFX_FW_TYPE_UVD1; 2282 break; 2283 case AMDGPU_UCODE_ID_VCE: 2284 *type = GFX_FW_TYPE_VCE; 2285 break; 2286 case AMDGPU_UCODE_ID_VCN: 2287 *type = GFX_FW_TYPE_VCN; 2288 break; 2289 case AMDGPU_UCODE_ID_VCN1: 2290 *type = GFX_FW_TYPE_VCN1; 2291 break; 2292 case AMDGPU_UCODE_ID_DMCU_ERAM: 2293 *type = GFX_FW_TYPE_DMCU_ERAM; 2294 break; 2295 case AMDGPU_UCODE_ID_DMCU_INTV: 2296 *type = GFX_FW_TYPE_DMCU_ISR; 2297 break; 2298 case AMDGPU_UCODE_ID_VCN0_RAM: 2299 *type = GFX_FW_TYPE_VCN0_RAM; 2300 break; 2301 case AMDGPU_UCODE_ID_VCN1_RAM: 2302 *type = GFX_FW_TYPE_VCN1_RAM; 2303 break; 2304 case AMDGPU_UCODE_ID_DMCUB: 2305 *type = GFX_FW_TYPE_DMUB; 2306 break; 2307 case AMDGPU_UCODE_ID_MAXIMUM: 2308 default: 2309 return -EINVAL; 2310 } 2311 2312 return 0; 2313 } 2314 2315 static void psp_print_fw_hdr(struct psp_context *psp, 2316 struct amdgpu_firmware_info *ucode) 2317 { 2318 struct amdgpu_device *adev = psp->adev; 2319 struct common_firmware_header *hdr; 2320 2321 switch (ucode->ucode_id) { 2322 case AMDGPU_UCODE_ID_SDMA0: 2323 case AMDGPU_UCODE_ID_SDMA1: 2324 case AMDGPU_UCODE_ID_SDMA2: 2325 case AMDGPU_UCODE_ID_SDMA3: 2326 case AMDGPU_UCODE_ID_SDMA4: 2327 case AMDGPU_UCODE_ID_SDMA5: 2328 case AMDGPU_UCODE_ID_SDMA6: 2329 case AMDGPU_UCODE_ID_SDMA7: 2330 hdr = (struct common_firmware_header *) 2331 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2332 amdgpu_ucode_print_sdma_hdr(hdr); 2333 break; 2334 case AMDGPU_UCODE_ID_CP_CE: 2335 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2336 amdgpu_ucode_print_gfx_hdr(hdr); 2337 break; 2338 case AMDGPU_UCODE_ID_CP_PFP: 2339 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2340 amdgpu_ucode_print_gfx_hdr(hdr); 2341 break; 2342 case AMDGPU_UCODE_ID_CP_ME: 2343 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2344 amdgpu_ucode_print_gfx_hdr(hdr); 2345 break; 2346 case AMDGPU_UCODE_ID_CP_MEC1: 2347 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2348 amdgpu_ucode_print_gfx_hdr(hdr); 2349 break; 2350 case AMDGPU_UCODE_ID_RLC_G: 2351 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2352 amdgpu_ucode_print_rlc_hdr(hdr); 2353 break; 2354 case AMDGPU_UCODE_ID_SMC: 2355 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2356 amdgpu_ucode_print_smc_hdr(hdr); 2357 break; 2358 default: 2359 break; 2360 } 2361 } 2362 2363 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2364 struct psp_gfx_cmd_resp *cmd) 2365 { 2366 int ret; 2367 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2368 2369 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 2370 2371 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2372 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2373 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2374 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2375 2376 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2377 if (ret) 2378 DRM_ERROR("Unknown firmware type\n"); 2379 2380 return ret; 2381 } 2382 2383 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2384 struct amdgpu_firmware_info *ucode) 2385 { 2386 int ret = 0; 2387 2388 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd); 2389 if (ret) 2390 return ret; 2391 2392 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 2393 psp->fence_buf_mc_addr); 2394 2395 return ret; 2396 } 2397 2398 static int psp_load_smu_fw(struct psp_context *psp) 2399 { 2400 int ret; 2401 struct amdgpu_device *adev = psp->adev; 2402 struct amdgpu_firmware_info *ucode = 2403 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2404 struct amdgpu_ras *ras = psp->ras.ras; 2405 2406 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2407 return 0; 2408 2409 if ((amdgpu_in_reset(adev) && 2410 ras && adev->ras_enabled && 2411 (adev->asic_type == CHIP_ARCTURUS || 2412 adev->asic_type == CHIP_VEGA20))) { 2413 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2414 if (ret) { 2415 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2416 } 2417 } 2418 2419 ret = psp_execute_non_psp_fw_load(psp, ucode); 2420 2421 if (ret) 2422 DRM_ERROR("PSP load smu failed!\n"); 2423 2424 return ret; 2425 } 2426 2427 static bool fw_load_skip_check(struct psp_context *psp, 2428 struct amdgpu_firmware_info *ucode) 2429 { 2430 if (!ucode->fw) 2431 return true; 2432 2433 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2434 (psp_smu_reload_quirk(psp) || 2435 psp->autoload_supported || 2436 psp->pmfw_centralized_cstate_management)) 2437 return true; 2438 2439 if (amdgpu_sriov_vf(psp->adev) && 2440 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2441 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2442 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2443 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2444 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2445 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2446 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2447 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2448 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2449 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2450 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2451 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2452 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2453 /*skip ucode loading in SRIOV VF */ 2454 return true; 2455 2456 if (psp->autoload_supported && 2457 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2458 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2459 /* skip mec JT when autoload is enabled */ 2460 return true; 2461 2462 return false; 2463 } 2464 2465 int psp_load_fw_list(struct psp_context *psp, 2466 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2467 { 2468 int ret = 0, i; 2469 struct amdgpu_firmware_info *ucode; 2470 2471 for (i = 0; i < ucode_count; ++i) { 2472 ucode = ucode_list[i]; 2473 psp_print_fw_hdr(psp, ucode); 2474 ret = psp_execute_non_psp_fw_load(psp, ucode); 2475 if (ret) 2476 return ret; 2477 } 2478 return ret; 2479 } 2480 2481 static int psp_load_non_psp_fw(struct psp_context *psp) 2482 { 2483 int i, ret; 2484 struct amdgpu_firmware_info *ucode; 2485 struct amdgpu_device *adev = psp->adev; 2486 2487 if (psp->autoload_supported && 2488 !psp->pmfw_centralized_cstate_management) { 2489 ret = psp_load_smu_fw(psp); 2490 if (ret) 2491 return ret; 2492 } 2493 2494 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2495 ucode = &adev->firmware.ucode[i]; 2496 2497 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2498 !fw_load_skip_check(psp, ucode)) { 2499 ret = psp_load_smu_fw(psp); 2500 if (ret) 2501 return ret; 2502 continue; 2503 } 2504 2505 if (fw_load_skip_check(psp, ucode)) 2506 continue; 2507 2508 if (psp->autoload_supported && 2509 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2510 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2511 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2512 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2513 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2514 /* PSP only receive one SDMA fw for sienna_cichlid, 2515 * as all four sdma fw are same */ 2516 continue; 2517 2518 psp_print_fw_hdr(psp, ucode); 2519 2520 ret = psp_execute_non_psp_fw_load(psp, ucode); 2521 if (ret) 2522 return ret; 2523 2524 /* Start rlc autoload after psp recieved all the gfx firmware */ 2525 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2526 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2527 ret = psp_rlc_autoload_start(psp); 2528 if (ret) { 2529 DRM_ERROR("Failed to start rlc autoload\n"); 2530 return ret; 2531 } 2532 } 2533 } 2534 2535 return 0; 2536 } 2537 2538 static int psp_load_fw(struct amdgpu_device *adev) 2539 { 2540 int ret; 2541 struct psp_context *psp = &adev->psp; 2542 2543 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2544 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2545 goto skip_memalloc; 2546 } 2547 2548 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2549 if (!psp->cmd) 2550 return -ENOMEM; 2551 2552 if (amdgpu_sriov_vf(adev)) { 2553 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2554 AMDGPU_GEM_DOMAIN_VRAM, 2555 &psp->fw_pri_bo, 2556 &psp->fw_pri_mc_addr, 2557 &psp->fw_pri_buf); 2558 } else { 2559 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2560 AMDGPU_GEM_DOMAIN_GTT, 2561 &psp->fw_pri_bo, 2562 &psp->fw_pri_mc_addr, 2563 &psp->fw_pri_buf); 2564 } 2565 2566 if (ret) 2567 goto failed; 2568 2569 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2570 AMDGPU_GEM_DOMAIN_VRAM, 2571 &psp->fence_buf_bo, 2572 &psp->fence_buf_mc_addr, 2573 &psp->fence_buf); 2574 if (ret) 2575 goto failed; 2576 2577 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2578 AMDGPU_GEM_DOMAIN_VRAM, 2579 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2580 (void **)&psp->cmd_buf_mem); 2581 if (ret) 2582 goto failed; 2583 2584 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2585 2586 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2587 if (ret) { 2588 DRM_ERROR("PSP ring init failed!\n"); 2589 goto failed; 2590 } 2591 2592 skip_memalloc: 2593 ret = psp_hw_start(psp); 2594 if (ret) 2595 goto failed; 2596 2597 ret = psp_load_non_psp_fw(psp); 2598 if (ret) 2599 goto failed; 2600 2601 ret = psp_asd_load(psp); 2602 if (ret) { 2603 DRM_ERROR("PSP load asd failed!\n"); 2604 return ret; 2605 } 2606 2607 ret = psp_rl_load(adev); 2608 if (ret) { 2609 DRM_ERROR("PSP load RL failed!\n"); 2610 return ret; 2611 } 2612 2613 if (psp->adev->psp.ta_fw) { 2614 ret = psp_ras_initialize(psp); 2615 if (ret) 2616 dev_err(psp->adev->dev, 2617 "RAS: Failed to initialize RAS\n"); 2618 2619 ret = psp_hdcp_initialize(psp); 2620 if (ret) 2621 dev_err(psp->adev->dev, 2622 "HDCP: Failed to initialize HDCP\n"); 2623 2624 ret = psp_dtm_initialize(psp); 2625 if (ret) 2626 dev_err(psp->adev->dev, 2627 "DTM: Failed to initialize DTM\n"); 2628 2629 ret = psp_rap_initialize(psp); 2630 if (ret) 2631 dev_err(psp->adev->dev, 2632 "RAP: Failed to initialize RAP\n"); 2633 2634 ret = psp_securedisplay_initialize(psp); 2635 if (ret) 2636 dev_err(psp->adev->dev, 2637 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2638 } 2639 2640 return 0; 2641 2642 failed: 2643 /* 2644 * all cleanup jobs (xgmi terminate, ras terminate, 2645 * ring destroy, cmd/fence/fw buffers destory, 2646 * psp->cmd destory) are delayed to psp_hw_fini 2647 */ 2648 return ret; 2649 } 2650 2651 static int psp_hw_init(void *handle) 2652 { 2653 int ret; 2654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2655 2656 mutex_lock(&adev->firmware.mutex); 2657 /* 2658 * This sequence is just used on hw_init only once, no need on 2659 * resume. 2660 */ 2661 ret = amdgpu_ucode_init_bo(adev); 2662 if (ret) 2663 goto failed; 2664 2665 ret = psp_load_fw(adev); 2666 if (ret) { 2667 DRM_ERROR("PSP firmware loading failed\n"); 2668 goto failed; 2669 } 2670 2671 mutex_unlock(&adev->firmware.mutex); 2672 return 0; 2673 2674 failed: 2675 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2676 mutex_unlock(&adev->firmware.mutex); 2677 return -EINVAL; 2678 } 2679 2680 static int psp_hw_fini(void *handle) 2681 { 2682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2683 struct psp_context *psp = &adev->psp; 2684 2685 if (psp->adev->psp.ta_fw) { 2686 psp_ras_terminate(psp); 2687 psp_securedisplay_terminate(psp); 2688 psp_rap_terminate(psp); 2689 psp_dtm_terminate(psp); 2690 psp_hdcp_terminate(psp); 2691 } 2692 2693 psp_asd_unload(psp); 2694 2695 psp_tmr_terminate(psp); 2696 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2697 2698 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2699 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2700 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2701 &psp->fence_buf_mc_addr, &psp->fence_buf); 2702 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2703 (void **)&psp->cmd_buf_mem); 2704 2705 kfree(psp->cmd); 2706 psp->cmd = NULL; 2707 2708 return 0; 2709 } 2710 2711 static int psp_suspend(void *handle) 2712 { 2713 int ret; 2714 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2715 struct psp_context *psp = &adev->psp; 2716 2717 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2718 psp->xgmi_context.initialized == 1) { 2719 ret = psp_xgmi_terminate(psp); 2720 if (ret) { 2721 DRM_ERROR("Failed to terminate xgmi ta\n"); 2722 return ret; 2723 } 2724 } 2725 2726 if (psp->adev->psp.ta_fw) { 2727 ret = psp_ras_terminate(psp); 2728 if (ret) { 2729 DRM_ERROR("Failed to terminate ras ta\n"); 2730 return ret; 2731 } 2732 ret = psp_hdcp_terminate(psp); 2733 if (ret) { 2734 DRM_ERROR("Failed to terminate hdcp ta\n"); 2735 return ret; 2736 } 2737 ret = psp_dtm_terminate(psp); 2738 if (ret) { 2739 DRM_ERROR("Failed to terminate dtm ta\n"); 2740 return ret; 2741 } 2742 ret = psp_rap_terminate(psp); 2743 if (ret) { 2744 DRM_ERROR("Failed to terminate rap ta\n"); 2745 return ret; 2746 } 2747 ret = psp_securedisplay_terminate(psp); 2748 if (ret) { 2749 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2750 return ret; 2751 } 2752 } 2753 2754 ret = psp_asd_unload(psp); 2755 if (ret) { 2756 DRM_ERROR("Failed to unload asd\n"); 2757 return ret; 2758 } 2759 2760 ret = psp_tmr_terminate(psp); 2761 if (ret) { 2762 DRM_ERROR("Failed to terminate tmr\n"); 2763 return ret; 2764 } 2765 2766 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2767 if (ret) { 2768 DRM_ERROR("PSP ring stop failed\n"); 2769 return ret; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int psp_resume(void *handle) 2776 { 2777 int ret; 2778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2779 struct psp_context *psp = &adev->psp; 2780 2781 DRM_INFO("PSP is resuming...\n"); 2782 2783 if (psp->mem_train_ctx.enable_mem_training) { 2784 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2785 if (ret) { 2786 DRM_ERROR("Failed to process memory training!\n"); 2787 return ret; 2788 } 2789 } 2790 2791 mutex_lock(&adev->firmware.mutex); 2792 2793 ret = psp_hw_start(psp); 2794 if (ret) 2795 goto failed; 2796 2797 ret = psp_load_non_psp_fw(psp); 2798 if (ret) 2799 goto failed; 2800 2801 ret = psp_asd_load(psp); 2802 if (ret) { 2803 DRM_ERROR("PSP load asd failed!\n"); 2804 goto failed; 2805 } 2806 2807 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2808 ret = psp_xgmi_initialize(psp); 2809 /* Warning the XGMI seesion initialize failure 2810 * Instead of stop driver initialization 2811 */ 2812 if (ret) 2813 dev_err(psp->adev->dev, 2814 "XGMI: Failed to initialize XGMI session\n"); 2815 } 2816 2817 if (psp->adev->psp.ta_fw) { 2818 ret = psp_ras_initialize(psp); 2819 if (ret) 2820 dev_err(psp->adev->dev, 2821 "RAS: Failed to initialize RAS\n"); 2822 2823 ret = psp_hdcp_initialize(psp); 2824 if (ret) 2825 dev_err(psp->adev->dev, 2826 "HDCP: Failed to initialize HDCP\n"); 2827 2828 ret = psp_dtm_initialize(psp); 2829 if (ret) 2830 dev_err(psp->adev->dev, 2831 "DTM: Failed to initialize DTM\n"); 2832 2833 ret = psp_rap_initialize(psp); 2834 if (ret) 2835 dev_err(psp->adev->dev, 2836 "RAP: Failed to initialize RAP\n"); 2837 2838 ret = psp_securedisplay_initialize(psp); 2839 if (ret) 2840 dev_err(psp->adev->dev, 2841 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2842 } 2843 2844 mutex_unlock(&adev->firmware.mutex); 2845 2846 return 0; 2847 2848 failed: 2849 DRM_ERROR("PSP resume failed\n"); 2850 mutex_unlock(&adev->firmware.mutex); 2851 return ret; 2852 } 2853 2854 int psp_gpu_reset(struct amdgpu_device *adev) 2855 { 2856 int ret; 2857 2858 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2859 return 0; 2860 2861 mutex_lock(&adev->psp.mutex); 2862 ret = psp_mode1_reset(&adev->psp); 2863 mutex_unlock(&adev->psp.mutex); 2864 2865 return ret; 2866 } 2867 2868 int psp_rlc_autoload_start(struct psp_context *psp) 2869 { 2870 int ret; 2871 struct psp_gfx_cmd_resp *cmd; 2872 2873 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 2874 if (!cmd) 2875 return -ENOMEM; 2876 2877 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2878 2879 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2880 psp->fence_buf_mc_addr); 2881 kfree(cmd); 2882 return ret; 2883 } 2884 2885 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2886 uint64_t cmd_gpu_addr, int cmd_size) 2887 { 2888 struct amdgpu_firmware_info ucode = {0}; 2889 2890 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2891 AMDGPU_UCODE_ID_VCN0_RAM; 2892 ucode.mc_addr = cmd_gpu_addr; 2893 ucode.ucode_size = cmd_size; 2894 2895 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2896 } 2897 2898 int psp_ring_cmd_submit(struct psp_context *psp, 2899 uint64_t cmd_buf_mc_addr, 2900 uint64_t fence_mc_addr, 2901 int index) 2902 { 2903 unsigned int psp_write_ptr_reg = 0; 2904 struct psp_gfx_rb_frame *write_frame; 2905 struct psp_ring *ring = &psp->km_ring; 2906 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2907 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2908 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2909 struct amdgpu_device *adev = psp->adev; 2910 uint32_t ring_size_dw = ring->ring_size / 4; 2911 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2912 2913 /* KM (GPCOM) prepare write pointer */ 2914 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2915 2916 /* Update KM RB frame pointer to new frame */ 2917 /* write_frame ptr increments by size of rb_frame in bytes */ 2918 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2919 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2920 write_frame = ring_buffer_start; 2921 else 2922 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2923 /* Check invalid write_frame ptr address */ 2924 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2925 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2926 ring_buffer_start, ring_buffer_end, write_frame); 2927 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2928 return -EINVAL; 2929 } 2930 2931 /* Initialize KM RB frame */ 2932 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2933 2934 /* Update KM RB frame */ 2935 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2936 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2937 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2938 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2939 write_frame->fence_value = index; 2940 amdgpu_device_flush_hdp(adev, NULL); 2941 2942 /* Update the write Pointer in DWORDs */ 2943 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2944 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2945 return 0; 2946 } 2947 2948 int psp_init_asd_microcode(struct psp_context *psp, 2949 const char *chip_name) 2950 { 2951 struct amdgpu_device *adev = psp->adev; 2952 char fw_name[PSP_FW_NAME_LEN]; 2953 const struct psp_firmware_header_v1_0 *asd_hdr; 2954 int err = 0; 2955 2956 if (!chip_name) { 2957 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2958 return -EINVAL; 2959 } 2960 2961 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2962 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2963 if (err) 2964 goto out; 2965 2966 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2967 if (err) 2968 goto out; 2969 2970 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2971 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2972 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2973 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2974 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2975 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2976 return 0; 2977 out: 2978 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2979 release_firmware(adev->psp.asd_fw); 2980 adev->psp.asd_fw = NULL; 2981 return err; 2982 } 2983 2984 int psp_init_toc_microcode(struct psp_context *psp, 2985 const char *chip_name) 2986 { 2987 struct amdgpu_device *adev = psp->adev; 2988 char fw_name[PSP_FW_NAME_LEN]; 2989 const struct psp_firmware_header_v1_0 *toc_hdr; 2990 int err = 0; 2991 2992 if (!chip_name) { 2993 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2994 return -EINVAL; 2995 } 2996 2997 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2998 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2999 if (err) 3000 goto out; 3001 3002 err = amdgpu_ucode_validate(adev->psp.toc_fw); 3003 if (err) 3004 goto out; 3005 3006 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3007 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3008 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3009 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3010 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3011 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3012 return 0; 3013 out: 3014 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3015 release_firmware(adev->psp.toc_fw); 3016 adev->psp.toc_fw = NULL; 3017 return err; 3018 } 3019 3020 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3021 { 3022 const struct psp_firmware_header_v1_0 *sos_hdr; 3023 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3024 uint8_t *ucode_array_start_addr; 3025 3026 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3027 ucode_array_start_addr = (uint8_t *)sos_hdr + 3028 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3029 3030 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3031 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3032 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3033 3034 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3035 adev->psp.sys.start_addr = ucode_array_start_addr; 3036 3037 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3038 adev->psp.sos.start_addr = ucode_array_start_addr + 3039 le32_to_cpu(sos_hdr->sos.offset_bytes); 3040 } else { 3041 /* Load alternate PSP SOS FW */ 3042 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3043 3044 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3045 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3046 3047 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3048 adev->psp.sys.start_addr = ucode_array_start_addr + 3049 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3050 3051 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3052 adev->psp.sos.start_addr = ucode_array_start_addr + 3053 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3054 } 3055 3056 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3057 dev_warn(adev->dev, "PSP SOS FW not available"); 3058 return -EINVAL; 3059 } 3060 3061 return 0; 3062 } 3063 3064 int psp_init_sos_microcode(struct psp_context *psp, 3065 const char *chip_name) 3066 { 3067 struct amdgpu_device *adev = psp->adev; 3068 char fw_name[PSP_FW_NAME_LEN]; 3069 const struct psp_firmware_header_v1_0 *sos_hdr; 3070 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3071 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3072 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3073 int err = 0; 3074 uint8_t *ucode_array_start_addr; 3075 3076 if (!chip_name) { 3077 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3078 return -EINVAL; 3079 } 3080 3081 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3082 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3083 if (err) 3084 goto out; 3085 3086 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3087 if (err) 3088 goto out; 3089 3090 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3091 ucode_array_start_addr = (uint8_t *)sos_hdr + 3092 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3093 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3094 3095 switch (sos_hdr->header.header_version_major) { 3096 case 1: 3097 err = psp_init_sos_base_fw(adev); 3098 if (err) 3099 goto out; 3100 3101 if (sos_hdr->header.header_version_minor == 1) { 3102 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3103 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3104 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3105 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3106 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3107 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3108 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3109 } 3110 if (sos_hdr->header.header_version_minor == 2) { 3111 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3112 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3113 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3114 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3115 } 3116 if (sos_hdr->header.header_version_minor == 3) { 3117 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3118 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3119 adev->psp.toc.start_addr = ucode_array_start_addr + 3120 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3121 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3122 adev->psp.kdb.start_addr = ucode_array_start_addr + 3123 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3124 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3125 adev->psp.spl.start_addr = ucode_array_start_addr + 3126 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3127 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3128 adev->psp.rl.start_addr = ucode_array_start_addr + 3129 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3130 } 3131 break; 3132 default: 3133 dev_err(adev->dev, 3134 "unsupported psp sos firmware\n"); 3135 err = -EINVAL; 3136 goto out; 3137 } 3138 3139 return 0; 3140 out: 3141 dev_err(adev->dev, 3142 "failed to init sos firmware\n"); 3143 release_firmware(adev->psp.sos_fw); 3144 adev->psp.sos_fw = NULL; 3145 3146 return err; 3147 } 3148 3149 static int parse_ta_bin_descriptor(struct psp_context *psp, 3150 const struct ta_fw_bin_desc *desc, 3151 const struct ta_firmware_header_v2_0 *ta_hdr) 3152 { 3153 uint8_t *ucode_start_addr = NULL; 3154 3155 if (!psp || !desc || !ta_hdr) 3156 return -EINVAL; 3157 3158 ucode_start_addr = (uint8_t *)ta_hdr + 3159 le32_to_cpu(desc->offset_bytes) + 3160 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3161 3162 switch (desc->fw_type) { 3163 case TA_FW_TYPE_PSP_ASD: 3164 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3165 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3166 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3167 psp->asd_start_addr = ucode_start_addr; 3168 break; 3169 case TA_FW_TYPE_PSP_XGMI: 3170 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3171 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3172 psp->ta_xgmi_start_addr = ucode_start_addr; 3173 break; 3174 case TA_FW_TYPE_PSP_RAS: 3175 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3176 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3177 psp->ta_ras_start_addr = ucode_start_addr; 3178 break; 3179 case TA_FW_TYPE_PSP_HDCP: 3180 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3181 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3182 psp->ta_hdcp_start_addr = ucode_start_addr; 3183 break; 3184 case TA_FW_TYPE_PSP_DTM: 3185 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3186 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3187 psp->ta_dtm_start_addr = ucode_start_addr; 3188 break; 3189 case TA_FW_TYPE_PSP_RAP: 3190 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3191 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3192 psp->ta_rap_start_addr = ucode_start_addr; 3193 break; 3194 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3195 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3196 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3197 psp->ta_securedisplay_start_addr = ucode_start_addr; 3198 break; 3199 default: 3200 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3201 break; 3202 } 3203 3204 return 0; 3205 } 3206 3207 int psp_init_ta_microcode(struct psp_context *psp, 3208 const char *chip_name) 3209 { 3210 struct amdgpu_device *adev = psp->adev; 3211 char fw_name[PSP_FW_NAME_LEN]; 3212 const struct ta_firmware_header_v2_0 *ta_hdr; 3213 int err = 0; 3214 int ta_index = 0; 3215 3216 if (!chip_name) { 3217 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3218 return -EINVAL; 3219 } 3220 3221 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3222 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3223 if (err) 3224 goto out; 3225 3226 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3227 if (err) 3228 goto out; 3229 3230 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3231 3232 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3233 dev_err(adev->dev, "unsupported TA header version\n"); 3234 err = -EINVAL; 3235 goto out; 3236 } 3237 3238 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) { 3239 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3240 err = -EINVAL; 3241 goto out; 3242 } 3243 3244 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3245 err = parse_ta_bin_descriptor(psp, 3246 &ta_hdr->ta_fw_bin[ta_index], 3247 ta_hdr); 3248 if (err) 3249 goto out; 3250 } 3251 3252 return 0; 3253 out: 3254 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3255 release_firmware(adev->psp.ta_fw); 3256 adev->psp.ta_fw = NULL; 3257 return err; 3258 } 3259 3260 static int psp_set_clockgating_state(void *handle, 3261 enum amd_clockgating_state state) 3262 { 3263 return 0; 3264 } 3265 3266 static int psp_set_powergating_state(void *handle, 3267 enum amd_powergating_state state) 3268 { 3269 return 0; 3270 } 3271 3272 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3273 struct device_attribute *attr, 3274 char *buf) 3275 { 3276 struct drm_device *ddev = dev_get_drvdata(dev); 3277 struct amdgpu_device *adev = drm_to_adev(ddev); 3278 uint32_t fw_ver; 3279 int ret; 3280 3281 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3282 DRM_INFO("PSP block is not ready yet."); 3283 return -EBUSY; 3284 } 3285 3286 mutex_lock(&adev->psp.mutex); 3287 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3288 mutex_unlock(&adev->psp.mutex); 3289 3290 if (ret) { 3291 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3292 return ret; 3293 } 3294 3295 return sysfs_emit(buf, "%x\n", fw_ver); 3296 } 3297 3298 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3299 struct device_attribute *attr, 3300 const char *buf, 3301 size_t count) 3302 { 3303 struct drm_device *ddev = dev_get_drvdata(dev); 3304 struct amdgpu_device *adev = drm_to_adev(ddev); 3305 int ret, idx; 3306 char fw_name[100]; 3307 const struct firmware *usbc_pd_fw; 3308 struct amdgpu_bo *fw_buf_bo = NULL; 3309 uint64_t fw_pri_mc_addr; 3310 void *fw_pri_cpu_addr; 3311 3312 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3313 DRM_INFO("PSP block is not ready yet."); 3314 return -EBUSY; 3315 } 3316 3317 if (!drm_dev_enter(ddev, &idx)) 3318 return -ENODEV; 3319 3320 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3321 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3322 if (ret) 3323 goto fail; 3324 3325 /* LFB address which is aligned to 1MB boundary per PSP request */ 3326 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3327 AMDGPU_GEM_DOMAIN_VRAM, 3328 &fw_buf_bo, 3329 &fw_pri_mc_addr, 3330 &fw_pri_cpu_addr); 3331 if (ret) 3332 goto rel_buf; 3333 3334 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3335 3336 mutex_lock(&adev->psp.mutex); 3337 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3338 mutex_unlock(&adev->psp.mutex); 3339 3340 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3341 3342 rel_buf: 3343 release_firmware(usbc_pd_fw); 3344 fail: 3345 if (ret) { 3346 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3347 count = ret; 3348 } 3349 3350 drm_dev_exit(idx); 3351 return count; 3352 } 3353 3354 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3355 { 3356 int idx; 3357 3358 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3359 return; 3360 3361 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3362 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3363 3364 drm_dev_exit(idx); 3365 } 3366 3367 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3368 psp_usbc_pd_fw_sysfs_read, 3369 psp_usbc_pd_fw_sysfs_write); 3370 3371 int is_psp_fw_valid(struct psp_bin_desc bin) 3372 { 3373 return bin.size_bytes; 3374 } 3375 3376 const struct amd_ip_funcs psp_ip_funcs = { 3377 .name = "psp", 3378 .early_init = psp_early_init, 3379 .late_init = NULL, 3380 .sw_init = psp_sw_init, 3381 .sw_fini = psp_sw_fini, 3382 .hw_init = psp_hw_init, 3383 .hw_fini = psp_hw_fini, 3384 .suspend = psp_suspend, 3385 .resume = psp_resume, 3386 .is_idle = NULL, 3387 .check_soft_reset = NULL, 3388 .wait_for_idle = NULL, 3389 .soft_reset = NULL, 3390 .set_clockgating_state = psp_set_clockgating_state, 3391 .set_powergating_state = psp_set_powergating_state, 3392 }; 3393 3394 static int psp_sysfs_init(struct amdgpu_device *adev) 3395 { 3396 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3397 3398 if (ret) 3399 DRM_ERROR("Failed to create USBC PD FW control file!"); 3400 3401 return ret; 3402 } 3403 3404 static void psp_sysfs_fini(struct amdgpu_device *adev) 3405 { 3406 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3407 } 3408 3409 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3410 { 3411 .type = AMD_IP_BLOCK_TYPE_PSP, 3412 .major = 3, 3413 .minor = 1, 3414 .rev = 0, 3415 .funcs = &psp_ip_funcs, 3416 }; 3417 3418 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3419 { 3420 .type = AMD_IP_BLOCK_TYPE_PSP, 3421 .major = 10, 3422 .minor = 0, 3423 .rev = 0, 3424 .funcs = &psp_ip_funcs, 3425 }; 3426 3427 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3428 { 3429 .type = AMD_IP_BLOCK_TYPE_PSP, 3430 .major = 11, 3431 .minor = 0, 3432 .rev = 0, 3433 .funcs = &psp_ip_funcs, 3434 }; 3435 3436 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3437 { 3438 .type = AMD_IP_BLOCK_TYPE_PSP, 3439 .major = 12, 3440 .minor = 0, 3441 .rev = 0, 3442 .funcs = &psp_ip_funcs, 3443 }; 3444 3445 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3446 .type = AMD_IP_BLOCK_TYPE_PSP, 3447 .major = 13, 3448 .minor = 0, 3449 .rev = 0, 3450 .funcs = &psp_ip_funcs, 3451 }; 3452