1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 #include "psp_v10_0.h" 34 35 static void psp_set_funcs(struct amdgpu_device *adev); 36 37 static int psp_early_init(void *handle) 38 { 39 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 40 41 psp_set_funcs(adev); 42 43 return 0; 44 } 45 46 static int psp_sw_init(void *handle) 47 { 48 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 49 struct psp_context *psp = &adev->psp; 50 int ret; 51 52 switch (adev->asic_type) { 53 case CHIP_VEGA10: 54 psp->init_microcode = psp_v3_1_init_microcode; 55 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv; 56 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos; 57 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf; 58 psp->ring_init = psp_v3_1_ring_init; 59 psp->ring_create = psp_v3_1_ring_create; 60 psp->ring_destroy = psp_v3_1_ring_destroy; 61 psp->cmd_submit = psp_v3_1_cmd_submit; 62 psp->compare_sram_data = psp_v3_1_compare_sram_data; 63 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; 64 break; 65 case CHIP_RAVEN: 66 #if 0 67 psp->init_microcode = psp_v10_0_init_microcode; 68 #endif 69 psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf; 70 psp->ring_init = psp_v10_0_ring_init; 71 psp->ring_create = psp_v10_0_ring_create; 72 psp->ring_destroy = psp_v10_0_ring_destroy; 73 psp->cmd_submit = psp_v10_0_cmd_submit; 74 psp->compare_sram_data = psp_v10_0_compare_sram_data; 75 break; 76 default: 77 return -EINVAL; 78 } 79 80 psp->adev = adev; 81 82 ret = psp_init_microcode(psp); 83 if (ret) { 84 DRM_ERROR("Failed to load psp firmware!\n"); 85 return ret; 86 } 87 88 return 0; 89 } 90 91 static int psp_sw_fini(void *handle) 92 { 93 return 0; 94 } 95 96 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 97 uint32_t reg_val, uint32_t mask, bool check_changed) 98 { 99 uint32_t val; 100 int i; 101 struct amdgpu_device *adev = psp->adev; 102 103 for (i = 0; i < adev->usec_timeout; i++) { 104 val = RREG32(reg_index); 105 if (check_changed) { 106 if (val != reg_val) 107 return 0; 108 } else { 109 if ((val & mask) == reg_val) 110 return 0; 111 } 112 udelay(1); 113 } 114 115 return -ETIME; 116 } 117 118 static int 119 psp_cmd_submit_buf(struct psp_context *psp, 120 struct amdgpu_firmware_info *ucode, 121 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr, 122 int index) 123 { 124 int ret; 125 126 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 127 128 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 129 130 ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, 131 fence_mc_addr, index); 132 133 while (*((unsigned int *)psp->fence_buf) != index) { 134 msleep(1); 135 } 136 137 return ret; 138 } 139 140 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, 141 uint64_t tmr_mc, uint32_t size) 142 { 143 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 144 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 145 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 146 cmd->cmd.cmd_setup_tmr.buf_size = size; 147 } 148 149 /* Set up Trusted Memory Region */ 150 static int psp_tmr_init(struct psp_context *psp) 151 { 152 int ret; 153 154 /* 155 * Allocate 3M memory aligned to 1M from Frame Buffer (local 156 * physical). 157 * 158 * Note: this memory need be reserved till the driver 159 * uninitializes. 160 */ 161 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000, 162 AMDGPU_GEM_DOMAIN_VRAM, 163 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 164 165 return ret; 166 } 167 168 static int psp_tmr_load(struct psp_context *psp) 169 { 170 int ret; 171 struct psp_gfx_cmd_resp *cmd; 172 173 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 174 if (!cmd) 175 return -ENOMEM; 176 177 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000); 178 179 ret = psp_cmd_submit_buf(psp, NULL, cmd, 180 psp->fence_buf_mc_addr, 1); 181 if (ret) 182 goto failed; 183 184 kfree(cmd); 185 186 return 0; 187 188 failed: 189 kfree(cmd); 190 return ret; 191 } 192 193 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, 194 uint64_t asd_mc, uint64_t asd_mc_shared, 195 uint32_t size, uint32_t shared_size) 196 { 197 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 198 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 199 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 200 cmd->cmd.cmd_load_ta.app_len = size; 201 202 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); 203 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); 204 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; 205 } 206 207 static int psp_asd_init(struct psp_context *psp) 208 { 209 int ret; 210 211 /* 212 * Allocate 16k memory aligned to 4k from Frame Buffer (local 213 * physical) for shared ASD <-> Driver 214 */ 215 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, 216 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 217 &psp->asd_shared_bo, 218 &psp->asd_shared_mc_addr, 219 &psp->asd_shared_buf); 220 221 return ret; 222 } 223 224 static int psp_asd_load(struct psp_context *psp) 225 { 226 int ret; 227 struct psp_gfx_cmd_resp *cmd; 228 229 /* If PSP version doesn't match ASD version, asd loading will be failed. 230 * add workaround to bypass it for sriov now. 231 * TODO: add version check to make it common 232 */ 233 if (amdgpu_sriov_vf(psp->adev)) 234 return 0; 235 236 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 237 if (!cmd) 238 return -ENOMEM; 239 240 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 241 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size); 242 243 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr, 244 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); 245 246 ret = psp_cmd_submit_buf(psp, NULL, cmd, 247 psp->fence_buf_mc_addr, 2); 248 249 kfree(cmd); 250 251 return ret; 252 } 253 254 static int psp_hw_start(struct psp_context *psp) 255 { 256 int ret; 257 258 ret = psp_bootloader_load_sysdrv(psp); 259 if (ret) 260 return ret; 261 262 ret = psp_bootloader_load_sos(psp); 263 if (ret) 264 return ret; 265 266 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 267 if (ret) 268 return ret; 269 270 ret = psp_tmr_load(psp); 271 if (ret) 272 return ret; 273 274 ret = psp_asd_load(psp); 275 if (ret) 276 return ret; 277 278 return 0; 279 } 280 281 static int psp_np_fw_load(struct psp_context *psp) 282 { 283 int i, ret; 284 struct amdgpu_firmware_info *ucode; 285 struct amdgpu_device* adev = psp->adev; 286 287 for (i = 0; i < adev->firmware.max_ucodes; i++) { 288 ucode = &adev->firmware.ucode[i]; 289 if (!ucode->fw) 290 continue; 291 292 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 293 psp_smu_reload_quirk(psp)) 294 continue; 295 if (amdgpu_sriov_vf(adev) && 296 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 297 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 298 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) 299 /*skip ucode loading in SRIOV VF */ 300 continue; 301 302 ret = psp_prep_cmd_buf(ucode, psp->cmd); 303 if (ret) 304 return ret; 305 306 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, 307 psp->fence_buf_mc_addr, i + 3); 308 if (ret) 309 return ret; 310 311 #if 0 312 /* check if firmware loaded sucessfully */ 313 if (!amdgpu_psp_check_fw_loading_status(adev, i)) 314 return -EINVAL; 315 #endif 316 } 317 318 return 0; 319 } 320 321 static int psp_load_fw(struct amdgpu_device *adev) 322 { 323 int ret; 324 struct psp_context *psp = &adev->psp; 325 326 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 327 if (!psp->cmd) 328 return -ENOMEM; 329 330 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 331 AMDGPU_GEM_DOMAIN_GTT, 332 &psp->fw_pri_bo, 333 &psp->fw_pri_mc_addr, 334 &psp->fw_pri_buf); 335 if (ret) 336 goto failed; 337 338 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 339 AMDGPU_GEM_DOMAIN_VRAM, 340 &psp->fence_buf_bo, 341 &psp->fence_buf_mc_addr, 342 &psp->fence_buf); 343 if (ret) 344 goto failed_mem2; 345 346 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 347 AMDGPU_GEM_DOMAIN_VRAM, 348 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 349 (void **)&psp->cmd_buf_mem); 350 if (ret) 351 goto failed_mem1; 352 353 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 354 355 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 356 if (ret) 357 goto failed_mem; 358 359 ret = psp_tmr_init(psp); 360 if (ret) 361 goto failed_mem; 362 363 ret = psp_asd_init(psp); 364 if (ret) 365 goto failed_mem; 366 367 ret = psp_hw_start(psp); 368 if (ret) 369 goto failed_mem; 370 371 ret = psp_np_fw_load(psp); 372 if (ret) 373 goto failed_mem; 374 375 return 0; 376 377 failed_mem: 378 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, 379 &psp->cmd_buf_mc_addr, 380 (void **)&psp->cmd_buf_mem); 381 failed_mem1: 382 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 383 &psp->fence_buf_mc_addr, &psp->fence_buf); 384 failed_mem2: 385 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 386 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 387 failed: 388 kfree(psp->cmd); 389 psp->cmd = NULL; 390 return ret; 391 } 392 393 static int psp_hw_init(void *handle) 394 { 395 int ret; 396 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 397 398 399 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 400 return 0; 401 402 mutex_lock(&adev->firmware.mutex); 403 /* 404 * This sequence is just used on hw_init only once, no need on 405 * resume. 406 */ 407 ret = amdgpu_ucode_init_bo(adev); 408 if (ret) 409 goto failed; 410 411 ret = psp_load_fw(adev); 412 if (ret) { 413 DRM_ERROR("PSP firmware loading failed\n"); 414 goto failed; 415 } 416 417 mutex_unlock(&adev->firmware.mutex); 418 return 0; 419 420 failed: 421 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 422 mutex_unlock(&adev->firmware.mutex); 423 return -EINVAL; 424 } 425 426 static int psp_hw_fini(void *handle) 427 { 428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 429 struct psp_context *psp = &adev->psp; 430 431 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 432 return 0; 433 434 amdgpu_ucode_fini_bo(adev); 435 436 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 437 438 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 439 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 440 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 441 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 442 &psp->fence_buf_mc_addr, &psp->fence_buf); 443 amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr, 444 &psp->asd_shared_buf); 445 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 446 (void **)&psp->cmd_buf_mem); 447 448 kfree(psp->cmd); 449 psp->cmd = NULL; 450 451 return 0; 452 } 453 454 static int psp_suspend(void *handle) 455 { 456 return 0; 457 } 458 459 static int psp_resume(void *handle) 460 { 461 int ret; 462 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 463 struct psp_context *psp = &adev->psp; 464 465 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 466 return 0; 467 468 DRM_INFO("PSP is resuming...\n"); 469 470 mutex_lock(&adev->firmware.mutex); 471 472 ret = psp_hw_start(psp); 473 if (ret) 474 goto failed; 475 476 ret = psp_np_fw_load(psp); 477 if (ret) 478 goto failed; 479 480 mutex_unlock(&adev->firmware.mutex); 481 482 return 0; 483 484 failed: 485 DRM_ERROR("PSP resume failed\n"); 486 mutex_unlock(&adev->firmware.mutex); 487 return ret; 488 } 489 490 static bool psp_check_fw_loading_status(struct amdgpu_device *adev, 491 enum AMDGPU_UCODE_ID ucode_type) 492 { 493 struct amdgpu_firmware_info *ucode = NULL; 494 495 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 496 DRM_INFO("firmware is not loaded by PSP\n"); 497 return true; 498 } 499 500 if (!adev->firmware.fw_size) 501 return false; 502 503 ucode = &adev->firmware.ucode[ucode_type]; 504 if (!ucode->fw || !ucode->ucode_size) 505 return false; 506 507 return psp_compare_sram_data(&adev->psp, ucode, ucode_type); 508 } 509 510 static int psp_set_clockgating_state(void *handle, 511 enum amd_clockgating_state state) 512 { 513 return 0; 514 } 515 516 static int psp_set_powergating_state(void *handle, 517 enum amd_powergating_state state) 518 { 519 return 0; 520 } 521 522 const struct amd_ip_funcs psp_ip_funcs = { 523 .name = "psp", 524 .early_init = psp_early_init, 525 .late_init = NULL, 526 .sw_init = psp_sw_init, 527 .sw_fini = psp_sw_fini, 528 .hw_init = psp_hw_init, 529 .hw_fini = psp_hw_fini, 530 .suspend = psp_suspend, 531 .resume = psp_resume, 532 .is_idle = NULL, 533 .wait_for_idle = NULL, 534 .soft_reset = NULL, 535 .set_clockgating_state = psp_set_clockgating_state, 536 .set_powergating_state = psp_set_powergating_state, 537 }; 538 539 static const struct amdgpu_psp_funcs psp_funcs = { 540 .check_fw_loading_status = psp_check_fw_loading_status, 541 }; 542 543 static void psp_set_funcs(struct amdgpu_device *adev) 544 { 545 if (NULL == adev->firmware.funcs) 546 adev->firmware.funcs = &psp_funcs; 547 } 548 549 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 550 { 551 .type = AMD_IP_BLOCK_TYPE_PSP, 552 .major = 3, 553 .minor = 1, 554 .rev = 0, 555 .funcs = &psp_ip_funcs, 556 }; 557 558 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 559 { 560 .type = AMD_IP_BLOCK_TYPE_PSP, 561 .major = 10, 562 .minor = 0, 563 .rev = 0, 564 .funcs = &psp_ip_funcs, 565 }; 566