1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v3_1.h" 34 #include "psp_v10_0.h" 35 #include "psp_v11_0.h" 36 #include "psp_v11_0_8.h" 37 #include "psp_v12_0.h" 38 #include "psp_v13_0.h" 39 40 #include "amdgpu_ras.h" 41 #include "amdgpu_securedisplay.h" 42 #include "amdgpu_atomfirmware.h" 43 44 static int psp_sysfs_init(struct amdgpu_device *adev); 45 static void psp_sysfs_fini(struct amdgpu_device *adev); 46 47 static int psp_load_smu_fw(struct psp_context *psp); 48 49 /* 50 * Due to DF Cstate management centralized to PMFW, the firmware 51 * loading sequence will be updated as below: 52 * - Load KDB 53 * - Load SYS_DRV 54 * - Load tOS 55 * - Load PMFW 56 * - Setup TMR 57 * - Load other non-psp fw 58 * - Load ASD 59 * - Load XGMI/RAS/HDCP/DTM TA if any 60 * 61 * This new sequence is required for 62 * - Arcturus and onwards 63 * - Navi12 and onwards 64 */ 65 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 66 { 67 struct amdgpu_device *adev = psp->adev; 68 69 psp->pmfw_centralized_cstate_management = false; 70 71 if (amdgpu_sriov_vf(adev)) 72 return; 73 74 if (adev->flags & AMD_IS_APU) 75 return; 76 77 if ((adev->asic_type >= CHIP_ARCTURUS) || 78 (adev->asic_type >= CHIP_NAVI12)) 79 psp->pmfw_centralized_cstate_management = true; 80 } 81 82 static int psp_early_init(void *handle) 83 { 84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 85 struct psp_context *psp = &adev->psp; 86 87 switch (adev->asic_type) { 88 case CHIP_VEGA10: 89 case CHIP_VEGA12: 90 psp_v3_1_set_psp_funcs(psp); 91 psp->autoload_supported = false; 92 break; 93 case CHIP_RAVEN: 94 psp_v10_0_set_psp_funcs(psp); 95 psp->autoload_supported = false; 96 break; 97 case CHIP_VEGA20: 98 case CHIP_ARCTURUS: 99 psp_v11_0_set_psp_funcs(psp); 100 psp->autoload_supported = false; 101 break; 102 case CHIP_NAVI10: 103 case CHIP_NAVI14: 104 case CHIP_NAVI12: 105 case CHIP_SIENNA_CICHLID: 106 case CHIP_NAVY_FLOUNDER: 107 case CHIP_VANGOGH: 108 case CHIP_DIMGREY_CAVEFISH: 109 case CHIP_BEIGE_GOBY: 110 psp_v11_0_set_psp_funcs(psp); 111 psp->autoload_supported = true; 112 break; 113 case CHIP_RENOIR: 114 psp_v12_0_set_psp_funcs(psp); 115 break; 116 case CHIP_ALDEBARAN: 117 psp_v13_0_set_psp_funcs(psp); 118 break; 119 case CHIP_YELLOW_CARP: 120 psp_v13_0_set_psp_funcs(psp); 121 psp->autoload_supported = true; 122 break; 123 case CHIP_CYAN_SKILLFISH: 124 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 125 psp_v11_0_8_set_psp_funcs(psp); 126 psp->autoload_supported = false; 127 } 128 break; 129 default: 130 return -EINVAL; 131 } 132 133 psp->adev = adev; 134 135 psp_check_pmfw_centralized_cstate_management(psp); 136 137 return 0; 138 } 139 140 static void psp_memory_training_fini(struct psp_context *psp) 141 { 142 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 143 144 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 145 kfree(ctx->sys_cache); 146 ctx->sys_cache = NULL; 147 } 148 149 static int psp_memory_training_init(struct psp_context *psp) 150 { 151 int ret; 152 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 153 154 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 155 DRM_DEBUG("memory training is not supported!\n"); 156 return 0; 157 } 158 159 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 160 if (ctx->sys_cache == NULL) { 161 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 162 ret = -ENOMEM; 163 goto Err_out; 164 } 165 166 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 167 ctx->train_data_size, 168 ctx->p2c_train_data_offset, 169 ctx->c2p_train_data_offset); 170 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 171 return 0; 172 173 Err_out: 174 psp_memory_training_fini(psp); 175 return ret; 176 } 177 178 /* 179 * Helper funciton to query psp runtime database entry 180 * 181 * @adev: amdgpu_device pointer 182 * @entry_type: the type of psp runtime database entry 183 * @db_entry: runtime database entry pointer 184 * 185 * Return false if runtime database doesn't exit or entry is invalid 186 * or true if the specific database entry is found, and copy to @db_entry 187 */ 188 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 189 enum psp_runtime_entry_type entry_type, 190 void *db_entry) 191 { 192 uint64_t db_header_pos, db_dir_pos; 193 struct psp_runtime_data_header db_header = {0}; 194 struct psp_runtime_data_directory db_dir = {0}; 195 bool ret = false; 196 int i; 197 198 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 199 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 200 201 /* read runtime db header from vram */ 202 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 203 sizeof(struct psp_runtime_data_header), false); 204 205 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 206 /* runtime db doesn't exist, exit */ 207 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 208 return false; 209 } 210 211 /* read runtime database entry from vram */ 212 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 213 sizeof(struct psp_runtime_data_directory), false); 214 215 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 216 /* invalid db entry count, exit */ 217 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 218 return false; 219 } 220 221 /* look up for requested entry type */ 222 for (i = 0; i < db_dir.entry_count && !ret; i++) { 223 if (db_dir.entry_list[i].entry_type == entry_type) { 224 switch (entry_type) { 225 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 226 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 227 /* invalid db entry size */ 228 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 229 return false; 230 } 231 /* read runtime database entry */ 232 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 233 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 234 ret = true; 235 break; 236 default: 237 ret = false; 238 break; 239 } 240 } 241 } 242 243 return ret; 244 } 245 246 static int psp_sw_init(void *handle) 247 { 248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 249 struct psp_context *psp = &adev->psp; 250 int ret; 251 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 252 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 253 254 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 255 if (!psp->cmd) { 256 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 257 ret = -ENOMEM; 258 } 259 260 if (!amdgpu_sriov_vf(adev)) { 261 ret = psp_init_microcode(psp); 262 if (ret) { 263 DRM_ERROR("Failed to load psp firmware!\n"); 264 return ret; 265 } 266 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 267 ret = psp_init_ta_microcode(psp, "aldebaran"); 268 if (ret) { 269 DRM_ERROR("Failed to initialize ta microcode!\n"); 270 return ret; 271 } 272 } 273 274 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 275 if (psp_get_runtime_db_entry(adev, 276 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 277 &boot_cfg_entry)) { 278 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 279 if ((psp->boot_cfg_bitmask) & 280 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 281 /* If psp runtime database exists, then 282 * only enable two stage memory training 283 * when TWO_STAGE_DRAM_TRAINING bit is set 284 * in runtime database */ 285 mem_training_ctx->enable_mem_training = true; 286 } 287 288 } else { 289 /* If psp runtime database doesn't exist or 290 * is invalid, force enable two stage memory 291 * training */ 292 mem_training_ctx->enable_mem_training = true; 293 } 294 295 if (mem_training_ctx->enable_mem_training) { 296 ret = psp_memory_training_init(psp); 297 if (ret) { 298 DRM_ERROR("Failed to initialize memory training!\n"); 299 return ret; 300 } 301 302 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 303 if (ret) { 304 DRM_ERROR("Failed to process memory training!\n"); 305 return ret; 306 } 307 } 308 309 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 310 ret= psp_sysfs_init(adev); 311 if (ret) { 312 return ret; 313 } 314 } 315 316 return 0; 317 } 318 319 static int psp_sw_fini(void *handle) 320 { 321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 322 struct psp_context *psp = &adev->psp; 323 struct psp_gfx_cmd_resp *cmd = psp->cmd; 324 325 psp_memory_training_fini(psp); 326 if (psp->sos_fw) { 327 release_firmware(psp->sos_fw); 328 psp->sos_fw = NULL; 329 } 330 if (psp->asd_fw) { 331 release_firmware(psp->asd_fw); 332 psp->asd_fw = NULL; 333 } 334 if (psp->ta_fw) { 335 release_firmware(psp->ta_fw); 336 psp->ta_fw = NULL; 337 } 338 339 if (adev->asic_type == CHIP_NAVI10 || 340 adev->asic_type == CHIP_SIENNA_CICHLID) 341 psp_sysfs_fini(adev); 342 343 kfree(cmd); 344 cmd = NULL; 345 346 return 0; 347 } 348 349 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 350 uint32_t reg_val, uint32_t mask, bool check_changed) 351 { 352 uint32_t val; 353 int i; 354 struct amdgpu_device *adev = psp->adev; 355 356 if (psp->adev->no_hw_access) 357 return 0; 358 359 for (i = 0; i < adev->usec_timeout; i++) { 360 val = RREG32(reg_index); 361 if (check_changed) { 362 if (val != reg_val) 363 return 0; 364 } else { 365 if ((val & mask) == reg_val) 366 return 0; 367 } 368 udelay(1); 369 } 370 371 return -ETIME; 372 } 373 374 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 375 { 376 switch (cmd_id) { 377 case GFX_CMD_ID_LOAD_TA: 378 return "LOAD_TA"; 379 case GFX_CMD_ID_UNLOAD_TA: 380 return "UNLOAD_TA"; 381 case GFX_CMD_ID_INVOKE_CMD: 382 return "INVOKE_CMD"; 383 case GFX_CMD_ID_LOAD_ASD: 384 return "LOAD_ASD"; 385 case GFX_CMD_ID_SETUP_TMR: 386 return "SETUP_TMR"; 387 case GFX_CMD_ID_LOAD_IP_FW: 388 return "LOAD_IP_FW"; 389 case GFX_CMD_ID_DESTROY_TMR: 390 return "DESTROY_TMR"; 391 case GFX_CMD_ID_SAVE_RESTORE: 392 return "SAVE_RESTORE_IP_FW"; 393 case GFX_CMD_ID_SETUP_VMR: 394 return "SETUP_VMR"; 395 case GFX_CMD_ID_DESTROY_VMR: 396 return "DESTROY_VMR"; 397 case GFX_CMD_ID_PROG_REG: 398 return "PROG_REG"; 399 case GFX_CMD_ID_GET_FW_ATTESTATION: 400 return "GET_FW_ATTESTATION"; 401 case GFX_CMD_ID_LOAD_TOC: 402 return "ID_LOAD_TOC"; 403 case GFX_CMD_ID_AUTOLOAD_RLC: 404 return "AUTOLOAD_RLC"; 405 case GFX_CMD_ID_BOOT_CFG: 406 return "BOOT_CFG"; 407 default: 408 return "UNKNOWN CMD"; 409 } 410 } 411 412 static int 413 psp_cmd_submit_buf(struct psp_context *psp, 414 struct amdgpu_firmware_info *ucode, 415 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 416 { 417 int ret; 418 int index, idx; 419 int timeout = 20000; 420 bool ras_intr = false; 421 bool skip_unsupport = false; 422 423 if (psp->adev->no_hw_access) 424 return 0; 425 426 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 427 return 0; 428 429 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 430 431 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 432 433 index = atomic_inc_return(&psp->fence_value); 434 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 435 if (ret) { 436 atomic_dec(&psp->fence_value); 437 goto exit; 438 } 439 440 amdgpu_device_invalidate_hdp(psp->adev, NULL); 441 while (*((unsigned int *)psp->fence_buf) != index) { 442 if (--timeout == 0) 443 break; 444 /* 445 * Shouldn't wait for timeout when err_event_athub occurs, 446 * because gpu reset thread triggered and lock resource should 447 * be released for psp resume sequence. 448 */ 449 ras_intr = amdgpu_ras_intr_triggered(); 450 if (ras_intr) 451 break; 452 usleep_range(10, 100); 453 amdgpu_device_invalidate_hdp(psp->adev, NULL); 454 } 455 456 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 457 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 458 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 459 460 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 461 462 /* In some cases, psp response status is not 0 even there is no 463 * problem while the command is submitted. Some version of PSP FW 464 * doesn't write 0 to that field. 465 * So here we would like to only print a warning instead of an error 466 * during psp initialization to avoid breaking hw_init and it doesn't 467 * return -EINVAL. 468 */ 469 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 470 if (ucode) 471 DRM_WARN("failed to load ucode (%s) ", 472 amdgpu_ucode_name(ucode->ucode_id)); 473 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n", 474 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 475 psp->cmd_buf_mem->resp.status); 476 if (!timeout) { 477 ret = -EINVAL; 478 goto exit; 479 } 480 } 481 482 if (ucode) { 483 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 484 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 485 } 486 487 exit: 488 drm_dev_exit(idx); 489 return ret; 490 } 491 492 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 493 { 494 struct psp_gfx_cmd_resp *cmd = psp->cmd; 495 496 mutex_lock(&psp->mutex); 497 498 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 499 500 return cmd; 501 } 502 503 void release_psp_cmd_buf(struct psp_context *psp) 504 { 505 mutex_unlock(&psp->mutex); 506 } 507 508 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 509 struct psp_gfx_cmd_resp *cmd, 510 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 511 { 512 struct amdgpu_device *adev = psp->adev; 513 uint32_t size = amdgpu_bo_size(tmr_bo); 514 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 515 516 if (amdgpu_sriov_vf(psp->adev)) 517 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 518 else 519 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 520 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 521 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 522 cmd->cmd.cmd_setup_tmr.buf_size = size; 523 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 524 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 525 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 526 } 527 528 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 529 uint64_t pri_buf_mc, uint32_t size) 530 { 531 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 532 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 533 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 534 cmd->cmd.cmd_load_toc.toc_size = size; 535 } 536 537 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 538 static int psp_load_toc(struct psp_context *psp, 539 uint32_t *tmr_size) 540 { 541 int ret; 542 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 543 544 /* Copy toc to psp firmware private buffer */ 545 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 546 547 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 548 549 ret = psp_cmd_submit_buf(psp, NULL, cmd, 550 psp->fence_buf_mc_addr); 551 if (!ret) 552 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 553 554 release_psp_cmd_buf(psp); 555 556 return ret; 557 } 558 559 /* Set up Trusted Memory Region */ 560 static int psp_tmr_init(struct psp_context *psp) 561 { 562 int ret; 563 int tmr_size; 564 void *tmr_buf; 565 void **pptr; 566 567 /* 568 * According to HW engineer, they prefer the TMR address be "naturally 569 * aligned" , e.g. the start address be an integer divide of TMR size. 570 * 571 * Note: this memory need be reserved till the driver 572 * uninitializes. 573 */ 574 tmr_size = PSP_TMR_SIZE(psp->adev); 575 576 /* For ASICs support RLC autoload, psp will parse the toc 577 * and calculate the total size of TMR needed */ 578 if (!amdgpu_sriov_vf(psp->adev) && 579 psp->toc.start_addr && 580 psp->toc.size_bytes && 581 psp->fw_pri_buf) { 582 ret = psp_load_toc(psp, &tmr_size); 583 if (ret) { 584 DRM_ERROR("Failed to load toc\n"); 585 return ret; 586 } 587 } 588 589 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 590 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 591 AMDGPU_GEM_DOMAIN_VRAM, 592 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 593 594 return ret; 595 } 596 597 static bool psp_skip_tmr(struct psp_context *psp) 598 { 599 switch (psp->adev->asic_type) { 600 case CHIP_NAVI12: 601 case CHIP_SIENNA_CICHLID: 602 case CHIP_ALDEBARAN: 603 return true; 604 default: 605 return false; 606 } 607 } 608 609 static int psp_tmr_load(struct psp_context *psp) 610 { 611 int ret; 612 struct psp_gfx_cmd_resp *cmd; 613 614 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 615 * Already set up by host driver. 616 */ 617 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 618 return 0; 619 620 cmd = acquire_psp_cmd_buf(psp); 621 622 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 623 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 624 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 625 626 ret = psp_cmd_submit_buf(psp, NULL, cmd, 627 psp->fence_buf_mc_addr); 628 629 release_psp_cmd_buf(psp); 630 631 return ret; 632 } 633 634 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 635 struct psp_gfx_cmd_resp *cmd) 636 { 637 if (amdgpu_sriov_vf(psp->adev)) 638 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 639 else 640 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 641 } 642 643 static int psp_tmr_unload(struct psp_context *psp) 644 { 645 int ret; 646 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 647 648 psp_prep_tmr_unload_cmd_buf(psp, cmd); 649 DRM_INFO("free PSP TMR buffer\n"); 650 651 ret = psp_cmd_submit_buf(psp, NULL, cmd, 652 psp->fence_buf_mc_addr); 653 654 release_psp_cmd_buf(psp); 655 656 return ret; 657 } 658 659 static int psp_tmr_terminate(struct psp_context *psp) 660 { 661 int ret; 662 void *tmr_buf; 663 void **pptr; 664 665 ret = psp_tmr_unload(psp); 666 if (ret) 667 return ret; 668 669 /* free TMR memory buffer */ 670 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 671 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 672 673 return 0; 674 } 675 676 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 677 uint64_t *output_ptr) 678 { 679 int ret; 680 struct psp_gfx_cmd_resp *cmd; 681 682 if (!output_ptr) 683 return -EINVAL; 684 685 if (amdgpu_sriov_vf(psp->adev)) 686 return 0; 687 688 cmd = acquire_psp_cmd_buf(psp); 689 690 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 691 692 ret = psp_cmd_submit_buf(psp, NULL, cmd, 693 psp->fence_buf_mc_addr); 694 695 if (!ret) { 696 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 697 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 698 } 699 700 release_psp_cmd_buf(psp); 701 702 return ret; 703 } 704 705 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 706 { 707 struct psp_context *psp = &adev->psp; 708 struct psp_gfx_cmd_resp *cmd; 709 int ret; 710 711 if (amdgpu_sriov_vf(adev)) 712 return 0; 713 714 cmd = acquire_psp_cmd_buf(psp); 715 716 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 717 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 718 719 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 720 if (!ret) { 721 *boot_cfg = 722 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 723 } 724 725 release_psp_cmd_buf(psp); 726 727 return ret; 728 } 729 730 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 731 { 732 int ret; 733 struct psp_context *psp = &adev->psp; 734 struct psp_gfx_cmd_resp *cmd; 735 736 if (amdgpu_sriov_vf(adev)) 737 return 0; 738 739 cmd = acquire_psp_cmd_buf(psp); 740 741 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 742 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 743 cmd->cmd.boot_cfg.boot_config = boot_cfg; 744 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 745 746 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 747 748 release_psp_cmd_buf(psp); 749 750 return ret; 751 } 752 753 static int psp_rl_load(struct amdgpu_device *adev) 754 { 755 int ret; 756 struct psp_context *psp = &adev->psp; 757 struct psp_gfx_cmd_resp *cmd; 758 759 if (!is_psp_fw_valid(psp->rl)) 760 return 0; 761 762 cmd = acquire_psp_cmd_buf(psp); 763 764 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 765 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 766 767 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 768 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 769 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 770 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 771 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 772 773 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 774 775 release_psp_cmd_buf(psp); 776 777 return ret; 778 } 779 780 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 781 uint64_t asd_mc, uint32_t size) 782 { 783 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 784 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 785 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 786 cmd->cmd.cmd_load_ta.app_len = size; 787 788 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 789 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 790 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 791 } 792 793 static int psp_asd_load(struct psp_context *psp) 794 { 795 int ret; 796 struct psp_gfx_cmd_resp *cmd; 797 798 /* If PSP version doesn't match ASD version, asd loading will be failed. 799 * add workaround to bypass it for sriov now. 800 * TODO: add version check to make it common 801 */ 802 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size) 803 return 0; 804 805 cmd = acquire_psp_cmd_buf(psp); 806 807 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size); 808 809 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 810 psp->asd_ucode_size); 811 812 ret = psp_cmd_submit_buf(psp, NULL, cmd, 813 psp->fence_buf_mc_addr); 814 if (!ret) { 815 psp->asd_context.asd_initialized = true; 816 psp->asd_context.session_id = cmd->resp.session_id; 817 } 818 819 release_psp_cmd_buf(psp); 820 821 return ret; 822 } 823 824 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 825 uint32_t session_id) 826 { 827 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 828 cmd->cmd.cmd_unload_ta.session_id = session_id; 829 } 830 831 static int psp_asd_unload(struct psp_context *psp) 832 { 833 int ret; 834 struct psp_gfx_cmd_resp *cmd; 835 836 if (amdgpu_sriov_vf(psp->adev)) 837 return 0; 838 839 if (!psp->asd_context.asd_initialized) 840 return 0; 841 842 cmd = acquire_psp_cmd_buf(psp); 843 844 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 845 846 ret = psp_cmd_submit_buf(psp, NULL, cmd, 847 psp->fence_buf_mc_addr); 848 if (!ret) 849 psp->asd_context.asd_initialized = false; 850 851 release_psp_cmd_buf(psp); 852 853 return ret; 854 } 855 856 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 857 uint32_t id, uint32_t value) 858 { 859 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 860 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 861 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 862 } 863 864 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 865 uint32_t value) 866 { 867 struct psp_gfx_cmd_resp *cmd; 868 int ret = 0; 869 870 if (reg >= PSP_REG_LAST) 871 return -EINVAL; 872 873 cmd = acquire_psp_cmd_buf(psp); 874 875 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 876 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 877 if (ret) 878 DRM_ERROR("PSP failed to program reg id %d", reg); 879 880 release_psp_cmd_buf(psp); 881 882 return ret; 883 } 884 885 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 886 uint64_t ta_bin_mc, 887 uint32_t ta_bin_size, 888 uint64_t ta_shared_mc, 889 uint32_t ta_shared_size) 890 { 891 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 892 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 893 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 894 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 895 896 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 897 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 898 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 899 } 900 901 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 902 { 903 int ret; 904 905 /* 906 * Allocate 16k memory aligned to 4k from Frame Buffer (local 907 * physical) for xgmi ta <-> Driver 908 */ 909 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE, 910 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 911 &psp->xgmi_context.xgmi_shared_bo, 912 &psp->xgmi_context.xgmi_shared_mc_addr, 913 &psp->xgmi_context.xgmi_shared_buf); 914 915 return ret; 916 } 917 918 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 919 uint32_t ta_cmd_id, 920 uint32_t session_id) 921 { 922 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 923 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 924 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 925 } 926 927 static int psp_ta_invoke(struct psp_context *psp, 928 uint32_t ta_cmd_id, 929 uint32_t session_id) 930 { 931 int ret; 932 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 933 934 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 935 936 ret = psp_cmd_submit_buf(psp, NULL, cmd, 937 psp->fence_buf_mc_addr); 938 939 release_psp_cmd_buf(psp); 940 941 return ret; 942 } 943 944 static int psp_xgmi_load(struct psp_context *psp) 945 { 946 int ret; 947 struct psp_gfx_cmd_resp *cmd; 948 949 /* 950 * TODO: bypass the loading in sriov for now 951 */ 952 953 cmd = acquire_psp_cmd_buf(psp); 954 955 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size); 956 957 psp_prep_ta_load_cmd_buf(cmd, 958 psp->fw_pri_mc_addr, 959 psp->ta_xgmi_ucode_size, 960 psp->xgmi_context.xgmi_shared_mc_addr, 961 PSP_XGMI_SHARED_MEM_SIZE); 962 963 ret = psp_cmd_submit_buf(psp, NULL, cmd, 964 psp->fence_buf_mc_addr); 965 966 if (!ret) { 967 psp->xgmi_context.initialized = 1; 968 psp->xgmi_context.session_id = cmd->resp.session_id; 969 } 970 971 release_psp_cmd_buf(psp); 972 973 return ret; 974 } 975 976 static int psp_xgmi_unload(struct psp_context *psp) 977 { 978 int ret; 979 struct psp_gfx_cmd_resp *cmd; 980 struct amdgpu_device *adev = psp->adev; 981 982 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 983 if (adev->asic_type == CHIP_ARCTURUS || 984 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 985 return 0; 986 987 /* 988 * TODO: bypass the unloading in sriov for now 989 */ 990 991 cmd = acquire_psp_cmd_buf(psp); 992 993 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id); 994 995 ret = psp_cmd_submit_buf(psp, NULL, cmd, 996 psp->fence_buf_mc_addr); 997 998 release_psp_cmd_buf(psp); 999 1000 return ret; 1001 } 1002 1003 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1004 { 1005 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id); 1006 } 1007 1008 int psp_xgmi_terminate(struct psp_context *psp) 1009 { 1010 int ret; 1011 1012 if (!psp->xgmi_context.initialized) 1013 return 0; 1014 1015 ret = psp_xgmi_unload(psp); 1016 if (ret) 1017 return ret; 1018 1019 psp->xgmi_context.initialized = 0; 1020 1021 /* free xgmi shared memory */ 1022 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo, 1023 &psp->xgmi_context.xgmi_shared_mc_addr, 1024 &psp->xgmi_context.xgmi_shared_buf); 1025 1026 return 0; 1027 } 1028 1029 int psp_xgmi_initialize(struct psp_context *psp) 1030 { 1031 struct ta_xgmi_shared_memory *xgmi_cmd; 1032 int ret; 1033 1034 if (!psp->adev->psp.ta_fw || 1035 !psp->adev->psp.ta_xgmi_ucode_size || 1036 !psp->adev->psp.ta_xgmi_start_addr) 1037 return -ENOENT; 1038 1039 if (!psp->xgmi_context.initialized) { 1040 ret = psp_xgmi_init_shared_buf(psp); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 /* Load XGMI TA */ 1046 ret = psp_xgmi_load(psp); 1047 if (ret) 1048 return ret; 1049 1050 /* Initialize XGMI session */ 1051 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf); 1052 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1053 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1054 1055 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1056 1057 return ret; 1058 } 1059 1060 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1061 { 1062 struct ta_xgmi_shared_memory *xgmi_cmd; 1063 int ret; 1064 1065 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1066 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1067 1068 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1069 1070 /* Invoke xgmi ta to get hive id */ 1071 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1072 if (ret) 1073 return ret; 1074 1075 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1076 1077 return 0; 1078 } 1079 1080 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1081 { 1082 struct ta_xgmi_shared_memory *xgmi_cmd; 1083 int ret; 1084 1085 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1086 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1087 1088 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1089 1090 /* Invoke xgmi ta to get the node id */ 1091 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1092 if (ret) 1093 return ret; 1094 1095 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1096 1097 return 0; 1098 } 1099 1100 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1101 { 1102 return psp->adev->asic_type == CHIP_ALDEBARAN && 1103 psp->ta_xgmi_ucode_version >= 0x2000000b; 1104 } 1105 1106 int psp_xgmi_get_topology_info(struct psp_context *psp, 1107 int number_devices, 1108 struct psp_xgmi_topology_info *topology) 1109 { 1110 struct ta_xgmi_shared_memory *xgmi_cmd; 1111 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1112 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1113 int i; 1114 int ret; 1115 1116 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1117 return -EINVAL; 1118 1119 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1120 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1121 1122 /* Fill in the shared memory with topology information as input */ 1123 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1124 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1125 topology_info_input->num_nodes = number_devices; 1126 1127 for (i = 0; i < topology_info_input->num_nodes; i++) { 1128 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1129 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1130 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1131 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1132 } 1133 1134 /* Invoke xgmi ta to get the topology information */ 1135 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1136 if (ret) 1137 return ret; 1138 1139 /* Read the output topology information from the shared memory */ 1140 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1141 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1142 for (i = 0; i < topology->num_nodes; i++) { 1143 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1144 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1145 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 1146 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 1147 } 1148 1149 /* Invoke xgmi ta again to get the link information */ 1150 if (psp_xgmi_peer_link_info_supported(psp)) { 1151 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1152 1153 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1154 1155 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1156 1157 if (ret) 1158 return ret; 1159 1160 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1161 for (i = 0; i < topology->num_nodes; i++) 1162 topology->nodes[i].num_links = 1163 link_info_output->nodes[i].num_links; 1164 } 1165 1166 return 0; 1167 } 1168 1169 int psp_xgmi_set_topology_info(struct psp_context *psp, 1170 int number_devices, 1171 struct psp_xgmi_topology_info *topology) 1172 { 1173 struct ta_xgmi_shared_memory *xgmi_cmd; 1174 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1175 int i; 1176 1177 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1178 return -EINVAL; 1179 1180 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf; 1181 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1182 1183 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1184 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1185 topology_info_input->num_nodes = number_devices; 1186 1187 for (i = 0; i < topology_info_input->num_nodes; i++) { 1188 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1189 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1190 topology_info_input->nodes[i].is_sharing_enabled = 1; 1191 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1192 } 1193 1194 /* Invoke xgmi ta to set topology information */ 1195 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1196 } 1197 1198 // ras begin 1199 static int psp_ras_init_shared_buf(struct psp_context *psp) 1200 { 1201 int ret; 1202 1203 /* 1204 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1205 * physical) for ras ta <-> Driver 1206 */ 1207 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE, 1208 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1209 &psp->ras.ras_shared_bo, 1210 &psp->ras.ras_shared_mc_addr, 1211 &psp->ras.ras_shared_buf); 1212 1213 return ret; 1214 } 1215 1216 static int psp_ras_load(struct psp_context *psp) 1217 { 1218 int ret; 1219 struct psp_gfx_cmd_resp *cmd; 1220 struct ta_ras_shared_memory *ras_cmd; 1221 1222 /* 1223 * TODO: bypass the loading in sriov for now 1224 */ 1225 if (amdgpu_sriov_vf(psp->adev)) 1226 return 0; 1227 1228 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size); 1229 1230 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1231 1232 if (psp->adev->gmc.xgmi.connected_to_cpu) 1233 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1234 else 1235 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1236 1237 cmd = acquire_psp_cmd_buf(psp); 1238 1239 psp_prep_ta_load_cmd_buf(cmd, 1240 psp->fw_pri_mc_addr, 1241 psp->ta_ras_ucode_size, 1242 psp->ras.ras_shared_mc_addr, 1243 PSP_RAS_SHARED_MEM_SIZE); 1244 1245 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1246 psp->fence_buf_mc_addr); 1247 1248 if (!ret) { 1249 psp->ras.session_id = cmd->resp.session_id; 1250 1251 if (!ras_cmd->ras_status) 1252 psp->ras.ras_initialized = true; 1253 else 1254 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1255 } 1256 1257 release_psp_cmd_buf(psp); 1258 1259 if (ret || ras_cmd->ras_status) 1260 amdgpu_ras_fini(psp->adev); 1261 1262 return ret; 1263 } 1264 1265 static int psp_ras_unload(struct psp_context *psp) 1266 { 1267 int ret; 1268 struct psp_gfx_cmd_resp *cmd; 1269 1270 /* 1271 * TODO: bypass the unloading in sriov for now 1272 */ 1273 if (amdgpu_sriov_vf(psp->adev)) 1274 return 0; 1275 1276 cmd = acquire_psp_cmd_buf(psp); 1277 1278 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id); 1279 1280 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1281 psp->fence_buf_mc_addr); 1282 1283 release_psp_cmd_buf(psp); 1284 1285 return ret; 1286 } 1287 1288 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1289 { 1290 struct ta_ras_shared_memory *ras_cmd; 1291 int ret; 1292 1293 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1294 1295 /* 1296 * TODO: bypass the loading in sriov for now 1297 */ 1298 if (amdgpu_sriov_vf(psp->adev)) 1299 return 0; 1300 1301 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id); 1302 1303 if (amdgpu_ras_intr_triggered()) 1304 return ret; 1305 1306 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1307 { 1308 DRM_WARN("RAS: Unsupported Interface"); 1309 return -EINVAL; 1310 } 1311 1312 if (!ret) { 1313 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1314 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1315 1316 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1317 } 1318 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1319 dev_warn(psp->adev->dev, 1320 "RAS internal register access blocked\n"); 1321 } 1322 1323 return ret; 1324 } 1325 1326 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1327 enum ta_ras_status ras_status) 1328 { 1329 int ret = -EINVAL; 1330 1331 switch (ras_status) { 1332 case TA_RAS_STATUS__SUCCESS: 1333 ret = 0; 1334 break; 1335 case TA_RAS_STATUS__RESET_NEEDED: 1336 ret = -EAGAIN; 1337 break; 1338 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1339 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1340 break; 1341 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1342 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1343 break; 1344 default: 1345 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1346 } 1347 1348 return ret; 1349 } 1350 1351 int psp_ras_enable_features(struct psp_context *psp, 1352 union ta_ras_cmd_input *info, bool enable) 1353 { 1354 struct ta_ras_shared_memory *ras_cmd; 1355 int ret; 1356 1357 if (!psp->ras.ras_initialized) 1358 return -EINVAL; 1359 1360 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1361 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1362 1363 if (enable) 1364 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1365 else 1366 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1367 1368 ras_cmd->ras_in_message = *info; 1369 1370 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1371 if (ret) 1372 return -EINVAL; 1373 1374 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1375 } 1376 1377 static int psp_ras_terminate(struct psp_context *psp) 1378 { 1379 int ret; 1380 1381 /* 1382 * TODO: bypass the terminate in sriov for now 1383 */ 1384 if (amdgpu_sriov_vf(psp->adev)) 1385 return 0; 1386 1387 if (!psp->ras.ras_initialized) 1388 return 0; 1389 1390 ret = psp_ras_unload(psp); 1391 if (ret) 1392 return ret; 1393 1394 psp->ras.ras_initialized = false; 1395 1396 /* free ras shared memory */ 1397 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo, 1398 &psp->ras.ras_shared_mc_addr, 1399 &psp->ras.ras_shared_buf); 1400 1401 return 0; 1402 } 1403 1404 static int psp_ras_initialize(struct psp_context *psp) 1405 { 1406 int ret; 1407 uint32_t boot_cfg = 0xFF; 1408 struct amdgpu_device *adev = psp->adev; 1409 1410 /* 1411 * TODO: bypass the initialize in sriov for now 1412 */ 1413 if (amdgpu_sriov_vf(adev)) 1414 return 0; 1415 1416 if (!adev->psp.ta_ras_ucode_size || 1417 !adev->psp.ta_ras_start_addr) { 1418 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1419 return 0; 1420 } 1421 1422 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1423 /* query GECC enablement status from boot config 1424 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1425 */ 1426 ret = psp_boot_config_get(adev, &boot_cfg); 1427 if (ret) 1428 dev_warn(adev->dev, "PSP get boot config failed\n"); 1429 1430 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1431 if (!boot_cfg) { 1432 dev_info(adev->dev, "GECC is disabled\n"); 1433 } else { 1434 /* disable GECC in next boot cycle if ras is 1435 * disabled by module parameter amdgpu_ras_enable 1436 * and/or amdgpu_ras_mask, or boot_config_get call 1437 * is failed 1438 */ 1439 ret = psp_boot_config_set(adev, 0); 1440 if (ret) 1441 dev_warn(adev->dev, "PSP set boot config failed\n"); 1442 else 1443 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1444 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1445 } 1446 } else { 1447 if (1 == boot_cfg) { 1448 dev_info(adev->dev, "GECC is enabled\n"); 1449 } else { 1450 /* enable GECC in next boot cycle if it is disabled 1451 * in boot config, or force enable GECC if failed to 1452 * get boot configuration 1453 */ 1454 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1455 if (ret) 1456 dev_warn(adev->dev, "PSP set boot config failed\n"); 1457 else 1458 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1459 } 1460 } 1461 } 1462 1463 if (!psp->ras.ras_initialized) { 1464 ret = psp_ras_init_shared_buf(psp); 1465 if (ret) 1466 return ret; 1467 } 1468 1469 ret = psp_ras_load(psp); 1470 if (ret) 1471 return ret; 1472 1473 return 0; 1474 } 1475 1476 int psp_ras_trigger_error(struct psp_context *psp, 1477 struct ta_ras_trigger_error_input *info) 1478 { 1479 struct ta_ras_shared_memory *ras_cmd; 1480 int ret; 1481 1482 if (!psp->ras.ras_initialized) 1483 return -EINVAL; 1484 1485 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 1486 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1487 1488 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1489 ras_cmd->ras_in_message.trigger_error = *info; 1490 1491 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1492 if (ret) 1493 return -EINVAL; 1494 1495 /* If err_event_athub occurs error inject was successful, however 1496 return status from TA is no long reliable */ 1497 if (amdgpu_ras_intr_triggered()) 1498 return 0; 1499 1500 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1501 } 1502 // ras end 1503 1504 // HDCP start 1505 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1506 { 1507 int ret; 1508 1509 /* 1510 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1511 * physical) for hdcp ta <-> Driver 1512 */ 1513 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE, 1514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1515 &psp->hdcp_context.hdcp_shared_bo, 1516 &psp->hdcp_context.hdcp_shared_mc_addr, 1517 &psp->hdcp_context.hdcp_shared_buf); 1518 1519 return ret; 1520 } 1521 1522 static int psp_hdcp_load(struct psp_context *psp) 1523 { 1524 int ret; 1525 struct psp_gfx_cmd_resp *cmd; 1526 1527 /* 1528 * TODO: bypass the loading in sriov for now 1529 */ 1530 if (amdgpu_sriov_vf(psp->adev)) 1531 return 0; 1532 1533 psp_copy_fw(psp, psp->ta_hdcp_start_addr, 1534 psp->ta_hdcp_ucode_size); 1535 1536 cmd = acquire_psp_cmd_buf(psp); 1537 1538 psp_prep_ta_load_cmd_buf(cmd, 1539 psp->fw_pri_mc_addr, 1540 psp->ta_hdcp_ucode_size, 1541 psp->hdcp_context.hdcp_shared_mc_addr, 1542 PSP_HDCP_SHARED_MEM_SIZE); 1543 1544 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1545 1546 if (!ret) { 1547 psp->hdcp_context.hdcp_initialized = true; 1548 psp->hdcp_context.session_id = cmd->resp.session_id; 1549 mutex_init(&psp->hdcp_context.mutex); 1550 } 1551 1552 release_psp_cmd_buf(psp); 1553 1554 return ret; 1555 } 1556 static int psp_hdcp_initialize(struct psp_context *psp) 1557 { 1558 int ret; 1559 1560 /* 1561 * TODO: bypass the initialize in sriov for now 1562 */ 1563 if (amdgpu_sriov_vf(psp->adev)) 1564 return 0; 1565 1566 if (!psp->adev->psp.ta_hdcp_ucode_size || 1567 !psp->adev->psp.ta_hdcp_start_addr) { 1568 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1569 return 0; 1570 } 1571 1572 if (!psp->hdcp_context.hdcp_initialized) { 1573 ret = psp_hdcp_init_shared_buf(psp); 1574 if (ret) 1575 return ret; 1576 } 1577 1578 ret = psp_hdcp_load(psp); 1579 if (ret) 1580 return ret; 1581 1582 return 0; 1583 } 1584 1585 static int psp_hdcp_unload(struct psp_context *psp) 1586 { 1587 int ret; 1588 struct psp_gfx_cmd_resp *cmd; 1589 1590 /* 1591 * TODO: bypass the unloading in sriov for now 1592 */ 1593 if (amdgpu_sriov_vf(psp->adev)) 1594 return 0; 1595 1596 cmd = acquire_psp_cmd_buf(psp); 1597 1598 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id); 1599 1600 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1601 1602 release_psp_cmd_buf(psp); 1603 1604 return ret; 1605 } 1606 1607 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1608 { 1609 /* 1610 * TODO: bypass the loading in sriov for now 1611 */ 1612 if (amdgpu_sriov_vf(psp->adev)) 1613 return 0; 1614 1615 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id); 1616 } 1617 1618 static int psp_hdcp_terminate(struct psp_context *psp) 1619 { 1620 int ret; 1621 1622 /* 1623 * TODO: bypass the terminate in sriov for now 1624 */ 1625 if (amdgpu_sriov_vf(psp->adev)) 1626 return 0; 1627 1628 if (!psp->hdcp_context.hdcp_initialized) { 1629 if (psp->hdcp_context.hdcp_shared_buf) 1630 goto out; 1631 else 1632 return 0; 1633 } 1634 1635 ret = psp_hdcp_unload(psp); 1636 if (ret) 1637 return ret; 1638 1639 psp->hdcp_context.hdcp_initialized = false; 1640 1641 out: 1642 /* free hdcp shared memory */ 1643 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo, 1644 &psp->hdcp_context.hdcp_shared_mc_addr, 1645 &psp->hdcp_context.hdcp_shared_buf); 1646 1647 return 0; 1648 } 1649 // HDCP end 1650 1651 // DTM start 1652 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1653 { 1654 int ret; 1655 1656 /* 1657 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1658 * physical) for dtm ta <-> Driver 1659 */ 1660 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE, 1661 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1662 &psp->dtm_context.dtm_shared_bo, 1663 &psp->dtm_context.dtm_shared_mc_addr, 1664 &psp->dtm_context.dtm_shared_buf); 1665 1666 return ret; 1667 } 1668 1669 static int psp_dtm_load(struct psp_context *psp) 1670 { 1671 int ret; 1672 struct psp_gfx_cmd_resp *cmd; 1673 1674 /* 1675 * TODO: bypass the loading in sriov for now 1676 */ 1677 if (amdgpu_sriov_vf(psp->adev)) 1678 return 0; 1679 1680 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size); 1681 1682 cmd = acquire_psp_cmd_buf(psp); 1683 1684 psp_prep_ta_load_cmd_buf(cmd, 1685 psp->fw_pri_mc_addr, 1686 psp->ta_dtm_ucode_size, 1687 psp->dtm_context.dtm_shared_mc_addr, 1688 PSP_DTM_SHARED_MEM_SIZE); 1689 1690 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1691 1692 if (!ret) { 1693 psp->dtm_context.dtm_initialized = true; 1694 psp->dtm_context.session_id = cmd->resp.session_id; 1695 mutex_init(&psp->dtm_context.mutex); 1696 } 1697 1698 release_psp_cmd_buf(psp); 1699 1700 return ret; 1701 } 1702 1703 static int psp_dtm_initialize(struct psp_context *psp) 1704 { 1705 int ret; 1706 1707 /* 1708 * TODO: bypass the initialize in sriov for now 1709 */ 1710 if (amdgpu_sriov_vf(psp->adev)) 1711 return 0; 1712 1713 if (!psp->adev->psp.ta_dtm_ucode_size || 1714 !psp->adev->psp.ta_dtm_start_addr) { 1715 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1716 return 0; 1717 } 1718 1719 if (!psp->dtm_context.dtm_initialized) { 1720 ret = psp_dtm_init_shared_buf(psp); 1721 if (ret) 1722 return ret; 1723 } 1724 1725 ret = psp_dtm_load(psp); 1726 if (ret) 1727 return ret; 1728 1729 return 0; 1730 } 1731 1732 static int psp_dtm_unload(struct psp_context *psp) 1733 { 1734 int ret; 1735 struct psp_gfx_cmd_resp *cmd; 1736 1737 /* 1738 * TODO: bypass the unloading in sriov for now 1739 */ 1740 if (amdgpu_sriov_vf(psp->adev)) 1741 return 0; 1742 1743 cmd = acquire_psp_cmd_buf(psp); 1744 1745 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id); 1746 1747 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1748 1749 release_psp_cmd_buf(psp); 1750 1751 return ret; 1752 } 1753 1754 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1755 { 1756 /* 1757 * TODO: bypass the loading in sriov for now 1758 */ 1759 if (amdgpu_sriov_vf(psp->adev)) 1760 return 0; 1761 1762 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id); 1763 } 1764 1765 static int psp_dtm_terminate(struct psp_context *psp) 1766 { 1767 int ret; 1768 1769 /* 1770 * TODO: bypass the terminate in sriov for now 1771 */ 1772 if (amdgpu_sriov_vf(psp->adev)) 1773 return 0; 1774 1775 if (!psp->dtm_context.dtm_initialized) { 1776 if (psp->dtm_context.dtm_shared_buf) 1777 goto out; 1778 else 1779 return 0; 1780 } 1781 1782 ret = psp_dtm_unload(psp); 1783 if (ret) 1784 return ret; 1785 1786 psp->dtm_context.dtm_initialized = false; 1787 1788 out: 1789 /* free hdcp shared memory */ 1790 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo, 1791 &psp->dtm_context.dtm_shared_mc_addr, 1792 &psp->dtm_context.dtm_shared_buf); 1793 1794 return 0; 1795 } 1796 // DTM end 1797 1798 // RAP start 1799 static int psp_rap_init_shared_buf(struct psp_context *psp) 1800 { 1801 int ret; 1802 1803 /* 1804 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1805 * physical) for rap ta <-> Driver 1806 */ 1807 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE, 1808 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1809 &psp->rap_context.rap_shared_bo, 1810 &psp->rap_context.rap_shared_mc_addr, 1811 &psp->rap_context.rap_shared_buf); 1812 1813 return ret; 1814 } 1815 1816 static int psp_rap_load(struct psp_context *psp) 1817 { 1818 int ret; 1819 struct psp_gfx_cmd_resp *cmd; 1820 1821 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size); 1822 1823 cmd = acquire_psp_cmd_buf(psp); 1824 1825 psp_prep_ta_load_cmd_buf(cmd, 1826 psp->fw_pri_mc_addr, 1827 psp->ta_rap_ucode_size, 1828 psp->rap_context.rap_shared_mc_addr, 1829 PSP_RAP_SHARED_MEM_SIZE); 1830 1831 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1832 1833 if (!ret) { 1834 psp->rap_context.rap_initialized = true; 1835 psp->rap_context.session_id = cmd->resp.session_id; 1836 mutex_init(&psp->rap_context.mutex); 1837 } 1838 1839 release_psp_cmd_buf(psp); 1840 1841 return ret; 1842 } 1843 1844 static int psp_rap_unload(struct psp_context *psp) 1845 { 1846 int ret; 1847 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1848 1849 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id); 1850 1851 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1852 1853 release_psp_cmd_buf(psp); 1854 1855 return ret; 1856 } 1857 1858 static int psp_rap_initialize(struct psp_context *psp) 1859 { 1860 int ret; 1861 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1862 1863 /* 1864 * TODO: bypass the initialize in sriov for now 1865 */ 1866 if (amdgpu_sriov_vf(psp->adev)) 1867 return 0; 1868 1869 if (!psp->adev->psp.ta_rap_ucode_size || 1870 !psp->adev->psp.ta_rap_start_addr) { 1871 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1872 return 0; 1873 } 1874 1875 if (!psp->rap_context.rap_initialized) { 1876 ret = psp_rap_init_shared_buf(psp); 1877 if (ret) 1878 return ret; 1879 } 1880 1881 ret = psp_rap_load(psp); 1882 if (ret) 1883 return ret; 1884 1885 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1886 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1887 psp_rap_unload(psp); 1888 1889 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1890 &psp->rap_context.rap_shared_mc_addr, 1891 &psp->rap_context.rap_shared_buf); 1892 1893 psp->rap_context.rap_initialized = false; 1894 1895 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1896 ret, status); 1897 1898 return ret; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static int psp_rap_terminate(struct psp_context *psp) 1905 { 1906 int ret; 1907 1908 if (!psp->rap_context.rap_initialized) 1909 return 0; 1910 1911 ret = psp_rap_unload(psp); 1912 1913 psp->rap_context.rap_initialized = false; 1914 1915 /* free rap shared memory */ 1916 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo, 1917 &psp->rap_context.rap_shared_mc_addr, 1918 &psp->rap_context.rap_shared_buf); 1919 1920 return ret; 1921 } 1922 1923 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1924 { 1925 struct ta_rap_shared_memory *rap_cmd; 1926 int ret = 0; 1927 1928 if (!psp->rap_context.rap_initialized) 1929 return 0; 1930 1931 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1932 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1933 return -EINVAL; 1934 1935 mutex_lock(&psp->rap_context.mutex); 1936 1937 rap_cmd = (struct ta_rap_shared_memory *) 1938 psp->rap_context.rap_shared_buf; 1939 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1940 1941 rap_cmd->cmd_id = ta_cmd_id; 1942 rap_cmd->validation_method_id = METHOD_A; 1943 1944 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id); 1945 if (ret) 1946 goto out_unlock; 1947 1948 if (status) 1949 *status = rap_cmd->rap_status; 1950 1951 out_unlock: 1952 mutex_unlock(&psp->rap_context.mutex); 1953 1954 return ret; 1955 } 1956 // RAP end 1957 1958 /* securedisplay start */ 1959 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1960 { 1961 int ret; 1962 1963 /* 1964 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1965 * physical) for sa ta <-> Driver 1966 */ 1967 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE, 1968 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1969 &psp->securedisplay_context.securedisplay_shared_bo, 1970 &psp->securedisplay_context.securedisplay_shared_mc_addr, 1971 &psp->securedisplay_context.securedisplay_shared_buf); 1972 1973 return ret; 1974 } 1975 1976 static int psp_securedisplay_load(struct psp_context *psp) 1977 { 1978 int ret; 1979 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1980 1981 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1982 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); 1983 1984 psp_prep_ta_load_cmd_buf(cmd, 1985 psp->fw_pri_mc_addr, 1986 psp->ta_securedisplay_ucode_size, 1987 psp->securedisplay_context.securedisplay_shared_mc_addr, 1988 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 1989 1990 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1991 1992 if (!ret) { 1993 psp->securedisplay_context.securedisplay_initialized = true; 1994 psp->securedisplay_context.session_id = cmd->resp.session_id; 1995 mutex_init(&psp->securedisplay_context.mutex); 1996 } 1997 1998 release_psp_cmd_buf(psp); 1999 2000 return ret; 2001 } 2002 2003 static int psp_securedisplay_unload(struct psp_context *psp) 2004 { 2005 int ret; 2006 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2007 2008 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); 2009 2010 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2011 2012 release_psp_cmd_buf(psp); 2013 2014 return ret; 2015 } 2016 2017 static int psp_securedisplay_initialize(struct psp_context *psp) 2018 { 2019 int ret; 2020 struct securedisplay_cmd *securedisplay_cmd; 2021 2022 /* 2023 * TODO: bypass the initialize in sriov for now 2024 */ 2025 if (amdgpu_sriov_vf(psp->adev)) 2026 return 0; 2027 2028 if (!psp->adev->psp.ta_securedisplay_ucode_size || 2029 !psp->adev->psp.ta_securedisplay_start_addr) { 2030 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2031 return 0; 2032 } 2033 2034 if (!psp->securedisplay_context.securedisplay_initialized) { 2035 ret = psp_securedisplay_init_shared_buf(psp); 2036 if (ret) 2037 return ret; 2038 } 2039 2040 ret = psp_securedisplay_load(psp); 2041 if (ret) 2042 return ret; 2043 2044 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2045 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2046 2047 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2048 if (ret) { 2049 psp_securedisplay_unload(psp); 2050 2051 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2052 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2053 &psp->securedisplay_context.securedisplay_shared_buf); 2054 2055 psp->securedisplay_context.securedisplay_initialized = false; 2056 2057 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2058 return -EINVAL; 2059 } 2060 2061 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2062 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2063 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2064 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2065 } 2066 2067 return 0; 2068 } 2069 2070 static int psp_securedisplay_terminate(struct psp_context *psp) 2071 { 2072 int ret; 2073 2074 /* 2075 * TODO:bypass the terminate in sriov for now 2076 */ 2077 if (amdgpu_sriov_vf(psp->adev)) 2078 return 0; 2079 2080 if (!psp->securedisplay_context.securedisplay_initialized) 2081 return 0; 2082 2083 ret = psp_securedisplay_unload(psp); 2084 if (ret) 2085 return ret; 2086 2087 psp->securedisplay_context.securedisplay_initialized = false; 2088 2089 /* free securedisplay shared memory */ 2090 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, 2091 &psp->securedisplay_context.securedisplay_shared_mc_addr, 2092 &psp->securedisplay_context.securedisplay_shared_buf); 2093 2094 return ret; 2095 } 2096 2097 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2098 { 2099 int ret; 2100 2101 if (!psp->securedisplay_context.securedisplay_initialized) 2102 return -EINVAL; 2103 2104 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2105 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2106 return -EINVAL; 2107 2108 mutex_lock(&psp->securedisplay_context.mutex); 2109 2110 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); 2111 2112 mutex_unlock(&psp->securedisplay_context.mutex); 2113 2114 return ret; 2115 } 2116 /* SECUREDISPLAY end */ 2117 2118 static int psp_hw_start(struct psp_context *psp) 2119 { 2120 struct amdgpu_device *adev = psp->adev; 2121 int ret; 2122 2123 if (!amdgpu_sriov_vf(adev)) { 2124 if ((is_psp_fw_valid(psp->kdb)) && 2125 (psp->funcs->bootloader_load_kdb != NULL)) { 2126 ret = psp_bootloader_load_kdb(psp); 2127 if (ret) { 2128 DRM_ERROR("PSP load kdb failed!\n"); 2129 return ret; 2130 } 2131 } 2132 2133 if ((is_psp_fw_valid(psp->spl)) && 2134 (psp->funcs->bootloader_load_spl != NULL)) { 2135 ret = psp_bootloader_load_spl(psp); 2136 if (ret) { 2137 DRM_ERROR("PSP load spl failed!\n"); 2138 return ret; 2139 } 2140 } 2141 2142 if ((is_psp_fw_valid(psp->sys)) && 2143 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2144 ret = psp_bootloader_load_sysdrv(psp); 2145 if (ret) { 2146 DRM_ERROR("PSP load sys drv failed!\n"); 2147 return ret; 2148 } 2149 } 2150 2151 if ((is_psp_fw_valid(psp->soc_drv)) && 2152 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2153 ret = psp_bootloader_load_soc_drv(psp); 2154 if (ret) { 2155 DRM_ERROR("PSP load soc drv failed!\n"); 2156 return ret; 2157 } 2158 } 2159 2160 if ((is_psp_fw_valid(psp->intf_drv)) && 2161 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2162 ret = psp_bootloader_load_intf_drv(psp); 2163 if (ret) { 2164 DRM_ERROR("PSP load intf drv failed!\n"); 2165 return ret; 2166 } 2167 } 2168 2169 if ((is_psp_fw_valid(psp->dbg_drv)) && 2170 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2171 ret = psp_bootloader_load_dbg_drv(psp); 2172 if (ret) { 2173 DRM_ERROR("PSP load dbg drv failed!\n"); 2174 return ret; 2175 } 2176 } 2177 2178 if ((is_psp_fw_valid(psp->sos)) && 2179 (psp->funcs->bootloader_load_sos != NULL)) { 2180 ret = psp_bootloader_load_sos(psp); 2181 if (ret) { 2182 DRM_ERROR("PSP load sos failed!\n"); 2183 return ret; 2184 } 2185 } 2186 } 2187 2188 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2189 if (ret) { 2190 DRM_ERROR("PSP create ring failed!\n"); 2191 return ret; 2192 } 2193 2194 ret = psp_tmr_init(psp); 2195 if (ret) { 2196 DRM_ERROR("PSP tmr init failed!\n"); 2197 return ret; 2198 } 2199 2200 /* 2201 * For ASICs with DF Cstate management centralized 2202 * to PMFW, TMR setup should be performed after PMFW 2203 * loaded and before other non-psp firmware loaded. 2204 */ 2205 if (psp->pmfw_centralized_cstate_management) { 2206 ret = psp_load_smu_fw(psp); 2207 if (ret) 2208 return ret; 2209 } 2210 2211 ret = psp_tmr_load(psp); 2212 if (ret) { 2213 DRM_ERROR("PSP load tmr failed!\n"); 2214 return ret; 2215 } 2216 2217 return 0; 2218 } 2219 2220 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2221 enum psp_gfx_fw_type *type) 2222 { 2223 switch (ucode->ucode_id) { 2224 case AMDGPU_UCODE_ID_SDMA0: 2225 *type = GFX_FW_TYPE_SDMA0; 2226 break; 2227 case AMDGPU_UCODE_ID_SDMA1: 2228 *type = GFX_FW_TYPE_SDMA1; 2229 break; 2230 case AMDGPU_UCODE_ID_SDMA2: 2231 *type = GFX_FW_TYPE_SDMA2; 2232 break; 2233 case AMDGPU_UCODE_ID_SDMA3: 2234 *type = GFX_FW_TYPE_SDMA3; 2235 break; 2236 case AMDGPU_UCODE_ID_SDMA4: 2237 *type = GFX_FW_TYPE_SDMA4; 2238 break; 2239 case AMDGPU_UCODE_ID_SDMA5: 2240 *type = GFX_FW_TYPE_SDMA5; 2241 break; 2242 case AMDGPU_UCODE_ID_SDMA6: 2243 *type = GFX_FW_TYPE_SDMA6; 2244 break; 2245 case AMDGPU_UCODE_ID_SDMA7: 2246 *type = GFX_FW_TYPE_SDMA7; 2247 break; 2248 case AMDGPU_UCODE_ID_CP_MES: 2249 *type = GFX_FW_TYPE_CP_MES; 2250 break; 2251 case AMDGPU_UCODE_ID_CP_MES_DATA: 2252 *type = GFX_FW_TYPE_MES_STACK; 2253 break; 2254 case AMDGPU_UCODE_ID_CP_CE: 2255 *type = GFX_FW_TYPE_CP_CE; 2256 break; 2257 case AMDGPU_UCODE_ID_CP_PFP: 2258 *type = GFX_FW_TYPE_CP_PFP; 2259 break; 2260 case AMDGPU_UCODE_ID_CP_ME: 2261 *type = GFX_FW_TYPE_CP_ME; 2262 break; 2263 case AMDGPU_UCODE_ID_CP_MEC1: 2264 *type = GFX_FW_TYPE_CP_MEC; 2265 break; 2266 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2267 *type = GFX_FW_TYPE_CP_MEC_ME1; 2268 break; 2269 case AMDGPU_UCODE_ID_CP_MEC2: 2270 *type = GFX_FW_TYPE_CP_MEC; 2271 break; 2272 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2273 *type = GFX_FW_TYPE_CP_MEC_ME2; 2274 break; 2275 case AMDGPU_UCODE_ID_RLC_G: 2276 *type = GFX_FW_TYPE_RLC_G; 2277 break; 2278 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2279 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2280 break; 2281 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2282 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2283 break; 2284 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2285 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2286 break; 2287 case AMDGPU_UCODE_ID_RLC_IRAM: 2288 *type = GFX_FW_TYPE_RLC_IRAM; 2289 break; 2290 case AMDGPU_UCODE_ID_RLC_DRAM: 2291 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2292 break; 2293 case AMDGPU_UCODE_ID_SMC: 2294 *type = GFX_FW_TYPE_SMU; 2295 break; 2296 case AMDGPU_UCODE_ID_UVD: 2297 *type = GFX_FW_TYPE_UVD; 2298 break; 2299 case AMDGPU_UCODE_ID_UVD1: 2300 *type = GFX_FW_TYPE_UVD1; 2301 break; 2302 case AMDGPU_UCODE_ID_VCE: 2303 *type = GFX_FW_TYPE_VCE; 2304 break; 2305 case AMDGPU_UCODE_ID_VCN: 2306 *type = GFX_FW_TYPE_VCN; 2307 break; 2308 case AMDGPU_UCODE_ID_VCN1: 2309 *type = GFX_FW_TYPE_VCN1; 2310 break; 2311 case AMDGPU_UCODE_ID_DMCU_ERAM: 2312 *type = GFX_FW_TYPE_DMCU_ERAM; 2313 break; 2314 case AMDGPU_UCODE_ID_DMCU_INTV: 2315 *type = GFX_FW_TYPE_DMCU_ISR; 2316 break; 2317 case AMDGPU_UCODE_ID_VCN0_RAM: 2318 *type = GFX_FW_TYPE_VCN0_RAM; 2319 break; 2320 case AMDGPU_UCODE_ID_VCN1_RAM: 2321 *type = GFX_FW_TYPE_VCN1_RAM; 2322 break; 2323 case AMDGPU_UCODE_ID_DMCUB: 2324 *type = GFX_FW_TYPE_DMUB; 2325 break; 2326 case AMDGPU_UCODE_ID_MAXIMUM: 2327 default: 2328 return -EINVAL; 2329 } 2330 2331 return 0; 2332 } 2333 2334 static void psp_print_fw_hdr(struct psp_context *psp, 2335 struct amdgpu_firmware_info *ucode) 2336 { 2337 struct amdgpu_device *adev = psp->adev; 2338 struct common_firmware_header *hdr; 2339 2340 switch (ucode->ucode_id) { 2341 case AMDGPU_UCODE_ID_SDMA0: 2342 case AMDGPU_UCODE_ID_SDMA1: 2343 case AMDGPU_UCODE_ID_SDMA2: 2344 case AMDGPU_UCODE_ID_SDMA3: 2345 case AMDGPU_UCODE_ID_SDMA4: 2346 case AMDGPU_UCODE_ID_SDMA5: 2347 case AMDGPU_UCODE_ID_SDMA6: 2348 case AMDGPU_UCODE_ID_SDMA7: 2349 hdr = (struct common_firmware_header *) 2350 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2351 amdgpu_ucode_print_sdma_hdr(hdr); 2352 break; 2353 case AMDGPU_UCODE_ID_CP_CE: 2354 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2355 amdgpu_ucode_print_gfx_hdr(hdr); 2356 break; 2357 case AMDGPU_UCODE_ID_CP_PFP: 2358 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2359 amdgpu_ucode_print_gfx_hdr(hdr); 2360 break; 2361 case AMDGPU_UCODE_ID_CP_ME: 2362 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2363 amdgpu_ucode_print_gfx_hdr(hdr); 2364 break; 2365 case AMDGPU_UCODE_ID_CP_MEC1: 2366 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2367 amdgpu_ucode_print_gfx_hdr(hdr); 2368 break; 2369 case AMDGPU_UCODE_ID_RLC_G: 2370 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2371 amdgpu_ucode_print_rlc_hdr(hdr); 2372 break; 2373 case AMDGPU_UCODE_ID_SMC: 2374 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2375 amdgpu_ucode_print_smc_hdr(hdr); 2376 break; 2377 default: 2378 break; 2379 } 2380 } 2381 2382 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2383 struct psp_gfx_cmd_resp *cmd) 2384 { 2385 int ret; 2386 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2387 2388 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2389 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2390 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2391 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2392 2393 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2394 if (ret) 2395 DRM_ERROR("Unknown firmware type\n"); 2396 2397 return ret; 2398 } 2399 2400 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2401 struct amdgpu_firmware_info *ucode) 2402 { 2403 int ret = 0; 2404 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2405 2406 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2407 if (!ret) { 2408 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2409 psp->fence_buf_mc_addr); 2410 } 2411 2412 release_psp_cmd_buf(psp); 2413 2414 return ret; 2415 } 2416 2417 static int psp_load_smu_fw(struct psp_context *psp) 2418 { 2419 int ret; 2420 struct amdgpu_device *adev = psp->adev; 2421 struct amdgpu_firmware_info *ucode = 2422 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2423 struct amdgpu_ras *ras = psp->ras.ras; 2424 2425 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2426 return 0; 2427 2428 if ((amdgpu_in_reset(adev) && 2429 ras && adev->ras_enabled && 2430 (adev->asic_type == CHIP_ARCTURUS || 2431 adev->asic_type == CHIP_VEGA20))) { 2432 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2433 if (ret) { 2434 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2435 } 2436 } 2437 2438 ret = psp_execute_non_psp_fw_load(psp, ucode); 2439 2440 if (ret) 2441 DRM_ERROR("PSP load smu failed!\n"); 2442 2443 return ret; 2444 } 2445 2446 static bool fw_load_skip_check(struct psp_context *psp, 2447 struct amdgpu_firmware_info *ucode) 2448 { 2449 if (!ucode->fw) 2450 return true; 2451 2452 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2453 (psp_smu_reload_quirk(psp) || 2454 psp->autoload_supported || 2455 psp->pmfw_centralized_cstate_management)) 2456 return true; 2457 2458 if (amdgpu_sriov_vf(psp->adev) && 2459 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2460 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2461 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2462 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2463 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2464 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2465 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2466 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2467 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2468 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2469 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2470 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2471 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2472 /*skip ucode loading in SRIOV VF */ 2473 return true; 2474 2475 if (psp->autoload_supported && 2476 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2477 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2478 /* skip mec JT when autoload is enabled */ 2479 return true; 2480 2481 return false; 2482 } 2483 2484 int psp_load_fw_list(struct psp_context *psp, 2485 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2486 { 2487 int ret = 0, i; 2488 struct amdgpu_firmware_info *ucode; 2489 2490 for (i = 0; i < ucode_count; ++i) { 2491 ucode = ucode_list[i]; 2492 psp_print_fw_hdr(psp, ucode); 2493 ret = psp_execute_non_psp_fw_load(psp, ucode); 2494 if (ret) 2495 return ret; 2496 } 2497 return ret; 2498 } 2499 2500 static int psp_load_non_psp_fw(struct psp_context *psp) 2501 { 2502 int i, ret; 2503 struct amdgpu_firmware_info *ucode; 2504 struct amdgpu_device *adev = psp->adev; 2505 2506 if (psp->autoload_supported && 2507 !psp->pmfw_centralized_cstate_management) { 2508 ret = psp_load_smu_fw(psp); 2509 if (ret) 2510 return ret; 2511 } 2512 2513 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2514 ucode = &adev->firmware.ucode[i]; 2515 2516 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2517 !fw_load_skip_check(psp, ucode)) { 2518 ret = psp_load_smu_fw(psp); 2519 if (ret) 2520 return ret; 2521 continue; 2522 } 2523 2524 if (fw_load_skip_check(psp, ucode)) 2525 continue; 2526 2527 if (psp->autoload_supported && 2528 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2529 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2530 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2531 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2532 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2533 /* PSP only receive one SDMA fw for sienna_cichlid, 2534 * as all four sdma fw are same */ 2535 continue; 2536 2537 psp_print_fw_hdr(psp, ucode); 2538 2539 ret = psp_execute_non_psp_fw_load(psp, ucode); 2540 if (ret) 2541 return ret; 2542 2543 /* Start rlc autoload after psp recieved all the gfx firmware */ 2544 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2545 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2546 ret = psp_rlc_autoload_start(psp); 2547 if (ret) { 2548 DRM_ERROR("Failed to start rlc autoload\n"); 2549 return ret; 2550 } 2551 } 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int psp_load_fw(struct amdgpu_device *adev) 2558 { 2559 int ret; 2560 struct psp_context *psp = &adev->psp; 2561 2562 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2563 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2564 goto skip_memalloc; 2565 } 2566 2567 if (amdgpu_sriov_vf(adev)) { 2568 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2569 AMDGPU_GEM_DOMAIN_VRAM, 2570 &psp->fw_pri_bo, 2571 &psp->fw_pri_mc_addr, 2572 &psp->fw_pri_buf); 2573 } else { 2574 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2575 AMDGPU_GEM_DOMAIN_GTT, 2576 &psp->fw_pri_bo, 2577 &psp->fw_pri_mc_addr, 2578 &psp->fw_pri_buf); 2579 } 2580 2581 if (ret) 2582 goto failed; 2583 2584 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2585 AMDGPU_GEM_DOMAIN_VRAM, 2586 &psp->fence_buf_bo, 2587 &psp->fence_buf_mc_addr, 2588 &psp->fence_buf); 2589 if (ret) 2590 goto failed; 2591 2592 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2593 AMDGPU_GEM_DOMAIN_VRAM, 2594 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2595 (void **)&psp->cmd_buf_mem); 2596 if (ret) 2597 goto failed; 2598 2599 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2600 2601 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2602 if (ret) { 2603 DRM_ERROR("PSP ring init failed!\n"); 2604 goto failed; 2605 } 2606 2607 skip_memalloc: 2608 ret = psp_hw_start(psp); 2609 if (ret) 2610 goto failed; 2611 2612 ret = psp_load_non_psp_fw(psp); 2613 if (ret) 2614 goto failed; 2615 2616 ret = psp_asd_load(psp); 2617 if (ret) { 2618 DRM_ERROR("PSP load asd failed!\n"); 2619 return ret; 2620 } 2621 2622 ret = psp_rl_load(adev); 2623 if (ret) { 2624 DRM_ERROR("PSP load RL failed!\n"); 2625 return ret; 2626 } 2627 2628 if (psp->adev->psp.ta_fw) { 2629 ret = psp_ras_initialize(psp); 2630 if (ret) 2631 dev_err(psp->adev->dev, 2632 "RAS: Failed to initialize RAS\n"); 2633 2634 ret = psp_hdcp_initialize(psp); 2635 if (ret) 2636 dev_err(psp->adev->dev, 2637 "HDCP: Failed to initialize HDCP\n"); 2638 2639 ret = psp_dtm_initialize(psp); 2640 if (ret) 2641 dev_err(psp->adev->dev, 2642 "DTM: Failed to initialize DTM\n"); 2643 2644 ret = psp_rap_initialize(psp); 2645 if (ret) 2646 dev_err(psp->adev->dev, 2647 "RAP: Failed to initialize RAP\n"); 2648 2649 ret = psp_securedisplay_initialize(psp); 2650 if (ret) 2651 dev_err(psp->adev->dev, 2652 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2653 } 2654 2655 return 0; 2656 2657 failed: 2658 /* 2659 * all cleanup jobs (xgmi terminate, ras terminate, 2660 * ring destroy, cmd/fence/fw buffers destory, 2661 * psp->cmd destory) are delayed to psp_hw_fini 2662 */ 2663 return ret; 2664 } 2665 2666 static int psp_hw_init(void *handle) 2667 { 2668 int ret; 2669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2670 2671 mutex_lock(&adev->firmware.mutex); 2672 /* 2673 * This sequence is just used on hw_init only once, no need on 2674 * resume. 2675 */ 2676 ret = amdgpu_ucode_init_bo(adev); 2677 if (ret) 2678 goto failed; 2679 2680 ret = psp_load_fw(adev); 2681 if (ret) { 2682 DRM_ERROR("PSP firmware loading failed\n"); 2683 goto failed; 2684 } 2685 2686 mutex_unlock(&adev->firmware.mutex); 2687 return 0; 2688 2689 failed: 2690 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2691 mutex_unlock(&adev->firmware.mutex); 2692 return -EINVAL; 2693 } 2694 2695 static int psp_hw_fini(void *handle) 2696 { 2697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2698 struct psp_context *psp = &adev->psp; 2699 2700 if (psp->adev->psp.ta_fw) { 2701 psp_ras_terminate(psp); 2702 psp_securedisplay_terminate(psp); 2703 psp_rap_terminate(psp); 2704 psp_dtm_terminate(psp); 2705 psp_hdcp_terminate(psp); 2706 } 2707 2708 psp_asd_unload(psp); 2709 2710 psp_tmr_terminate(psp); 2711 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2712 2713 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2714 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2715 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2716 &psp->fence_buf_mc_addr, &psp->fence_buf); 2717 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2718 (void **)&psp->cmd_buf_mem); 2719 2720 return 0; 2721 } 2722 2723 static int psp_suspend(void *handle) 2724 { 2725 int ret; 2726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2727 struct psp_context *psp = &adev->psp; 2728 2729 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2730 psp->xgmi_context.initialized == 1) { 2731 ret = psp_xgmi_terminate(psp); 2732 if (ret) { 2733 DRM_ERROR("Failed to terminate xgmi ta\n"); 2734 return ret; 2735 } 2736 } 2737 2738 if (psp->adev->psp.ta_fw) { 2739 ret = psp_ras_terminate(psp); 2740 if (ret) { 2741 DRM_ERROR("Failed to terminate ras ta\n"); 2742 return ret; 2743 } 2744 ret = psp_hdcp_terminate(psp); 2745 if (ret) { 2746 DRM_ERROR("Failed to terminate hdcp ta\n"); 2747 return ret; 2748 } 2749 ret = psp_dtm_terminate(psp); 2750 if (ret) { 2751 DRM_ERROR("Failed to terminate dtm ta\n"); 2752 return ret; 2753 } 2754 ret = psp_rap_terminate(psp); 2755 if (ret) { 2756 DRM_ERROR("Failed to terminate rap ta\n"); 2757 return ret; 2758 } 2759 ret = psp_securedisplay_terminate(psp); 2760 if (ret) { 2761 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2762 return ret; 2763 } 2764 } 2765 2766 ret = psp_asd_unload(psp); 2767 if (ret) { 2768 DRM_ERROR("Failed to unload asd\n"); 2769 return ret; 2770 } 2771 2772 ret = psp_tmr_terminate(psp); 2773 if (ret) { 2774 DRM_ERROR("Failed to terminate tmr\n"); 2775 return ret; 2776 } 2777 2778 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2779 if (ret) { 2780 DRM_ERROR("PSP ring stop failed\n"); 2781 return ret; 2782 } 2783 2784 return 0; 2785 } 2786 2787 static int psp_resume(void *handle) 2788 { 2789 int ret; 2790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2791 struct psp_context *psp = &adev->psp; 2792 2793 DRM_INFO("PSP is resuming...\n"); 2794 2795 if (psp->mem_train_ctx.enable_mem_training) { 2796 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2797 if (ret) { 2798 DRM_ERROR("Failed to process memory training!\n"); 2799 return ret; 2800 } 2801 } 2802 2803 mutex_lock(&adev->firmware.mutex); 2804 2805 ret = psp_hw_start(psp); 2806 if (ret) 2807 goto failed; 2808 2809 ret = psp_load_non_psp_fw(psp); 2810 if (ret) 2811 goto failed; 2812 2813 ret = psp_asd_load(psp); 2814 if (ret) { 2815 DRM_ERROR("PSP load asd failed!\n"); 2816 goto failed; 2817 } 2818 2819 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2820 ret = psp_xgmi_initialize(psp); 2821 /* Warning the XGMI seesion initialize failure 2822 * Instead of stop driver initialization 2823 */ 2824 if (ret) 2825 dev_err(psp->adev->dev, 2826 "XGMI: Failed to initialize XGMI session\n"); 2827 } 2828 2829 if (psp->adev->psp.ta_fw) { 2830 ret = psp_ras_initialize(psp); 2831 if (ret) 2832 dev_err(psp->adev->dev, 2833 "RAS: Failed to initialize RAS\n"); 2834 2835 ret = psp_hdcp_initialize(psp); 2836 if (ret) 2837 dev_err(psp->adev->dev, 2838 "HDCP: Failed to initialize HDCP\n"); 2839 2840 ret = psp_dtm_initialize(psp); 2841 if (ret) 2842 dev_err(psp->adev->dev, 2843 "DTM: Failed to initialize DTM\n"); 2844 2845 ret = psp_rap_initialize(psp); 2846 if (ret) 2847 dev_err(psp->adev->dev, 2848 "RAP: Failed to initialize RAP\n"); 2849 2850 ret = psp_securedisplay_initialize(psp); 2851 if (ret) 2852 dev_err(psp->adev->dev, 2853 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2854 } 2855 2856 mutex_unlock(&adev->firmware.mutex); 2857 2858 return 0; 2859 2860 failed: 2861 DRM_ERROR("PSP resume failed\n"); 2862 mutex_unlock(&adev->firmware.mutex); 2863 return ret; 2864 } 2865 2866 int psp_gpu_reset(struct amdgpu_device *adev) 2867 { 2868 int ret; 2869 2870 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2871 return 0; 2872 2873 mutex_lock(&adev->psp.mutex); 2874 ret = psp_mode1_reset(&adev->psp); 2875 mutex_unlock(&adev->psp.mutex); 2876 2877 return ret; 2878 } 2879 2880 int psp_rlc_autoload_start(struct psp_context *psp) 2881 { 2882 int ret; 2883 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2884 2885 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2886 2887 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2888 psp->fence_buf_mc_addr); 2889 2890 release_psp_cmd_buf(psp); 2891 2892 return ret; 2893 } 2894 2895 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2896 uint64_t cmd_gpu_addr, int cmd_size) 2897 { 2898 struct amdgpu_firmware_info ucode = {0}; 2899 2900 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2901 AMDGPU_UCODE_ID_VCN0_RAM; 2902 ucode.mc_addr = cmd_gpu_addr; 2903 ucode.ucode_size = cmd_size; 2904 2905 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2906 } 2907 2908 int psp_ring_cmd_submit(struct psp_context *psp, 2909 uint64_t cmd_buf_mc_addr, 2910 uint64_t fence_mc_addr, 2911 int index) 2912 { 2913 unsigned int psp_write_ptr_reg = 0; 2914 struct psp_gfx_rb_frame *write_frame; 2915 struct psp_ring *ring = &psp->km_ring; 2916 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2917 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2918 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2919 struct amdgpu_device *adev = psp->adev; 2920 uint32_t ring_size_dw = ring->ring_size / 4; 2921 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2922 2923 /* KM (GPCOM) prepare write pointer */ 2924 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2925 2926 /* Update KM RB frame pointer to new frame */ 2927 /* write_frame ptr increments by size of rb_frame in bytes */ 2928 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2929 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2930 write_frame = ring_buffer_start; 2931 else 2932 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2933 /* Check invalid write_frame ptr address */ 2934 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2935 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2936 ring_buffer_start, ring_buffer_end, write_frame); 2937 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2938 return -EINVAL; 2939 } 2940 2941 /* Initialize KM RB frame */ 2942 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2943 2944 /* Update KM RB frame */ 2945 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2946 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2947 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2948 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2949 write_frame->fence_value = index; 2950 amdgpu_device_flush_hdp(adev, NULL); 2951 2952 /* Update the write Pointer in DWORDs */ 2953 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2954 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2955 return 0; 2956 } 2957 2958 int psp_init_asd_microcode(struct psp_context *psp, 2959 const char *chip_name) 2960 { 2961 struct amdgpu_device *adev = psp->adev; 2962 char fw_name[PSP_FW_NAME_LEN]; 2963 const struct psp_firmware_header_v1_0 *asd_hdr; 2964 int err = 0; 2965 2966 if (!chip_name) { 2967 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2968 return -EINVAL; 2969 } 2970 2971 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2972 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2973 if (err) 2974 goto out; 2975 2976 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2977 if (err) 2978 goto out; 2979 2980 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2981 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2982 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2983 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2984 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 2985 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2986 return 0; 2987 out: 2988 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2989 release_firmware(adev->psp.asd_fw); 2990 adev->psp.asd_fw = NULL; 2991 return err; 2992 } 2993 2994 int psp_init_toc_microcode(struct psp_context *psp, 2995 const char *chip_name) 2996 { 2997 struct amdgpu_device *adev = psp->adev; 2998 char fw_name[PSP_FW_NAME_LEN]; 2999 const struct psp_firmware_header_v1_0 *toc_hdr; 3000 int err = 0; 3001 3002 if (!chip_name) { 3003 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 3004 return -EINVAL; 3005 } 3006 3007 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3008 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 3009 if (err) 3010 goto out; 3011 3012 err = amdgpu_ucode_validate(adev->psp.toc_fw); 3013 if (err) 3014 goto out; 3015 3016 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3017 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3018 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3019 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3020 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3021 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3022 return 0; 3023 out: 3024 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3025 release_firmware(adev->psp.toc_fw); 3026 adev->psp.toc_fw = NULL; 3027 return err; 3028 } 3029 3030 static int parse_sos_bin_descriptor(struct psp_context *psp, 3031 const struct psp_fw_bin_desc *desc, 3032 const struct psp_firmware_header_v2_0 *sos_hdr) 3033 { 3034 uint8_t *ucode_start_addr = NULL; 3035 3036 if (!psp || !desc || !sos_hdr) 3037 return -EINVAL; 3038 3039 ucode_start_addr = (uint8_t *)sos_hdr + 3040 le32_to_cpu(desc->offset_bytes) + 3041 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3042 3043 switch (desc->fw_type) { 3044 case PSP_FW_TYPE_PSP_SOS: 3045 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3046 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3047 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3048 psp->sos.start_addr = ucode_start_addr; 3049 break; 3050 case PSP_FW_TYPE_PSP_SYS_DRV: 3051 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3052 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3053 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3054 psp->sys.start_addr = ucode_start_addr; 3055 break; 3056 case PSP_FW_TYPE_PSP_KDB: 3057 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3058 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3059 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3060 psp->kdb.start_addr = ucode_start_addr; 3061 break; 3062 case PSP_FW_TYPE_PSP_TOC: 3063 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3064 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3065 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3066 psp->toc.start_addr = ucode_start_addr; 3067 break; 3068 case PSP_FW_TYPE_PSP_SPL: 3069 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3070 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3071 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3072 psp->spl.start_addr = ucode_start_addr; 3073 break; 3074 case PSP_FW_TYPE_PSP_RL: 3075 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3076 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3077 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3078 psp->rl.start_addr = ucode_start_addr; 3079 break; 3080 case PSP_FW_TYPE_PSP_SOC_DRV: 3081 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3082 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3083 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3084 psp->soc_drv.start_addr = ucode_start_addr; 3085 break; 3086 case PSP_FW_TYPE_PSP_INTF_DRV: 3087 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3088 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3089 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3090 psp->intf_drv.start_addr = ucode_start_addr; 3091 break; 3092 case PSP_FW_TYPE_PSP_DBG_DRV: 3093 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3094 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3095 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3096 psp->dbg_drv.start_addr = ucode_start_addr; 3097 break; 3098 default: 3099 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3100 break; 3101 } 3102 3103 return 0; 3104 } 3105 3106 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3107 { 3108 const struct psp_firmware_header_v1_0 *sos_hdr; 3109 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3110 uint8_t *ucode_array_start_addr; 3111 3112 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3113 ucode_array_start_addr = (uint8_t *)sos_hdr + 3114 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3115 3116 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3117 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3118 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3119 3120 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3121 adev->psp.sys.start_addr = ucode_array_start_addr; 3122 3123 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3124 adev->psp.sos.start_addr = ucode_array_start_addr + 3125 le32_to_cpu(sos_hdr->sos.offset_bytes); 3126 } else { 3127 /* Load alternate PSP SOS FW */ 3128 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3129 3130 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3131 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3132 3133 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3134 adev->psp.sys.start_addr = ucode_array_start_addr + 3135 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3136 3137 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3138 adev->psp.sos.start_addr = ucode_array_start_addr + 3139 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3140 } 3141 3142 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3143 dev_warn(adev->dev, "PSP SOS FW not available"); 3144 return -EINVAL; 3145 } 3146 3147 return 0; 3148 } 3149 3150 int psp_init_sos_microcode(struct psp_context *psp, 3151 const char *chip_name) 3152 { 3153 struct amdgpu_device *adev = psp->adev; 3154 char fw_name[PSP_FW_NAME_LEN]; 3155 const struct psp_firmware_header_v1_0 *sos_hdr; 3156 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3157 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3158 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3159 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3160 int err = 0; 3161 uint8_t *ucode_array_start_addr; 3162 int fw_index = 0; 3163 3164 if (!chip_name) { 3165 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3166 return -EINVAL; 3167 } 3168 3169 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3170 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3171 if (err) 3172 goto out; 3173 3174 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3175 if (err) 3176 goto out; 3177 3178 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3179 ucode_array_start_addr = (uint8_t *)sos_hdr + 3180 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3181 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3182 3183 switch (sos_hdr->header.header_version_major) { 3184 case 1: 3185 err = psp_init_sos_base_fw(adev); 3186 if (err) 3187 goto out; 3188 3189 if (sos_hdr->header.header_version_minor == 1) { 3190 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3191 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3192 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3193 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3194 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3195 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3196 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3197 } 3198 if (sos_hdr->header.header_version_minor == 2) { 3199 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3200 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3201 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3202 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3203 } 3204 if (sos_hdr->header.header_version_minor == 3) { 3205 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3206 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3207 adev->psp.toc.start_addr = ucode_array_start_addr + 3208 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3209 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3210 adev->psp.kdb.start_addr = ucode_array_start_addr + 3211 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3212 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3213 adev->psp.spl.start_addr = ucode_array_start_addr + 3214 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3215 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3216 adev->psp.rl.start_addr = ucode_array_start_addr + 3217 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3218 } 3219 break; 3220 case 2: 3221 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3222 3223 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3224 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3225 err = -EINVAL; 3226 goto out; 3227 } 3228 3229 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3230 err = parse_sos_bin_descriptor(psp, 3231 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3232 sos_hdr_v2_0); 3233 if (err) 3234 goto out; 3235 } 3236 break; 3237 default: 3238 dev_err(adev->dev, 3239 "unsupported psp sos firmware\n"); 3240 err = -EINVAL; 3241 goto out; 3242 } 3243 3244 return 0; 3245 out: 3246 dev_err(adev->dev, 3247 "failed to init sos firmware\n"); 3248 release_firmware(adev->psp.sos_fw); 3249 adev->psp.sos_fw = NULL; 3250 3251 return err; 3252 } 3253 3254 static int parse_ta_bin_descriptor(struct psp_context *psp, 3255 const struct psp_fw_bin_desc *desc, 3256 const struct ta_firmware_header_v2_0 *ta_hdr) 3257 { 3258 uint8_t *ucode_start_addr = NULL; 3259 3260 if (!psp || !desc || !ta_hdr) 3261 return -EINVAL; 3262 3263 ucode_start_addr = (uint8_t *)ta_hdr + 3264 le32_to_cpu(desc->offset_bytes) + 3265 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3266 3267 switch (desc->fw_type) { 3268 case TA_FW_TYPE_PSP_ASD: 3269 psp->asd_fw_version = le32_to_cpu(desc->fw_version); 3270 psp->asd_feature_version = le32_to_cpu(desc->fw_version); 3271 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes); 3272 psp->asd_start_addr = ucode_start_addr; 3273 break; 3274 case TA_FW_TYPE_PSP_XGMI: 3275 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version); 3276 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes); 3277 psp->ta_xgmi_start_addr = ucode_start_addr; 3278 break; 3279 case TA_FW_TYPE_PSP_RAS: 3280 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version); 3281 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes); 3282 psp->ta_ras_start_addr = ucode_start_addr; 3283 break; 3284 case TA_FW_TYPE_PSP_HDCP: 3285 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version); 3286 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes); 3287 psp->ta_hdcp_start_addr = ucode_start_addr; 3288 break; 3289 case TA_FW_TYPE_PSP_DTM: 3290 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version); 3291 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes); 3292 psp->ta_dtm_start_addr = ucode_start_addr; 3293 break; 3294 case TA_FW_TYPE_PSP_RAP: 3295 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version); 3296 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes); 3297 psp->ta_rap_start_addr = ucode_start_addr; 3298 break; 3299 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3300 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); 3301 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); 3302 psp->ta_securedisplay_start_addr = ucode_start_addr; 3303 break; 3304 default: 3305 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3306 break; 3307 } 3308 3309 return 0; 3310 } 3311 3312 int psp_init_ta_microcode(struct psp_context *psp, 3313 const char *chip_name) 3314 { 3315 struct amdgpu_device *adev = psp->adev; 3316 char fw_name[PSP_FW_NAME_LEN]; 3317 const struct ta_firmware_header_v2_0 *ta_hdr; 3318 int err = 0; 3319 int ta_index = 0; 3320 3321 if (!chip_name) { 3322 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3323 return -EINVAL; 3324 } 3325 3326 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3327 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3328 if (err) 3329 goto out; 3330 3331 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3332 if (err) 3333 goto out; 3334 3335 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3336 3337 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3338 dev_err(adev->dev, "unsupported TA header version\n"); 3339 err = -EINVAL; 3340 goto out; 3341 } 3342 3343 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3344 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3345 err = -EINVAL; 3346 goto out; 3347 } 3348 3349 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3350 err = parse_ta_bin_descriptor(psp, 3351 &ta_hdr->ta_fw_bin[ta_index], 3352 ta_hdr); 3353 if (err) 3354 goto out; 3355 } 3356 3357 return 0; 3358 out: 3359 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3360 release_firmware(adev->psp.ta_fw); 3361 adev->psp.ta_fw = NULL; 3362 return err; 3363 } 3364 3365 static int psp_set_clockgating_state(void *handle, 3366 enum amd_clockgating_state state) 3367 { 3368 return 0; 3369 } 3370 3371 static int psp_set_powergating_state(void *handle, 3372 enum amd_powergating_state state) 3373 { 3374 return 0; 3375 } 3376 3377 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3378 struct device_attribute *attr, 3379 char *buf) 3380 { 3381 struct drm_device *ddev = dev_get_drvdata(dev); 3382 struct amdgpu_device *adev = drm_to_adev(ddev); 3383 uint32_t fw_ver; 3384 int ret; 3385 3386 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3387 DRM_INFO("PSP block is not ready yet."); 3388 return -EBUSY; 3389 } 3390 3391 mutex_lock(&adev->psp.mutex); 3392 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3393 mutex_unlock(&adev->psp.mutex); 3394 3395 if (ret) { 3396 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3397 return ret; 3398 } 3399 3400 return sysfs_emit(buf, "%x\n", fw_ver); 3401 } 3402 3403 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3404 struct device_attribute *attr, 3405 const char *buf, 3406 size_t count) 3407 { 3408 struct drm_device *ddev = dev_get_drvdata(dev); 3409 struct amdgpu_device *adev = drm_to_adev(ddev); 3410 int ret, idx; 3411 char fw_name[100]; 3412 const struct firmware *usbc_pd_fw; 3413 struct amdgpu_bo *fw_buf_bo = NULL; 3414 uint64_t fw_pri_mc_addr; 3415 void *fw_pri_cpu_addr; 3416 3417 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3418 DRM_INFO("PSP block is not ready yet."); 3419 return -EBUSY; 3420 } 3421 3422 if (!drm_dev_enter(ddev, &idx)) 3423 return -ENODEV; 3424 3425 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3426 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3427 if (ret) 3428 goto fail; 3429 3430 /* LFB address which is aligned to 1MB boundary per PSP request */ 3431 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3432 AMDGPU_GEM_DOMAIN_VRAM, 3433 &fw_buf_bo, 3434 &fw_pri_mc_addr, 3435 &fw_pri_cpu_addr); 3436 if (ret) 3437 goto rel_buf; 3438 3439 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3440 3441 mutex_lock(&adev->psp.mutex); 3442 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3443 mutex_unlock(&adev->psp.mutex); 3444 3445 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3446 3447 rel_buf: 3448 release_firmware(usbc_pd_fw); 3449 fail: 3450 if (ret) { 3451 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3452 count = ret; 3453 } 3454 3455 drm_dev_exit(idx); 3456 return count; 3457 } 3458 3459 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3460 { 3461 int idx; 3462 3463 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3464 return; 3465 3466 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3467 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3468 3469 drm_dev_exit(idx); 3470 } 3471 3472 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3473 psp_usbc_pd_fw_sysfs_read, 3474 psp_usbc_pd_fw_sysfs_write); 3475 3476 int is_psp_fw_valid(struct psp_bin_desc bin) 3477 { 3478 return bin.size_bytes; 3479 } 3480 3481 const struct amd_ip_funcs psp_ip_funcs = { 3482 .name = "psp", 3483 .early_init = psp_early_init, 3484 .late_init = NULL, 3485 .sw_init = psp_sw_init, 3486 .sw_fini = psp_sw_fini, 3487 .hw_init = psp_hw_init, 3488 .hw_fini = psp_hw_fini, 3489 .suspend = psp_suspend, 3490 .resume = psp_resume, 3491 .is_idle = NULL, 3492 .check_soft_reset = NULL, 3493 .wait_for_idle = NULL, 3494 .soft_reset = NULL, 3495 .set_clockgating_state = psp_set_clockgating_state, 3496 .set_powergating_state = psp_set_powergating_state, 3497 }; 3498 3499 static int psp_sysfs_init(struct amdgpu_device *adev) 3500 { 3501 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3502 3503 if (ret) 3504 DRM_ERROR("Failed to create USBC PD FW control file!"); 3505 3506 return ret; 3507 } 3508 3509 static void psp_sysfs_fini(struct amdgpu_device *adev) 3510 { 3511 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3512 } 3513 3514 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3515 { 3516 .type = AMD_IP_BLOCK_TYPE_PSP, 3517 .major = 3, 3518 .minor = 1, 3519 .rev = 0, 3520 .funcs = &psp_ip_funcs, 3521 }; 3522 3523 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3524 { 3525 .type = AMD_IP_BLOCK_TYPE_PSP, 3526 .major = 10, 3527 .minor = 0, 3528 .rev = 0, 3529 .funcs = &psp_ip_funcs, 3530 }; 3531 3532 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3533 { 3534 .type = AMD_IP_BLOCK_TYPE_PSP, 3535 .major = 11, 3536 .minor = 0, 3537 .rev = 0, 3538 .funcs = &psp_ip_funcs, 3539 }; 3540 3541 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3542 .type = AMD_IP_BLOCK_TYPE_PSP, 3543 .major = 11, 3544 .minor = 0, 3545 .rev = 8, 3546 .funcs = &psp_ip_funcs, 3547 }; 3548 3549 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3550 { 3551 .type = AMD_IP_BLOCK_TYPE_PSP, 3552 .major = 12, 3553 .minor = 0, 3554 .rev = 0, 3555 .funcs = &psp_ip_funcs, 3556 }; 3557 3558 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3559 .type = AMD_IP_BLOCK_TYPE_PSP, 3560 .major = 13, 3561 .minor = 0, 3562 .rev = 0, 3563 .funcs = &psp_ip_funcs, 3564 }; 3565