1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 43 #include "amdgpu_ras.h" 44 #include "amdgpu_securedisplay.h" 45 #include "amdgpu_atomfirmware.h" 46 47 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 48 49 static int psp_load_smu_fw(struct psp_context *psp); 50 static int psp_rap_terminate(struct psp_context *psp); 51 static int psp_securedisplay_terminate(struct psp_context *psp); 52 53 static int psp_ring_init(struct psp_context *psp, 54 enum psp_ring_type ring_type) 55 { 56 int ret = 0; 57 struct psp_ring *ring; 58 struct amdgpu_device *adev = psp->adev; 59 60 ring = &psp->km_ring; 61 62 ring->ring_type = ring_type; 63 64 /* allocate 4k Page of Local Frame Buffer memory for ring */ 65 ring->ring_size = 0x1000; 66 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 67 AMDGPU_GEM_DOMAIN_VRAM | 68 AMDGPU_GEM_DOMAIN_GTT, 69 &adev->firmware.rbuf, 70 &ring->ring_mem_mc_addr, 71 (void **)&ring->ring_mem); 72 if (ret) { 73 ring->ring_size = 0; 74 return ret; 75 } 76 77 return 0; 78 } 79 80 /* 81 * Due to DF Cstate management centralized to PMFW, the firmware 82 * loading sequence will be updated as below: 83 * - Load KDB 84 * - Load SYS_DRV 85 * - Load tOS 86 * - Load PMFW 87 * - Setup TMR 88 * - Load other non-psp fw 89 * - Load ASD 90 * - Load XGMI/RAS/HDCP/DTM TA if any 91 * 92 * This new sequence is required for 93 * - Arcturus and onwards 94 */ 95 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 99 if (amdgpu_sriov_vf(adev)) { 100 psp->pmfw_centralized_cstate_management = false; 101 return; 102 } 103 104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 105 case IP_VERSION(11, 0, 0): 106 case IP_VERSION(11, 0, 4): 107 case IP_VERSION(11, 0, 5): 108 case IP_VERSION(11, 0, 7): 109 case IP_VERSION(11, 0, 9): 110 case IP_VERSION(11, 0, 11): 111 case IP_VERSION(11, 0, 12): 112 case IP_VERSION(11, 0, 13): 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): 115 case IP_VERSION(13, 0, 7): 116 psp->pmfw_centralized_cstate_management = true; 117 break; 118 default: 119 psp->pmfw_centralized_cstate_management = false; 120 break; 121 } 122 } 123 124 static int psp_init_sriov_microcode(struct psp_context *psp) 125 { 126 struct amdgpu_device *adev = psp->adev; 127 char ucode_prefix[30]; 128 int ret = 0; 129 130 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 131 132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 133 case IP_VERSION(9, 0, 0): 134 case IP_VERSION(11, 0, 7): 135 case IP_VERSION(11, 0, 9): 136 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 137 ret = psp_init_cap_microcode(psp, ucode_prefix); 138 break; 139 case IP_VERSION(13, 0, 2): 140 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 141 ret = psp_init_cap_microcode(psp, ucode_prefix); 142 ret &= psp_init_ta_microcode(psp, ucode_prefix); 143 break; 144 case IP_VERSION(13, 0, 0): 145 adev->virt.autoload_ucode_id = 0; 146 break; 147 case IP_VERSION(13, 0, 6): 148 case IP_VERSION(13, 0, 14): 149 ret = psp_init_cap_microcode(psp, ucode_prefix); 150 ret &= psp_init_ta_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 10): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 default: 157 return -EINVAL; 158 } 159 return ret; 160 } 161 162 static int psp_early_init(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 struct psp_context *psp = &adev->psp; 166 167 psp->autoload_supported = true; 168 psp->boot_time_tmr = true; 169 170 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 171 case IP_VERSION(9, 0, 0): 172 psp_v3_1_set_psp_funcs(psp); 173 psp->autoload_supported = false; 174 psp->boot_time_tmr = false; 175 break; 176 case IP_VERSION(10, 0, 0): 177 case IP_VERSION(10, 0, 1): 178 psp_v10_0_set_psp_funcs(psp); 179 psp->autoload_supported = false; 180 psp->boot_time_tmr = false; 181 break; 182 case IP_VERSION(11, 0, 2): 183 case IP_VERSION(11, 0, 4): 184 psp_v11_0_set_psp_funcs(psp); 185 psp->autoload_supported = false; 186 psp->boot_time_tmr = false; 187 break; 188 case IP_VERSION(11, 0, 0): 189 case IP_VERSION(11, 0, 7): 190 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 191 fallthrough; 192 case IP_VERSION(11, 0, 5): 193 case IP_VERSION(11, 0, 9): 194 case IP_VERSION(11, 0, 11): 195 case IP_VERSION(11, 5, 0): 196 case IP_VERSION(11, 0, 12): 197 case IP_VERSION(11, 0, 13): 198 psp_v11_0_set_psp_funcs(psp); 199 psp->boot_time_tmr = false; 200 break; 201 case IP_VERSION(11, 0, 3): 202 case IP_VERSION(12, 0, 1): 203 psp_v12_0_set_psp_funcs(psp); 204 psp->autoload_supported = false; 205 psp->boot_time_tmr = false; 206 break; 207 case IP_VERSION(13, 0, 2): 208 psp->boot_time_tmr = false; 209 fallthrough; 210 case IP_VERSION(13, 0, 6): 211 case IP_VERSION(13, 0, 14): 212 psp_v13_0_set_psp_funcs(psp); 213 psp->autoload_supported = false; 214 break; 215 case IP_VERSION(13, 0, 1): 216 case IP_VERSION(13, 0, 3): 217 case IP_VERSION(13, 0, 5): 218 case IP_VERSION(13, 0, 8): 219 case IP_VERSION(13, 0, 11): 220 case IP_VERSION(14, 0, 0): 221 case IP_VERSION(14, 0, 1): 222 psp_v13_0_set_psp_funcs(psp); 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(11, 0, 8): 226 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 227 psp_v11_0_8_set_psp_funcs(psp); 228 } 229 psp->autoload_supported = false; 230 psp->boot_time_tmr = false; 231 break; 232 case IP_VERSION(13, 0, 0): 233 case IP_VERSION(13, 0, 7): 234 case IP_VERSION(13, 0, 10): 235 psp_v13_0_set_psp_funcs(psp); 236 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 237 psp->boot_time_tmr = false; 238 break; 239 case IP_VERSION(13, 0, 4): 240 psp_v13_0_4_set_psp_funcs(psp); 241 psp->boot_time_tmr = false; 242 break; 243 case IP_VERSION(14, 0, 2): 244 case IP_VERSION(14, 0, 3): 245 psp_v14_0_set_psp_funcs(psp); 246 break; 247 default: 248 return -EINVAL; 249 } 250 251 psp->adev = adev; 252 253 adev->psp_timeout = 20000; 254 255 psp_check_pmfw_centralized_cstate_management(psp); 256 257 if (amdgpu_sriov_vf(adev)) 258 return psp_init_sriov_microcode(psp); 259 else 260 return psp_init_microcode(psp); 261 } 262 263 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 264 { 265 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 266 &mem_ctx->shared_buf); 267 mem_ctx->shared_bo = NULL; 268 } 269 270 static void psp_free_shared_bufs(struct psp_context *psp) 271 { 272 void *tmr_buf; 273 void **pptr; 274 275 /* free TMR memory buffer */ 276 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 277 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 278 psp->tmr_bo = NULL; 279 280 /* free xgmi shared memory */ 281 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 282 283 /* free ras shared memory */ 284 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 285 286 /* free hdcp shared memory */ 287 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 288 289 /* free dtm shared memory */ 290 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 291 292 /* free rap shared memory */ 293 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 294 295 /* free securedisplay shared memory */ 296 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 297 298 299 } 300 301 static void psp_memory_training_fini(struct psp_context *psp) 302 { 303 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 304 305 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 306 kfree(ctx->sys_cache); 307 ctx->sys_cache = NULL; 308 } 309 310 static int psp_memory_training_init(struct psp_context *psp) 311 { 312 int ret; 313 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 314 315 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 316 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 317 return 0; 318 } 319 320 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 321 if (ctx->sys_cache == NULL) { 322 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 323 ret = -ENOMEM; 324 goto Err_out; 325 } 326 327 dev_dbg(psp->adev->dev, 328 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 329 ctx->train_data_size, 330 ctx->p2c_train_data_offset, 331 ctx->c2p_train_data_offset); 332 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 333 return 0; 334 335 Err_out: 336 psp_memory_training_fini(psp); 337 return ret; 338 } 339 340 /* 341 * Helper funciton to query psp runtime database entry 342 * 343 * @adev: amdgpu_device pointer 344 * @entry_type: the type of psp runtime database entry 345 * @db_entry: runtime database entry pointer 346 * 347 * Return false if runtime database doesn't exit or entry is invalid 348 * or true if the specific database entry is found, and copy to @db_entry 349 */ 350 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 351 enum psp_runtime_entry_type entry_type, 352 void *db_entry) 353 { 354 uint64_t db_header_pos, db_dir_pos; 355 struct psp_runtime_data_header db_header = {0}; 356 struct psp_runtime_data_directory db_dir = {0}; 357 bool ret = false; 358 int i; 359 360 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 361 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) 362 return false; 363 364 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 365 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 366 367 /* read runtime db header from vram */ 368 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 369 sizeof(struct psp_runtime_data_header), false); 370 371 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 372 /* runtime db doesn't exist, exit */ 373 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 374 return false; 375 } 376 377 /* read runtime database entry from vram */ 378 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 379 sizeof(struct psp_runtime_data_directory), false); 380 381 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 382 /* invalid db entry count, exit */ 383 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 384 return false; 385 } 386 387 /* look up for requested entry type */ 388 for (i = 0; i < db_dir.entry_count && !ret; i++) { 389 if (db_dir.entry_list[i].entry_type == entry_type) { 390 switch (entry_type) { 391 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 392 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 393 /* invalid db entry size */ 394 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 395 return false; 396 } 397 /* read runtime database entry */ 398 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 399 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 400 ret = true; 401 break; 402 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 403 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 404 /* invalid db entry size */ 405 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 406 return false; 407 } 408 /* read runtime database entry */ 409 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 410 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 411 ret = true; 412 break; 413 default: 414 ret = false; 415 break; 416 } 417 } 418 } 419 420 return ret; 421 } 422 423 static int psp_sw_init(void *handle) 424 { 425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 426 struct psp_context *psp = &adev->psp; 427 int ret; 428 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 429 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 430 struct psp_runtime_scpm_entry scpm_entry; 431 432 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 433 if (!psp->cmd) { 434 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 435 ret = -ENOMEM; 436 } 437 438 adev->psp.xgmi_context.supports_extended_data = 439 !adev->gmc.xgmi.connected_to_cpu && 440 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 441 442 memset(&scpm_entry, 0, sizeof(scpm_entry)); 443 if ((psp_get_runtime_db_entry(adev, 444 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 445 &scpm_entry)) && 446 (scpm_entry.scpm_status != SCPM_DISABLE)) { 447 adev->scpm_enabled = true; 448 adev->scpm_status = scpm_entry.scpm_status; 449 } else { 450 adev->scpm_enabled = false; 451 adev->scpm_status = SCPM_DISABLE; 452 } 453 454 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 455 456 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 457 if (psp_get_runtime_db_entry(adev, 458 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 459 &boot_cfg_entry)) { 460 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 461 if ((psp->boot_cfg_bitmask) & 462 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 463 /* If psp runtime database exists, then 464 * only enable two stage memory training 465 * when TWO_STAGE_DRAM_TRAINING bit is set 466 * in runtime database 467 */ 468 mem_training_ctx->enable_mem_training = true; 469 } 470 471 } else { 472 /* If psp runtime database doesn't exist or is 473 * invalid, force enable two stage memory training 474 */ 475 mem_training_ctx->enable_mem_training = true; 476 } 477 478 if (mem_training_ctx->enable_mem_training) { 479 ret = psp_memory_training_init(psp); 480 if (ret) { 481 dev_err(adev->dev, "Failed to initialize memory training!\n"); 482 return ret; 483 } 484 485 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 486 if (ret) { 487 dev_err(adev->dev, "Failed to process memory training!\n"); 488 return ret; 489 } 490 } 491 492 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 493 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? 494 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 495 &psp->fw_pri_bo, 496 &psp->fw_pri_mc_addr, 497 &psp->fw_pri_buf); 498 if (ret) 499 return ret; 500 501 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 502 AMDGPU_GEM_DOMAIN_VRAM | 503 AMDGPU_GEM_DOMAIN_GTT, 504 &psp->fence_buf_bo, 505 &psp->fence_buf_mc_addr, 506 &psp->fence_buf); 507 if (ret) 508 goto failed1; 509 510 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 511 AMDGPU_GEM_DOMAIN_VRAM | 512 AMDGPU_GEM_DOMAIN_GTT, 513 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 514 (void **)&psp->cmd_buf_mem); 515 if (ret) 516 goto failed2; 517 518 return 0; 519 520 failed2: 521 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 522 &psp->fence_buf_mc_addr, &psp->fence_buf); 523 failed1: 524 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 525 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 526 return ret; 527 } 528 529 static int psp_sw_fini(void *handle) 530 { 531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 532 struct psp_context *psp = &adev->psp; 533 struct psp_gfx_cmd_resp *cmd = psp->cmd; 534 535 psp_memory_training_fini(psp); 536 537 amdgpu_ucode_release(&psp->sos_fw); 538 amdgpu_ucode_release(&psp->asd_fw); 539 amdgpu_ucode_release(&psp->ta_fw); 540 amdgpu_ucode_release(&psp->cap_fw); 541 amdgpu_ucode_release(&psp->toc_fw); 542 543 kfree(cmd); 544 cmd = NULL; 545 546 psp_free_shared_bufs(psp); 547 548 if (psp->km_ring.ring_mem) 549 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 550 &psp->km_ring.ring_mem_mc_addr, 551 (void **)&psp->km_ring.ring_mem); 552 553 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 554 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 555 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 556 &psp->fence_buf_mc_addr, &psp->fence_buf); 557 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 558 (void **)&psp->cmd_buf_mem); 559 560 return 0; 561 } 562 563 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 564 uint32_t reg_val, uint32_t mask, bool check_changed) 565 { 566 uint32_t val; 567 int i; 568 struct amdgpu_device *adev = psp->adev; 569 570 if (psp->adev->no_hw_access) 571 return 0; 572 573 for (i = 0; i < adev->usec_timeout; i++) { 574 val = RREG32(reg_index); 575 if (check_changed) { 576 if (val != reg_val) 577 return 0; 578 } else { 579 if ((val & mask) == reg_val) 580 return 0; 581 } 582 udelay(1); 583 } 584 585 return -ETIME; 586 } 587 588 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 589 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 590 { 591 uint32_t val; 592 int i; 593 struct amdgpu_device *adev = psp->adev; 594 595 if (psp->adev->no_hw_access) 596 return 0; 597 598 for (i = 0; i < msec_timeout; i++) { 599 val = RREG32(reg_index); 600 if ((val & mask) == reg_val) 601 return 0; 602 msleep(1); 603 } 604 605 return -ETIME; 606 } 607 608 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 609 { 610 switch (cmd_id) { 611 case GFX_CMD_ID_LOAD_TA: 612 return "LOAD_TA"; 613 case GFX_CMD_ID_UNLOAD_TA: 614 return "UNLOAD_TA"; 615 case GFX_CMD_ID_INVOKE_CMD: 616 return "INVOKE_CMD"; 617 case GFX_CMD_ID_LOAD_ASD: 618 return "LOAD_ASD"; 619 case GFX_CMD_ID_SETUP_TMR: 620 return "SETUP_TMR"; 621 case GFX_CMD_ID_LOAD_IP_FW: 622 return "LOAD_IP_FW"; 623 case GFX_CMD_ID_DESTROY_TMR: 624 return "DESTROY_TMR"; 625 case GFX_CMD_ID_SAVE_RESTORE: 626 return "SAVE_RESTORE_IP_FW"; 627 case GFX_CMD_ID_SETUP_VMR: 628 return "SETUP_VMR"; 629 case GFX_CMD_ID_DESTROY_VMR: 630 return "DESTROY_VMR"; 631 case GFX_CMD_ID_PROG_REG: 632 return "PROG_REG"; 633 case GFX_CMD_ID_GET_FW_ATTESTATION: 634 return "GET_FW_ATTESTATION"; 635 case GFX_CMD_ID_LOAD_TOC: 636 return "ID_LOAD_TOC"; 637 case GFX_CMD_ID_AUTOLOAD_RLC: 638 return "AUTOLOAD_RLC"; 639 case GFX_CMD_ID_BOOT_CFG: 640 return "BOOT_CFG"; 641 default: 642 return "UNKNOWN CMD"; 643 } 644 } 645 646 static int 647 psp_cmd_submit_buf(struct psp_context *psp, 648 struct amdgpu_firmware_info *ucode, 649 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 650 { 651 int ret; 652 int index; 653 int timeout = psp->adev->psp_timeout; 654 bool ras_intr = false; 655 bool skip_unsupport = false; 656 657 if (psp->adev->no_hw_access) 658 return 0; 659 660 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 661 662 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 663 664 index = atomic_inc_return(&psp->fence_value); 665 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 666 if (ret) { 667 atomic_dec(&psp->fence_value); 668 goto exit; 669 } 670 671 amdgpu_device_invalidate_hdp(psp->adev, NULL); 672 while (*((unsigned int *)psp->fence_buf) != index) { 673 if (--timeout == 0) 674 break; 675 /* 676 * Shouldn't wait for timeout when err_event_athub occurs, 677 * because gpu reset thread triggered and lock resource should 678 * be released for psp resume sequence. 679 */ 680 ras_intr = amdgpu_ras_intr_triggered(); 681 if (ras_intr) 682 break; 683 usleep_range(10, 100); 684 amdgpu_device_invalidate_hdp(psp->adev, NULL); 685 } 686 687 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 688 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 689 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 690 691 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 692 693 /* In some cases, psp response status is not 0 even there is no 694 * problem while the command is submitted. Some version of PSP FW 695 * doesn't write 0 to that field. 696 * So here we would like to only print a warning instead of an error 697 * during psp initialization to avoid breaking hw_init and it doesn't 698 * return -EINVAL. 699 */ 700 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 701 if (ucode) 702 dev_warn(psp->adev->dev, 703 "failed to load ucode %s(0x%X) ", 704 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 705 dev_warn(psp->adev->dev, 706 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 707 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 708 psp->cmd_buf_mem->resp.status); 709 /* If any firmware (including CAP) load fails under SRIOV, it should 710 * return failure to stop the VF from initializing. 711 * Also return failure in case of timeout 712 */ 713 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 714 ret = -EINVAL; 715 goto exit; 716 } 717 } 718 719 if (ucode) { 720 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 721 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 722 } 723 724 exit: 725 return ret; 726 } 727 728 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 729 { 730 struct psp_gfx_cmd_resp *cmd = psp->cmd; 731 732 mutex_lock(&psp->mutex); 733 734 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 735 736 return cmd; 737 } 738 739 static void release_psp_cmd_buf(struct psp_context *psp) 740 { 741 mutex_unlock(&psp->mutex); 742 } 743 744 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 745 struct psp_gfx_cmd_resp *cmd, 746 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 747 { 748 struct amdgpu_device *adev = psp->adev; 749 uint32_t size = 0; 750 uint64_t tmr_pa = 0; 751 752 if (tmr_bo) { 753 size = amdgpu_bo_size(tmr_bo); 754 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 755 } 756 757 if (amdgpu_sriov_vf(psp->adev)) 758 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 759 else 760 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 761 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 762 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 763 cmd->cmd.cmd_setup_tmr.buf_size = size; 764 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 765 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 766 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 767 } 768 769 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 770 uint64_t pri_buf_mc, uint32_t size) 771 { 772 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 773 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 774 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 775 cmd->cmd.cmd_load_toc.toc_size = size; 776 } 777 778 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 779 static int psp_load_toc(struct psp_context *psp, 780 uint32_t *tmr_size) 781 { 782 int ret; 783 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 784 785 /* Copy toc to psp firmware private buffer */ 786 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 787 788 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 789 790 ret = psp_cmd_submit_buf(psp, NULL, cmd, 791 psp->fence_buf_mc_addr); 792 if (!ret) 793 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 794 795 release_psp_cmd_buf(psp); 796 797 return ret; 798 } 799 800 /* Set up Trusted Memory Region */ 801 static int psp_tmr_init(struct psp_context *psp) 802 { 803 int ret = 0; 804 int tmr_size; 805 void *tmr_buf; 806 void **pptr; 807 808 /* 809 * According to HW engineer, they prefer the TMR address be "naturally 810 * aligned" , e.g. the start address be an integer divide of TMR size. 811 * 812 * Note: this memory need be reserved till the driver 813 * uninitializes. 814 */ 815 tmr_size = PSP_TMR_SIZE(psp->adev); 816 817 /* For ASICs support RLC autoload, psp will parse the toc 818 * and calculate the total size of TMR needed 819 */ 820 if (!amdgpu_sriov_vf(psp->adev) && 821 psp->toc.start_addr && 822 psp->toc.size_bytes && 823 psp->fw_pri_buf) { 824 ret = psp_load_toc(psp, &tmr_size); 825 if (ret) { 826 dev_err(psp->adev->dev, "Failed to load toc\n"); 827 return ret; 828 } 829 } 830 831 if (!psp->tmr_bo && !psp->boot_time_tmr) { 832 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 833 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 834 PSP_TMR_ALIGNMENT, 835 AMDGPU_HAS_VRAM(psp->adev) ? 836 AMDGPU_GEM_DOMAIN_VRAM : 837 AMDGPU_GEM_DOMAIN_GTT, 838 &psp->tmr_bo, &psp->tmr_mc_addr, 839 pptr); 840 } 841 842 return ret; 843 } 844 845 static bool psp_skip_tmr(struct psp_context *psp) 846 { 847 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 848 case IP_VERSION(11, 0, 9): 849 case IP_VERSION(11, 0, 7): 850 case IP_VERSION(13, 0, 2): 851 case IP_VERSION(13, 0, 6): 852 case IP_VERSION(13, 0, 10): 853 case IP_VERSION(13, 0, 14): 854 return true; 855 default: 856 return false; 857 } 858 } 859 860 static int psp_tmr_load(struct psp_context *psp) 861 { 862 int ret; 863 struct psp_gfx_cmd_resp *cmd; 864 865 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 866 * Already set up by host driver. 867 */ 868 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 869 return 0; 870 871 cmd = acquire_psp_cmd_buf(psp); 872 873 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 874 if (psp->tmr_bo) 875 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 876 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 877 878 ret = psp_cmd_submit_buf(psp, NULL, cmd, 879 psp->fence_buf_mc_addr); 880 881 release_psp_cmd_buf(psp); 882 883 return ret; 884 } 885 886 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 887 struct psp_gfx_cmd_resp *cmd) 888 { 889 if (amdgpu_sriov_vf(psp->adev)) 890 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 891 else 892 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 893 } 894 895 static int psp_tmr_unload(struct psp_context *psp) 896 { 897 int ret; 898 struct psp_gfx_cmd_resp *cmd; 899 900 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, 901 * as TMR is not loaded at all 902 */ 903 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 904 return 0; 905 906 cmd = acquire_psp_cmd_buf(psp); 907 908 psp_prep_tmr_unload_cmd_buf(psp, cmd); 909 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 910 911 ret = psp_cmd_submit_buf(psp, NULL, cmd, 912 psp->fence_buf_mc_addr); 913 914 release_psp_cmd_buf(psp); 915 916 return ret; 917 } 918 919 static int psp_tmr_terminate(struct psp_context *psp) 920 { 921 return psp_tmr_unload(psp); 922 } 923 924 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 925 uint64_t *output_ptr) 926 { 927 int ret; 928 struct psp_gfx_cmd_resp *cmd; 929 930 if (!output_ptr) 931 return -EINVAL; 932 933 if (amdgpu_sriov_vf(psp->adev)) 934 return 0; 935 936 cmd = acquire_psp_cmd_buf(psp); 937 938 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 939 940 ret = psp_cmd_submit_buf(psp, NULL, cmd, 941 psp->fence_buf_mc_addr); 942 943 if (!ret) { 944 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 945 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 946 } 947 948 release_psp_cmd_buf(psp); 949 950 return ret; 951 } 952 953 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 954 { 955 struct psp_context *psp = &adev->psp; 956 struct psp_gfx_cmd_resp *cmd; 957 int ret; 958 959 if (amdgpu_sriov_vf(adev)) 960 return 0; 961 962 cmd = acquire_psp_cmd_buf(psp); 963 964 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 965 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 966 967 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 968 if (!ret) { 969 *boot_cfg = 970 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 971 } 972 973 release_psp_cmd_buf(psp); 974 975 return ret; 976 } 977 978 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 979 { 980 int ret; 981 struct psp_context *psp = &adev->psp; 982 struct psp_gfx_cmd_resp *cmd; 983 984 if (amdgpu_sriov_vf(adev)) 985 return 0; 986 987 cmd = acquire_psp_cmd_buf(psp); 988 989 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 990 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 991 cmd->cmd.boot_cfg.boot_config = boot_cfg; 992 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 993 994 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 995 996 release_psp_cmd_buf(psp); 997 998 return ret; 999 } 1000 1001 static int psp_rl_load(struct amdgpu_device *adev) 1002 { 1003 int ret; 1004 struct psp_context *psp = &adev->psp; 1005 struct psp_gfx_cmd_resp *cmd; 1006 1007 if (!is_psp_fw_valid(psp->rl)) 1008 return 0; 1009 1010 cmd = acquire_psp_cmd_buf(psp); 1011 1012 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1013 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 1014 1015 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1016 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1017 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1018 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1019 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1020 1021 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1022 1023 release_psp_cmd_buf(psp); 1024 1025 return ret; 1026 } 1027 1028 int psp_spatial_partition(struct psp_context *psp, int mode) 1029 { 1030 struct psp_gfx_cmd_resp *cmd; 1031 int ret; 1032 1033 if (amdgpu_sriov_vf(psp->adev)) 1034 return 0; 1035 1036 cmd = acquire_psp_cmd_buf(psp); 1037 1038 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1039 cmd->cmd.cmd_spatial_part.mode = mode; 1040 1041 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1042 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1043 1044 release_psp_cmd_buf(psp); 1045 1046 return ret; 1047 } 1048 1049 static int psp_asd_initialize(struct psp_context *psp) 1050 { 1051 int ret; 1052 1053 /* If PSP version doesn't match ASD version, asd loading will be failed. 1054 * add workaround to bypass it for sriov now. 1055 * TODO: add version check to make it common 1056 */ 1057 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1058 return 0; 1059 1060 /* bypass asd if display hardware is not available */ 1061 if (!amdgpu_device_has_display_hardware(psp->adev) && 1062 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1063 return 0; 1064 1065 psp->asd_context.mem_context.shared_mc_addr = 0; 1066 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1067 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1068 1069 ret = psp_ta_load(psp, &psp->asd_context); 1070 if (!ret) 1071 psp->asd_context.initialized = true; 1072 1073 return ret; 1074 } 1075 1076 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1077 uint32_t session_id) 1078 { 1079 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1080 cmd->cmd.cmd_unload_ta.session_id = session_id; 1081 } 1082 1083 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1084 { 1085 int ret; 1086 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1087 1088 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1089 1090 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1091 1092 context->resp_status = cmd->resp.status; 1093 1094 release_psp_cmd_buf(psp); 1095 1096 return ret; 1097 } 1098 1099 static int psp_asd_terminate(struct psp_context *psp) 1100 { 1101 int ret; 1102 1103 if (amdgpu_sriov_vf(psp->adev)) 1104 return 0; 1105 1106 if (!psp->asd_context.initialized) 1107 return 0; 1108 1109 ret = psp_ta_unload(psp, &psp->asd_context); 1110 if (!ret) 1111 psp->asd_context.initialized = false; 1112 1113 return ret; 1114 } 1115 1116 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1117 uint32_t id, uint32_t value) 1118 { 1119 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1120 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1121 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1122 } 1123 1124 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1125 uint32_t value) 1126 { 1127 struct psp_gfx_cmd_resp *cmd; 1128 int ret = 0; 1129 1130 if (reg >= PSP_REG_LAST) 1131 return -EINVAL; 1132 1133 cmd = acquire_psp_cmd_buf(psp); 1134 1135 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1136 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1137 if (ret) 1138 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1139 1140 release_psp_cmd_buf(psp); 1141 1142 return ret; 1143 } 1144 1145 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1146 uint64_t ta_bin_mc, 1147 struct ta_context *context) 1148 { 1149 cmd->cmd_id = context->ta_load_type; 1150 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1151 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1152 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1153 1154 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1155 lower_32_bits(context->mem_context.shared_mc_addr); 1156 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1157 upper_32_bits(context->mem_context.shared_mc_addr); 1158 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1159 } 1160 1161 int psp_ta_init_shared_buf(struct psp_context *psp, 1162 struct ta_mem_context *mem_ctx) 1163 { 1164 /* 1165 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1166 * physical) for ta to host memory 1167 */ 1168 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1169 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1170 AMDGPU_GEM_DOMAIN_GTT, 1171 &mem_ctx->shared_bo, 1172 &mem_ctx->shared_mc_addr, 1173 &mem_ctx->shared_buf); 1174 } 1175 1176 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1177 uint32_t ta_cmd_id, 1178 uint32_t session_id) 1179 { 1180 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1181 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1182 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1183 } 1184 1185 int psp_ta_invoke(struct psp_context *psp, 1186 uint32_t ta_cmd_id, 1187 struct ta_context *context) 1188 { 1189 int ret; 1190 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1191 1192 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1195 psp->fence_buf_mc_addr); 1196 1197 context->resp_status = cmd->resp.status; 1198 1199 release_psp_cmd_buf(psp); 1200 1201 return ret; 1202 } 1203 1204 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1205 { 1206 int ret; 1207 struct psp_gfx_cmd_resp *cmd; 1208 1209 cmd = acquire_psp_cmd_buf(psp); 1210 1211 psp_copy_fw(psp, context->bin_desc.start_addr, 1212 context->bin_desc.size_bytes); 1213 1214 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1215 1216 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1217 psp->fence_buf_mc_addr); 1218 1219 context->resp_status = cmd->resp.status; 1220 1221 if (!ret) 1222 context->session_id = cmd->resp.session_id; 1223 1224 release_psp_cmd_buf(psp); 1225 1226 return ret; 1227 } 1228 1229 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1230 { 1231 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1232 } 1233 1234 int psp_xgmi_terminate(struct psp_context *psp) 1235 { 1236 int ret; 1237 struct amdgpu_device *adev = psp->adev; 1238 1239 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1240 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1241 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1242 adev->gmc.xgmi.connected_to_cpu)) 1243 return 0; 1244 1245 if (!psp->xgmi_context.context.initialized) 1246 return 0; 1247 1248 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1249 1250 psp->xgmi_context.context.initialized = false; 1251 1252 return ret; 1253 } 1254 1255 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1256 { 1257 struct ta_xgmi_shared_memory *xgmi_cmd; 1258 int ret; 1259 1260 if (!psp->ta_fw || 1261 !psp->xgmi_context.context.bin_desc.size_bytes || 1262 !psp->xgmi_context.context.bin_desc.start_addr) 1263 return -ENOENT; 1264 1265 if (!load_ta) 1266 goto invoke; 1267 1268 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1269 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1270 1271 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1272 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1273 if (ret) 1274 return ret; 1275 } 1276 1277 /* Load XGMI TA */ 1278 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1279 if (!ret) 1280 psp->xgmi_context.context.initialized = true; 1281 else 1282 return ret; 1283 1284 invoke: 1285 /* Initialize XGMI session */ 1286 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1287 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1288 xgmi_cmd->flag_extend_link_record = set_extended_data; 1289 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1290 1291 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1292 /* note down the capbility flag for XGMI TA */ 1293 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1294 1295 return ret; 1296 } 1297 1298 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1299 { 1300 struct ta_xgmi_shared_memory *xgmi_cmd; 1301 int ret; 1302 1303 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1304 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1305 1306 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1307 1308 /* Invoke xgmi ta to get hive id */ 1309 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1310 if (ret) 1311 return ret; 1312 1313 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1314 1315 return 0; 1316 } 1317 1318 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1319 { 1320 struct ta_xgmi_shared_memory *xgmi_cmd; 1321 int ret; 1322 1323 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1324 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1325 1326 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1327 1328 /* Invoke xgmi ta to get the node id */ 1329 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1330 if (ret) 1331 return ret; 1332 1333 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1334 1335 return 0; 1336 } 1337 1338 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1339 { 1340 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1341 IP_VERSION(13, 0, 2) && 1342 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1343 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1344 IP_VERSION(13, 0, 6); 1345 } 1346 1347 /* 1348 * Chips that support extended topology information require the driver to 1349 * reflect topology information in the opposite direction. This is 1350 * because the TA has already exceeded its link record limit and if the 1351 * TA holds bi-directional information, the driver would have to do 1352 * multiple fetches instead of just two. 1353 */ 1354 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1355 struct psp_xgmi_node_info node_info) 1356 { 1357 struct amdgpu_device *mirror_adev; 1358 struct amdgpu_hive_info *hive; 1359 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1360 uint64_t dst_node_id = node_info.node_id; 1361 uint8_t dst_num_hops = node_info.num_hops; 1362 uint8_t dst_num_links = node_info.num_links; 1363 1364 hive = amdgpu_get_xgmi_hive(psp->adev); 1365 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1366 struct psp_xgmi_topology_info *mirror_top_info; 1367 int j; 1368 1369 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1370 continue; 1371 1372 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1373 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1374 if (mirror_top_info->nodes[j].node_id != src_node_id) 1375 continue; 1376 1377 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1378 /* 1379 * prevent 0 num_links value re-reflection since reflection 1380 * criteria is based on num_hops (direct or indirect). 1381 * 1382 */ 1383 if (dst_num_links) 1384 mirror_top_info->nodes[j].num_links = dst_num_links; 1385 1386 break; 1387 } 1388 1389 break; 1390 } 1391 1392 amdgpu_put_xgmi_hive(hive); 1393 } 1394 1395 int psp_xgmi_get_topology_info(struct psp_context *psp, 1396 int number_devices, 1397 struct psp_xgmi_topology_info *topology, 1398 bool get_extended_data) 1399 { 1400 struct ta_xgmi_shared_memory *xgmi_cmd; 1401 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1402 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1403 int i; 1404 int ret; 1405 1406 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1407 return -EINVAL; 1408 1409 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1410 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1411 xgmi_cmd->flag_extend_link_record = get_extended_data; 1412 1413 /* Fill in the shared memory with topology information as input */ 1414 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1415 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 1416 topology_info_input->num_nodes = number_devices; 1417 1418 for (i = 0; i < topology_info_input->num_nodes; i++) { 1419 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1420 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1421 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1422 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1423 } 1424 1425 /* Invoke xgmi ta to get the topology information */ 1426 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 1427 if (ret) 1428 return ret; 1429 1430 /* Read the output topology information from the shared memory */ 1431 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1432 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1433 for (i = 0; i < topology->num_nodes; i++) { 1434 /* extended data will either be 0 or equal to non-extended data */ 1435 if (topology_info_output->nodes[i].num_hops) 1436 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1437 1438 /* non-extended data gets everything here so no need to update */ 1439 if (!get_extended_data) { 1440 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1441 topology->nodes[i].is_sharing_enabled = 1442 topology_info_output->nodes[i].is_sharing_enabled; 1443 topology->nodes[i].sdma_engine = 1444 topology_info_output->nodes[i].sdma_engine; 1445 } 1446 1447 } 1448 1449 /* Invoke xgmi ta again to get the link information */ 1450 if (psp_xgmi_peer_link_info_supported(psp)) { 1451 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 1452 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 1453 bool requires_reflection = 1454 (psp->xgmi_context.supports_extended_data && 1455 get_extended_data) || 1456 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1457 IP_VERSION(13, 0, 6) || 1458 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1459 IP_VERSION(13, 0, 14); 1460 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : 1461 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; 1462 1463 /* popluate the shared output buffer rather than the cmd input buffer 1464 * with node_ids as the input for GET_PEER_LINKS command execution. 1465 * This is required for GET_PEER_LINKS per xgmi ta implementation. 1466 * The same requirement for GET_EXTEND_PEER_LINKS command. 1467 */ 1468 if (ta_port_num_support) { 1469 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 1470 1471 for (i = 0; i < topology->num_nodes; i++) 1472 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1473 1474 link_extend_info_output->num_nodes = topology->num_nodes; 1475 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 1476 } else { 1477 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1478 1479 for (i = 0; i < topology->num_nodes; i++) 1480 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 1481 1482 link_info_output->num_nodes = topology->num_nodes; 1483 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1484 } 1485 1486 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1487 if (ret) 1488 return ret; 1489 1490 for (i = 0; i < topology->num_nodes; i++) { 1491 uint8_t node_num_links = ta_port_num_support ? 1492 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 1493 /* accumulate num_links on extended data */ 1494 if (get_extended_data) { 1495 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 1496 } else { 1497 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 1498 topology->nodes[i].num_links : node_num_links; 1499 } 1500 /* popluate the connected port num info if supported and available */ 1501 if (ta_port_num_support && topology->nodes[i].num_links) { 1502 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 1503 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 1504 } 1505 1506 /* reflect the topology information for bi-directionality */ 1507 if (requires_reflection && topology->nodes[i].num_hops) 1508 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1509 } 1510 } 1511 1512 return 0; 1513 } 1514 1515 int psp_xgmi_set_topology_info(struct psp_context *psp, 1516 int number_devices, 1517 struct psp_xgmi_topology_info *topology) 1518 { 1519 struct ta_xgmi_shared_memory *xgmi_cmd; 1520 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1521 int i; 1522 1523 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1524 return -EINVAL; 1525 1526 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1527 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1528 1529 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1530 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1531 topology_info_input->num_nodes = number_devices; 1532 1533 for (i = 0; i < topology_info_input->num_nodes; i++) { 1534 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1535 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1536 topology_info_input->nodes[i].is_sharing_enabled = 1; 1537 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1538 } 1539 1540 /* Invoke xgmi ta to set topology information */ 1541 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1542 } 1543 1544 // ras begin 1545 static void psp_ras_ta_check_status(struct psp_context *psp) 1546 { 1547 struct ta_ras_shared_memory *ras_cmd = 1548 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1549 1550 switch (ras_cmd->ras_status) { 1551 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1552 dev_warn(psp->adev->dev, 1553 "RAS WARNING: cmd failed due to unsupported ip\n"); 1554 break; 1555 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1556 dev_warn(psp->adev->dev, 1557 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1558 break; 1559 case TA_RAS_STATUS__SUCCESS: 1560 break; 1561 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1562 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1563 dev_warn(psp->adev->dev, 1564 "RAS WARNING: Inject error to critical region is not allowed\n"); 1565 break; 1566 default: 1567 dev_warn(psp->adev->dev, 1568 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1569 break; 1570 } 1571 } 1572 1573 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1574 { 1575 struct ta_ras_shared_memory *ras_cmd; 1576 int ret; 1577 1578 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1579 1580 /* 1581 * TODO: bypass the loading in sriov for now 1582 */ 1583 if (amdgpu_sriov_vf(psp->adev)) 1584 return 0; 1585 1586 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1587 1588 if (amdgpu_ras_intr_triggered()) 1589 return ret; 1590 1591 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 1592 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 1593 return -EINVAL; 1594 } 1595 1596 if (!ret) { 1597 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1598 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1599 1600 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1601 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1602 dev_warn(psp->adev->dev, 1603 "RAS internal register access blocked\n"); 1604 1605 psp_ras_ta_check_status(psp); 1606 } 1607 1608 return ret; 1609 } 1610 1611 int psp_ras_enable_features(struct psp_context *psp, 1612 union ta_ras_cmd_input *info, bool enable) 1613 { 1614 struct ta_ras_shared_memory *ras_cmd; 1615 int ret; 1616 1617 if (!psp->ras_context.context.initialized) 1618 return -EINVAL; 1619 1620 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1621 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1622 1623 if (enable) 1624 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1625 else 1626 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1627 1628 ras_cmd->ras_in_message = *info; 1629 1630 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1631 if (ret) 1632 return -EINVAL; 1633 1634 return 0; 1635 } 1636 1637 int psp_ras_terminate(struct psp_context *psp) 1638 { 1639 int ret; 1640 1641 /* 1642 * TODO: bypass the terminate in sriov for now 1643 */ 1644 if (amdgpu_sriov_vf(psp->adev)) 1645 return 0; 1646 1647 if (!psp->ras_context.context.initialized) 1648 return 0; 1649 1650 ret = psp_ta_unload(psp, &psp->ras_context.context); 1651 1652 psp->ras_context.context.initialized = false; 1653 1654 return ret; 1655 } 1656 1657 int psp_ras_initialize(struct psp_context *psp) 1658 { 1659 int ret; 1660 uint32_t boot_cfg = 0xFF; 1661 struct amdgpu_device *adev = psp->adev; 1662 struct ta_ras_shared_memory *ras_cmd; 1663 1664 /* 1665 * TODO: bypass the initialize in sriov for now 1666 */ 1667 if (amdgpu_sriov_vf(adev)) 1668 return 0; 1669 1670 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1671 !adev->psp.ras_context.context.bin_desc.start_addr) { 1672 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1673 return 0; 1674 } 1675 1676 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1677 /* query GECC enablement status from boot config 1678 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1679 */ 1680 ret = psp_boot_config_get(adev, &boot_cfg); 1681 if (ret) 1682 dev_warn(adev->dev, "PSP get boot config failed\n"); 1683 1684 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1685 if (!boot_cfg) { 1686 dev_info(adev->dev, "GECC is disabled\n"); 1687 } else { 1688 /* disable GECC in next boot cycle if ras is 1689 * disabled by module parameter amdgpu_ras_enable 1690 * and/or amdgpu_ras_mask, or boot_config_get call 1691 * is failed 1692 */ 1693 ret = psp_boot_config_set(adev, 0); 1694 if (ret) 1695 dev_warn(adev->dev, "PSP set boot config failed\n"); 1696 else 1697 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1698 } 1699 } else { 1700 if (boot_cfg == 1) { 1701 dev_info(adev->dev, "GECC is enabled\n"); 1702 } else { 1703 /* enable GECC in next boot cycle if it is disabled 1704 * in boot config, or force enable GECC if failed to 1705 * get boot configuration 1706 */ 1707 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1708 if (ret) 1709 dev_warn(adev->dev, "PSP set boot config failed\n"); 1710 else 1711 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1712 } 1713 } 1714 } 1715 1716 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1717 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1718 1719 if (!psp->ras_context.context.mem_context.shared_buf) { 1720 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1721 if (ret) 1722 return ret; 1723 } 1724 1725 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1726 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1727 1728 if (amdgpu_ras_is_poison_mode_supported(adev)) 1729 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1730 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1731 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1732 ras_cmd->ras_in_message.init_flags.xcc_mask = 1733 adev->gfx.xcc_mask; 1734 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1735 1736 ret = psp_ta_load(psp, &psp->ras_context.context); 1737 1738 if (!ret && !ras_cmd->ras_status) 1739 psp->ras_context.context.initialized = true; 1740 else { 1741 if (ras_cmd->ras_status) 1742 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1743 1744 /* fail to load RAS TA */ 1745 psp->ras_context.context.initialized = false; 1746 } 1747 1748 return ret; 1749 } 1750 1751 int psp_ras_trigger_error(struct psp_context *psp, 1752 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 1753 { 1754 struct ta_ras_shared_memory *ras_cmd; 1755 struct amdgpu_device *adev = psp->adev; 1756 int ret; 1757 uint32_t dev_mask; 1758 1759 if (!psp->ras_context.context.initialized) 1760 return -EINVAL; 1761 1762 switch (info->block_id) { 1763 case TA_RAS_BLOCK__GFX: 1764 dev_mask = GET_MASK(GC, instance_mask); 1765 break; 1766 case TA_RAS_BLOCK__SDMA: 1767 dev_mask = GET_MASK(SDMA0, instance_mask); 1768 break; 1769 case TA_RAS_BLOCK__VCN: 1770 case TA_RAS_BLOCK__JPEG: 1771 dev_mask = GET_MASK(VCN, instance_mask); 1772 break; 1773 default: 1774 dev_mask = instance_mask; 1775 break; 1776 } 1777 1778 /* reuse sub_block_index for backward compatibility */ 1779 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 1780 dev_mask &= AMDGPU_RAS_INST_MASK; 1781 info->sub_block_index |= dev_mask; 1782 1783 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1784 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1785 1786 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1787 ras_cmd->ras_in_message.trigger_error = *info; 1788 1789 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1790 if (ret) 1791 return -EINVAL; 1792 1793 /* If err_event_athub occurs error inject was successful, however 1794 * return status from TA is no long reliable 1795 */ 1796 if (amdgpu_ras_intr_triggered()) 1797 return 0; 1798 1799 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1800 return -EACCES; 1801 else if (ras_cmd->ras_status) 1802 return -EINVAL; 1803 1804 return 0; 1805 } 1806 1807 int psp_ras_query_address(struct psp_context *psp, 1808 struct ta_ras_query_address_input *addr_in, 1809 struct ta_ras_query_address_output *addr_out) 1810 { 1811 struct ta_ras_shared_memory *ras_cmd; 1812 int ret; 1813 1814 if (!psp->ras_context.context.initialized) 1815 return -EINVAL; 1816 1817 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1818 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1819 1820 ras_cmd->cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS; 1821 ras_cmd->ras_in_message.address = *addr_in; 1822 1823 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1824 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 1825 return -EINVAL; 1826 1827 *addr_out = ras_cmd->ras_out_message.address; 1828 1829 return 0; 1830 } 1831 // ras end 1832 1833 // HDCP start 1834 static int psp_hdcp_initialize(struct psp_context *psp) 1835 { 1836 int ret; 1837 1838 /* 1839 * TODO: bypass the initialize in sriov for now 1840 */ 1841 if (amdgpu_sriov_vf(psp->adev)) 1842 return 0; 1843 1844 /* bypass hdcp initialization if dmu is harvested */ 1845 if (!amdgpu_device_has_display_hardware(psp->adev)) 1846 return 0; 1847 1848 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1849 !psp->hdcp_context.context.bin_desc.start_addr) { 1850 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1851 return 0; 1852 } 1853 1854 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1855 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1856 1857 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1858 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1859 if (ret) 1860 return ret; 1861 } 1862 1863 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1864 if (!ret) { 1865 psp->hdcp_context.context.initialized = true; 1866 mutex_init(&psp->hdcp_context.mutex); 1867 } 1868 1869 return ret; 1870 } 1871 1872 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1873 { 1874 /* 1875 * TODO: bypass the loading in sriov for now 1876 */ 1877 if (amdgpu_sriov_vf(psp->adev)) 1878 return 0; 1879 1880 if (!psp->hdcp_context.context.initialized) 1881 return 0; 1882 1883 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1884 } 1885 1886 static int psp_hdcp_terminate(struct psp_context *psp) 1887 { 1888 int ret; 1889 1890 /* 1891 * TODO: bypass the terminate in sriov for now 1892 */ 1893 if (amdgpu_sriov_vf(psp->adev)) 1894 return 0; 1895 1896 if (!psp->hdcp_context.context.initialized) 1897 return 0; 1898 1899 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1900 1901 psp->hdcp_context.context.initialized = false; 1902 1903 return ret; 1904 } 1905 // HDCP end 1906 1907 // DTM start 1908 static int psp_dtm_initialize(struct psp_context *psp) 1909 { 1910 int ret; 1911 1912 /* 1913 * TODO: bypass the initialize in sriov for now 1914 */ 1915 if (amdgpu_sriov_vf(psp->adev)) 1916 return 0; 1917 1918 /* bypass dtm initialization if dmu is harvested */ 1919 if (!amdgpu_device_has_display_hardware(psp->adev)) 1920 return 0; 1921 1922 if (!psp->dtm_context.context.bin_desc.size_bytes || 1923 !psp->dtm_context.context.bin_desc.start_addr) { 1924 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1925 return 0; 1926 } 1927 1928 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1929 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1930 1931 if (!psp->dtm_context.context.mem_context.shared_buf) { 1932 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1933 if (ret) 1934 return ret; 1935 } 1936 1937 ret = psp_ta_load(psp, &psp->dtm_context.context); 1938 if (!ret) { 1939 psp->dtm_context.context.initialized = true; 1940 mutex_init(&psp->dtm_context.mutex); 1941 } 1942 1943 return ret; 1944 } 1945 1946 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1947 { 1948 /* 1949 * TODO: bypass the loading in sriov for now 1950 */ 1951 if (amdgpu_sriov_vf(psp->adev)) 1952 return 0; 1953 1954 if (!psp->dtm_context.context.initialized) 1955 return 0; 1956 1957 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1958 } 1959 1960 static int psp_dtm_terminate(struct psp_context *psp) 1961 { 1962 int ret; 1963 1964 /* 1965 * TODO: bypass the terminate in sriov for now 1966 */ 1967 if (amdgpu_sriov_vf(psp->adev)) 1968 return 0; 1969 1970 if (!psp->dtm_context.context.initialized) 1971 return 0; 1972 1973 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1974 1975 psp->dtm_context.context.initialized = false; 1976 1977 return ret; 1978 } 1979 // DTM end 1980 1981 // RAP start 1982 static int psp_rap_initialize(struct psp_context *psp) 1983 { 1984 int ret; 1985 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1986 1987 /* 1988 * TODO: bypass the initialize in sriov for now 1989 */ 1990 if (amdgpu_sriov_vf(psp->adev)) 1991 return 0; 1992 1993 if (!psp->rap_context.context.bin_desc.size_bytes || 1994 !psp->rap_context.context.bin_desc.start_addr) { 1995 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1996 return 0; 1997 } 1998 1999 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2000 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2001 2002 if (!psp->rap_context.context.mem_context.shared_buf) { 2003 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2004 if (ret) 2005 return ret; 2006 } 2007 2008 ret = psp_ta_load(psp, &psp->rap_context.context); 2009 if (!ret) { 2010 psp->rap_context.context.initialized = true; 2011 mutex_init(&psp->rap_context.mutex); 2012 } else 2013 return ret; 2014 2015 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2016 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2017 psp_rap_terminate(psp); 2018 /* free rap shared memory */ 2019 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2020 2021 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2022 ret, status); 2023 2024 return ret; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int psp_rap_terminate(struct psp_context *psp) 2031 { 2032 int ret; 2033 2034 if (!psp->rap_context.context.initialized) 2035 return 0; 2036 2037 ret = psp_ta_unload(psp, &psp->rap_context.context); 2038 2039 psp->rap_context.context.initialized = false; 2040 2041 return ret; 2042 } 2043 2044 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2045 { 2046 struct ta_rap_shared_memory *rap_cmd; 2047 int ret = 0; 2048 2049 if (!psp->rap_context.context.initialized) 2050 return 0; 2051 2052 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2053 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2054 return -EINVAL; 2055 2056 mutex_lock(&psp->rap_context.mutex); 2057 2058 rap_cmd = (struct ta_rap_shared_memory *) 2059 psp->rap_context.context.mem_context.shared_buf; 2060 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2061 2062 rap_cmd->cmd_id = ta_cmd_id; 2063 rap_cmd->validation_method_id = METHOD_A; 2064 2065 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2066 if (ret) 2067 goto out_unlock; 2068 2069 if (status) 2070 *status = rap_cmd->rap_status; 2071 2072 out_unlock: 2073 mutex_unlock(&psp->rap_context.mutex); 2074 2075 return ret; 2076 } 2077 // RAP end 2078 2079 /* securedisplay start */ 2080 static int psp_securedisplay_initialize(struct psp_context *psp) 2081 { 2082 int ret; 2083 struct ta_securedisplay_cmd *securedisplay_cmd; 2084 2085 /* 2086 * TODO: bypass the initialize in sriov for now 2087 */ 2088 if (amdgpu_sriov_vf(psp->adev)) 2089 return 0; 2090 2091 /* bypass securedisplay initialization if dmu is harvested */ 2092 if (!amdgpu_device_has_display_hardware(psp->adev)) 2093 return 0; 2094 2095 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2096 !psp->securedisplay_context.context.bin_desc.start_addr) { 2097 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2098 return 0; 2099 } 2100 2101 psp->securedisplay_context.context.mem_context.shared_mem_size = 2102 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2103 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2104 2105 if (!psp->securedisplay_context.context.initialized) { 2106 ret = psp_ta_init_shared_buf(psp, 2107 &psp->securedisplay_context.context.mem_context); 2108 if (ret) 2109 return ret; 2110 } 2111 2112 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2113 if (!ret) { 2114 psp->securedisplay_context.context.initialized = true; 2115 mutex_init(&psp->securedisplay_context.mutex); 2116 } else 2117 return ret; 2118 2119 mutex_lock(&psp->securedisplay_context.mutex); 2120 2121 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2122 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2123 2124 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2125 2126 mutex_unlock(&psp->securedisplay_context.mutex); 2127 2128 if (ret) { 2129 psp_securedisplay_terminate(psp); 2130 /* free securedisplay shared memory */ 2131 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2132 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2133 return -EINVAL; 2134 } 2135 2136 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2137 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2138 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2139 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2140 /* don't try again */ 2141 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int psp_securedisplay_terminate(struct psp_context *psp) 2148 { 2149 int ret; 2150 2151 /* 2152 * TODO:bypass the terminate in sriov for now 2153 */ 2154 if (amdgpu_sriov_vf(psp->adev)) 2155 return 0; 2156 2157 if (!psp->securedisplay_context.context.initialized) 2158 return 0; 2159 2160 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2161 2162 psp->securedisplay_context.context.initialized = false; 2163 2164 return ret; 2165 } 2166 2167 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2168 { 2169 int ret; 2170 2171 if (!psp->securedisplay_context.context.initialized) 2172 return -EINVAL; 2173 2174 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2175 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2176 return -EINVAL; 2177 2178 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2179 2180 return ret; 2181 } 2182 /* SECUREDISPLAY end */ 2183 2184 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2185 { 2186 struct psp_context *psp = &adev->psp; 2187 int ret = 0; 2188 2189 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2190 ret = psp->funcs->wait_for_bootloader(psp); 2191 2192 return ret; 2193 } 2194 2195 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2196 { 2197 if (psp->funcs && 2198 psp->funcs->get_ras_capability) { 2199 return psp->funcs->get_ras_capability(psp); 2200 } else { 2201 return false; 2202 } 2203 } 2204 2205 static int psp_hw_start(struct psp_context *psp) 2206 { 2207 struct amdgpu_device *adev = psp->adev; 2208 int ret; 2209 2210 if (!amdgpu_sriov_vf(adev)) { 2211 if ((is_psp_fw_valid(psp->kdb)) && 2212 (psp->funcs->bootloader_load_kdb != NULL)) { 2213 ret = psp_bootloader_load_kdb(psp); 2214 if (ret) { 2215 dev_err(adev->dev, "PSP load kdb failed!\n"); 2216 return ret; 2217 } 2218 } 2219 2220 if ((is_psp_fw_valid(psp->spl)) && 2221 (psp->funcs->bootloader_load_spl != NULL)) { 2222 ret = psp_bootloader_load_spl(psp); 2223 if (ret) { 2224 dev_err(adev->dev, "PSP load spl failed!\n"); 2225 return ret; 2226 } 2227 } 2228 2229 if ((is_psp_fw_valid(psp->sys)) && 2230 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2231 ret = psp_bootloader_load_sysdrv(psp); 2232 if (ret) { 2233 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2234 return ret; 2235 } 2236 } 2237 2238 if ((is_psp_fw_valid(psp->soc_drv)) && 2239 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2240 ret = psp_bootloader_load_soc_drv(psp); 2241 if (ret) { 2242 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2243 return ret; 2244 } 2245 } 2246 2247 if ((is_psp_fw_valid(psp->intf_drv)) && 2248 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2249 ret = psp_bootloader_load_intf_drv(psp); 2250 if (ret) { 2251 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2252 return ret; 2253 } 2254 } 2255 2256 if ((is_psp_fw_valid(psp->dbg_drv)) && 2257 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2258 ret = psp_bootloader_load_dbg_drv(psp); 2259 if (ret) { 2260 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2261 return ret; 2262 } 2263 } 2264 2265 if ((is_psp_fw_valid(psp->ras_drv)) && 2266 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2267 ret = psp_bootloader_load_ras_drv(psp); 2268 if (ret) { 2269 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2270 return ret; 2271 } 2272 } 2273 2274 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2275 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2276 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2277 if (ret) { 2278 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2279 return ret; 2280 } 2281 } 2282 2283 if ((is_psp_fw_valid(psp->sos)) && 2284 (psp->funcs->bootloader_load_sos != NULL)) { 2285 ret = psp_bootloader_load_sos(psp); 2286 if (ret) { 2287 dev_err(adev->dev, "PSP load sos failed!\n"); 2288 return ret; 2289 } 2290 } 2291 } 2292 2293 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2294 if (ret) { 2295 dev_err(adev->dev, "PSP create ring failed!\n"); 2296 return ret; 2297 } 2298 2299 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2300 goto skip_pin_bo; 2301 2302 if (!psp->boot_time_tmr || psp->autoload_supported) { 2303 ret = psp_tmr_init(psp); 2304 if (ret) { 2305 dev_err(adev->dev, "PSP tmr init failed!\n"); 2306 return ret; 2307 } 2308 } 2309 2310 skip_pin_bo: 2311 /* 2312 * For ASICs with DF Cstate management centralized 2313 * to PMFW, TMR setup should be performed after PMFW 2314 * loaded and before other non-psp firmware loaded. 2315 */ 2316 if (psp->pmfw_centralized_cstate_management) { 2317 ret = psp_load_smu_fw(psp); 2318 if (ret) 2319 return ret; 2320 } 2321 2322 if (!psp->boot_time_tmr || !psp->autoload_supported) { 2323 ret = psp_tmr_load(psp); 2324 if (ret) { 2325 dev_err(adev->dev, "PSP load tmr failed!\n"); 2326 return ret; 2327 } 2328 } 2329 2330 return 0; 2331 } 2332 2333 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2334 enum psp_gfx_fw_type *type) 2335 { 2336 switch (ucode->ucode_id) { 2337 case AMDGPU_UCODE_ID_CAP: 2338 *type = GFX_FW_TYPE_CAP; 2339 break; 2340 case AMDGPU_UCODE_ID_SDMA0: 2341 *type = GFX_FW_TYPE_SDMA0; 2342 break; 2343 case AMDGPU_UCODE_ID_SDMA1: 2344 *type = GFX_FW_TYPE_SDMA1; 2345 break; 2346 case AMDGPU_UCODE_ID_SDMA2: 2347 *type = GFX_FW_TYPE_SDMA2; 2348 break; 2349 case AMDGPU_UCODE_ID_SDMA3: 2350 *type = GFX_FW_TYPE_SDMA3; 2351 break; 2352 case AMDGPU_UCODE_ID_SDMA4: 2353 *type = GFX_FW_TYPE_SDMA4; 2354 break; 2355 case AMDGPU_UCODE_ID_SDMA5: 2356 *type = GFX_FW_TYPE_SDMA5; 2357 break; 2358 case AMDGPU_UCODE_ID_SDMA6: 2359 *type = GFX_FW_TYPE_SDMA6; 2360 break; 2361 case AMDGPU_UCODE_ID_SDMA7: 2362 *type = GFX_FW_TYPE_SDMA7; 2363 break; 2364 case AMDGPU_UCODE_ID_CP_MES: 2365 *type = GFX_FW_TYPE_CP_MES; 2366 break; 2367 case AMDGPU_UCODE_ID_CP_MES_DATA: 2368 *type = GFX_FW_TYPE_MES_STACK; 2369 break; 2370 case AMDGPU_UCODE_ID_CP_MES1: 2371 *type = GFX_FW_TYPE_CP_MES_KIQ; 2372 break; 2373 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2374 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2375 break; 2376 case AMDGPU_UCODE_ID_CP_CE: 2377 *type = GFX_FW_TYPE_CP_CE; 2378 break; 2379 case AMDGPU_UCODE_ID_CP_PFP: 2380 *type = GFX_FW_TYPE_CP_PFP; 2381 break; 2382 case AMDGPU_UCODE_ID_CP_ME: 2383 *type = GFX_FW_TYPE_CP_ME; 2384 break; 2385 case AMDGPU_UCODE_ID_CP_MEC1: 2386 *type = GFX_FW_TYPE_CP_MEC; 2387 break; 2388 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2389 *type = GFX_FW_TYPE_CP_MEC_ME1; 2390 break; 2391 case AMDGPU_UCODE_ID_CP_MEC2: 2392 *type = GFX_FW_TYPE_CP_MEC; 2393 break; 2394 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2395 *type = GFX_FW_TYPE_CP_MEC_ME2; 2396 break; 2397 case AMDGPU_UCODE_ID_RLC_P: 2398 *type = GFX_FW_TYPE_RLC_P; 2399 break; 2400 case AMDGPU_UCODE_ID_RLC_V: 2401 *type = GFX_FW_TYPE_RLC_V; 2402 break; 2403 case AMDGPU_UCODE_ID_RLC_G: 2404 *type = GFX_FW_TYPE_RLC_G; 2405 break; 2406 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2407 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2408 break; 2409 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2410 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2411 break; 2412 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2413 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2414 break; 2415 case AMDGPU_UCODE_ID_RLC_IRAM: 2416 *type = GFX_FW_TYPE_RLC_IRAM; 2417 break; 2418 case AMDGPU_UCODE_ID_RLC_DRAM: 2419 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2420 break; 2421 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2422 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2423 break; 2424 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2425 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2426 break; 2427 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2428 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2429 break; 2430 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2431 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2432 break; 2433 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2434 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2435 break; 2436 case AMDGPU_UCODE_ID_SMC: 2437 *type = GFX_FW_TYPE_SMU; 2438 break; 2439 case AMDGPU_UCODE_ID_PPTABLE: 2440 *type = GFX_FW_TYPE_PPTABLE; 2441 break; 2442 case AMDGPU_UCODE_ID_UVD: 2443 *type = GFX_FW_TYPE_UVD; 2444 break; 2445 case AMDGPU_UCODE_ID_UVD1: 2446 *type = GFX_FW_TYPE_UVD1; 2447 break; 2448 case AMDGPU_UCODE_ID_VCE: 2449 *type = GFX_FW_TYPE_VCE; 2450 break; 2451 case AMDGPU_UCODE_ID_VCN: 2452 *type = GFX_FW_TYPE_VCN; 2453 break; 2454 case AMDGPU_UCODE_ID_VCN1: 2455 *type = GFX_FW_TYPE_VCN1; 2456 break; 2457 case AMDGPU_UCODE_ID_DMCU_ERAM: 2458 *type = GFX_FW_TYPE_DMCU_ERAM; 2459 break; 2460 case AMDGPU_UCODE_ID_DMCU_INTV: 2461 *type = GFX_FW_TYPE_DMCU_ISR; 2462 break; 2463 case AMDGPU_UCODE_ID_VCN0_RAM: 2464 *type = GFX_FW_TYPE_VCN0_RAM; 2465 break; 2466 case AMDGPU_UCODE_ID_VCN1_RAM: 2467 *type = GFX_FW_TYPE_VCN1_RAM; 2468 break; 2469 case AMDGPU_UCODE_ID_DMCUB: 2470 *type = GFX_FW_TYPE_DMUB; 2471 break; 2472 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2473 case AMDGPU_UCODE_ID_SDMA_RS64: 2474 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2475 break; 2476 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2477 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2478 break; 2479 case AMDGPU_UCODE_ID_IMU_I: 2480 *type = GFX_FW_TYPE_IMU_I; 2481 break; 2482 case AMDGPU_UCODE_ID_IMU_D: 2483 *type = GFX_FW_TYPE_IMU_D; 2484 break; 2485 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2486 *type = GFX_FW_TYPE_RS64_PFP; 2487 break; 2488 case AMDGPU_UCODE_ID_CP_RS64_ME: 2489 *type = GFX_FW_TYPE_RS64_ME; 2490 break; 2491 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2492 *type = GFX_FW_TYPE_RS64_MEC; 2493 break; 2494 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2495 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2496 break; 2497 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2498 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2499 break; 2500 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2501 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2502 break; 2503 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2504 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2505 break; 2506 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2507 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2508 break; 2509 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2510 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2511 break; 2512 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2513 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2514 break; 2515 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2516 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2517 break; 2518 case AMDGPU_UCODE_ID_VPE_CTX: 2519 *type = GFX_FW_TYPE_VPEC_FW1; 2520 break; 2521 case AMDGPU_UCODE_ID_VPE_CTL: 2522 *type = GFX_FW_TYPE_VPEC_FW2; 2523 break; 2524 case AMDGPU_UCODE_ID_VPE: 2525 *type = GFX_FW_TYPE_VPE; 2526 break; 2527 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 2528 *type = GFX_FW_TYPE_UMSCH_UCODE; 2529 break; 2530 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 2531 *type = GFX_FW_TYPE_UMSCH_DATA; 2532 break; 2533 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 2534 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 2535 break; 2536 case AMDGPU_UCODE_ID_P2S_TABLE: 2537 *type = GFX_FW_TYPE_P2S_TABLE; 2538 break; 2539 case AMDGPU_UCODE_ID_JPEG_RAM: 2540 *type = GFX_FW_TYPE_JPEG_RAM; 2541 break; 2542 case AMDGPU_UCODE_ID_MAXIMUM: 2543 default: 2544 return -EINVAL; 2545 } 2546 2547 return 0; 2548 } 2549 2550 static void psp_print_fw_hdr(struct psp_context *psp, 2551 struct amdgpu_firmware_info *ucode) 2552 { 2553 struct amdgpu_device *adev = psp->adev; 2554 struct common_firmware_header *hdr; 2555 2556 switch (ucode->ucode_id) { 2557 case AMDGPU_UCODE_ID_SDMA0: 2558 case AMDGPU_UCODE_ID_SDMA1: 2559 case AMDGPU_UCODE_ID_SDMA2: 2560 case AMDGPU_UCODE_ID_SDMA3: 2561 case AMDGPU_UCODE_ID_SDMA4: 2562 case AMDGPU_UCODE_ID_SDMA5: 2563 case AMDGPU_UCODE_ID_SDMA6: 2564 case AMDGPU_UCODE_ID_SDMA7: 2565 hdr = (struct common_firmware_header *) 2566 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2567 amdgpu_ucode_print_sdma_hdr(hdr); 2568 break; 2569 case AMDGPU_UCODE_ID_CP_CE: 2570 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2571 amdgpu_ucode_print_gfx_hdr(hdr); 2572 break; 2573 case AMDGPU_UCODE_ID_CP_PFP: 2574 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2575 amdgpu_ucode_print_gfx_hdr(hdr); 2576 break; 2577 case AMDGPU_UCODE_ID_CP_ME: 2578 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2579 amdgpu_ucode_print_gfx_hdr(hdr); 2580 break; 2581 case AMDGPU_UCODE_ID_CP_MEC1: 2582 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2583 amdgpu_ucode_print_gfx_hdr(hdr); 2584 break; 2585 case AMDGPU_UCODE_ID_RLC_G: 2586 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2587 amdgpu_ucode_print_rlc_hdr(hdr); 2588 break; 2589 case AMDGPU_UCODE_ID_SMC: 2590 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2591 amdgpu_ucode_print_smc_hdr(hdr); 2592 break; 2593 default: 2594 break; 2595 } 2596 } 2597 2598 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 2599 struct amdgpu_firmware_info *ucode, 2600 struct psp_gfx_cmd_resp *cmd) 2601 { 2602 int ret; 2603 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2604 2605 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2606 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2607 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2608 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2609 2610 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2611 if (ret) 2612 dev_err(psp->adev->dev, "Unknown firmware type\n"); 2613 2614 return ret; 2615 } 2616 2617 int psp_execute_ip_fw_load(struct psp_context *psp, 2618 struct amdgpu_firmware_info *ucode) 2619 { 2620 int ret = 0; 2621 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2622 2623 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 2624 if (!ret) { 2625 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2626 psp->fence_buf_mc_addr); 2627 } 2628 2629 release_psp_cmd_buf(psp); 2630 2631 return ret; 2632 } 2633 2634 static int psp_load_p2s_table(struct psp_context *psp) 2635 { 2636 int ret; 2637 struct amdgpu_device *adev = psp->adev; 2638 struct amdgpu_firmware_info *ucode = 2639 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 2640 2641 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2642 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2643 return 0; 2644 2645 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 2646 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 2647 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 2648 0x0036003C; 2649 if (psp->sos.fw_version < supp_vers) 2650 return 0; 2651 } 2652 2653 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2654 return 0; 2655 2656 ret = psp_execute_ip_fw_load(psp, ucode); 2657 2658 return ret; 2659 } 2660 2661 static int psp_load_smu_fw(struct psp_context *psp) 2662 { 2663 int ret; 2664 struct amdgpu_device *adev = psp->adev; 2665 struct amdgpu_firmware_info *ucode = 2666 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2667 struct amdgpu_ras *ras = psp->ras_context.ras; 2668 2669 /* 2670 * Skip SMU FW reloading in case of using BACO for runpm only, 2671 * as SMU is always alive. 2672 */ 2673 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2674 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 2675 return 0; 2676 2677 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2678 return 0; 2679 2680 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 2681 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2682 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 2683 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2684 if (ret) 2685 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 2686 } 2687 2688 ret = psp_execute_ip_fw_load(psp, ucode); 2689 2690 if (ret) 2691 dev_err(adev->dev, "PSP load smu failed!\n"); 2692 2693 return ret; 2694 } 2695 2696 static bool fw_load_skip_check(struct psp_context *psp, 2697 struct amdgpu_firmware_info *ucode) 2698 { 2699 if (!ucode->fw || !ucode->ucode_size) 2700 return true; 2701 2702 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 2703 return true; 2704 2705 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2706 (psp_smu_reload_quirk(psp) || 2707 psp->autoload_supported || 2708 psp->pmfw_centralized_cstate_management)) 2709 return true; 2710 2711 if (amdgpu_sriov_vf(psp->adev) && 2712 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2713 return true; 2714 2715 if (psp->autoload_supported && 2716 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2717 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2718 /* skip mec JT when autoload is enabled */ 2719 return true; 2720 2721 return false; 2722 } 2723 2724 int psp_load_fw_list(struct psp_context *psp, 2725 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2726 { 2727 int ret = 0, i; 2728 struct amdgpu_firmware_info *ucode; 2729 2730 for (i = 0; i < ucode_count; ++i) { 2731 ucode = ucode_list[i]; 2732 psp_print_fw_hdr(psp, ucode); 2733 ret = psp_execute_ip_fw_load(psp, ucode); 2734 if (ret) 2735 return ret; 2736 } 2737 return ret; 2738 } 2739 2740 static int psp_load_non_psp_fw(struct psp_context *psp) 2741 { 2742 int i, ret; 2743 struct amdgpu_firmware_info *ucode; 2744 struct amdgpu_device *adev = psp->adev; 2745 2746 if (psp->autoload_supported && 2747 !psp->pmfw_centralized_cstate_management) { 2748 ret = psp_load_smu_fw(psp); 2749 if (ret) 2750 return ret; 2751 } 2752 2753 /* Load P2S table first if it's available */ 2754 psp_load_p2s_table(psp); 2755 2756 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2757 ucode = &adev->firmware.ucode[i]; 2758 2759 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2760 !fw_load_skip_check(psp, ucode)) { 2761 ret = psp_load_smu_fw(psp); 2762 if (ret) 2763 return ret; 2764 continue; 2765 } 2766 2767 if (fw_load_skip_check(psp, ucode)) 2768 continue; 2769 2770 if (psp->autoload_supported && 2771 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 2772 IP_VERSION(11, 0, 7) || 2773 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2774 IP_VERSION(11, 0, 11) || 2775 amdgpu_ip_version(adev, MP0_HWIP, 0) == 2776 IP_VERSION(11, 0, 12)) && 2777 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2778 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2779 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2780 /* PSP only receive one SDMA fw for sienna_cichlid, 2781 * as all four sdma fw are same 2782 */ 2783 continue; 2784 2785 psp_print_fw_hdr(psp, ucode); 2786 2787 ret = psp_execute_ip_fw_load(psp, ucode); 2788 if (ret) 2789 return ret; 2790 2791 /* Start rlc autoload after psp recieved all the gfx firmware */ 2792 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2793 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2794 ret = psp_rlc_autoload_start(psp); 2795 if (ret) { 2796 dev_err(adev->dev, "Failed to start rlc autoload\n"); 2797 return ret; 2798 } 2799 } 2800 } 2801 2802 return 0; 2803 } 2804 2805 static int psp_load_fw(struct amdgpu_device *adev) 2806 { 2807 int ret; 2808 struct psp_context *psp = &adev->psp; 2809 2810 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2811 /* should not destroy ring, only stop */ 2812 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2813 } else { 2814 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2815 2816 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2817 if (ret) { 2818 dev_err(adev->dev, "PSP ring init failed!\n"); 2819 goto failed; 2820 } 2821 } 2822 2823 ret = psp_hw_start(psp); 2824 if (ret) 2825 goto failed; 2826 2827 ret = psp_load_non_psp_fw(psp); 2828 if (ret) 2829 goto failed1; 2830 2831 ret = psp_asd_initialize(psp); 2832 if (ret) { 2833 dev_err(adev->dev, "PSP load asd failed!\n"); 2834 goto failed1; 2835 } 2836 2837 ret = psp_rl_load(adev); 2838 if (ret) { 2839 dev_err(adev->dev, "PSP load RL failed!\n"); 2840 goto failed1; 2841 } 2842 2843 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2844 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2845 ret = psp_xgmi_initialize(psp, false, true); 2846 /* Warning the XGMI seesion initialize failure 2847 * Instead of stop driver initialization 2848 */ 2849 if (ret) 2850 dev_err(psp->adev->dev, 2851 "XGMI: Failed to initialize XGMI session\n"); 2852 } 2853 } 2854 2855 if (psp->ta_fw) { 2856 ret = psp_ras_initialize(psp); 2857 if (ret) 2858 dev_err(psp->adev->dev, 2859 "RAS: Failed to initialize RAS\n"); 2860 2861 ret = psp_hdcp_initialize(psp); 2862 if (ret) 2863 dev_err(psp->adev->dev, 2864 "HDCP: Failed to initialize HDCP\n"); 2865 2866 ret = psp_dtm_initialize(psp); 2867 if (ret) 2868 dev_err(psp->adev->dev, 2869 "DTM: Failed to initialize DTM\n"); 2870 2871 ret = psp_rap_initialize(psp); 2872 if (ret) 2873 dev_err(psp->adev->dev, 2874 "RAP: Failed to initialize RAP\n"); 2875 2876 ret = psp_securedisplay_initialize(psp); 2877 if (ret) 2878 dev_err(psp->adev->dev, 2879 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2880 } 2881 2882 return 0; 2883 2884 failed1: 2885 psp_free_shared_bufs(psp); 2886 failed: 2887 /* 2888 * all cleanup jobs (xgmi terminate, ras terminate, 2889 * ring destroy, cmd/fence/fw buffers destory, 2890 * psp->cmd destory) are delayed to psp_hw_fini 2891 */ 2892 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2893 return ret; 2894 } 2895 2896 static int psp_hw_init(void *handle) 2897 { 2898 int ret; 2899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2900 2901 mutex_lock(&adev->firmware.mutex); 2902 /* 2903 * This sequence is just used on hw_init only once, no need on 2904 * resume. 2905 */ 2906 ret = amdgpu_ucode_init_bo(adev); 2907 if (ret) 2908 goto failed; 2909 2910 ret = psp_load_fw(adev); 2911 if (ret) { 2912 dev_err(adev->dev, "PSP firmware loading failed\n"); 2913 goto failed; 2914 } 2915 2916 mutex_unlock(&adev->firmware.mutex); 2917 return 0; 2918 2919 failed: 2920 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2921 mutex_unlock(&adev->firmware.mutex); 2922 return -EINVAL; 2923 } 2924 2925 static int psp_hw_fini(void *handle) 2926 { 2927 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2928 struct psp_context *psp = &adev->psp; 2929 2930 if (psp->ta_fw) { 2931 psp_ras_terminate(psp); 2932 psp_securedisplay_terminate(psp); 2933 psp_rap_terminate(psp); 2934 psp_dtm_terminate(psp); 2935 psp_hdcp_terminate(psp); 2936 2937 if (adev->gmc.xgmi.num_physical_nodes > 1) 2938 psp_xgmi_terminate(psp); 2939 } 2940 2941 psp_asd_terminate(psp); 2942 psp_tmr_terminate(psp); 2943 2944 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2945 2946 return 0; 2947 } 2948 2949 static int psp_suspend(void *handle) 2950 { 2951 int ret = 0; 2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2953 struct psp_context *psp = &adev->psp; 2954 2955 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2956 psp->xgmi_context.context.initialized) { 2957 ret = psp_xgmi_terminate(psp); 2958 if (ret) { 2959 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 2960 goto out; 2961 } 2962 } 2963 2964 if (psp->ta_fw) { 2965 ret = psp_ras_terminate(psp); 2966 if (ret) { 2967 dev_err(adev->dev, "Failed to terminate ras ta\n"); 2968 goto out; 2969 } 2970 ret = psp_hdcp_terminate(psp); 2971 if (ret) { 2972 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 2973 goto out; 2974 } 2975 ret = psp_dtm_terminate(psp); 2976 if (ret) { 2977 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 2978 goto out; 2979 } 2980 ret = psp_rap_terminate(psp); 2981 if (ret) { 2982 dev_err(adev->dev, "Failed to terminate rap ta\n"); 2983 goto out; 2984 } 2985 ret = psp_securedisplay_terminate(psp); 2986 if (ret) { 2987 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 2988 goto out; 2989 } 2990 } 2991 2992 ret = psp_asd_terminate(psp); 2993 if (ret) { 2994 dev_err(adev->dev, "Failed to terminate asd\n"); 2995 goto out; 2996 } 2997 2998 ret = psp_tmr_terminate(psp); 2999 if (ret) { 3000 dev_err(adev->dev, "Failed to terminate tmr\n"); 3001 goto out; 3002 } 3003 3004 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3005 if (ret) 3006 dev_err(adev->dev, "PSP ring stop failed\n"); 3007 3008 out: 3009 return ret; 3010 } 3011 3012 static int psp_resume(void *handle) 3013 { 3014 int ret; 3015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3016 struct psp_context *psp = &adev->psp; 3017 3018 dev_info(adev->dev, "PSP is resuming...\n"); 3019 3020 if (psp->mem_train_ctx.enable_mem_training) { 3021 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3022 if (ret) { 3023 dev_err(adev->dev, "Failed to process memory training!\n"); 3024 return ret; 3025 } 3026 } 3027 3028 mutex_lock(&adev->firmware.mutex); 3029 3030 ret = psp_hw_start(psp); 3031 if (ret) 3032 goto failed; 3033 3034 ret = psp_load_non_psp_fw(psp); 3035 if (ret) 3036 goto failed; 3037 3038 ret = psp_asd_initialize(psp); 3039 if (ret) { 3040 dev_err(adev->dev, "PSP load asd failed!\n"); 3041 goto failed; 3042 } 3043 3044 ret = psp_rl_load(adev); 3045 if (ret) { 3046 dev_err(adev->dev, "PSP load RL failed!\n"); 3047 goto failed; 3048 } 3049 3050 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3051 ret = psp_xgmi_initialize(psp, false, true); 3052 /* Warning the XGMI seesion initialize failure 3053 * Instead of stop driver initialization 3054 */ 3055 if (ret) 3056 dev_err(psp->adev->dev, 3057 "XGMI: Failed to initialize XGMI session\n"); 3058 } 3059 3060 if (psp->ta_fw) { 3061 ret = psp_ras_initialize(psp); 3062 if (ret) 3063 dev_err(psp->adev->dev, 3064 "RAS: Failed to initialize RAS\n"); 3065 3066 ret = psp_hdcp_initialize(psp); 3067 if (ret) 3068 dev_err(psp->adev->dev, 3069 "HDCP: Failed to initialize HDCP\n"); 3070 3071 ret = psp_dtm_initialize(psp); 3072 if (ret) 3073 dev_err(psp->adev->dev, 3074 "DTM: Failed to initialize DTM\n"); 3075 3076 ret = psp_rap_initialize(psp); 3077 if (ret) 3078 dev_err(psp->adev->dev, 3079 "RAP: Failed to initialize RAP\n"); 3080 3081 ret = psp_securedisplay_initialize(psp); 3082 if (ret) 3083 dev_err(psp->adev->dev, 3084 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3085 } 3086 3087 mutex_unlock(&adev->firmware.mutex); 3088 3089 return 0; 3090 3091 failed: 3092 dev_err(adev->dev, "PSP resume failed\n"); 3093 mutex_unlock(&adev->firmware.mutex); 3094 return ret; 3095 } 3096 3097 int psp_gpu_reset(struct amdgpu_device *adev) 3098 { 3099 int ret; 3100 3101 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3102 return 0; 3103 3104 mutex_lock(&adev->psp.mutex); 3105 ret = psp_mode1_reset(&adev->psp); 3106 mutex_unlock(&adev->psp.mutex); 3107 3108 return ret; 3109 } 3110 3111 int psp_rlc_autoload_start(struct psp_context *psp) 3112 { 3113 int ret; 3114 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3115 3116 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3117 3118 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3119 psp->fence_buf_mc_addr); 3120 3121 release_psp_cmd_buf(psp); 3122 3123 return ret; 3124 } 3125 3126 int psp_ring_cmd_submit(struct psp_context *psp, 3127 uint64_t cmd_buf_mc_addr, 3128 uint64_t fence_mc_addr, 3129 int index) 3130 { 3131 unsigned int psp_write_ptr_reg = 0; 3132 struct psp_gfx_rb_frame *write_frame; 3133 struct psp_ring *ring = &psp->km_ring; 3134 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3135 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3136 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3137 struct amdgpu_device *adev = psp->adev; 3138 uint32_t ring_size_dw = ring->ring_size / 4; 3139 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3140 3141 /* KM (GPCOM) prepare write pointer */ 3142 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3143 3144 /* Update KM RB frame pointer to new frame */ 3145 /* write_frame ptr increments by size of rb_frame in bytes */ 3146 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3147 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3148 write_frame = ring_buffer_start; 3149 else 3150 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3151 /* Check invalid write_frame ptr address */ 3152 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3153 dev_err(adev->dev, 3154 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3155 ring_buffer_start, ring_buffer_end, write_frame); 3156 dev_err(adev->dev, 3157 "write_frame is pointing to address out of bounds\n"); 3158 return -EINVAL; 3159 } 3160 3161 /* Initialize KM RB frame */ 3162 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3163 3164 /* Update KM RB frame */ 3165 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3166 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3167 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3168 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3169 write_frame->fence_value = index; 3170 amdgpu_device_flush_hdp(adev, NULL); 3171 3172 /* Update the write Pointer in DWORDs */ 3173 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3174 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3175 return 0; 3176 } 3177 3178 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3179 { 3180 struct amdgpu_device *adev = psp->adev; 3181 char fw_name[PSP_FW_NAME_LEN]; 3182 const struct psp_firmware_header_v1_0 *asd_hdr; 3183 int err = 0; 3184 3185 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 3186 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name); 3187 if (err) 3188 goto out; 3189 3190 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3191 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3192 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3193 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3194 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3195 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3196 return 0; 3197 out: 3198 amdgpu_ucode_release(&adev->psp.asd_fw); 3199 return err; 3200 } 3201 3202 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3203 { 3204 struct amdgpu_device *adev = psp->adev; 3205 char fw_name[PSP_FW_NAME_LEN]; 3206 const struct psp_firmware_header_v1_0 *toc_hdr; 3207 int err = 0; 3208 3209 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3210 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 3211 if (err) 3212 goto out; 3213 3214 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3215 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3216 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3217 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3218 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3219 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3220 return 0; 3221 out: 3222 amdgpu_ucode_release(&adev->psp.toc_fw); 3223 return err; 3224 } 3225 3226 static int parse_sos_bin_descriptor(struct psp_context *psp, 3227 const struct psp_fw_bin_desc *desc, 3228 const struct psp_firmware_header_v2_0 *sos_hdr) 3229 { 3230 uint8_t *ucode_start_addr = NULL; 3231 3232 if (!psp || !desc || !sos_hdr) 3233 return -EINVAL; 3234 3235 ucode_start_addr = (uint8_t *)sos_hdr + 3236 le32_to_cpu(desc->offset_bytes) + 3237 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3238 3239 switch (desc->fw_type) { 3240 case PSP_FW_TYPE_PSP_SOS: 3241 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3242 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3243 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3244 psp->sos.start_addr = ucode_start_addr; 3245 break; 3246 case PSP_FW_TYPE_PSP_SYS_DRV: 3247 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3248 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3249 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3250 psp->sys.start_addr = ucode_start_addr; 3251 break; 3252 case PSP_FW_TYPE_PSP_KDB: 3253 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3254 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3255 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3256 psp->kdb.start_addr = ucode_start_addr; 3257 break; 3258 case PSP_FW_TYPE_PSP_TOC: 3259 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3260 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3261 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3262 psp->toc.start_addr = ucode_start_addr; 3263 break; 3264 case PSP_FW_TYPE_PSP_SPL: 3265 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3266 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3267 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3268 psp->spl.start_addr = ucode_start_addr; 3269 break; 3270 case PSP_FW_TYPE_PSP_RL: 3271 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3272 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3273 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3274 psp->rl.start_addr = ucode_start_addr; 3275 break; 3276 case PSP_FW_TYPE_PSP_SOC_DRV: 3277 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3278 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3279 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3280 psp->soc_drv.start_addr = ucode_start_addr; 3281 break; 3282 case PSP_FW_TYPE_PSP_INTF_DRV: 3283 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3284 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3285 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3286 psp->intf_drv.start_addr = ucode_start_addr; 3287 break; 3288 case PSP_FW_TYPE_PSP_DBG_DRV: 3289 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3290 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3291 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3292 psp->dbg_drv.start_addr = ucode_start_addr; 3293 break; 3294 case PSP_FW_TYPE_PSP_RAS_DRV: 3295 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3296 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3297 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3298 psp->ras_drv.start_addr = ucode_start_addr; 3299 break; 3300 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 3301 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 3302 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 3303 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3304 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 3305 break; 3306 default: 3307 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3308 break; 3309 } 3310 3311 return 0; 3312 } 3313 3314 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3315 { 3316 const struct psp_firmware_header_v1_0 *sos_hdr; 3317 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3318 uint8_t *ucode_array_start_addr; 3319 3320 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3321 ucode_array_start_addr = (uint8_t *)sos_hdr + 3322 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3323 3324 if (adev->gmc.xgmi.connected_to_cpu || 3325 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 3326 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3327 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3328 3329 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3330 adev->psp.sys.start_addr = ucode_array_start_addr; 3331 3332 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3333 adev->psp.sos.start_addr = ucode_array_start_addr + 3334 le32_to_cpu(sos_hdr->sos.offset_bytes); 3335 } else { 3336 /* Load alternate PSP SOS FW */ 3337 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3338 3339 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3340 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3341 3342 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3343 adev->psp.sys.start_addr = ucode_array_start_addr + 3344 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3345 3346 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3347 adev->psp.sos.start_addr = ucode_array_start_addr + 3348 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3349 } 3350 3351 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3352 dev_warn(adev->dev, "PSP SOS FW not available"); 3353 return -EINVAL; 3354 } 3355 3356 return 0; 3357 } 3358 3359 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 3360 { 3361 struct amdgpu_device *adev = psp->adev; 3362 char fw_name[PSP_FW_NAME_LEN]; 3363 const struct psp_firmware_header_v1_0 *sos_hdr; 3364 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3365 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3366 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3367 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3368 int err = 0; 3369 uint8_t *ucode_array_start_addr; 3370 int fw_index = 0; 3371 3372 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3373 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name); 3374 if (err) 3375 goto out; 3376 3377 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3378 ucode_array_start_addr = (uint8_t *)sos_hdr + 3379 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3380 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3381 3382 switch (sos_hdr->header.header_version_major) { 3383 case 1: 3384 err = psp_init_sos_base_fw(adev); 3385 if (err) 3386 goto out; 3387 3388 if (sos_hdr->header.header_version_minor == 1) { 3389 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3390 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3391 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3392 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3393 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3394 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3395 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3396 } 3397 if (sos_hdr->header.header_version_minor == 2) { 3398 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3399 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3400 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3401 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3402 } 3403 if (sos_hdr->header.header_version_minor == 3) { 3404 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3405 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3406 adev->psp.toc.start_addr = ucode_array_start_addr + 3407 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3408 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3409 adev->psp.kdb.start_addr = ucode_array_start_addr + 3410 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3411 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3412 adev->psp.spl.start_addr = ucode_array_start_addr + 3413 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3414 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3415 adev->psp.rl.start_addr = ucode_array_start_addr + 3416 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3417 } 3418 break; 3419 case 2: 3420 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3421 3422 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3423 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3424 err = -EINVAL; 3425 goto out; 3426 } 3427 3428 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3429 err = parse_sos_bin_descriptor(psp, 3430 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3431 sos_hdr_v2_0); 3432 if (err) 3433 goto out; 3434 } 3435 break; 3436 default: 3437 dev_err(adev->dev, 3438 "unsupported psp sos firmware\n"); 3439 err = -EINVAL; 3440 goto out; 3441 } 3442 3443 return 0; 3444 out: 3445 amdgpu_ucode_release(&adev->psp.sos_fw); 3446 3447 return err; 3448 } 3449 3450 static int parse_ta_bin_descriptor(struct psp_context *psp, 3451 const struct psp_fw_bin_desc *desc, 3452 const struct ta_firmware_header_v2_0 *ta_hdr) 3453 { 3454 uint8_t *ucode_start_addr = NULL; 3455 3456 if (!psp || !desc || !ta_hdr) 3457 return -EINVAL; 3458 3459 ucode_start_addr = (uint8_t *)ta_hdr + 3460 le32_to_cpu(desc->offset_bytes) + 3461 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3462 3463 switch (desc->fw_type) { 3464 case TA_FW_TYPE_PSP_ASD: 3465 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3466 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3467 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3468 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3469 break; 3470 case TA_FW_TYPE_PSP_XGMI: 3471 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3472 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3473 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3474 break; 3475 case TA_FW_TYPE_PSP_RAS: 3476 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3477 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3478 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3479 break; 3480 case TA_FW_TYPE_PSP_HDCP: 3481 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3482 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3483 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3484 break; 3485 case TA_FW_TYPE_PSP_DTM: 3486 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3487 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3488 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3489 break; 3490 case TA_FW_TYPE_PSP_RAP: 3491 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3492 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3493 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3494 break; 3495 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3496 psp->securedisplay_context.context.bin_desc.fw_version = 3497 le32_to_cpu(desc->fw_version); 3498 psp->securedisplay_context.context.bin_desc.size_bytes = 3499 le32_to_cpu(desc->size_bytes); 3500 psp->securedisplay_context.context.bin_desc.start_addr = 3501 ucode_start_addr; 3502 break; 3503 default: 3504 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3505 break; 3506 } 3507 3508 return 0; 3509 } 3510 3511 static int parse_ta_v1_microcode(struct psp_context *psp) 3512 { 3513 const struct ta_firmware_header_v1_0 *ta_hdr; 3514 struct amdgpu_device *adev = psp->adev; 3515 3516 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 3517 3518 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 3519 return -EINVAL; 3520 3521 adev->psp.xgmi_context.context.bin_desc.fw_version = 3522 le32_to_cpu(ta_hdr->xgmi.fw_version); 3523 adev->psp.xgmi_context.context.bin_desc.size_bytes = 3524 le32_to_cpu(ta_hdr->xgmi.size_bytes); 3525 adev->psp.xgmi_context.context.bin_desc.start_addr = 3526 (uint8_t *)ta_hdr + 3527 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3528 3529 adev->psp.ras_context.context.bin_desc.fw_version = 3530 le32_to_cpu(ta_hdr->ras.fw_version); 3531 adev->psp.ras_context.context.bin_desc.size_bytes = 3532 le32_to_cpu(ta_hdr->ras.size_bytes); 3533 adev->psp.ras_context.context.bin_desc.start_addr = 3534 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 3535 le32_to_cpu(ta_hdr->ras.offset_bytes); 3536 3537 adev->psp.hdcp_context.context.bin_desc.fw_version = 3538 le32_to_cpu(ta_hdr->hdcp.fw_version); 3539 adev->psp.hdcp_context.context.bin_desc.size_bytes = 3540 le32_to_cpu(ta_hdr->hdcp.size_bytes); 3541 adev->psp.hdcp_context.context.bin_desc.start_addr = 3542 (uint8_t *)ta_hdr + 3543 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3544 3545 adev->psp.dtm_context.context.bin_desc.fw_version = 3546 le32_to_cpu(ta_hdr->dtm.fw_version); 3547 adev->psp.dtm_context.context.bin_desc.size_bytes = 3548 le32_to_cpu(ta_hdr->dtm.size_bytes); 3549 adev->psp.dtm_context.context.bin_desc.start_addr = 3550 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3551 le32_to_cpu(ta_hdr->dtm.offset_bytes); 3552 3553 adev->psp.securedisplay_context.context.bin_desc.fw_version = 3554 le32_to_cpu(ta_hdr->securedisplay.fw_version); 3555 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 3556 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 3557 adev->psp.securedisplay_context.context.bin_desc.start_addr = 3558 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 3559 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 3560 3561 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 3562 3563 return 0; 3564 } 3565 3566 static int parse_ta_v2_microcode(struct psp_context *psp) 3567 { 3568 const struct ta_firmware_header_v2_0 *ta_hdr; 3569 struct amdgpu_device *adev = psp->adev; 3570 int err = 0; 3571 int ta_index = 0; 3572 3573 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3574 3575 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 3576 return -EINVAL; 3577 3578 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3579 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3580 return -EINVAL; 3581 } 3582 3583 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3584 err = parse_ta_bin_descriptor(psp, 3585 &ta_hdr->ta_fw_bin[ta_index], 3586 ta_hdr); 3587 if (err) 3588 return err; 3589 } 3590 3591 return 0; 3592 } 3593 3594 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 3595 { 3596 const struct common_firmware_header *hdr; 3597 struct amdgpu_device *adev = psp->adev; 3598 char fw_name[PSP_FW_NAME_LEN]; 3599 int err; 3600 3601 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3602 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name); 3603 if (err) 3604 return err; 3605 3606 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 3607 switch (le16_to_cpu(hdr->header_version_major)) { 3608 case 1: 3609 err = parse_ta_v1_microcode(psp); 3610 break; 3611 case 2: 3612 err = parse_ta_v2_microcode(psp); 3613 break; 3614 default: 3615 dev_err(adev->dev, "unsupported TA header version\n"); 3616 err = -EINVAL; 3617 } 3618 3619 if (err) 3620 amdgpu_ucode_release(&adev->psp.ta_fw); 3621 3622 return err; 3623 } 3624 3625 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 3626 { 3627 struct amdgpu_device *adev = psp->adev; 3628 char fw_name[PSP_FW_NAME_LEN]; 3629 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3630 struct amdgpu_firmware_info *info = NULL; 3631 int err = 0; 3632 3633 if (!amdgpu_sriov_vf(adev)) { 3634 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3635 return -EINVAL; 3636 } 3637 3638 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3639 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name); 3640 if (err) { 3641 if (err == -ENODEV) { 3642 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3643 err = 0; 3644 goto out; 3645 } 3646 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3647 } 3648 3649 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3650 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3651 info->fw = adev->psp.cap_fw; 3652 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3653 adev->psp.cap_fw->data; 3654 adev->firmware.fw_size += ALIGN( 3655 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3656 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3657 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3658 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3659 3660 return 0; 3661 3662 out: 3663 amdgpu_ucode_release(&adev->psp.cap_fw); 3664 return err; 3665 } 3666 3667 static int psp_set_clockgating_state(void *handle, 3668 enum amd_clockgating_state state) 3669 { 3670 return 0; 3671 } 3672 3673 static int psp_set_powergating_state(void *handle, 3674 enum amd_powergating_state state) 3675 { 3676 return 0; 3677 } 3678 3679 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3680 struct device_attribute *attr, 3681 char *buf) 3682 { 3683 struct drm_device *ddev = dev_get_drvdata(dev); 3684 struct amdgpu_device *adev = drm_to_adev(ddev); 3685 uint32_t fw_ver; 3686 int ret; 3687 3688 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3689 dev_info(adev->dev, "PSP block is not ready yet\n."); 3690 return -EBUSY; 3691 } 3692 3693 mutex_lock(&adev->psp.mutex); 3694 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3695 mutex_unlock(&adev->psp.mutex); 3696 3697 if (ret) { 3698 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 3699 return ret; 3700 } 3701 3702 return sysfs_emit(buf, "%x\n", fw_ver); 3703 } 3704 3705 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3706 struct device_attribute *attr, 3707 const char *buf, 3708 size_t count) 3709 { 3710 struct drm_device *ddev = dev_get_drvdata(dev); 3711 struct amdgpu_device *adev = drm_to_adev(ddev); 3712 int ret, idx; 3713 char fw_name[100]; 3714 const struct firmware *usbc_pd_fw; 3715 struct amdgpu_bo *fw_buf_bo = NULL; 3716 uint64_t fw_pri_mc_addr; 3717 void *fw_pri_cpu_addr; 3718 3719 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3720 dev_err(adev->dev, "PSP block is not ready yet."); 3721 return -EBUSY; 3722 } 3723 3724 if (!drm_dev_enter(ddev, &idx)) 3725 return -ENODEV; 3726 3727 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3728 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3729 if (ret) 3730 goto fail; 3731 3732 /* LFB address which is aligned to 1MB boundary per PSP request */ 3733 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3734 AMDGPU_GEM_DOMAIN_VRAM | 3735 AMDGPU_GEM_DOMAIN_GTT, 3736 &fw_buf_bo, &fw_pri_mc_addr, 3737 &fw_pri_cpu_addr); 3738 if (ret) 3739 goto rel_buf; 3740 3741 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3742 3743 mutex_lock(&adev->psp.mutex); 3744 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3745 mutex_unlock(&adev->psp.mutex); 3746 3747 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3748 3749 rel_buf: 3750 release_firmware(usbc_pd_fw); 3751 fail: 3752 if (ret) { 3753 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 3754 count = ret; 3755 } 3756 3757 drm_dev_exit(idx); 3758 return count; 3759 } 3760 3761 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3762 { 3763 int idx; 3764 3765 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3766 return; 3767 3768 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3769 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3770 3771 drm_dev_exit(idx); 3772 } 3773 3774 /** 3775 * DOC: usbc_pd_fw 3776 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 3777 * this file will trigger the update process. 3778 */ 3779 static DEVICE_ATTR(usbc_pd_fw, 0644, 3780 psp_usbc_pd_fw_sysfs_read, 3781 psp_usbc_pd_fw_sysfs_write); 3782 3783 int is_psp_fw_valid(struct psp_bin_desc bin) 3784 { 3785 return bin.size_bytes; 3786 } 3787 3788 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3789 struct bin_attribute *bin_attr, 3790 char *buffer, loff_t pos, size_t count) 3791 { 3792 struct device *dev = kobj_to_dev(kobj); 3793 struct drm_device *ddev = dev_get_drvdata(dev); 3794 struct amdgpu_device *adev = drm_to_adev(ddev); 3795 3796 adev->psp.vbflash_done = false; 3797 3798 /* Safeguard against memory drain */ 3799 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3800 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 3801 kvfree(adev->psp.vbflash_tmp_buf); 3802 adev->psp.vbflash_tmp_buf = NULL; 3803 adev->psp.vbflash_image_size = 0; 3804 return -ENOMEM; 3805 } 3806 3807 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3808 if (!adev->psp.vbflash_tmp_buf) { 3809 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3810 if (!adev->psp.vbflash_tmp_buf) 3811 return -ENOMEM; 3812 } 3813 3814 mutex_lock(&adev->psp.mutex); 3815 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3816 adev->psp.vbflash_image_size += count; 3817 mutex_unlock(&adev->psp.mutex); 3818 3819 dev_dbg(adev->dev, "IFWI staged for update\n"); 3820 3821 return count; 3822 } 3823 3824 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3825 struct bin_attribute *bin_attr, char *buffer, 3826 loff_t pos, size_t count) 3827 { 3828 struct device *dev = kobj_to_dev(kobj); 3829 struct drm_device *ddev = dev_get_drvdata(dev); 3830 struct amdgpu_device *adev = drm_to_adev(ddev); 3831 struct amdgpu_bo *fw_buf_bo = NULL; 3832 uint64_t fw_pri_mc_addr; 3833 void *fw_pri_cpu_addr; 3834 int ret; 3835 3836 if (adev->psp.vbflash_image_size == 0) 3837 return -EINVAL; 3838 3839 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 3840 3841 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3842 AMDGPU_GPU_PAGE_SIZE, 3843 AMDGPU_GEM_DOMAIN_VRAM, 3844 &fw_buf_bo, 3845 &fw_pri_mc_addr, 3846 &fw_pri_cpu_addr); 3847 if (ret) 3848 goto rel_buf; 3849 3850 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3851 3852 mutex_lock(&adev->psp.mutex); 3853 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3854 mutex_unlock(&adev->psp.mutex); 3855 3856 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3857 3858 rel_buf: 3859 kvfree(adev->psp.vbflash_tmp_buf); 3860 adev->psp.vbflash_tmp_buf = NULL; 3861 adev->psp.vbflash_image_size = 0; 3862 3863 if (ret) { 3864 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 3865 return ret; 3866 } 3867 3868 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 3869 return 0; 3870 } 3871 3872 /** 3873 * DOC: psp_vbflash 3874 * Writing to this file will stage an IFWI for update. Reading from this file 3875 * will trigger the update process. 3876 */ 3877 static struct bin_attribute psp_vbflash_bin_attr = { 3878 .attr = {.name = "psp_vbflash", .mode = 0660}, 3879 .size = 0, 3880 .write = amdgpu_psp_vbflash_write, 3881 .read = amdgpu_psp_vbflash_read, 3882 }; 3883 3884 /** 3885 * DOC: psp_vbflash_status 3886 * The status of the flash process. 3887 * 0: IFWI flash not complete. 3888 * 1: IFWI flash complete. 3889 */ 3890 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3891 struct device_attribute *attr, 3892 char *buf) 3893 { 3894 struct drm_device *ddev = dev_get_drvdata(dev); 3895 struct amdgpu_device *adev = drm_to_adev(ddev); 3896 uint32_t vbflash_status; 3897 3898 vbflash_status = psp_vbflash_status(&adev->psp); 3899 if (!adev->psp.vbflash_done) 3900 vbflash_status = 0; 3901 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3902 vbflash_status = 1; 3903 3904 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3905 } 3906 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3907 3908 static struct bin_attribute *bin_flash_attrs[] = { 3909 &psp_vbflash_bin_attr, 3910 NULL 3911 }; 3912 3913 static struct attribute *flash_attrs[] = { 3914 &dev_attr_psp_vbflash_status.attr, 3915 &dev_attr_usbc_pd_fw.attr, 3916 NULL 3917 }; 3918 3919 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 3920 { 3921 struct device *dev = kobj_to_dev(kobj); 3922 struct drm_device *ddev = dev_get_drvdata(dev); 3923 struct amdgpu_device *adev = drm_to_adev(ddev); 3924 3925 if (attr == &dev_attr_usbc_pd_fw.attr) 3926 return adev->psp.sup_pd_fw_up ? 0660 : 0; 3927 3928 return adev->psp.sup_ifwi_up ? 0440 : 0; 3929 } 3930 3931 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 3932 struct bin_attribute *attr, 3933 int idx) 3934 { 3935 struct device *dev = kobj_to_dev(kobj); 3936 struct drm_device *ddev = dev_get_drvdata(dev); 3937 struct amdgpu_device *adev = drm_to_adev(ddev); 3938 3939 return adev->psp.sup_ifwi_up ? 0660 : 0; 3940 } 3941 3942 const struct attribute_group amdgpu_flash_attr_group = { 3943 .attrs = flash_attrs, 3944 .bin_attrs = bin_flash_attrs, 3945 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 3946 .is_visible = amdgpu_flash_attr_is_visible, 3947 }; 3948 3949 const struct amd_ip_funcs psp_ip_funcs = { 3950 .name = "psp", 3951 .early_init = psp_early_init, 3952 .late_init = NULL, 3953 .sw_init = psp_sw_init, 3954 .sw_fini = psp_sw_fini, 3955 .hw_init = psp_hw_init, 3956 .hw_fini = psp_hw_fini, 3957 .suspend = psp_suspend, 3958 .resume = psp_resume, 3959 .is_idle = NULL, 3960 .check_soft_reset = NULL, 3961 .wait_for_idle = NULL, 3962 .soft_reset = NULL, 3963 .set_clockgating_state = psp_set_clockgating_state, 3964 .set_powergating_state = psp_set_powergating_state, 3965 }; 3966 3967 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 3968 .type = AMD_IP_BLOCK_TYPE_PSP, 3969 .major = 3, 3970 .minor = 1, 3971 .rev = 0, 3972 .funcs = &psp_ip_funcs, 3973 }; 3974 3975 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 3976 .type = AMD_IP_BLOCK_TYPE_PSP, 3977 .major = 10, 3978 .minor = 0, 3979 .rev = 0, 3980 .funcs = &psp_ip_funcs, 3981 }; 3982 3983 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 3984 .type = AMD_IP_BLOCK_TYPE_PSP, 3985 .major = 11, 3986 .minor = 0, 3987 .rev = 0, 3988 .funcs = &psp_ip_funcs, 3989 }; 3990 3991 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3992 .type = AMD_IP_BLOCK_TYPE_PSP, 3993 .major = 11, 3994 .minor = 0, 3995 .rev = 8, 3996 .funcs = &psp_ip_funcs, 3997 }; 3998 3999 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4000 .type = AMD_IP_BLOCK_TYPE_PSP, 4001 .major = 12, 4002 .minor = 0, 4003 .rev = 0, 4004 .funcs = &psp_ip_funcs, 4005 }; 4006 4007 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4008 .type = AMD_IP_BLOCK_TYPE_PSP, 4009 .major = 13, 4010 .minor = 0, 4011 .rev = 0, 4012 .funcs = &psp_ip_funcs, 4013 }; 4014 4015 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 4016 .type = AMD_IP_BLOCK_TYPE_PSP, 4017 .major = 13, 4018 .minor = 0, 4019 .rev = 4, 4020 .funcs = &psp_ip_funcs, 4021 }; 4022 4023 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 4024 .type = AMD_IP_BLOCK_TYPE_PSP, 4025 .major = 14, 4026 .minor = 0, 4027 .rev = 0, 4028 .funcs = &psp_ip_funcs, 4029 }; 4030