1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 #include "psp_v14_0.h" 42 #include "psp_v15_0.h" 43 #include "psp_v15_0_8.h" 44 45 #include "amdgpu_ras.h" 46 #include "amdgpu_securedisplay.h" 47 #include "amdgpu_atomfirmware.h" 48 49 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 static const char * const amdgpu_ptl_fmt_str[] = { 56 [AMDGPU_PTL_FMT_I8] = "I8", 57 [AMDGPU_PTL_FMT_F16] = "F16", 58 [AMDGPU_PTL_FMT_BF16] = "BF16", 59 [AMDGPU_PTL_FMT_F32] = "F32", 60 [AMDGPU_PTL_FMT_F64] = "F64", 61 [AMDGPU_PTL_FMT_F8] = "F8", 62 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 63 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 64 }; 65 66 static int psp_ring_init(struct psp_context *psp, 67 enum psp_ring_type ring_type) 68 { 69 int ret = 0; 70 struct psp_ring *ring; 71 struct amdgpu_device *adev = psp->adev; 72 73 ring = &psp->km_ring; 74 75 ring->ring_type = ring_type; 76 77 /* allocate 4k Page of Local Frame Buffer memory for ring */ 78 ring->ring_size = 0x1000; 79 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 80 AMDGPU_GEM_DOMAIN_VRAM | 81 AMDGPU_GEM_DOMAIN_GTT, 82 &adev->firmware.rbuf, 83 &ring->ring_mem_mc_addr, 84 (void **)&ring->ring_mem); 85 if (ret) { 86 ring->ring_size = 0; 87 return ret; 88 } 89 90 return 0; 91 } 92 93 /* 94 * Due to DF Cstate management centralized to PMFW, the firmware 95 * loading sequence will be updated as below: 96 * - Load KDB 97 * - Load SYS_DRV 98 * - Load tOS 99 * - Load PMFW 100 * - Setup TMR 101 * - Load other non-psp fw 102 * - Load ASD 103 * - Load XGMI/RAS/HDCP/DTM TA if any 104 * 105 * This new sequence is required for 106 * - Arcturus and onwards 107 */ 108 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 109 { 110 struct amdgpu_device *adev = psp->adev; 111 112 if (amdgpu_sriov_vf(adev)) { 113 psp->pmfw_centralized_cstate_management = false; 114 return; 115 } 116 117 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 118 case IP_VERSION(11, 0, 0): 119 case IP_VERSION(11, 0, 4): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 7): 122 case IP_VERSION(11, 0, 9): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 case IP_VERSION(13, 0, 0): 127 case IP_VERSION(13, 0, 2): 128 case IP_VERSION(13, 0, 7): 129 psp->pmfw_centralized_cstate_management = true; 130 break; 131 default: 132 psp->pmfw_centralized_cstate_management = false; 133 break; 134 } 135 } 136 137 static int psp_init_sriov_microcode(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 char ucode_prefix[30]; 141 int ret = 0; 142 143 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 144 145 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 146 case IP_VERSION(9, 0, 0): 147 case IP_VERSION(11, 0, 7): 148 case IP_VERSION(11, 0, 9): 149 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 150 ret = psp_init_cap_microcode(psp, ucode_prefix); 151 break; 152 case IP_VERSION(13, 0, 2): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 ret &= psp_init_ta_microcode(psp, ucode_prefix); 156 break; 157 case IP_VERSION(13, 0, 0): 158 adev->virt.autoload_ucode_id = 0; 159 break; 160 case IP_VERSION(13, 0, 6): 161 case IP_VERSION(13, 0, 14): 162 case IP_VERSION(13, 0, 15): 163 ret = psp_init_cap_microcode(psp, ucode_prefix); 164 ret &= psp_init_ta_microcode(psp, ucode_prefix); 165 break; 166 case IP_VERSION(13, 0, 10): 167 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 168 ret = psp_init_cap_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 12): 171 ret = psp_init_ta_microcode(psp, ucode_prefix); 172 break; 173 default: 174 return -EINVAL; 175 } 176 return ret; 177 } 178 179 static int psp_early_init(struct amdgpu_ip_block *ip_block) 180 { 181 struct amdgpu_device *adev = ip_block->adev; 182 struct psp_context *psp = &adev->psp; 183 184 psp->autoload_supported = true; 185 psp->boot_time_tmr = true; 186 187 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 188 case IP_VERSION(9, 0, 0): 189 psp_v3_1_set_psp_funcs(psp); 190 psp->autoload_supported = false; 191 psp->boot_time_tmr = false; 192 break; 193 case IP_VERSION(10, 0, 0): 194 case IP_VERSION(10, 0, 1): 195 psp_v10_0_set_psp_funcs(psp); 196 psp->autoload_supported = false; 197 psp->boot_time_tmr = false; 198 break; 199 case IP_VERSION(11, 0, 2): 200 case IP_VERSION(11, 0, 4): 201 psp_v11_0_set_psp_funcs(psp); 202 psp->autoload_supported = false; 203 psp->boot_time_tmr = false; 204 break; 205 case IP_VERSION(11, 0, 0): 206 case IP_VERSION(11, 0, 7): 207 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 208 fallthrough; 209 case IP_VERSION(11, 0, 5): 210 case IP_VERSION(11, 0, 9): 211 case IP_VERSION(11, 0, 11): 212 case IP_VERSION(11, 5, 0): 213 case IP_VERSION(11, 5, 2): 214 case IP_VERSION(11, 0, 12): 215 case IP_VERSION(11, 0, 13): 216 psp_v11_0_set_psp_funcs(psp); 217 psp->boot_time_tmr = false; 218 break; 219 case IP_VERSION(11, 0, 3): 220 case IP_VERSION(12, 0, 1): 221 psp_v12_0_set_psp_funcs(psp); 222 psp->autoload_supported = false; 223 psp->boot_time_tmr = false; 224 break; 225 case IP_VERSION(13, 0, 2): 226 psp->boot_time_tmr = false; 227 fallthrough; 228 case IP_VERSION(13, 0, 6): 229 case IP_VERSION(13, 0, 14): 230 psp_v13_0_set_psp_funcs(psp); 231 psp->autoload_supported = false; 232 break; 233 case IP_VERSION(13, 0, 12): 234 case IP_VERSION(13, 0, 15): 235 psp_v13_0_set_psp_funcs(psp); 236 psp->autoload_supported = false; 237 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 238 break; 239 case IP_VERSION(13, 0, 1): 240 case IP_VERSION(13, 0, 3): 241 case IP_VERSION(13, 0, 5): 242 case IP_VERSION(13, 0, 8): 243 case IP_VERSION(13, 0, 11): 244 case IP_VERSION(14, 0, 0): 245 case IP_VERSION(14, 0, 1): 246 case IP_VERSION(14, 0, 4): 247 psp_v13_0_set_psp_funcs(psp); 248 psp->boot_time_tmr = false; 249 break; 250 case IP_VERSION(11, 0, 8): 251 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 252 psp_v11_0_8_set_psp_funcs(psp); 253 } 254 psp->autoload_supported = false; 255 psp->boot_time_tmr = false; 256 break; 257 case IP_VERSION(13, 0, 0): 258 case IP_VERSION(13, 0, 7): 259 case IP_VERSION(13, 0, 10): 260 psp_v13_0_set_psp_funcs(psp); 261 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 262 psp->boot_time_tmr = false; 263 break; 264 case IP_VERSION(13, 0, 4): 265 psp_v13_0_4_set_psp_funcs(psp); 266 psp->boot_time_tmr = false; 267 break; 268 case IP_VERSION(14, 0, 2): 269 case IP_VERSION(14, 0, 3): 270 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 271 psp_v14_0_set_psp_funcs(psp); 272 break; 273 case IP_VERSION(14, 0, 5): 274 psp_v14_0_set_psp_funcs(psp); 275 psp->boot_time_tmr = false; 276 break; 277 case IP_VERSION(15, 0, 0): 278 case IP_VERSION(15, 0, 5): 279 case IP_VERSION(15, 0, 9): 280 psp_v15_0_0_set_psp_funcs(psp); 281 psp->boot_time_tmr = false; 282 break; 283 case IP_VERSION(15, 0, 8): 284 psp_v15_0_8_set_psp_funcs(psp); 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 psp->adev = adev; 291 292 adev->psp_timeout = 20000; 293 294 psp_check_pmfw_centralized_cstate_management(psp); 295 296 if (amdgpu_sriov_vf(adev)) 297 return psp_init_sriov_microcode(psp); 298 else 299 return psp_init_microcode(psp); 300 } 301 302 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 303 { 304 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 305 &mem_ctx->shared_buf); 306 mem_ctx->shared_bo = NULL; 307 } 308 309 static void psp_free_shared_bufs(struct psp_context *psp) 310 { 311 void *tmr_buf; 312 void **pptr; 313 314 /* free TMR memory buffer */ 315 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 316 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 317 psp->tmr_bo = NULL; 318 319 /* free xgmi shared memory */ 320 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 321 322 /* free ras shared memory */ 323 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 324 325 /* free hdcp shared memory */ 326 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 327 328 /* free dtm shared memory */ 329 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 330 331 /* free rap shared memory */ 332 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 333 334 /* free securedisplay shared memory */ 335 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 336 337 338 } 339 340 static void psp_memory_training_fini(struct psp_context *psp) 341 { 342 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 343 344 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 345 kfree(ctx->sys_cache); 346 ctx->sys_cache = NULL; 347 } 348 349 static int psp_memory_training_init(struct psp_context *psp) 350 { 351 int ret; 352 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 353 354 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 355 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 356 return 0; 357 } 358 359 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 360 if (ctx->sys_cache == NULL) { 361 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 362 ret = -ENOMEM; 363 goto Err_out; 364 } 365 366 dev_dbg(psp->adev->dev, 367 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 368 ctx->train_data_size, 369 ctx->p2c_train_data_offset, 370 ctx->c2p_train_data_offset); 371 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 372 return 0; 373 374 Err_out: 375 psp_memory_training_fini(psp); 376 return ret; 377 } 378 379 /* 380 * Helper funciton to query psp runtime database entry 381 * 382 * @adev: amdgpu_device pointer 383 * @entry_type: the type of psp runtime database entry 384 * @db_entry: runtime database entry pointer 385 * 386 * Return false if runtime database doesn't exit or entry is invalid 387 * or true if the specific database entry is found, and copy to @db_entry 388 */ 389 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 390 enum psp_runtime_entry_type entry_type, 391 void *db_entry) 392 { 393 uint64_t db_header_pos, db_dir_pos; 394 struct psp_runtime_data_header db_header = {0}; 395 struct psp_runtime_data_directory db_dir = {0}; 396 bool ret = false; 397 int i; 398 399 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 400 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 401 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 402 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 403 return false; 404 405 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 406 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 407 408 /* read runtime db header from vram */ 409 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 410 sizeof(struct psp_runtime_data_header), false); 411 412 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 413 /* runtime db doesn't exist, exit */ 414 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 415 return false; 416 } 417 418 /* read runtime database entry from vram */ 419 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 420 sizeof(struct psp_runtime_data_directory), false); 421 422 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 423 /* invalid db entry count, exit */ 424 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 425 return false; 426 } 427 428 /* look up for requested entry type */ 429 for (i = 0; i < db_dir.entry_count && !ret; i++) { 430 if (db_dir.entry_list[i].entry_type == entry_type) { 431 switch (entry_type) { 432 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 433 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 434 /* invalid db entry size */ 435 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 436 return false; 437 } 438 /* read runtime database entry */ 439 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 440 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 441 ret = true; 442 break; 443 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 444 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 445 /* invalid db entry size */ 446 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 447 return false; 448 } 449 /* read runtime database entry */ 450 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 451 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 452 ret = true; 453 break; 454 default: 455 ret = false; 456 break; 457 } 458 } 459 } 460 461 return ret; 462 } 463 464 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 465 { 466 struct amdgpu_device *adev = ip_block->adev; 467 struct psp_context *psp = &adev->psp; 468 int ret; 469 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 470 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 471 struct psp_runtime_scpm_entry scpm_entry; 472 473 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 474 if (!psp->cmd) { 475 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 476 return -ENOMEM; 477 } 478 479 adev->psp.xgmi_context.supports_extended_data = 480 !adev->gmc.xgmi.connected_to_cpu && 481 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 482 483 memset(&scpm_entry, 0, sizeof(scpm_entry)); 484 if ((psp_get_runtime_db_entry(adev, 485 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 486 &scpm_entry)) && 487 (scpm_entry.scpm_status != SCPM_DISABLE)) { 488 adev->scpm_enabled = true; 489 adev->scpm_status = scpm_entry.scpm_status; 490 } else { 491 adev->scpm_enabled = false; 492 adev->scpm_status = SCPM_DISABLE; 493 } 494 495 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 496 497 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 498 if (psp_get_runtime_db_entry(adev, 499 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 500 &boot_cfg_entry)) { 501 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 502 if ((psp->boot_cfg_bitmask) & 503 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 504 /* If psp runtime database exists, then 505 * only enable two stage memory training 506 * when TWO_STAGE_DRAM_TRAINING bit is set 507 * in runtime database 508 */ 509 mem_training_ctx->enable_mem_training = true; 510 } 511 512 } else { 513 /* If psp runtime database doesn't exist or is 514 * invalid, force enable two stage memory training 515 */ 516 mem_training_ctx->enable_mem_training = true; 517 } 518 519 if (mem_training_ctx->enable_mem_training) { 520 ret = psp_memory_training_init(psp); 521 if (ret) { 522 dev_err(adev->dev, "Failed to initialize memory training!\n"); 523 return ret; 524 } 525 526 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 527 if (ret) { 528 dev_err(adev->dev, "Failed to process memory training!\n"); 529 return ret; 530 } 531 } 532 533 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 534 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 535 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 536 &psp->fw_pri_bo, 537 &psp->fw_pri_mc_addr, 538 &psp->fw_pri_buf); 539 if (ret) 540 return ret; 541 542 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 543 AMDGPU_GEM_DOMAIN_VRAM | 544 AMDGPU_GEM_DOMAIN_GTT, 545 &psp->fence_buf_bo, 546 &psp->fence_buf_mc_addr, 547 &psp->fence_buf); 548 if (ret) 549 goto failed1; 550 551 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 552 AMDGPU_GEM_DOMAIN_VRAM | 553 AMDGPU_GEM_DOMAIN_GTT, 554 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 555 (void **)&psp->cmd_buf_mem); 556 if (ret) 557 goto failed2; 558 559 return 0; 560 561 failed2: 562 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 563 &psp->fence_buf_mc_addr, &psp->fence_buf); 564 failed1: 565 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 566 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 567 return ret; 568 } 569 570 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 571 { 572 struct amdgpu_device *adev = ip_block->adev; 573 struct psp_context *psp = &adev->psp; 574 575 psp_memory_training_fini(psp); 576 577 amdgpu_ucode_release(&psp->sos_fw); 578 amdgpu_ucode_release(&psp->asd_fw); 579 amdgpu_ucode_release(&psp->ta_fw); 580 amdgpu_ucode_release(&psp->cap_fw); 581 amdgpu_ucode_release(&psp->toc_fw); 582 583 kfree(psp->cmd); 584 psp->cmd = NULL; 585 586 psp_free_shared_bufs(psp); 587 588 if (psp->km_ring.ring_mem) 589 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 590 &psp->km_ring.ring_mem_mc_addr, 591 (void **)&psp->km_ring.ring_mem); 592 593 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 594 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 595 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 596 &psp->fence_buf_mc_addr, &psp->fence_buf); 597 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 598 (void **)&psp->cmd_buf_mem); 599 600 return 0; 601 } 602 603 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 604 uint32_t mask, uint32_t flags) 605 { 606 bool check_changed = flags & PSP_WAITREG_CHANGED; 607 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 608 uint32_t val; 609 int i; 610 struct amdgpu_device *adev = psp->adev; 611 612 if (psp->adev->no_hw_access) 613 return 0; 614 615 for (i = 0; i < adev->usec_timeout; i++) { 616 val = RREG32(reg_index); 617 if (check_changed) { 618 if (val != reg_val) 619 return 0; 620 } else { 621 if ((val & mask) == reg_val) 622 return 0; 623 } 624 udelay(1); 625 } 626 627 if (verbose) 628 dev_err(adev->dev, 629 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 630 reg_index, mask, val, reg_val); 631 632 return -ETIME; 633 } 634 635 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 636 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 637 { 638 uint32_t val; 639 int i; 640 struct amdgpu_device *adev = psp->adev; 641 642 if (psp->adev->no_hw_access) 643 return 0; 644 645 for (i = 0; i < msec_timeout; i++) { 646 val = RREG32(reg_index); 647 if ((val & mask) == reg_val) 648 return 0; 649 msleep(1); 650 } 651 652 return -ETIME; 653 } 654 655 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 656 { 657 switch (cmd_id) { 658 case GFX_CMD_ID_LOAD_TA: 659 return "LOAD_TA"; 660 case GFX_CMD_ID_UNLOAD_TA: 661 return "UNLOAD_TA"; 662 case GFX_CMD_ID_INVOKE_CMD: 663 return "INVOKE_CMD"; 664 case GFX_CMD_ID_LOAD_ASD: 665 return "LOAD_ASD"; 666 case GFX_CMD_ID_SETUP_TMR: 667 return "SETUP_TMR"; 668 case GFX_CMD_ID_LOAD_IP_FW: 669 return "LOAD_IP_FW"; 670 case GFX_CMD_ID_DESTROY_TMR: 671 return "DESTROY_TMR"; 672 case GFX_CMD_ID_SAVE_RESTORE: 673 return "SAVE_RESTORE_IP_FW"; 674 case GFX_CMD_ID_SETUP_VMR: 675 return "SETUP_VMR"; 676 case GFX_CMD_ID_DESTROY_VMR: 677 return "DESTROY_VMR"; 678 case GFX_CMD_ID_PROG_REG: 679 return "PROG_REG"; 680 case GFX_CMD_ID_GET_FW_ATTESTATION: 681 return "GET_FW_ATTESTATION"; 682 case GFX_CMD_ID_LOAD_TOC: 683 return "ID_LOAD_TOC"; 684 case GFX_CMD_ID_AUTOLOAD_RLC: 685 return "AUTOLOAD_RLC"; 686 case GFX_CMD_ID_BOOT_CFG: 687 return "BOOT_CFG"; 688 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 689 return "CONFIG_SQ_PERFMON"; 690 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 691 return "FB_FW_RESERV_ADDR"; 692 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 693 return "FB_FW_RESERV_EXT_ADDR"; 694 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 695 return "SPATIAL_PARTITION"; 696 case GFX_CMD_ID_FB_NPS_MODE: 697 return "NPS_MODE_CHANGE"; 698 case GFX_CMD_ID_PERF_HW: 699 return "PERF MONITORING HW"; 700 default: 701 return "UNKNOWN CMD"; 702 } 703 } 704 705 static bool psp_err_warn(struct psp_context *psp) 706 { 707 struct psp_gfx_cmd_resp *cmd = psp->cmd_buf_mem; 708 709 /* This response indicates reg list is already loaded */ 710 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 711 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 712 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 713 cmd->resp.status == TEE_ERROR_CANCEL) 714 return false; 715 716 return true; 717 } 718 719 static int 720 psp_cmd_submit_buf(struct psp_context *psp, 721 struct amdgpu_firmware_info *ucode, 722 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 723 { 724 int ret; 725 int index; 726 int timeout = psp->adev->psp_timeout; 727 bool ras_intr = false; 728 bool skip_unsupport = false; 729 730 if (psp->adev->no_hw_access) 731 return 0; 732 733 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 734 735 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 736 737 index = atomic_inc_return(&psp->fence_value); 738 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 739 if (ret) { 740 atomic_dec(&psp->fence_value); 741 goto exit; 742 } 743 744 amdgpu_device_invalidate_hdp(psp->adev, NULL); 745 while (*((unsigned int *)psp->fence_buf) != index) { 746 if (--timeout == 0) 747 break; 748 /* 749 * Shouldn't wait for timeout when err_event_athub occurs, 750 * because gpu reset thread triggered and lock resource should 751 * be released for psp resume sequence. 752 */ 753 ras_intr = amdgpu_ras_intr_triggered(); 754 if (ras_intr) 755 break; 756 usleep_range(60, 100); 757 amdgpu_device_invalidate_hdp(psp->adev, NULL); 758 } 759 760 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 761 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 762 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 763 764 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 765 766 /* In some cases, psp response status is not 0 even there is no 767 * problem while the command is submitted. Some version of PSP FW 768 * doesn't write 0 to that field. 769 * So here we would like to only print a warning instead of an error 770 * during psp initialization to avoid breaking hw_init and it doesn't 771 * return -EINVAL. 772 */ 773 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 774 if (ucode) 775 dev_warn(psp->adev->dev, 776 "failed to load ucode %s(0x%X) ", 777 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 778 if (psp_err_warn(psp)) 779 dev_warn( 780 psp->adev->dev, 781 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 782 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), 783 psp->cmd_buf_mem->cmd_id, 784 psp->cmd_buf_mem->resp.status); 785 /* If any firmware (including CAP) load fails under SRIOV, it should 786 * return failure to stop the VF from initializing. 787 * Also return failure in case of timeout 788 */ 789 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 790 ret = -EINVAL; 791 goto exit; 792 } 793 } 794 795 if (ucode) { 796 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 797 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 798 } 799 800 exit: 801 return ret; 802 } 803 804 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 805 { 806 struct psp_gfx_cmd_resp *cmd = psp->cmd; 807 808 mutex_lock(&psp->mutex); 809 810 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 811 812 return cmd; 813 } 814 815 static void release_psp_cmd_buf(struct psp_context *psp) 816 { 817 mutex_unlock(&psp->mutex); 818 } 819 820 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 821 struct psp_gfx_cmd_resp *cmd, 822 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 823 { 824 struct amdgpu_device *adev = psp->adev; 825 uint32_t size = 0; 826 uint64_t tmr_pa = 0; 827 828 if (tmr_bo) { 829 size = amdgpu_bo_size(tmr_bo); 830 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 831 } 832 833 if (amdgpu_sriov_vf(psp->adev)) 834 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 835 else 836 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 837 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 838 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 839 cmd->cmd.cmd_setup_tmr.buf_size = size; 840 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 841 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 842 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 843 } 844 845 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 846 uint64_t pri_buf_mc, uint32_t size) 847 { 848 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 849 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 850 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 851 cmd->cmd.cmd_load_toc.toc_size = size; 852 } 853 854 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 855 static int psp_load_toc(struct psp_context *psp, 856 uint32_t *tmr_size) 857 { 858 int ret; 859 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 860 861 /* Copy toc to psp firmware private buffer */ 862 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 863 if (ret) { 864 release_psp_cmd_buf(psp); 865 return ret; 866 } 867 868 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 869 870 ret = psp_cmd_submit_buf(psp, NULL, cmd, 871 psp->fence_buf_mc_addr); 872 if (!ret) 873 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 874 875 release_psp_cmd_buf(psp); 876 877 return ret; 878 } 879 880 /* Set up Trusted Memory Region */ 881 static int psp_tmr_init(struct psp_context *psp) 882 { 883 int ret = 0; 884 int tmr_size; 885 void *tmr_buf; 886 void **pptr; 887 888 /* 889 * According to HW engineer, they prefer the TMR address be "naturally 890 * aligned" , e.g. the start address be an integer divide of TMR size. 891 * 892 * Note: this memory need be reserved till the driver 893 * uninitializes. 894 */ 895 tmr_size = PSP_TMR_SIZE(psp->adev); 896 897 /* For ASICs support RLC autoload, psp will parse the toc 898 * and calculate the total size of TMR needed 899 */ 900 if (!amdgpu_sriov_vf(psp->adev) && 901 psp->toc.start_addr && 902 psp->toc.size_bytes && 903 psp->fw_pri_buf) { 904 ret = psp_load_toc(psp, &tmr_size); 905 if (ret) { 906 dev_err(psp->adev->dev, "Failed to load toc\n"); 907 return ret; 908 } 909 } 910 911 if (!psp->tmr_bo && !psp->boot_time_tmr) { 912 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 913 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 914 PSP_TMR_ALIGNMENT, 915 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 916 &psp->tmr_bo, &psp->tmr_mc_addr, 917 pptr); 918 } 919 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 920 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 921 922 return ret; 923 } 924 925 static bool psp_skip_tmr(struct psp_context *psp) 926 { 927 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 928 929 if (amdgpu_sriov_vf(psp->adev)) 930 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 931 else 932 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 933 } 934 935 static int psp_tmr_load(struct psp_context *psp) 936 { 937 int ret; 938 struct psp_gfx_cmd_resp *cmd; 939 940 if (psp_skip_tmr(psp)) 941 return 0; 942 943 cmd = acquire_psp_cmd_buf(psp); 944 945 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 946 if (psp->tmr_bo) 947 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 948 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 949 950 ret = psp_cmd_submit_buf(psp, NULL, cmd, 951 psp->fence_buf_mc_addr); 952 953 release_psp_cmd_buf(psp); 954 955 return ret; 956 } 957 958 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 959 struct psp_gfx_cmd_resp *cmd) 960 { 961 if (amdgpu_sriov_vf(psp->adev)) 962 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 963 else 964 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 965 } 966 967 static int psp_tmr_unload(struct psp_context *psp) 968 { 969 int ret; 970 struct psp_gfx_cmd_resp *cmd; 971 972 if (psp_skip_tmr(psp)) 973 return 0; 974 975 cmd = acquire_psp_cmd_buf(psp); 976 977 psp_prep_tmr_unload_cmd_buf(psp, cmd); 978 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 979 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, 981 psp->fence_buf_mc_addr); 982 983 release_psp_cmd_buf(psp); 984 985 return ret; 986 } 987 988 static int psp_tmr_terminate(struct psp_context *psp) 989 { 990 return psp_tmr_unload(psp); 991 } 992 993 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 994 uint64_t *output_ptr) 995 { 996 int ret; 997 struct psp_gfx_cmd_resp *cmd; 998 999 if (!output_ptr) 1000 return -EINVAL; 1001 1002 if (amdgpu_sriov_vf(psp->adev)) 1003 return 0; 1004 1005 cmd = acquire_psp_cmd_buf(psp); 1006 1007 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1008 1009 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1010 psp->fence_buf_mc_addr); 1011 1012 if (!ret) { 1013 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1014 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1015 } 1016 1017 release_psp_cmd_buf(psp); 1018 1019 return ret; 1020 } 1021 1022 static int psp_get_fw_reservation_info(struct psp_context *psp, 1023 uint32_t cmd_id, 1024 uint64_t *addr, 1025 uint32_t *size) 1026 { 1027 int ret; 1028 uint32_t status; 1029 struct psp_gfx_cmd_resp *cmd; 1030 1031 cmd = acquire_psp_cmd_buf(psp); 1032 1033 cmd->cmd_id = cmd_id; 1034 1035 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1036 psp->fence_buf_mc_addr); 1037 if (ret) { 1038 release_psp_cmd_buf(psp); 1039 return ret; 1040 } 1041 1042 status = cmd->resp.status; 1043 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1044 release_psp_cmd_buf(psp); 1045 *addr = 0; 1046 *size = 0; 1047 return 0; 1048 } 1049 1050 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1051 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1052 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1053 1054 release_psp_cmd_buf(psp); 1055 1056 return 0; 1057 } 1058 1059 int psp_update_fw_reservation(struct psp_context *psp) 1060 { 1061 int ret; 1062 uint64_t reserv_addr, reserv_addr_ext; 1063 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1064 struct amdgpu_device *adev = psp->adev; 1065 1066 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1067 1068 if (amdgpu_sriov_vf(psp->adev)) 1069 return 0; 1070 1071 switch (mp0_ip_ver) { 1072 case IP_VERSION(14, 0, 2): 1073 if (adev->psp.sos.fw_version < 0x3b0e0d) 1074 return 0; 1075 break; 1076 1077 case IP_VERSION(14, 0, 3): 1078 if (adev->psp.sos.fw_version < 0x3a0e14) 1079 return 0; 1080 break; 1081 1082 default: 1083 return 0; 1084 } 1085 1086 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1087 if (ret) 1088 return ret; 1089 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1090 if (ret) 1091 return ret; 1092 1093 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1094 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1095 return 0; 1096 } 1097 1098 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1099 1100 reserv_size = roundup(reserv_size, SZ_1M); 1101 1102 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1103 reserv_addr, reserv_size, false); 1104 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1105 if (ret) { 1106 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1107 return ret; 1108 } 1109 1110 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1111 1112 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1113 reserv_addr_ext, reserv_size_ext, false); 1114 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1115 if (ret) { 1116 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1124 { 1125 struct psp_context *psp = &adev->psp; 1126 struct psp_gfx_cmd_resp *cmd; 1127 int ret; 1128 1129 if (amdgpu_sriov_vf(adev)) 1130 return 0; 1131 1132 cmd = acquire_psp_cmd_buf(psp); 1133 1134 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1135 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1136 1137 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1138 if (!ret) { 1139 *boot_cfg = 1140 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1141 } 1142 1143 release_psp_cmd_buf(psp); 1144 1145 return ret; 1146 } 1147 1148 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1149 { 1150 int ret; 1151 struct psp_context *psp = &adev->psp; 1152 struct psp_gfx_cmd_resp *cmd; 1153 1154 if (amdgpu_sriov_vf(adev)) 1155 return 0; 1156 1157 cmd = acquire_psp_cmd_buf(psp); 1158 1159 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1160 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1161 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1162 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1163 1164 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1165 1166 release_psp_cmd_buf(psp); 1167 1168 return ret; 1169 } 1170 1171 static int psp_rl_load(struct amdgpu_device *adev) 1172 { 1173 int ret; 1174 struct psp_context *psp = &adev->psp; 1175 struct psp_gfx_cmd_resp *cmd; 1176 1177 if (!is_psp_fw_valid(psp->rl)) 1178 return 0; 1179 1180 cmd = acquire_psp_cmd_buf(psp); 1181 1182 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1183 if (ret) { 1184 release_psp_cmd_buf(psp); 1185 return ret; 1186 } 1187 1188 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1189 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1190 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1191 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1192 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1193 1194 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1195 1196 release_psp_cmd_buf(psp); 1197 1198 return ret; 1199 } 1200 1201 int psp_memory_partition(struct psp_context *psp, int mode) 1202 { 1203 struct psp_gfx_cmd_resp *cmd; 1204 int ret; 1205 1206 if (amdgpu_sriov_vf(psp->adev)) 1207 return 0; 1208 1209 cmd = acquire_psp_cmd_buf(psp); 1210 1211 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1212 cmd->cmd.cmd_memory_part.mode = mode; 1213 1214 dev_info(psp->adev->dev, 1215 "Requesting %d memory partition change through PSP", mode); 1216 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1217 if (ret) 1218 dev_err(psp->adev->dev, 1219 "PSP request failed to change to NPS%d mode\n", mode); 1220 1221 release_psp_cmd_buf(psp); 1222 1223 return ret; 1224 } 1225 1226 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 1227 { 1228 int ret; 1229 struct psp_context *psp = &adev->psp; 1230 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1231 1232 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL; 1233 1234 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1235 if (ret) { 1236 dev_err(psp->adev->dev, 1237 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret); 1238 release_psp_cmd_buf(psp); 1239 return ret; 1240 } 1241 1242 if (cmd->resp.status) { 1243 dev_err(psp->adev->dev, 1244 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n", 1245 cmd->cmd_id, cmd->resp.status); 1246 ret = -EIO; 1247 } 1248 release_psp_cmd_buf(psp); 1249 1250 return ret; 1251 } 1252 1253 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1254 uint32_t *ptl_fmt) 1255 { 1256 struct amdgpu_device *adev = psp->adev; 1257 1258 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1259 return -EINVAL; 1260 1261 switch (fmt) { 1262 case AMDGPU_PTL_FMT_I8: 1263 *ptl_fmt = GFX_FTYPE_I8; 1264 break; 1265 case AMDGPU_PTL_FMT_F16: 1266 *ptl_fmt = GFX_FTYPE_F16; 1267 break; 1268 case AMDGPU_PTL_FMT_BF16: 1269 *ptl_fmt = GFX_FTYPE_BF16; 1270 break; 1271 case AMDGPU_PTL_FMT_F32: 1272 *ptl_fmt = GFX_FTYPE_F32; 1273 break; 1274 case AMDGPU_PTL_FMT_F64: 1275 *ptl_fmt = GFX_FTYPE_F64; 1276 break; 1277 case AMDGPU_PTL_FMT_F8: 1278 *ptl_fmt = GFX_FTYPE_F8; 1279 break; 1280 case AMDGPU_PTL_FMT_VECTOR: 1281 *ptl_fmt = GFX_FTYPE_VECTOR; 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1291 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1292 { 1293 struct psp_gfx_cmd_resp *cmd; 1294 struct amdgpu_ptl *ptl = &psp->ptl; 1295 int ret; 1296 1297 cmd = acquire_psp_cmd_buf(psp); 1298 1299 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1300 cmd->cmd.cmd_req_perf_hw.req = req_code; 1301 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1302 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1303 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1304 1305 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1306 if (ret) 1307 goto out; 1308 1309 /* 1310 * Check response status explicitly to avoid 1311 * updating cached PTL state with invalid data. 1312 */ 1313 if (cmd->resp.status) { 1314 dev_err(psp->adev->dev, 1315 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1316 req_code, cmd->resp.status, 1317 cmd->resp.uresp.perf_hw_info.resp); 1318 ret = -EIO; 1319 goto out; 1320 } 1321 1322 /* Parse response */ 1323 switch (req_code) { 1324 case PSP_PTL_PERF_MON_QUERY: 1325 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1326 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1327 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1328 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1329 *ptl_state, *fmt1, *fmt2); 1330 break; 1331 case PSP_PTL_PERF_MON_SET: 1332 /* Update cached state only on success */ 1333 ptl->enabled = *ptl_state; 1334 ptl->fmt1 = *fmt1; 1335 ptl->fmt2 = *fmt2; 1336 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1337 *ptl_state, *fmt1, *fmt2); 1338 break; 1339 } 1340 1341 out: 1342 release_psp_cmd_buf(psp); 1343 return ret; 1344 } 1345 1346 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1347 uint32_t *ptl_state, 1348 enum amdgpu_ptl_fmt *fmt1, 1349 enum amdgpu_ptl_fmt *fmt2) 1350 { 1351 uint32_t ptl_fmt1, ptl_fmt2; 1352 struct psp_context *psp; 1353 struct amdgpu_ptl *ptl; 1354 int ret; 1355 1356 if (!adev || !ptl_state || !fmt1 || !fmt2) 1357 return -EINVAL; 1358 1359 if (amdgpu_sriov_vf(adev)) 1360 return 0; 1361 1362 psp = &adev->psp; 1363 ptl = &psp->ptl; 1364 1365 if (ptl->permanently_disabled && *ptl_state == 1) 1366 return 0; 1367 1368 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1369 psp->sos.fw_version < 0x0036081a) 1370 return -EOPNOTSUPP; 1371 1372 /* Verify formats */ 1373 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1374 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1375 return -EINVAL; 1376 1377 /* 1378 * Add check to skip if state and formats are identical to current ones 1379 */ 1380 if (req_code == PSP_PTL_PERF_MON_SET && 1381 ptl->enabled == *ptl_state && 1382 ptl->fmt1 == ptl_fmt1 && 1383 ptl->fmt2 == ptl_fmt2) 1384 return 0; 1385 1386 /* If enabling PTL, check disable bitmap */ 1387 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1388 if (!bitmap_empty(ptl->disable_bitmap, 1389 AMDGPU_PTL_DISABLE_MAX)) { 1390 dev_dbg(adev->dev, 1391 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1392 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1393 ptl->disable_bitmap), 1394 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1395 ptl->disable_bitmap), 1396 atomic_read(&ptl->disable_ref)); 1397 return 0; 1398 } 1399 } 1400 1401 if (req_code == PSP_PTL_PERF_MON_SET) { 1402 amdgpu_amdkfd_stop_sched_all(adev); 1403 /* Wait for GFX engine idle before PTL state transition */ 1404 ret = amdgpu_device_ip_wait_for_idle(adev, 1405 AMD_IP_BLOCK_TYPE_GFX); 1406 if (ret) { 1407 amdgpu_amdkfd_start_sched_all(adev); 1408 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1409 return ret; 1410 } 1411 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1412 amdgpu_amdkfd_start_sched_all(adev); 1413 } else { 1414 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1415 } 1416 1417 return ret; 1418 } 1419 1420 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1421 { 1422 int i; 1423 1424 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1425 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1426 return (enum amdgpu_ptl_fmt)i; 1427 } 1428 1429 return AMDGPU_PTL_FMT_INVALID; 1430 } 1431 1432 static ssize_t ptl_supported_formats_show(struct device *dev, 1433 struct device_attribute *attr, char *buf) 1434 { 1435 ssize_t len = 0; 1436 1437 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1438 const char *fmt = amdgpu_ptl_fmt_str[i]; 1439 1440 len += sysfs_emit_at(buf, len, "%s%s", 1441 fmt ? fmt : "UNKNOWN", 1442 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1443 } 1444 1445 return len; 1446 } 1447 1448 static ssize_t ptl_enable_store(struct device *dev, 1449 struct device_attribute *attr, 1450 const char *buf, size_t count) 1451 { 1452 struct drm_device *ddev = dev_get_drvdata(dev); 1453 struct amdgpu_device *adev = drm_to_adev(ddev); 1454 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1455 uint32_t ptl_state, fmt1, fmt2; 1456 int ret; 1457 bool enable; 1458 bool bit_changed = false; 1459 1460 mutex_lock(&ptl->mutex); 1461 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1462 enable = true; 1463 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1464 enable = false; 1465 } else { 1466 mutex_unlock(&ptl->mutex); 1467 return -EINVAL; 1468 } 1469 1470 /* Block enable when permanently disabled */ 1471 if (ptl->permanently_disabled) { 1472 mutex_unlock(&ptl->mutex); 1473 return -EPERM; 1474 } 1475 1476 fmt1 = ptl->fmt1; 1477 fmt2 = ptl->fmt2; 1478 ptl_state = enable ? 1 : 0; 1479 1480 if (enable) 1481 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1482 ptl->disable_bitmap); 1483 1484 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1485 if (ret) { 1486 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1487 if (enable && bit_changed) 1488 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1489 mutex_unlock(&ptl->mutex); 1490 return ret; 1491 } 1492 1493 if (!enable) 1494 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1495 1496 mutex_unlock(&ptl->mutex); 1497 1498 return count; 1499 } 1500 1501 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1502 { 1503 struct drm_device *ddev = dev_get_drvdata(dev); 1504 struct amdgpu_device *adev = drm_to_adev(ddev); 1505 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1506 1507 if (ptl->permanently_disabled) 1508 return sysfs_emit(buf, "permanently disabled\n"); 1509 1510 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1511 } 1512 1513 static ssize_t ptl_format_store(struct device *dev, 1514 struct device_attribute *attr, 1515 const char *buf, size_t count) 1516 { 1517 struct drm_device *ddev = dev_get_drvdata(dev); 1518 struct amdgpu_device *adev = drm_to_adev(ddev); 1519 char fmt1_str[8], fmt2_str[8]; 1520 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1521 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1522 uint32_t ptl_state, fmt1, fmt2; 1523 int ret; 1524 1525 /* Only allow format update when PTL is enabled */ 1526 if (!ptl->enabled) 1527 return -EPERM; 1528 1529 mutex_lock(&ptl->mutex); 1530 /* Parse input, expecting "FMT1,FMT2" */ 1531 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1532 mutex_unlock(&ptl->mutex); 1533 return -EINVAL; 1534 } 1535 1536 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1537 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1538 1539 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1540 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 1541 fmt1_enum == fmt2_enum) { 1542 mutex_unlock(&ptl->mutex); 1543 return -EINVAL; 1544 } 1545 1546 ptl_state = ptl->enabled; 1547 fmt1 = fmt1_enum; 1548 fmt2 = fmt2_enum; 1549 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1550 if (ret) { 1551 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 1552 mutex_unlock(&ptl->mutex); 1553 return ret; 1554 } 1555 mutex_unlock(&ptl->mutex); 1556 1557 return count; 1558 } 1559 1560 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 1561 { 1562 struct drm_device *ddev = dev_get_drvdata(dev); 1563 struct amdgpu_device *adev = drm_to_adev(ddev); 1564 struct psp_context *psp = &adev->psp; 1565 1566 return sysfs_emit(buf, "%s,%s\n", 1567 amdgpu_ptl_fmt_str[psp->ptl.fmt1], 1568 amdgpu_ptl_fmt_str[psp->ptl.fmt2]); 1569 } 1570 1571 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 1572 { 1573 struct device *dev = kobj_to_dev(kobj); 1574 struct drm_device *ddev = dev_get_drvdata(dev); 1575 struct amdgpu_device *adev = drm_to_adev(ddev); 1576 1577 /* Only show PTL sysfs files if PTL hardware is supported */ 1578 if (!adev->psp.ptl.hw_supported) 1579 return 0; 1580 1581 return attr->mode; 1582 } 1583 1584 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 1585 { 1586 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1587 int ret; 1588 1589 if (!ptl->hw_supported) 1590 return 0; 1591 1592 if (ptl->ptl_sysfs_created) 1593 return 0; 1594 1595 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1596 if (!ret) 1597 ptl->ptl_sysfs_created = true; 1598 1599 return ret; 1600 } 1601 1602 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 1603 { 1604 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1605 1606 if (!ptl->hw_supported) 1607 return; 1608 1609 if (!ptl->ptl_sysfs_created) 1610 return; 1611 1612 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 1613 ptl->ptl_sysfs_created = false; 1614 } 1615 1616 int psp_spatial_partition(struct psp_context *psp, int mode) 1617 { 1618 struct psp_gfx_cmd_resp *cmd; 1619 int ret; 1620 1621 if (amdgpu_sriov_vf(psp->adev)) 1622 return 0; 1623 1624 cmd = acquire_psp_cmd_buf(psp); 1625 1626 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 1627 cmd->cmd.cmd_spatial_part.mode = mode; 1628 1629 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 1630 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1631 1632 release_psp_cmd_buf(psp); 1633 1634 return ret; 1635 } 1636 1637 static int psp_asd_initialize(struct psp_context *psp) 1638 { 1639 int ret; 1640 1641 /* If PSP version doesn't match ASD version, asd loading will be failed. 1642 * add workaround to bypass it for sriov now. 1643 * TODO: add version check to make it common 1644 */ 1645 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 1646 return 0; 1647 1648 /* bypass asd if display hardware is not available */ 1649 if (!amdgpu_device_has_display_hardware(psp->adev) && 1650 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 1651 return 0; 1652 1653 psp->asd_context.mem_context.shared_mc_addr = 0; 1654 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 1655 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 1656 1657 ret = psp_ta_load(psp, &psp->asd_context); 1658 if (!ret) 1659 psp->asd_context.initialized = true; 1660 1661 return ret; 1662 } 1663 1664 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1665 uint32_t session_id) 1666 { 1667 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 1668 cmd->cmd.cmd_unload_ta.session_id = session_id; 1669 } 1670 1671 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 1672 { 1673 int ret; 1674 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1675 1676 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 1677 1678 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1679 1680 context->resp_status = cmd->resp.status; 1681 1682 release_psp_cmd_buf(psp); 1683 1684 return ret; 1685 } 1686 1687 static int psp_asd_terminate(struct psp_context *psp) 1688 { 1689 int ret; 1690 1691 if (amdgpu_sriov_vf(psp->adev)) 1692 return 0; 1693 1694 if (!psp->asd_context.initialized) 1695 return 0; 1696 1697 ret = psp_ta_unload(psp, &psp->asd_context); 1698 if (!ret) 1699 psp->asd_context.initialized = false; 1700 1701 return ret; 1702 } 1703 1704 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1705 uint32_t id, uint32_t value) 1706 { 1707 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1708 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1709 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1710 } 1711 1712 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1713 uint32_t value) 1714 { 1715 struct psp_gfx_cmd_resp *cmd; 1716 int ret = 0; 1717 1718 if (reg >= PSP_REG_LAST) 1719 return -EINVAL; 1720 1721 cmd = acquire_psp_cmd_buf(psp); 1722 1723 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1724 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1725 if (ret) 1726 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 1727 1728 release_psp_cmd_buf(psp); 1729 1730 return ret; 1731 } 1732 1733 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1734 uint64_t ta_bin_mc, 1735 struct ta_context *context) 1736 { 1737 cmd->cmd_id = context->ta_load_type; 1738 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1739 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1740 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1741 1742 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1743 lower_32_bits(context->mem_context.shared_mc_addr); 1744 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1745 upper_32_bits(context->mem_context.shared_mc_addr); 1746 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1747 } 1748 1749 int psp_ta_init_shared_buf(struct psp_context *psp, 1750 struct ta_mem_context *mem_ctx) 1751 { 1752 /* 1753 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1754 * physical) for ta to host memory 1755 */ 1756 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1757 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 1758 AMDGPU_GEM_DOMAIN_GTT, 1759 &mem_ctx->shared_bo, 1760 &mem_ctx->shared_mc_addr, 1761 &mem_ctx->shared_buf); 1762 } 1763 1764 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1765 uint32_t ta_cmd_id, 1766 uint32_t session_id) 1767 { 1768 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1769 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1770 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1771 } 1772 1773 int psp_ta_invoke(struct psp_context *psp, 1774 uint32_t ta_cmd_id, 1775 struct ta_context *context) 1776 { 1777 int ret; 1778 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1779 1780 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1781 1782 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1783 psp->fence_buf_mc_addr); 1784 1785 context->resp_status = cmd->resp.status; 1786 1787 release_psp_cmd_buf(psp); 1788 1789 return ret; 1790 } 1791 1792 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1793 { 1794 int ret; 1795 struct psp_gfx_cmd_resp *cmd; 1796 1797 cmd = acquire_psp_cmd_buf(psp); 1798 1799 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 1800 context->bin_desc.size_bytes); 1801 if (ret) { 1802 release_psp_cmd_buf(psp); 1803 return ret; 1804 } 1805 1806 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 1807 context->mem_context.shared_bo) 1808 context->mem_context.shared_mc_addr = 1809 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 1810 1811 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1812 1813 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1814 psp->fence_buf_mc_addr); 1815 1816 context->resp_status = cmd->resp.status; 1817 1818 if (!ret) 1819 context->session_id = cmd->resp.session_id; 1820 1821 release_psp_cmd_buf(psp); 1822 1823 return ret; 1824 } 1825 1826 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1827 { 1828 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1829 } 1830 1831 int psp_xgmi_terminate(struct psp_context *psp) 1832 { 1833 int ret; 1834 struct amdgpu_device *adev = psp->adev; 1835 1836 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1837 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 1838 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 1839 adev->gmc.xgmi.connected_to_cpu)) 1840 return 0; 1841 1842 if (!psp->xgmi_context.context.initialized) 1843 return 0; 1844 1845 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1846 1847 psp->xgmi_context.context.initialized = false; 1848 1849 return ret; 1850 } 1851 1852 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1853 { 1854 struct ta_xgmi_shared_memory *xgmi_cmd; 1855 int ret; 1856 1857 if (!psp->ta_fw || 1858 !psp->xgmi_context.context.bin_desc.size_bytes || 1859 !psp->xgmi_context.context.bin_desc.start_addr) 1860 return -ENOENT; 1861 1862 if (!load_ta) 1863 goto invoke; 1864 1865 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1866 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1867 1868 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1869 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1870 if (ret) 1871 return ret; 1872 } 1873 1874 /* Load XGMI TA */ 1875 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1876 if (!ret) 1877 psp->xgmi_context.context.initialized = true; 1878 else 1879 return ret; 1880 1881 invoke: 1882 /* Initialize XGMI session */ 1883 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1884 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1885 xgmi_cmd->flag_extend_link_record = set_extended_data; 1886 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1887 1888 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1889 /* note down the capbility flag for XGMI TA */ 1890 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 1891 1892 if (!amdgpu_sriov_vf(psp->adev)) 1893 psp->xgmi_context.supports_ext_link_info = psp->xgmi_context.xgmi_ta_caps & 1894 EXTEND_PEER_LINK_INFO_CMD_FLAG; 1895 else 1896 psp->xgmi_context.supports_ext_link_info = amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 1897 1898 return ret; 1899 } 1900 1901 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1902 { 1903 struct ta_xgmi_shared_memory *xgmi_cmd; 1904 int ret; 1905 1906 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1907 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1908 1909 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1910 1911 /* Invoke xgmi ta to get hive id */ 1912 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1913 if (ret) 1914 return ret; 1915 1916 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1917 1918 return 0; 1919 } 1920 1921 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1922 { 1923 struct ta_xgmi_shared_memory *xgmi_cmd; 1924 int ret; 1925 1926 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1927 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1928 1929 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1930 1931 /* Invoke xgmi ta to get the node id */ 1932 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1933 if (ret) 1934 return ret; 1935 1936 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1937 1938 return 0; 1939 } 1940 1941 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1942 { 1943 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 1944 IP_VERSION(13, 0, 2) && 1945 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 1946 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 1947 IP_VERSION(13, 0, 6); 1948 } 1949 1950 /* 1951 * Chips that support extended topology information require the driver to 1952 * reflect topology information in the opposite direction. This is 1953 * because the TA has already exceeded its link record limit and if the 1954 * TA holds bi-directional information, the driver would have to do 1955 * multiple fetches instead of just two. 1956 */ 1957 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1958 struct psp_xgmi_node_info node_info) 1959 { 1960 struct amdgpu_device *mirror_adev; 1961 struct amdgpu_hive_info *hive; 1962 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1963 uint64_t dst_node_id = node_info.node_id; 1964 uint8_t dst_num_hops = node_info.num_hops; 1965 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 1966 uint8_t dst_num_links = node_info.num_links; 1967 1968 hive = amdgpu_get_xgmi_hive(psp->adev); 1969 if (WARN_ON(!hive)) 1970 return; 1971 1972 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1973 struct psp_xgmi_topology_info *mirror_top_info; 1974 int j; 1975 1976 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1977 continue; 1978 1979 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1980 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1981 if (mirror_top_info->nodes[j].node_id != src_node_id) 1982 continue; 1983 1984 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1985 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 1986 /* prevent 0 num_links value re-reflection since reflection 1987 * criteria is based on num_hops (direct or indirect). 1988 */ 1989 if (dst_num_links) { 1990 mirror_top_info->nodes[j].num_links = dst_num_links; 1991 /* swap src and dst due to frame of reference */ 1992 for (int k = 0; k < dst_num_links; k++) { 1993 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 1994 node_info.port_num[k].dst_xgmi_port_num; 1995 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 1996 node_info.port_num[k].src_xgmi_port_num; 1997 } 1998 } 1999 2000 break; 2001 } 2002 2003 break; 2004 } 2005 2006 amdgpu_put_xgmi_hive(hive); 2007 } 2008 2009 int psp_xgmi_get_topology_info(struct psp_context *psp, 2010 int number_devices, 2011 struct psp_xgmi_topology_info *topology, 2012 bool get_extended_data) 2013 { 2014 struct ta_xgmi_shared_memory *xgmi_cmd; 2015 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2016 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 2017 int i; 2018 int ret; 2019 2020 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2021 return -EINVAL; 2022 2023 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2024 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2025 xgmi_cmd->flag_extend_link_record = get_extended_data; 2026 2027 /* Fill in the shared memory with topology information as input */ 2028 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2029 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 2030 topology_info_input->num_nodes = number_devices; 2031 2032 for (i = 0; i < topology_info_input->num_nodes; i++) { 2033 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2034 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2035 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2036 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2037 } 2038 2039 /* Invoke xgmi ta to get the topology information */ 2040 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2041 if (ret) 2042 return ret; 2043 2044 /* Read the output topology information from the shared memory */ 2045 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2046 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2047 for (i = 0; i < topology->num_nodes; i++) { 2048 /* extended data will either be 0 or equal to non-extended data */ 2049 if (topology_info_output->nodes[i].num_hops) 2050 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2051 2052 /* non-extended data gets everything here so no need to update */ 2053 if (!get_extended_data) { 2054 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2055 topology->nodes[i].is_sharing_enabled = 2056 topology_info_output->nodes[i].is_sharing_enabled; 2057 topology->nodes[i].sdma_engine = 2058 topology_info_output->nodes[i].sdma_engine; 2059 } 2060 2061 } 2062 2063 /* Invoke xgmi ta again to get the link information */ 2064 if (psp_xgmi_peer_link_info_supported(psp)) { 2065 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2066 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2067 bool requires_reflection = 2068 (psp->xgmi_context.supports_extended_data && 2069 get_extended_data) || 2070 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2071 IP_VERSION(13, 0, 6) || 2072 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2073 IP_VERSION(13, 0, 14) || 2074 amdgpu_sriov_vf(psp->adev); 2075 2076 /* popluate the shared output buffer rather than the cmd input buffer 2077 * with node_ids as the input for GET_PEER_LINKS command execution. 2078 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2079 * The same requirement for GET_EXTEND_PEER_LINKS command. 2080 */ 2081 if (psp->xgmi_context.supports_ext_link_info) { 2082 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2083 2084 for (i = 0; i < topology->num_nodes; i++) 2085 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2086 2087 link_extend_info_output->num_nodes = topology->num_nodes; 2088 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2089 } else { 2090 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2091 2092 for (i = 0; i < topology->num_nodes; i++) 2093 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2094 2095 link_info_output->num_nodes = topology->num_nodes; 2096 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2097 } 2098 2099 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2100 if (ret) 2101 return ret; 2102 2103 for (i = 0; i < topology->num_nodes; i++) { 2104 uint8_t node_num_links = psp->xgmi_context.supports_ext_link_info ? 2105 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2106 /* accumulate num_links on extended data */ 2107 if (get_extended_data) { 2108 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2109 } else { 2110 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2111 topology->nodes[i].num_links : node_num_links; 2112 } 2113 /* popluate the connected port num info if supported and available */ 2114 if (psp->xgmi_context.supports_ext_link_info && topology->nodes[i].num_links) { 2115 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2116 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2117 } 2118 2119 /* reflect the topology information for bi-directionality */ 2120 if (requires_reflection && topology->nodes[i].num_hops) 2121 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2122 } 2123 } 2124 2125 return 0; 2126 } 2127 2128 int psp_xgmi_set_topology_info(struct psp_context *psp, 2129 int number_devices, 2130 struct psp_xgmi_topology_info *topology) 2131 { 2132 struct ta_xgmi_shared_memory *xgmi_cmd; 2133 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2134 int i; 2135 2136 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2137 return -EINVAL; 2138 2139 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2140 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2141 2142 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2143 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2144 topology_info_input->num_nodes = number_devices; 2145 2146 for (i = 0; i < topology_info_input->num_nodes; i++) { 2147 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2148 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2149 topology_info_input->nodes[i].is_sharing_enabled = 1; 2150 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2151 } 2152 2153 /* Invoke xgmi ta to set topology information */ 2154 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2155 } 2156 2157 // ras begin 2158 static void psp_ras_ta_check_status(struct psp_context *psp) 2159 { 2160 struct ta_ras_shared_memory *ras_cmd = 2161 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2162 2163 switch (ras_cmd->ras_status) { 2164 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2165 dev_warn(psp->adev->dev, 2166 "RAS WARNING: cmd failed due to unsupported ip\n"); 2167 break; 2168 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2169 dev_warn(psp->adev->dev, 2170 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2171 break; 2172 case TA_RAS_STATUS__SUCCESS: 2173 break; 2174 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2175 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2176 dev_warn(psp->adev->dev, 2177 "RAS WARNING: Inject error to critical region is not allowed\n"); 2178 break; 2179 default: 2180 dev_warn(psp->adev->dev, 2181 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2182 break; 2183 } 2184 } 2185 2186 static int psp_ras_send_cmd(struct psp_context *psp, 2187 enum ras_command cmd_id, void *in, void *out) 2188 { 2189 struct ta_ras_shared_memory *ras_cmd; 2190 uint32_t cmd = cmd_id; 2191 int ret = 0; 2192 2193 if (!in) 2194 return -EINVAL; 2195 2196 mutex_lock(&psp->ras_context.mutex); 2197 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2198 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2199 2200 switch (cmd) { 2201 case TA_RAS_COMMAND__ENABLE_FEATURES: 2202 case TA_RAS_COMMAND__DISABLE_FEATURES: 2203 memcpy(&ras_cmd->ras_in_message, 2204 in, sizeof(ras_cmd->ras_in_message)); 2205 break; 2206 case TA_RAS_COMMAND__TRIGGER_ERROR: 2207 memcpy(&ras_cmd->ras_in_message.trigger_error, 2208 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2209 break; 2210 case TA_RAS_COMMAND__QUERY_ADDRESS: 2211 memcpy(&ras_cmd->ras_in_message.address, 2212 in, sizeof(ras_cmd->ras_in_message.address)); 2213 break; 2214 default: 2215 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2216 ret = -EINVAL; 2217 goto err_out; 2218 } 2219 2220 ras_cmd->cmd_id = cmd; 2221 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2222 2223 switch (cmd) { 2224 case TA_RAS_COMMAND__TRIGGER_ERROR: 2225 if (!ret && out) 2226 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2227 break; 2228 case TA_RAS_COMMAND__QUERY_ADDRESS: 2229 if (ret || ras_cmd->ras_status || psp->cmd_buf_mem->resp.status) 2230 ret = -EINVAL; 2231 else if (out) 2232 memcpy(out, 2233 &ras_cmd->ras_out_message.address, 2234 sizeof(ras_cmd->ras_out_message.address)); 2235 break; 2236 default: 2237 break; 2238 } 2239 2240 err_out: 2241 mutex_unlock(&psp->ras_context.mutex); 2242 2243 return ret; 2244 } 2245 2246 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2247 { 2248 struct ta_ras_shared_memory *ras_cmd; 2249 int ret; 2250 2251 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2252 2253 /* 2254 * TODO: bypass the loading in sriov for now 2255 */ 2256 if (amdgpu_sriov_vf(psp->adev)) 2257 return 0; 2258 2259 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2260 2261 if (amdgpu_ras_intr_triggered()) 2262 return ret; 2263 2264 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2265 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2266 return -EINVAL; 2267 } 2268 2269 if (!ret) { 2270 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2271 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2272 2273 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2274 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2275 dev_warn(psp->adev->dev, 2276 "RAS internal register access blocked\n"); 2277 2278 psp_ras_ta_check_status(psp); 2279 } 2280 2281 return ret; 2282 } 2283 2284 int psp_ras_enable_features(struct psp_context *psp, 2285 union ta_ras_cmd_input *info, bool enable) 2286 { 2287 enum ras_command cmd_id; 2288 int ret; 2289 2290 if (!psp->ras_context.context.initialized || !info) 2291 return -EINVAL; 2292 2293 cmd_id = enable ? 2294 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2295 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2296 if (ret) 2297 return -EINVAL; 2298 2299 return 0; 2300 } 2301 2302 int psp_ras_terminate(struct psp_context *psp) 2303 { 2304 int ret; 2305 2306 /* 2307 * TODO: bypass the terminate in sriov for now 2308 */ 2309 if (amdgpu_sriov_vf(psp->adev)) 2310 return 0; 2311 2312 if (!psp->ras_context.context.initialized) 2313 return 0; 2314 2315 ret = psp_ta_unload(psp, &psp->ras_context.context); 2316 2317 psp->ras_context.context.initialized = false; 2318 2319 mutex_destroy(&psp->ras_context.mutex); 2320 2321 return ret; 2322 } 2323 2324 int psp_ras_initialize(struct psp_context *psp) 2325 { 2326 int ret; 2327 uint32_t boot_cfg = 0xFF; 2328 struct amdgpu_device *adev = psp->adev; 2329 struct ta_ras_shared_memory *ras_cmd; 2330 2331 /* 2332 * TODO: bypass the initialize in sriov for now 2333 */ 2334 if (amdgpu_sriov_vf(adev)) 2335 return 0; 2336 2337 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2338 !adev->psp.ras_context.context.bin_desc.start_addr) { 2339 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2340 return 0; 2341 } 2342 2343 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2344 /* query GECC enablement status from boot config 2345 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2346 */ 2347 ret = psp_boot_config_get(adev, &boot_cfg); 2348 if (ret) 2349 dev_warn(adev->dev, "PSP get boot config failed\n"); 2350 2351 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2352 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2353 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2354 dev_warn(adev->dev, 2355 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2356 } else { 2357 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2358 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2359 if (boot_cfg == 1) { 2360 dev_info(adev->dev, "GECC is enabled\n"); 2361 } else { 2362 /* enable GECC in next boot cycle if it is disabled 2363 * in boot config, or force enable GECC if failed to 2364 * get boot configuration 2365 */ 2366 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2367 if (ret) 2368 dev_warn(adev->dev, "PSP set boot config failed\n"); 2369 else 2370 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2371 } 2372 } else { 2373 if (!boot_cfg) { 2374 if (!adev->ras_default_ecc_enabled && 2375 amdgpu_ras_enable != 1 && 2376 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2377 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2378 else 2379 dev_info(adev->dev, "GECC is disabled\n"); 2380 } else { 2381 /* disable GECC in next boot cycle if ras is 2382 * disabled by module parameter amdgpu_ras_enable 2383 * and/or amdgpu_ras_mask, or boot_config_get call 2384 * is failed 2385 */ 2386 ret = psp_boot_config_set(adev, 0); 2387 if (ret) 2388 dev_warn(adev->dev, "PSP set boot config failed\n"); 2389 else 2390 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2391 } 2392 } 2393 } 2394 } 2395 2396 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2397 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2398 2399 if (!psp->ras_context.context.mem_context.shared_buf) { 2400 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2401 if (ret) 2402 return ret; 2403 } 2404 2405 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2406 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2407 2408 if (amdgpu_ras_is_poison_mode_supported(adev)) 2409 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2410 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2411 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2412 ras_cmd->ras_in_message.init_flags.xcc_mask = 2413 adev->gfx.xcc_mask; 2414 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2415 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2416 ras_cmd->ras_in_message.init_flags.nps_mode = 2417 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2418 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; 2419 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2420 2421 ret = psp_ta_load(psp, &psp->ras_context.context); 2422 2423 if (!ret && !ras_cmd->ras_status) { 2424 psp->ras_context.context.initialized = true; 2425 mutex_init(&psp->ras_context.mutex); 2426 } else { 2427 if (ras_cmd->ras_status) 2428 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2429 2430 /* fail to load RAS TA */ 2431 psp->ras_context.context.initialized = false; 2432 } 2433 2434 return ret; 2435 } 2436 2437 int psp_ras_trigger_error(struct psp_context *psp, 2438 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2439 { 2440 struct amdgpu_device *adev = psp->adev; 2441 int ret; 2442 uint32_t dev_mask; 2443 uint32_t ras_status = 0; 2444 2445 if (!psp->ras_context.context.initialized || !info) 2446 return -EINVAL; 2447 2448 switch (info->block_id) { 2449 case TA_RAS_BLOCK__GFX: 2450 dev_mask = GET_MASK(GC, instance_mask); 2451 break; 2452 case TA_RAS_BLOCK__SDMA: 2453 dev_mask = GET_MASK(SDMA0, instance_mask); 2454 break; 2455 case TA_RAS_BLOCK__VCN: 2456 case TA_RAS_BLOCK__JPEG: 2457 dev_mask = GET_MASK(VCN, instance_mask); 2458 break; 2459 default: 2460 dev_mask = instance_mask; 2461 break; 2462 } 2463 2464 /* reuse sub_block_index for backward compatibility */ 2465 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2466 dev_mask &= AMDGPU_RAS_INST_MASK; 2467 info->sub_block_index |= dev_mask; 2468 2469 ret = psp_ras_send_cmd(psp, 2470 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2471 if (ret) 2472 return -EINVAL; 2473 2474 /* If err_event_athub occurs error inject was successful, however 2475 * return status from TA is no long reliable 2476 */ 2477 if (amdgpu_ras_intr_triggered()) 2478 return 0; 2479 2480 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2481 return -EACCES; 2482 else if (ras_status) 2483 return -EINVAL; 2484 2485 return 0; 2486 } 2487 2488 int psp_ras_query_address(struct psp_context *psp, 2489 struct ta_ras_query_address_input *addr_in, 2490 struct ta_ras_query_address_output *addr_out) 2491 { 2492 int ret; 2493 2494 if (!psp->ras_context.context.initialized || 2495 !addr_in || !addr_out) 2496 return -EINVAL; 2497 2498 ret = psp_ras_send_cmd(psp, 2499 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2500 2501 return ret; 2502 } 2503 // ras end 2504 2505 // HDCP start 2506 static int psp_hdcp_initialize(struct psp_context *psp) 2507 { 2508 int ret; 2509 2510 /* 2511 * TODO: bypass the initialize in sriov for now 2512 */ 2513 if (amdgpu_sriov_vf(psp->adev)) 2514 return 0; 2515 2516 /* bypass hdcp initialization if dmu is harvested */ 2517 if (!amdgpu_device_has_display_hardware(psp->adev)) 2518 return 0; 2519 2520 if (!psp->hdcp_context.context.bin_desc.size_bytes || 2521 !psp->hdcp_context.context.bin_desc.start_addr) { 2522 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 2523 return 0; 2524 } 2525 2526 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 2527 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2528 2529 if (!psp->hdcp_context.context.mem_context.shared_buf) { 2530 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 2531 if (ret) 2532 return ret; 2533 } 2534 2535 ret = psp_ta_load(psp, &psp->hdcp_context.context); 2536 if (!ret) { 2537 psp->hdcp_context.context.initialized = true; 2538 mutex_init(&psp->hdcp_context.mutex); 2539 } 2540 2541 return ret; 2542 } 2543 2544 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2545 { 2546 /* 2547 * TODO: bypass the loading in sriov for now 2548 */ 2549 if (amdgpu_sriov_vf(psp->adev)) 2550 return 0; 2551 2552 if (!psp->hdcp_context.context.initialized) 2553 return 0; 2554 2555 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 2556 } 2557 2558 static int psp_hdcp_terminate(struct psp_context *psp) 2559 { 2560 int ret; 2561 2562 /* 2563 * TODO: bypass the terminate in sriov for now 2564 */ 2565 if (amdgpu_sriov_vf(psp->adev)) 2566 return 0; 2567 2568 if (!psp->hdcp_context.context.initialized) 2569 return 0; 2570 2571 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 2572 2573 psp->hdcp_context.context.initialized = false; 2574 2575 return ret; 2576 } 2577 // HDCP end 2578 2579 // DTM start 2580 static int psp_dtm_initialize(struct psp_context *psp) 2581 { 2582 int ret; 2583 2584 /* 2585 * TODO: bypass the initialize in sriov for now 2586 */ 2587 if (amdgpu_sriov_vf(psp->adev)) 2588 return 0; 2589 2590 /* bypass dtm initialization if dmu is harvested */ 2591 if (!amdgpu_device_has_display_hardware(psp->adev)) 2592 return 0; 2593 2594 if (!psp->dtm_context.context.bin_desc.size_bytes || 2595 !psp->dtm_context.context.bin_desc.start_addr) { 2596 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 2597 return 0; 2598 } 2599 2600 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 2601 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2602 2603 if (!psp->dtm_context.context.mem_context.shared_buf) { 2604 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 2605 if (ret) 2606 return ret; 2607 } 2608 2609 ret = psp_ta_load(psp, &psp->dtm_context.context); 2610 if (!ret) { 2611 psp->dtm_context.context.initialized = true; 2612 mutex_init(&psp->dtm_context.mutex); 2613 } 2614 2615 return ret; 2616 } 2617 2618 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2619 { 2620 /* 2621 * TODO: bypass the loading in sriov for now 2622 */ 2623 if (amdgpu_sriov_vf(psp->adev)) 2624 return 0; 2625 2626 if (!psp->dtm_context.context.initialized) 2627 return 0; 2628 2629 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 2630 } 2631 2632 static int psp_dtm_terminate(struct psp_context *psp) 2633 { 2634 int ret; 2635 2636 /* 2637 * TODO: bypass the terminate in sriov for now 2638 */ 2639 if (amdgpu_sriov_vf(psp->adev)) 2640 return 0; 2641 2642 if (!psp->dtm_context.context.initialized) 2643 return 0; 2644 2645 ret = psp_ta_unload(psp, &psp->dtm_context.context); 2646 2647 psp->dtm_context.context.initialized = false; 2648 2649 return ret; 2650 } 2651 // DTM end 2652 2653 // RAP start 2654 static int psp_rap_initialize(struct psp_context *psp) 2655 { 2656 int ret; 2657 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 2658 2659 /* 2660 * TODO: bypass the initialize in sriov for now 2661 */ 2662 if (amdgpu_sriov_vf(psp->adev)) 2663 return 0; 2664 2665 if (!psp->rap_context.context.bin_desc.size_bytes || 2666 !psp->rap_context.context.bin_desc.start_addr) { 2667 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 2668 return 0; 2669 } 2670 2671 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 2672 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2673 2674 if (!psp->rap_context.context.mem_context.shared_buf) { 2675 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 2676 if (ret) 2677 return ret; 2678 } 2679 2680 ret = psp_ta_load(psp, &psp->rap_context.context); 2681 if (!ret) { 2682 psp->rap_context.context.initialized = true; 2683 mutex_init(&psp->rap_context.mutex); 2684 } else 2685 return ret; 2686 2687 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 2688 if (ret || status != TA_RAP_STATUS__SUCCESS) { 2689 psp_rap_terminate(psp); 2690 /* free rap shared memory */ 2691 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 2692 2693 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 2694 ret, status); 2695 2696 return ret; 2697 } 2698 2699 return 0; 2700 } 2701 2702 static int psp_rap_terminate(struct psp_context *psp) 2703 { 2704 int ret; 2705 2706 if (!psp->rap_context.context.initialized) 2707 return 0; 2708 2709 ret = psp_ta_unload(psp, &psp->rap_context.context); 2710 2711 psp->rap_context.context.initialized = false; 2712 2713 return ret; 2714 } 2715 2716 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 2717 { 2718 struct ta_rap_shared_memory *rap_cmd; 2719 int ret = 0; 2720 2721 if (!psp->rap_context.context.initialized) 2722 return 0; 2723 2724 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2725 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2726 return -EINVAL; 2727 2728 mutex_lock(&psp->rap_context.mutex); 2729 2730 rap_cmd = (struct ta_rap_shared_memory *) 2731 psp->rap_context.context.mem_context.shared_buf; 2732 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2733 2734 rap_cmd->cmd_id = ta_cmd_id; 2735 rap_cmd->validation_method_id = METHOD_A; 2736 2737 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 2738 if (ret) 2739 goto out_unlock; 2740 2741 if (status) 2742 *status = rap_cmd->rap_status; 2743 2744 out_unlock: 2745 mutex_unlock(&psp->rap_context.mutex); 2746 2747 return ret; 2748 } 2749 // RAP end 2750 2751 /* securedisplay start */ 2752 static int psp_securedisplay_initialize(struct psp_context *psp) 2753 { 2754 int ret; 2755 struct ta_securedisplay_cmd *securedisplay_cmd; 2756 2757 /* 2758 * TODO: bypass the initialize in sriov for now 2759 */ 2760 if (amdgpu_sriov_vf(psp->adev)) 2761 return 0; 2762 2763 /* bypass securedisplay initialization if dmu is harvested */ 2764 if (!amdgpu_device_has_display_hardware(psp->adev)) 2765 return 0; 2766 2767 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 2768 !psp->securedisplay_context.context.bin_desc.start_addr) { 2769 dev_info(psp->adev->dev, 2770 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 2771 return 0; 2772 } 2773 2774 psp->securedisplay_context.context.mem_context.shared_mem_size = 2775 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 2776 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2777 2778 if (!psp->securedisplay_context.context.initialized) { 2779 ret = psp_ta_init_shared_buf(psp, 2780 &psp->securedisplay_context.context.mem_context); 2781 if (ret) 2782 return ret; 2783 } 2784 2785 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 2786 if (!ret && !psp->securedisplay_context.context.resp_status) { 2787 psp->securedisplay_context.context.initialized = true; 2788 mutex_init(&psp->securedisplay_context.mutex); 2789 } else { 2790 /* don't try again */ 2791 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2792 return ret; 2793 } 2794 2795 mutex_lock(&psp->securedisplay_context.mutex); 2796 2797 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2798 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2799 2800 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2801 2802 mutex_unlock(&psp->securedisplay_context.mutex); 2803 2804 if (ret) { 2805 psp_securedisplay_terminate(psp); 2806 /* free securedisplay shared memory */ 2807 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2808 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2809 return -EINVAL; 2810 } 2811 2812 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2813 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2814 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2815 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2816 /* don't try again */ 2817 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2818 } 2819 2820 return 0; 2821 } 2822 2823 static int psp_securedisplay_terminate(struct psp_context *psp) 2824 { 2825 int ret; 2826 2827 /* 2828 * TODO:bypass the terminate in sriov for now 2829 */ 2830 if (amdgpu_sriov_vf(psp->adev)) 2831 return 0; 2832 2833 if (!psp->securedisplay_context.context.initialized) 2834 return 0; 2835 2836 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 2837 2838 psp->securedisplay_context.context.initialized = false; 2839 2840 return ret; 2841 } 2842 2843 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2844 { 2845 int ret; 2846 2847 if (!psp->securedisplay_context.context.initialized) 2848 return -EINVAL; 2849 2850 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2851 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 2852 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 2853 return -EINVAL; 2854 2855 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2856 2857 return ret; 2858 } 2859 /* SECUREDISPLAY end */ 2860 2861 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 2862 { 2863 struct psp_context *psp = &adev->psp; 2864 int ret = 0; 2865 2866 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 2867 ret = psp->funcs->wait_for_bootloader(psp); 2868 2869 return ret; 2870 } 2871 2872 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 2873 { 2874 if (psp->funcs && 2875 psp->funcs->get_ras_capability) { 2876 return psp->funcs->get_ras_capability(psp); 2877 } else { 2878 return false; 2879 } 2880 } 2881 2882 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 2883 { 2884 struct psp_context *psp = &adev->psp; 2885 2886 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 2887 return false; 2888 2889 if (psp->funcs && psp->funcs->is_reload_needed) 2890 return psp->funcs->is_reload_needed(psp); 2891 2892 return false; 2893 } 2894 2895 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 2896 { 2897 struct psp_context *psp = &adev->psp; 2898 2899 if (psp->cmd_buf_bo && psp->cmd_buf_mem) { 2900 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 2901 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 2902 psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo); 2903 } 2904 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 2905 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 2906 } 2907 2908 static int psp_hw_start(struct psp_context *psp) 2909 { 2910 struct amdgpu_device *adev = psp->adev; 2911 int ret; 2912 2913 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 2914 psp_update_gpu_addresses(adev); 2915 2916 if (!amdgpu_sriov_vf(adev)) { 2917 if ((is_psp_fw_valid(psp->kdb)) && 2918 (psp->funcs->bootloader_load_kdb != NULL)) { 2919 ret = psp_bootloader_load_kdb(psp); 2920 if (ret) { 2921 dev_err(adev->dev, "PSP load kdb failed!\n"); 2922 return ret; 2923 } 2924 } 2925 2926 if ((is_psp_fw_valid(psp->spl)) && 2927 (psp->funcs->bootloader_load_spl != NULL)) { 2928 ret = psp_bootloader_load_spl(psp); 2929 if (ret) { 2930 dev_err(adev->dev, "PSP load spl failed!\n"); 2931 return ret; 2932 } 2933 } 2934 2935 if ((is_psp_fw_valid(psp->sys)) && 2936 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2937 ret = psp_bootloader_load_sysdrv(psp); 2938 if (ret) { 2939 dev_err(adev->dev, "PSP load sys drv failed!\n"); 2940 return ret; 2941 } 2942 } 2943 2944 if ((is_psp_fw_valid(psp->soc_drv)) && 2945 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2946 ret = psp_bootloader_load_soc_drv(psp); 2947 if (ret) { 2948 dev_err(adev->dev, "PSP load soc drv failed!\n"); 2949 return ret; 2950 } 2951 } 2952 2953 if ((is_psp_fw_valid(psp->intf_drv)) && 2954 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2955 ret = psp_bootloader_load_intf_drv(psp); 2956 if (ret) { 2957 dev_err(adev->dev, "PSP load intf drv failed!\n"); 2958 return ret; 2959 } 2960 } 2961 2962 if ((is_psp_fw_valid(psp->dbg_drv)) && 2963 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2964 ret = psp_bootloader_load_dbg_drv(psp); 2965 if (ret) { 2966 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 2967 return ret; 2968 } 2969 } 2970 2971 if ((is_psp_fw_valid(psp->ras_drv)) && 2972 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2973 ret = psp_bootloader_load_ras_drv(psp); 2974 if (ret) { 2975 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 2976 return ret; 2977 } 2978 } 2979 2980 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 2981 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 2982 ret = psp_bootloader_load_ipkeymgr_drv(psp); 2983 if (ret) { 2984 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 2985 return ret; 2986 } 2987 } 2988 2989 if ((is_psp_fw_valid(psp->spdm_drv)) && 2990 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 2991 ret = psp_bootloader_load_spdm_drv(psp); 2992 if (ret) { 2993 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 2994 return ret; 2995 } 2996 } 2997 2998 if ((is_psp_fw_valid(psp->sos)) && 2999 (psp->funcs->bootloader_load_sos != NULL)) { 3000 ret = psp_bootloader_load_sos(psp); 3001 if (ret) { 3002 dev_err(adev->dev, "PSP load sos failed!\n"); 3003 return ret; 3004 } 3005 } 3006 } 3007 3008 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 3009 if (ret) { 3010 dev_err(adev->dev, "PSP create ring failed!\n"); 3011 return ret; 3012 } 3013 3014 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3015 ret = psp_update_fw_reservation(psp); 3016 if (ret) { 3017 dev_err(adev->dev, "update fw reservation failed!\n"); 3018 return ret; 3019 } 3020 } 3021 3022 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 3023 goto skip_pin_bo; 3024 3025 if (!psp->boot_time_tmr || psp->autoload_supported) { 3026 ret = psp_tmr_init(psp); 3027 if (ret) { 3028 dev_err(adev->dev, "PSP tmr init failed!\n"); 3029 return ret; 3030 } 3031 } 3032 3033 skip_pin_bo: 3034 /* 3035 * For ASICs with DF Cstate management centralized 3036 * to PMFW, TMR setup should be performed after PMFW 3037 * loaded and before other non-psp firmware loaded. 3038 */ 3039 if (psp->pmfw_centralized_cstate_management) { 3040 ret = psp_load_smu_fw(psp); 3041 if (ret) 3042 return ret; 3043 } 3044 3045 ret = psp_tmr_load(psp); 3046 if (ret) { 3047 dev_err(adev->dev, "PSP load tmr failed!\n"); 3048 return ret; 3049 } 3050 3051 return 0; 3052 } 3053 3054 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3055 enum psp_gfx_fw_type *type) 3056 { 3057 switch (ucode->ucode_id) { 3058 case AMDGPU_UCODE_ID_CAP: 3059 *type = GFX_FW_TYPE_CAP; 3060 break; 3061 case AMDGPU_UCODE_ID_SDMA0: 3062 *type = GFX_FW_TYPE_SDMA0; 3063 break; 3064 case AMDGPU_UCODE_ID_SDMA1: 3065 *type = GFX_FW_TYPE_SDMA1; 3066 break; 3067 case AMDGPU_UCODE_ID_SDMA2: 3068 *type = GFX_FW_TYPE_SDMA2; 3069 break; 3070 case AMDGPU_UCODE_ID_SDMA3: 3071 *type = GFX_FW_TYPE_SDMA3; 3072 break; 3073 case AMDGPU_UCODE_ID_SDMA4: 3074 *type = GFX_FW_TYPE_SDMA4; 3075 break; 3076 case AMDGPU_UCODE_ID_SDMA5: 3077 *type = GFX_FW_TYPE_SDMA5; 3078 break; 3079 case AMDGPU_UCODE_ID_SDMA6: 3080 *type = GFX_FW_TYPE_SDMA6; 3081 break; 3082 case AMDGPU_UCODE_ID_SDMA7: 3083 *type = GFX_FW_TYPE_SDMA7; 3084 break; 3085 case AMDGPU_UCODE_ID_CP_MES: 3086 *type = GFX_FW_TYPE_CP_MES; 3087 break; 3088 case AMDGPU_UCODE_ID_CP_MES_DATA: 3089 *type = GFX_FW_TYPE_MES_STACK; 3090 break; 3091 case AMDGPU_UCODE_ID_CP_MES1: 3092 *type = GFX_FW_TYPE_CP_MES_KIQ; 3093 break; 3094 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3095 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3096 break; 3097 case AMDGPU_UCODE_ID_CP_CE: 3098 *type = GFX_FW_TYPE_CP_CE; 3099 break; 3100 case AMDGPU_UCODE_ID_CP_PFP: 3101 *type = GFX_FW_TYPE_CP_PFP; 3102 break; 3103 case AMDGPU_UCODE_ID_CP_ME: 3104 *type = GFX_FW_TYPE_CP_ME; 3105 break; 3106 case AMDGPU_UCODE_ID_CP_MEC1: 3107 *type = GFX_FW_TYPE_CP_MEC; 3108 break; 3109 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3110 *type = GFX_FW_TYPE_CP_MEC_ME1; 3111 break; 3112 case AMDGPU_UCODE_ID_CP_MEC2: 3113 *type = GFX_FW_TYPE_CP_MEC; 3114 break; 3115 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3116 *type = GFX_FW_TYPE_CP_MEC_ME2; 3117 break; 3118 case AMDGPU_UCODE_ID_RLC_P: 3119 *type = GFX_FW_TYPE_RLC_P; 3120 break; 3121 case AMDGPU_UCODE_ID_RLC_V: 3122 *type = GFX_FW_TYPE_RLC_V; 3123 break; 3124 case AMDGPU_UCODE_ID_RLC_G: 3125 *type = GFX_FW_TYPE_RLC_G; 3126 break; 3127 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3128 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3129 break; 3130 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3131 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3132 break; 3133 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3134 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3135 break; 3136 case AMDGPU_UCODE_ID_RLC_IRAM: 3137 *type = GFX_FW_TYPE_RLC_IRAM; 3138 break; 3139 case AMDGPU_UCODE_ID_RLC_DRAM: 3140 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3141 break; 3142 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3143 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3144 break; 3145 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3146 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3147 break; 3148 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3149 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3150 break; 3151 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3152 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3153 break; 3154 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3155 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3156 break; 3157 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3158 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3159 break; 3160 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3161 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3162 break; 3163 case AMDGPU_UCODE_ID_SMC: 3164 *type = GFX_FW_TYPE_SMU; 3165 break; 3166 case AMDGPU_UCODE_ID_PPTABLE: 3167 *type = GFX_FW_TYPE_PPTABLE; 3168 break; 3169 case AMDGPU_UCODE_ID_UVD: 3170 *type = GFX_FW_TYPE_UVD; 3171 break; 3172 case AMDGPU_UCODE_ID_UVD1: 3173 *type = GFX_FW_TYPE_UVD1; 3174 break; 3175 case AMDGPU_UCODE_ID_VCE: 3176 *type = GFX_FW_TYPE_VCE; 3177 break; 3178 case AMDGPU_UCODE_ID_VCN: 3179 *type = GFX_FW_TYPE_VCN; 3180 break; 3181 case AMDGPU_UCODE_ID_VCN1: 3182 *type = GFX_FW_TYPE_VCN1; 3183 break; 3184 case AMDGPU_UCODE_ID_DMCU_ERAM: 3185 *type = GFX_FW_TYPE_DMCU_ERAM; 3186 break; 3187 case AMDGPU_UCODE_ID_DMCU_INTV: 3188 *type = GFX_FW_TYPE_DMCU_ISR; 3189 break; 3190 case AMDGPU_UCODE_ID_VCN0_RAM: 3191 *type = GFX_FW_TYPE_VCN0_RAM; 3192 break; 3193 case AMDGPU_UCODE_ID_VCN1_RAM: 3194 *type = GFX_FW_TYPE_VCN1_RAM; 3195 break; 3196 case AMDGPU_UCODE_ID_DMCUB: 3197 *type = GFX_FW_TYPE_DMUB; 3198 break; 3199 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3200 case AMDGPU_UCODE_ID_SDMA_RS64: 3201 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3202 break; 3203 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3204 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3205 break; 3206 case AMDGPU_UCODE_ID_IMU_I: 3207 *type = GFX_FW_TYPE_IMU_I; 3208 break; 3209 case AMDGPU_UCODE_ID_IMU_D: 3210 *type = GFX_FW_TYPE_IMU_D; 3211 break; 3212 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3213 *type = GFX_FW_TYPE_RS64_PFP; 3214 break; 3215 case AMDGPU_UCODE_ID_CP_RS64_ME: 3216 *type = GFX_FW_TYPE_RS64_ME; 3217 break; 3218 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3219 *type = GFX_FW_TYPE_RS64_MEC; 3220 break; 3221 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3222 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3223 break; 3224 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3225 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3226 break; 3227 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3228 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3229 break; 3230 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3231 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3232 break; 3233 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3234 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3235 break; 3236 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3237 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3238 break; 3239 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3240 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3241 break; 3242 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3243 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3244 break; 3245 case AMDGPU_UCODE_ID_VPE_CTX: 3246 *type = GFX_FW_TYPE_VPEC_FW1; 3247 break; 3248 case AMDGPU_UCODE_ID_VPE_CTL: 3249 *type = GFX_FW_TYPE_VPEC_FW2; 3250 break; 3251 case AMDGPU_UCODE_ID_VPE: 3252 *type = GFX_FW_TYPE_VPE; 3253 break; 3254 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3255 *type = GFX_FW_TYPE_UMSCH_UCODE; 3256 break; 3257 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3258 *type = GFX_FW_TYPE_UMSCH_DATA; 3259 break; 3260 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3261 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3262 break; 3263 case AMDGPU_UCODE_ID_P2S_TABLE: 3264 *type = GFX_FW_TYPE_P2S_TABLE; 3265 break; 3266 case AMDGPU_UCODE_ID_JPEG_RAM: 3267 *type = GFX_FW_TYPE_JPEG_RAM; 3268 break; 3269 case AMDGPU_UCODE_ID_ISP: 3270 *type = GFX_FW_TYPE_ISP; 3271 break; 3272 case AMDGPU_UCODE_ID_MAXIMUM: 3273 default: 3274 return -EINVAL; 3275 } 3276 3277 return 0; 3278 } 3279 3280 static void psp_print_fw_hdr(struct psp_context *psp, 3281 struct amdgpu_firmware_info *ucode) 3282 { 3283 struct amdgpu_device *adev = psp->adev; 3284 struct common_firmware_header *hdr; 3285 3286 switch (ucode->ucode_id) { 3287 case AMDGPU_UCODE_ID_SDMA0: 3288 case AMDGPU_UCODE_ID_SDMA1: 3289 case AMDGPU_UCODE_ID_SDMA2: 3290 case AMDGPU_UCODE_ID_SDMA3: 3291 case AMDGPU_UCODE_ID_SDMA4: 3292 case AMDGPU_UCODE_ID_SDMA5: 3293 case AMDGPU_UCODE_ID_SDMA6: 3294 case AMDGPU_UCODE_ID_SDMA7: 3295 hdr = (struct common_firmware_header *) 3296 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3297 amdgpu_ucode_print_sdma_hdr(hdr); 3298 break; 3299 case AMDGPU_UCODE_ID_CP_CE: 3300 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3301 amdgpu_ucode_print_gfx_hdr(hdr); 3302 break; 3303 case AMDGPU_UCODE_ID_CP_PFP: 3304 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3305 amdgpu_ucode_print_gfx_hdr(hdr); 3306 break; 3307 case AMDGPU_UCODE_ID_CP_ME: 3308 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3309 amdgpu_ucode_print_gfx_hdr(hdr); 3310 break; 3311 case AMDGPU_UCODE_ID_CP_MEC1: 3312 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3313 amdgpu_ucode_print_gfx_hdr(hdr); 3314 break; 3315 case AMDGPU_UCODE_ID_RLC_G: 3316 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3317 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3318 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3319 amdgpu_ucode_print_rlc_hdr(hdr); 3320 break; 3321 case AMDGPU_UCODE_ID_SMC: 3322 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3323 amdgpu_ucode_print_smc_hdr(hdr); 3324 break; 3325 default: 3326 break; 3327 } 3328 } 3329 3330 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3331 struct amdgpu_firmware_info *ucode, 3332 struct psp_gfx_cmd_resp *cmd) 3333 { 3334 int ret; 3335 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3336 3337 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3338 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3339 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3340 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3341 3342 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3343 if (ret) 3344 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3345 return ret; 3346 } 3347 3348 int psp_execute_ip_fw_load(struct psp_context *psp, 3349 struct amdgpu_firmware_info *ucode) 3350 { 3351 int ret = 0; 3352 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3353 3354 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3355 if (!ret) { 3356 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3357 psp->fence_buf_mc_addr); 3358 } 3359 3360 release_psp_cmd_buf(psp); 3361 3362 return ret; 3363 } 3364 3365 static int psp_load_p2s_table(struct psp_context *psp) 3366 { 3367 int ret; 3368 struct amdgpu_device *adev = psp->adev; 3369 struct amdgpu_firmware_info *ucode = 3370 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3371 3372 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3373 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3374 return 0; 3375 3376 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3377 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3378 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3379 0x0036003C; 3380 if (psp->sos.fw_version < supp_vers) 3381 return 0; 3382 } 3383 3384 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3385 return 0; 3386 3387 ret = psp_execute_ip_fw_load(psp, ucode); 3388 3389 return ret; 3390 } 3391 3392 static int psp_load_smu_fw(struct psp_context *psp) 3393 { 3394 int ret; 3395 struct amdgpu_device *adev = psp->adev; 3396 struct amdgpu_firmware_info *ucode = 3397 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3398 struct amdgpu_ras *ras = psp->ras_context.ras; 3399 3400 /* 3401 * Skip SMU FW reloading in case of using BACO for runpm only, 3402 * as SMU is always alive. 3403 */ 3404 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3405 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3406 return 0; 3407 3408 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3409 return 0; 3410 3411 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3412 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3413 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3414 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3415 if (ret) 3416 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3417 } 3418 3419 ret = psp_execute_ip_fw_load(psp, ucode); 3420 3421 if (ret) 3422 dev_err(adev->dev, "PSP load smu failed!\n"); 3423 3424 return ret; 3425 } 3426 3427 static bool fw_load_skip_check(struct psp_context *psp, 3428 struct amdgpu_firmware_info *ucode) 3429 { 3430 if (!ucode->fw || !ucode->ucode_size) 3431 return true; 3432 3433 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3434 return true; 3435 3436 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3437 (psp_smu_reload_quirk(psp) || 3438 psp->autoload_supported || 3439 psp->pmfw_centralized_cstate_management)) 3440 return true; 3441 3442 if (amdgpu_sriov_vf(psp->adev) && 3443 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3444 return true; 3445 3446 if (psp->autoload_supported && 3447 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3448 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3449 /* skip mec JT when autoload is enabled */ 3450 return true; 3451 3452 return false; 3453 } 3454 3455 int psp_load_fw_list(struct psp_context *psp, 3456 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3457 { 3458 int ret = 0, i; 3459 struct amdgpu_firmware_info *ucode; 3460 3461 for (i = 0; i < ucode_count; ++i) { 3462 ucode = ucode_list[i]; 3463 psp_print_fw_hdr(psp, ucode); 3464 ret = psp_execute_ip_fw_load(psp, ucode); 3465 if (ret) 3466 return ret; 3467 } 3468 return ret; 3469 } 3470 3471 static int psp_load_non_psp_fw(struct psp_context *psp) 3472 { 3473 int i, ret; 3474 struct amdgpu_firmware_info *ucode; 3475 struct amdgpu_device *adev = psp->adev; 3476 3477 if (psp->autoload_supported && 3478 !psp->pmfw_centralized_cstate_management) { 3479 ret = psp_load_smu_fw(psp); 3480 if (ret) 3481 return ret; 3482 } 3483 3484 /* Load P2S table first if it's available */ 3485 psp_load_p2s_table(psp); 3486 3487 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3488 ucode = &adev->firmware.ucode[i]; 3489 3490 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3491 !fw_load_skip_check(psp, ucode)) { 3492 ret = psp_load_smu_fw(psp); 3493 if (ret) 3494 return ret; 3495 continue; 3496 } 3497 3498 if (fw_load_skip_check(psp, ucode)) 3499 continue; 3500 3501 if (psp->autoload_supported && 3502 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3503 IP_VERSION(11, 0, 7) || 3504 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3505 IP_VERSION(11, 0, 11) || 3506 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3507 IP_VERSION(11, 0, 12) || 3508 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3509 IP_VERSION(15, 0, 0) || 3510 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3511 IP_VERSION(15, 0, 5) || 3512 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3513 IP_VERSION(15, 0, 8) || 3514 amdgpu_ip_version(adev, MP0_HWIP, 0) == 3515 IP_VERSION(15, 0, 9)) && 3516 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 3517 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 3518 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 3519 /* PSP only receive one SDMA fw for sienna_cichlid, 3520 * as all four sdma fw are same 3521 */ 3522 continue; 3523 3524 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 3525 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3526 IP_VERSION(15, 0, 8) && 3527 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 3528 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 3529 continue; 3530 3531 psp_print_fw_hdr(psp, ucode); 3532 3533 ret = psp_execute_ip_fw_load(psp, ucode); 3534 if (ret) 3535 return ret; 3536 3537 /* Start rlc autoload after psp received all the gfx firmware */ 3538 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 3539 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 3540 ret = psp_rlc_autoload_start(psp); 3541 if (ret) { 3542 dev_err(adev->dev, "Failed to start rlc autoload\n"); 3543 return ret; 3544 } 3545 } 3546 } 3547 3548 return 0; 3549 } 3550 3551 static int psp_load_fw(struct amdgpu_device *adev) 3552 { 3553 int ret; 3554 struct psp_context *psp = &adev->psp; 3555 3556 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3557 /* should not destroy ring, only stop */ 3558 psp_ring_stop(psp, PSP_RING_TYPE__KM); 3559 } else { 3560 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 3561 3562 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 3563 if (ret) { 3564 dev_err(adev->dev, "PSP ring init failed!\n"); 3565 goto failed; 3566 } 3567 } 3568 3569 ret = psp_hw_start(psp); 3570 if (ret) 3571 goto failed; 3572 3573 ret = psp_load_non_psp_fw(psp); 3574 if (ret) 3575 goto failed1; 3576 3577 ret = psp_asd_initialize(psp); 3578 if (ret) { 3579 dev_err(adev->dev, "PSP load asd failed!\n"); 3580 goto failed1; 3581 } 3582 3583 ret = psp_rl_load(adev); 3584 if (ret) { 3585 dev_err(adev->dev, "PSP load RL failed!\n"); 3586 goto failed1; 3587 } 3588 3589 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 3590 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3591 ret = psp_xgmi_initialize(psp, false, true); 3592 /* Warning the XGMI seesion initialize failure 3593 * Instead of stop driver initialization 3594 */ 3595 if (ret) 3596 dev_err(psp->adev->dev, 3597 "XGMI: Failed to initialize XGMI session\n"); 3598 } 3599 } 3600 3601 if (psp->ta_fw) { 3602 ret = psp_ras_initialize(psp); 3603 if (ret) 3604 dev_err(psp->adev->dev, 3605 "RAS: Failed to initialize RAS\n"); 3606 3607 ret = psp_hdcp_initialize(psp); 3608 if (ret) 3609 dev_err(psp->adev->dev, 3610 "HDCP: Failed to initialize HDCP\n"); 3611 3612 ret = psp_dtm_initialize(psp); 3613 if (ret) 3614 dev_err(psp->adev->dev, 3615 "DTM: Failed to initialize DTM\n"); 3616 3617 ret = psp_rap_initialize(psp); 3618 if (ret) 3619 dev_err(psp->adev->dev, 3620 "RAP: Failed to initialize RAP\n"); 3621 3622 ret = psp_securedisplay_initialize(psp); 3623 if (ret) 3624 dev_err(psp->adev->dev, 3625 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3626 } 3627 3628 return 0; 3629 3630 failed1: 3631 psp_free_shared_bufs(psp); 3632 failed: 3633 /* 3634 * all cleanup jobs (xgmi terminate, ras terminate, 3635 * ring destroy, cmd/fence/fw buffers destory, 3636 * psp->cmd destory) are delayed to psp_hw_fini 3637 */ 3638 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3639 return ret; 3640 } 3641 3642 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 3643 { 3644 int ret; 3645 struct amdgpu_device *adev = ip_block->adev; 3646 3647 mutex_lock(&adev->firmware.mutex); 3648 3649 ret = amdgpu_ucode_init_bo(adev); 3650 if (ret) 3651 goto failed; 3652 3653 ret = psp_load_fw(adev); 3654 if (ret) { 3655 dev_err(adev->dev, "PSP firmware loading failed\n"); 3656 goto failed; 3657 } 3658 3659 mutex_unlock(&adev->firmware.mutex); 3660 return 0; 3661 3662 failed: 3663 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 3664 mutex_unlock(&adev->firmware.mutex); 3665 return -EINVAL; 3666 } 3667 3668 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 3669 { 3670 struct amdgpu_device *adev = ip_block->adev; 3671 struct psp_context *psp = &adev->psp; 3672 3673 if (psp->ta_fw) { 3674 psp_ras_terminate(psp); 3675 psp_securedisplay_terminate(psp); 3676 psp_rap_terminate(psp); 3677 psp_dtm_terminate(psp); 3678 psp_hdcp_terminate(psp); 3679 3680 if (adev->gmc.xgmi.num_physical_nodes > 1) 3681 psp_xgmi_terminate(psp); 3682 } 3683 3684 psp_asd_terminate(psp); 3685 psp_tmr_terminate(psp); 3686 3687 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 3688 3689 return 0; 3690 } 3691 3692 static int psp_suspend(struct amdgpu_ip_block *ip_block) 3693 { 3694 int ret = 0; 3695 struct amdgpu_device *adev = ip_block->adev; 3696 struct psp_context *psp = &adev->psp; 3697 3698 if (adev->gmc.xgmi.num_physical_nodes > 1 && 3699 psp->xgmi_context.context.initialized) { 3700 ret = psp_xgmi_terminate(psp); 3701 if (ret) { 3702 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 3703 goto out; 3704 } 3705 } 3706 3707 if (psp->ta_fw) { 3708 ret = psp_ras_terminate(psp); 3709 if (ret) { 3710 dev_err(adev->dev, "Failed to terminate ras ta\n"); 3711 goto out; 3712 } 3713 ret = psp_hdcp_terminate(psp); 3714 if (ret) { 3715 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 3716 goto out; 3717 } 3718 ret = psp_dtm_terminate(psp); 3719 if (ret) { 3720 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 3721 goto out; 3722 } 3723 ret = psp_rap_terminate(psp); 3724 if (ret) { 3725 dev_err(adev->dev, "Failed to terminate rap ta\n"); 3726 goto out; 3727 } 3728 ret = psp_securedisplay_terminate(psp); 3729 if (ret) { 3730 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 3731 goto out; 3732 } 3733 } 3734 3735 ret = psp_asd_terminate(psp); 3736 if (ret) { 3737 dev_err(adev->dev, "Failed to terminate asd\n"); 3738 goto out; 3739 } 3740 3741 ret = psp_tmr_terminate(psp); 3742 if (ret) { 3743 dev_err(adev->dev, "Failed to terminate tmr\n"); 3744 goto out; 3745 } 3746 3747 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 3748 if (ret) 3749 dev_err(adev->dev, "PSP ring stop failed\n"); 3750 3751 out: 3752 return ret; 3753 } 3754 3755 static int psp_resume(struct amdgpu_ip_block *ip_block) 3756 { 3757 int ret; 3758 struct amdgpu_device *adev = ip_block->adev; 3759 struct psp_context *psp = &adev->psp; 3760 3761 dev_info(adev->dev, "PSP is resuming...\n"); 3762 3763 if (psp->mem_train_ctx.enable_mem_training) { 3764 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 3765 if (ret) { 3766 dev_err(adev->dev, "Failed to process memory training!\n"); 3767 return ret; 3768 } 3769 } 3770 3771 mutex_lock(&adev->firmware.mutex); 3772 3773 ret = amdgpu_ucode_init_bo(adev); 3774 if (ret) 3775 goto failed; 3776 3777 ret = psp_hw_start(psp); 3778 if (ret) 3779 goto failed; 3780 3781 ret = psp_load_non_psp_fw(psp); 3782 if (ret) 3783 goto failed; 3784 3785 ret = psp_asd_initialize(psp); 3786 if (ret) { 3787 dev_err(adev->dev, "PSP load asd failed!\n"); 3788 goto failed; 3789 } 3790 3791 ret = psp_rl_load(adev); 3792 if (ret) { 3793 dev_err(adev->dev, "PSP load RL failed!\n"); 3794 goto failed; 3795 } 3796 3797 if (adev->gmc.xgmi.num_physical_nodes > 1) { 3798 ret = psp_xgmi_initialize(psp, false, true); 3799 /* Warning the XGMI seesion initialize failure 3800 * Instead of stop driver initialization 3801 */ 3802 if (ret) 3803 dev_err(psp->adev->dev, 3804 "XGMI: Failed to initialize XGMI session\n"); 3805 } 3806 3807 if (psp->ta_fw) { 3808 ret = psp_ras_initialize(psp); 3809 if (ret) 3810 dev_err(psp->adev->dev, 3811 "RAS: Failed to initialize RAS\n"); 3812 3813 ret = psp_hdcp_initialize(psp); 3814 if (ret) 3815 dev_err(psp->adev->dev, 3816 "HDCP: Failed to initialize HDCP\n"); 3817 3818 ret = psp_dtm_initialize(psp); 3819 if (ret) 3820 dev_err(psp->adev->dev, 3821 "DTM: Failed to initialize DTM\n"); 3822 3823 ret = psp_rap_initialize(psp); 3824 if (ret) 3825 dev_err(psp->adev->dev, 3826 "RAP: Failed to initialize RAP\n"); 3827 3828 ret = psp_securedisplay_initialize(psp); 3829 if (ret) 3830 dev_err(psp->adev->dev, 3831 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 3832 } 3833 3834 mutex_unlock(&adev->firmware.mutex); 3835 3836 return 0; 3837 3838 failed: 3839 dev_err(adev->dev, "PSP resume failed\n"); 3840 mutex_unlock(&adev->firmware.mutex); 3841 return ret; 3842 } 3843 3844 int psp_gpu_reset(struct amdgpu_device *adev) 3845 { 3846 int ret; 3847 3848 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 3849 return 0; 3850 3851 mutex_lock(&adev->psp.mutex); 3852 ret = psp_mode1_reset(&adev->psp); 3853 mutex_unlock(&adev->psp.mutex); 3854 3855 return ret; 3856 } 3857 3858 int psp_rlc_autoload_start(struct psp_context *psp) 3859 { 3860 int ret; 3861 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3862 3863 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 3864 3865 ret = psp_cmd_submit_buf(psp, NULL, cmd, 3866 psp->fence_buf_mc_addr); 3867 3868 release_psp_cmd_buf(psp); 3869 3870 return ret; 3871 } 3872 3873 int psp_ring_cmd_submit(struct psp_context *psp, 3874 uint64_t cmd_buf_mc_addr, 3875 uint64_t fence_mc_addr, 3876 int index) 3877 { 3878 unsigned int psp_write_ptr_reg = 0; 3879 struct psp_gfx_rb_frame *write_frame; 3880 struct psp_ring *ring = &psp->km_ring; 3881 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3882 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3883 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3884 struct amdgpu_device *adev = psp->adev; 3885 uint32_t ring_size_dw = ring->ring_size / 4; 3886 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3887 3888 /* KM (GPCOM) prepare write pointer */ 3889 psp_write_ptr_reg = psp_ring_get_wptr(psp); 3890 3891 /* Update KM RB frame pointer to new frame */ 3892 /* write_frame ptr increments by size of rb_frame in bytes */ 3893 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3894 if ((psp_write_ptr_reg % ring_size_dw) == 0) 3895 write_frame = ring_buffer_start; 3896 else 3897 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3898 /* Check invalid write_frame ptr address */ 3899 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3900 dev_err(adev->dev, 3901 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3902 ring_buffer_start, ring_buffer_end, write_frame); 3903 dev_err(adev->dev, 3904 "write_frame is pointing to address out of bounds\n"); 3905 return -EINVAL; 3906 } 3907 3908 /* Initialize KM RB frame */ 3909 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3910 3911 /* Update KM RB frame */ 3912 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3913 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3914 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3915 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3916 write_frame->fence_value = index; 3917 amdgpu_device_flush_hdp(adev, NULL); 3918 3919 /* Update the write Pointer in DWORDs */ 3920 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3921 psp_ring_set_wptr(psp, psp_write_ptr_reg); 3922 return 0; 3923 } 3924 3925 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 3926 { 3927 struct amdgpu_device *adev = psp->adev; 3928 const struct psp_firmware_header_v1_0 *asd_hdr; 3929 int err = 0; 3930 3931 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED, 3932 "amdgpu/%s_asd.bin", chip_name); 3933 if (err) 3934 goto out; 3935 3936 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3937 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3938 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3939 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3940 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 3941 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3942 return 0; 3943 out: 3944 amdgpu_ucode_release(&adev->psp.asd_fw); 3945 return err; 3946 } 3947 3948 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 3949 { 3950 struct amdgpu_device *adev = psp->adev; 3951 const struct psp_firmware_header_v1_0 *toc_hdr; 3952 int err = 0; 3953 3954 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 3955 adev->rev_id == 0) 3956 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3957 "amdgpu/%s_toc_1.bin", chip_name); 3958 else 3959 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED, 3960 "amdgpu/%s_toc.bin", chip_name); 3961 if (err) 3962 goto out; 3963 3964 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3965 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3966 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3967 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3968 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3969 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3970 return 0; 3971 out: 3972 amdgpu_ucode_release(&adev->psp.toc_fw); 3973 return err; 3974 } 3975 3976 static int parse_sos_bin_descriptor(struct psp_context *psp, 3977 const struct psp_fw_bin_desc *desc, 3978 const struct psp_firmware_header_v2_0 *sos_hdr) 3979 { 3980 uint8_t *ucode_start_addr = NULL; 3981 3982 if (!psp || !desc || !sos_hdr) 3983 return -EINVAL; 3984 3985 ucode_start_addr = (uint8_t *)sos_hdr + 3986 le32_to_cpu(desc->offset_bytes) + 3987 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3988 3989 switch (desc->fw_type) { 3990 case PSP_FW_TYPE_PSP_SOS: 3991 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3992 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3993 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3994 psp->sos.start_addr = ucode_start_addr; 3995 break; 3996 case PSP_FW_TYPE_PSP_SYS_DRV: 3997 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3998 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3999 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 4000 psp->sys.start_addr = ucode_start_addr; 4001 break; 4002 case PSP_FW_TYPE_PSP_KDB: 4003 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 4004 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 4005 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 4006 psp->kdb.start_addr = ucode_start_addr; 4007 break; 4008 case PSP_FW_TYPE_PSP_TOC: 4009 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 4010 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 4011 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 4012 psp->toc.start_addr = ucode_start_addr; 4013 break; 4014 case PSP_FW_TYPE_PSP_SPL: 4015 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 4016 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 4017 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 4018 psp->spl.start_addr = ucode_start_addr; 4019 break; 4020 case PSP_FW_TYPE_PSP_RL: 4021 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 4022 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 4023 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 4024 psp->rl.start_addr = ucode_start_addr; 4025 break; 4026 case PSP_FW_TYPE_PSP_SOC_DRV: 4027 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 4028 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 4029 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4030 psp->soc_drv.start_addr = ucode_start_addr; 4031 break; 4032 case PSP_FW_TYPE_PSP_INTF_DRV: 4033 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4034 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4035 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4036 psp->intf_drv.start_addr = ucode_start_addr; 4037 break; 4038 case PSP_FW_TYPE_PSP_DBG_DRV: 4039 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4040 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4041 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4042 psp->dbg_drv.start_addr = ucode_start_addr; 4043 break; 4044 case PSP_FW_TYPE_PSP_RAS_DRV: 4045 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4046 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4047 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4048 psp->ras_drv.start_addr = ucode_start_addr; 4049 break; 4050 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4051 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4052 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4053 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4054 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4055 break; 4056 case PSP_FW_TYPE_PSP_SPDM_DRV: 4057 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4058 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4059 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4060 psp->spdm_drv.start_addr = ucode_start_addr; 4061 break; 4062 default: 4063 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4064 break; 4065 } 4066 4067 return 0; 4068 } 4069 4070 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4071 { 4072 const struct psp_firmware_header_v1_0 *sos_hdr; 4073 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4074 uint8_t *ucode_array_start_addr; 4075 4076 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4077 ucode_array_start_addr = (uint8_t *)sos_hdr + 4078 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4079 4080 if (adev->gmc.xgmi.connected_to_cpu || 4081 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4082 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4083 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4084 4085 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4086 adev->psp.sys.start_addr = ucode_array_start_addr; 4087 4088 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4089 adev->psp.sos.start_addr = ucode_array_start_addr + 4090 le32_to_cpu(sos_hdr->sos.offset_bytes); 4091 } else { 4092 /* Load alternate PSP SOS FW */ 4093 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4094 4095 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4096 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4097 4098 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4099 adev->psp.sys.start_addr = ucode_array_start_addr + 4100 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4101 4102 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4103 adev->psp.sos.start_addr = ucode_array_start_addr + 4104 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4105 } 4106 4107 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4108 dev_warn(adev->dev, "PSP SOS FW not available"); 4109 return -EINVAL; 4110 } 4111 4112 return 0; 4113 } 4114 4115 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4116 { 4117 struct amdgpu_device *adev = psp->adev; 4118 const struct psp_firmware_header_v1_0 *sos_hdr; 4119 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4120 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4121 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4122 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4123 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4124 int fw_index, fw_bin_count, start_index = 0; 4125 const struct psp_fw_bin_desc *fw_bin; 4126 uint8_t *ucode_array_start_addr; 4127 int err = 0; 4128 4129 if (amdgpu_is_kicker_fw(adev)) 4130 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4131 "amdgpu/%s_sos_kicker.bin", chip_name); 4132 else 4133 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4134 "amdgpu/%s_sos.bin", chip_name); 4135 if (err) 4136 goto out; 4137 4138 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4139 ucode_array_start_addr = (uint8_t *)sos_hdr + 4140 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4141 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4142 4143 switch (sos_hdr->header.header_version_major) { 4144 case 1: 4145 err = psp_init_sos_base_fw(adev); 4146 if (err) 4147 goto out; 4148 4149 if (sos_hdr->header.header_version_minor == 1) { 4150 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4151 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4152 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4153 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4154 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4155 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4156 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4157 } 4158 if (sos_hdr->header.header_version_minor == 2) { 4159 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4160 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4161 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4162 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4163 } 4164 if (sos_hdr->header.header_version_minor == 3) { 4165 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4166 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4167 adev->psp.toc.start_addr = ucode_array_start_addr + 4168 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4169 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4170 adev->psp.kdb.start_addr = ucode_array_start_addr + 4171 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4172 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4173 adev->psp.spl.start_addr = ucode_array_start_addr + 4174 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4175 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4176 adev->psp.rl.start_addr = ucode_array_start_addr + 4177 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4178 } 4179 break; 4180 case 2: 4181 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4182 4183 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4184 4185 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4186 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4187 err = -EINVAL; 4188 goto out; 4189 } 4190 4191 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4192 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4193 4194 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4195 4196 if (psp_is_aux_sos_load_required(psp)) 4197 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4198 else 4199 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4200 4201 } else { 4202 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4203 } 4204 4205 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4206 err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, 4207 sos_hdr_v2_0); 4208 if (err) 4209 goto out; 4210 } 4211 break; 4212 default: 4213 dev_err(adev->dev, 4214 "unsupported psp sos firmware\n"); 4215 err = -EINVAL; 4216 goto out; 4217 } 4218 4219 return 0; 4220 out: 4221 amdgpu_ucode_release(&adev->psp.sos_fw); 4222 4223 return err; 4224 } 4225 4226 static bool is_ta_fw_applicable(struct psp_context *psp, 4227 const struct psp_fw_bin_desc *desc) 4228 { 4229 struct amdgpu_device *adev = psp->adev; 4230 uint32_t fw_version; 4231 4232 switch (desc->fw_type) { 4233 case TA_FW_TYPE_PSP_XGMI: 4234 case TA_FW_TYPE_PSP_XGMI_AUX: 4235 /* for now, AUX TA only exists on 13.0.6 ta bin, 4236 * from v20.00.0x.14 4237 */ 4238 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4239 IP_VERSION(13, 0, 6)) { 4240 fw_version = le32_to_cpu(desc->fw_version); 4241 4242 if (adev->flags & AMD_IS_APU && 4243 (fw_version & 0xff) >= 0x14) 4244 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4245 else 4246 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4247 } 4248 break; 4249 default: 4250 break; 4251 } 4252 4253 return true; 4254 } 4255 4256 static int parse_ta_bin_descriptor(struct psp_context *psp, 4257 const struct psp_fw_bin_desc *desc, 4258 const struct ta_firmware_header_v2_0 *ta_hdr) 4259 { 4260 uint8_t *ucode_start_addr = NULL; 4261 4262 if (!psp || !desc || !ta_hdr) 4263 return -EINVAL; 4264 4265 if (!is_ta_fw_applicable(psp, desc)) 4266 return 0; 4267 4268 ucode_start_addr = (uint8_t *)ta_hdr + 4269 le32_to_cpu(desc->offset_bytes) + 4270 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4271 4272 switch (desc->fw_type) { 4273 case TA_FW_TYPE_PSP_ASD: 4274 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4275 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4276 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4277 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4278 break; 4279 case TA_FW_TYPE_PSP_XGMI: 4280 case TA_FW_TYPE_PSP_XGMI_AUX: 4281 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4282 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4283 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4284 break; 4285 case TA_FW_TYPE_PSP_RAS: 4286 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4287 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4288 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4289 break; 4290 case TA_FW_TYPE_PSP_HDCP: 4291 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4292 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4293 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4294 break; 4295 case TA_FW_TYPE_PSP_DTM: 4296 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4297 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4298 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4299 break; 4300 case TA_FW_TYPE_PSP_RAP: 4301 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4302 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4303 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4304 break; 4305 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4306 psp->securedisplay_context.context.bin_desc.fw_version = 4307 le32_to_cpu(desc->fw_version); 4308 psp->securedisplay_context.context.bin_desc.size_bytes = 4309 le32_to_cpu(desc->size_bytes); 4310 psp->securedisplay_context.context.bin_desc.start_addr = 4311 ucode_start_addr; 4312 break; 4313 default: 4314 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4315 break; 4316 } 4317 4318 return 0; 4319 } 4320 4321 static int parse_ta_v1_microcode(struct psp_context *psp) 4322 { 4323 const struct ta_firmware_header_v1_0 *ta_hdr; 4324 struct amdgpu_device *adev = psp->adev; 4325 4326 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4327 4328 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4329 return -EINVAL; 4330 4331 adev->psp.xgmi_context.context.bin_desc.fw_version = 4332 le32_to_cpu(ta_hdr->xgmi.fw_version); 4333 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4334 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4335 adev->psp.xgmi_context.context.bin_desc.start_addr = 4336 (uint8_t *)ta_hdr + 4337 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4338 4339 adev->psp.ras_context.context.bin_desc.fw_version = 4340 le32_to_cpu(ta_hdr->ras.fw_version); 4341 adev->psp.ras_context.context.bin_desc.size_bytes = 4342 le32_to_cpu(ta_hdr->ras.size_bytes); 4343 adev->psp.ras_context.context.bin_desc.start_addr = 4344 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4345 le32_to_cpu(ta_hdr->ras.offset_bytes); 4346 4347 adev->psp.hdcp_context.context.bin_desc.fw_version = 4348 le32_to_cpu(ta_hdr->hdcp.fw_version); 4349 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4350 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4351 adev->psp.hdcp_context.context.bin_desc.start_addr = 4352 (uint8_t *)ta_hdr + 4353 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4354 4355 adev->psp.dtm_context.context.bin_desc.fw_version = 4356 le32_to_cpu(ta_hdr->dtm.fw_version); 4357 adev->psp.dtm_context.context.bin_desc.size_bytes = 4358 le32_to_cpu(ta_hdr->dtm.size_bytes); 4359 adev->psp.dtm_context.context.bin_desc.start_addr = 4360 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4361 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4362 4363 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4364 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4365 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4366 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4367 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4368 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4369 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4370 4371 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4372 4373 return 0; 4374 } 4375 4376 static int parse_ta_v2_microcode(struct psp_context *psp) 4377 { 4378 const struct ta_firmware_header_v2_0 *ta_hdr; 4379 struct amdgpu_device *adev = psp->adev; 4380 int err = 0; 4381 int ta_index = 0; 4382 4383 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4384 4385 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4386 return -EINVAL; 4387 4388 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4389 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4390 return -EINVAL; 4391 } 4392 4393 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4394 err = parse_ta_bin_descriptor(psp, 4395 &ta_hdr->ta_fw_bin[ta_index], 4396 ta_hdr); 4397 if (err) 4398 return err; 4399 } 4400 4401 return 0; 4402 } 4403 4404 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4405 { 4406 const struct common_firmware_header *hdr; 4407 struct amdgpu_device *adev = psp->adev; 4408 int err; 4409 4410 if (amdgpu_is_kicker_fw(adev)) 4411 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4412 "amdgpu/%s_ta_kicker.bin", chip_name); 4413 else 4414 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4415 "amdgpu/%s_ta.bin", chip_name); 4416 if (err) 4417 return err; 4418 4419 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4420 switch (le16_to_cpu(hdr->header_version_major)) { 4421 case 1: 4422 err = parse_ta_v1_microcode(psp); 4423 break; 4424 case 2: 4425 err = parse_ta_v2_microcode(psp); 4426 break; 4427 default: 4428 dev_err(adev->dev, "unsupported TA header version\n"); 4429 err = -EINVAL; 4430 } 4431 4432 if (err) 4433 amdgpu_ucode_release(&adev->psp.ta_fw); 4434 4435 return err; 4436 } 4437 4438 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4439 { 4440 struct amdgpu_device *adev = psp->adev; 4441 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 4442 struct amdgpu_firmware_info *info = NULL; 4443 int err = 0; 4444 4445 if (!amdgpu_sriov_vf(adev)) { 4446 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4447 return -EINVAL; 4448 } 4449 4450 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL, 4451 "amdgpu/%s_cap.bin", chip_name); 4452 if (err) { 4453 if (err == -ENODEV) { 4454 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4455 err = 0; 4456 } else { 4457 dev_err(adev->dev, "fail to initialize cap microcode\n"); 4458 } 4459 goto out; 4460 } 4461 4462 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 4463 info->ucode_id = AMDGPU_UCODE_ID_CAP; 4464 info->fw = adev->psp.cap_fw; 4465 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 4466 adev->psp.cap_fw->data; 4467 adev->firmware.fw_size += ALIGN( 4468 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 4469 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 4470 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 4471 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 4472 4473 return 0; 4474 4475 out: 4476 amdgpu_ucode_release(&adev->psp.cap_fw); 4477 return err; 4478 } 4479 4480 int psp_config_sq_perfmon(struct psp_context *psp, 4481 uint32_t xcp_id, bool core_override_enable, 4482 bool reg_override_enable, bool perfmon_override_enable) 4483 { 4484 int ret; 4485 4486 if (amdgpu_sriov_vf(psp->adev)) 4487 return 0; 4488 4489 if (xcp_id > MAX_XCP) { 4490 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 4491 return -EINVAL; 4492 } 4493 4494 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 4495 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 4496 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 4497 return -EINVAL; 4498 } 4499 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4500 4501 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 4502 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 4503 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 4504 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 4505 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 4506 4507 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 4508 if (ret) 4509 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 4510 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 4511 4512 release_psp_cmd_buf(psp); 4513 return ret; 4514 } 4515 4516 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4517 enum amd_clockgating_state state) 4518 { 4519 return 0; 4520 } 4521 4522 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 4523 enum amd_powergating_state state) 4524 { 4525 return 0; 4526 } 4527 4528 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 4529 struct device_attribute *attr, 4530 char *buf) 4531 { 4532 struct drm_device *ddev = dev_get_drvdata(dev); 4533 struct amdgpu_device *adev = drm_to_adev(ddev); 4534 struct amdgpu_ip_block *ip_block; 4535 uint32_t fw_ver; 4536 int ret; 4537 4538 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4539 if (!ip_block || !ip_block->status.late_initialized) { 4540 dev_info(adev->dev, "PSP block is not ready yet\n."); 4541 return -EBUSY; 4542 } 4543 4544 mutex_lock(&adev->psp.mutex); 4545 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 4546 mutex_unlock(&adev->psp.mutex); 4547 4548 if (ret) { 4549 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 4550 return ret; 4551 } 4552 4553 return sysfs_emit(buf, "%x\n", fw_ver); 4554 } 4555 4556 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 4557 struct device_attribute *attr, 4558 const char *buf, 4559 size_t count) 4560 { 4561 struct drm_device *ddev = dev_get_drvdata(dev); 4562 struct amdgpu_device *adev = drm_to_adev(ddev); 4563 int ret, idx; 4564 const struct firmware *usbc_pd_fw; 4565 struct amdgpu_bo *fw_buf_bo = NULL; 4566 uint64_t fw_pri_mc_addr; 4567 void *fw_pri_cpu_addr; 4568 struct amdgpu_ip_block *ip_block; 4569 4570 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 4571 if (!ip_block || !ip_block->status.late_initialized) { 4572 dev_err(adev->dev, "PSP block is not ready yet."); 4573 return -EBUSY; 4574 } 4575 4576 if (!drm_dev_enter(ddev, &idx)) 4577 return -ENODEV; 4578 4579 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 4580 "amdgpu/%s", buf); 4581 if (ret) 4582 goto fail; 4583 4584 /* LFB address which is aligned to 1MB boundary per PSP request */ 4585 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 4586 AMDGPU_GEM_DOMAIN_VRAM | 4587 AMDGPU_GEM_DOMAIN_GTT, 4588 &fw_buf_bo, &fw_pri_mc_addr, 4589 &fw_pri_cpu_addr); 4590 if (ret) 4591 goto rel_buf; 4592 4593 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 4594 4595 mutex_lock(&adev->psp.mutex); 4596 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 4597 mutex_unlock(&adev->psp.mutex); 4598 4599 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4600 4601 rel_buf: 4602 amdgpu_ucode_release(&usbc_pd_fw); 4603 fail: 4604 if (ret) { 4605 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 4606 count = ret; 4607 } 4608 4609 drm_dev_exit(idx); 4610 return count; 4611 } 4612 4613 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 4614 { 4615 int idx; 4616 4617 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 4618 return -ENODEV; 4619 4620 if (!bin_size || bin_size > PSP_1_MEG) { 4621 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 4622 drm_dev_exit(idx); 4623 return -EINVAL; 4624 } 4625 4626 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 4627 memcpy(psp->fw_pri_buf, start_addr, bin_size); 4628 4629 drm_dev_exit(idx); 4630 return 0; 4631 } 4632 4633 /** 4634 * DOC: usbc_pd_fw 4635 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 4636 * this file will trigger the update process. 4637 */ 4638 static DEVICE_ATTR(usbc_pd_fw, 0644, 4639 psp_usbc_pd_fw_sysfs_read, 4640 psp_usbc_pd_fw_sysfs_write); 4641 /** 4642 * DOC: PTL sysfs attributes 4643 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 4644 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 4645 * formats for each GPU. 4646 */ 4647 static DEVICE_ATTR(ptl_enable, 0644, 4648 ptl_enable_show, ptl_enable_store); 4649 static DEVICE_ATTR(ptl_format, 0644, 4650 ptl_format_show, ptl_format_store); 4651 static DEVICE_ATTR(ptl_supported_formats, 0444, 4652 ptl_supported_formats_show, NULL); 4653 4654 static struct attribute *ptl_attrs[] = { 4655 &dev_attr_ptl_enable.attr, 4656 &dev_attr_ptl_format.attr, 4657 &dev_attr_ptl_supported_formats.attr, 4658 NULL, 4659 }; 4660 4661 const struct attribute_group amdgpu_ptl_attr_group = { 4662 .name = "ptl", 4663 .attrs = ptl_attrs, 4664 .is_visible = amdgpu_ptl_is_visible, 4665 }; 4666 4667 int is_psp_fw_valid(struct psp_bin_desc bin) 4668 { 4669 return bin.size_bytes; 4670 } 4671 4672 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 4673 const struct bin_attribute *bin_attr, 4674 char *buffer, loff_t pos, size_t count) 4675 { 4676 struct device *dev = kobj_to_dev(kobj); 4677 struct drm_device *ddev = dev_get_drvdata(dev); 4678 struct amdgpu_device *adev = drm_to_adev(ddev); 4679 4680 adev->psp.vbflash_done = false; 4681 4682 /* Safeguard against memory drain */ 4683 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 4684 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 4685 kvfree(adev->psp.vbflash_tmp_buf); 4686 adev->psp.vbflash_tmp_buf = NULL; 4687 adev->psp.vbflash_image_size = 0; 4688 return -ENOMEM; 4689 } 4690 4691 mutex_lock(&adev->psp.mutex); 4692 4693 /* TODO Just allocate max for now and optimize to realloc later if needed */ 4694 if (!adev->psp.vbflash_tmp_buf) { 4695 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 4696 if (!adev->psp.vbflash_tmp_buf) { 4697 mutex_unlock(&adev->psp.mutex); 4698 return -ENOMEM; 4699 } 4700 } 4701 4702 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 4703 adev->psp.vbflash_image_size += count; 4704 mutex_unlock(&adev->psp.mutex); 4705 4706 dev_dbg(adev->dev, "IFWI staged for update\n"); 4707 4708 return count; 4709 } 4710 4711 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 4712 const struct bin_attribute *bin_attr, char *buffer, 4713 loff_t pos, size_t count) 4714 { 4715 struct device *dev = kobj_to_dev(kobj); 4716 struct drm_device *ddev = dev_get_drvdata(dev); 4717 struct amdgpu_device *adev = drm_to_adev(ddev); 4718 struct amdgpu_bo *fw_buf_bo = NULL; 4719 uint64_t fw_pri_mc_addr; 4720 void *fw_pri_cpu_addr; 4721 int ret; 4722 4723 if (adev->psp.vbflash_image_size == 0) 4724 return -EINVAL; 4725 4726 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 4727 4728 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 4729 AMDGPU_GPU_PAGE_SIZE, 4730 AMDGPU_GEM_DOMAIN_VRAM, 4731 &fw_buf_bo, 4732 &fw_pri_mc_addr, 4733 &fw_pri_cpu_addr); 4734 if (ret) 4735 goto rel_buf; 4736 4737 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 4738 4739 mutex_lock(&adev->psp.mutex); 4740 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 4741 mutex_unlock(&adev->psp.mutex); 4742 4743 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 4744 4745 rel_buf: 4746 kvfree(adev->psp.vbflash_tmp_buf); 4747 adev->psp.vbflash_tmp_buf = NULL; 4748 adev->psp.vbflash_image_size = 0; 4749 4750 if (ret) { 4751 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 4752 return ret; 4753 } 4754 4755 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 4756 return 0; 4757 } 4758 4759 /** 4760 * DOC: psp_vbflash 4761 * Writing to this file will stage an IFWI for update. Reading from this file 4762 * will trigger the update process. 4763 */ 4764 static const struct bin_attribute psp_vbflash_bin_attr = { 4765 .attr = {.name = "psp_vbflash", .mode = 0660}, 4766 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 4767 .write = amdgpu_psp_vbflash_write, 4768 .read = amdgpu_psp_vbflash_read, 4769 }; 4770 4771 /** 4772 * DOC: psp_vbflash_status 4773 * The status of the flash process. 4774 * 0: IFWI flash not complete. 4775 * 1: IFWI flash complete. 4776 */ 4777 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 4778 struct device_attribute *attr, 4779 char *buf) 4780 { 4781 struct drm_device *ddev = dev_get_drvdata(dev); 4782 struct amdgpu_device *adev = drm_to_adev(ddev); 4783 uint32_t vbflash_status; 4784 4785 vbflash_status = psp_vbflash_status(&adev->psp); 4786 if (!adev->psp.vbflash_done) 4787 vbflash_status = 0; 4788 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 4789 vbflash_status = 1; 4790 4791 return sysfs_emit(buf, "0x%x\n", vbflash_status); 4792 } 4793 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 4794 4795 static const struct bin_attribute *const bin_flash_attrs[] = { 4796 &psp_vbflash_bin_attr, 4797 NULL 4798 }; 4799 4800 static struct attribute *flash_attrs[] = { 4801 &dev_attr_psp_vbflash_status.attr, 4802 &dev_attr_usbc_pd_fw.attr, 4803 NULL 4804 }; 4805 4806 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 4807 { 4808 struct device *dev = kobj_to_dev(kobj); 4809 struct drm_device *ddev = dev_get_drvdata(dev); 4810 struct amdgpu_device *adev = drm_to_adev(ddev); 4811 4812 if (attr == &dev_attr_usbc_pd_fw.attr) 4813 return adev->psp.sup_pd_fw_up ? 0660 : 0; 4814 4815 return adev->psp.sup_ifwi_up ? 0440 : 0; 4816 } 4817 4818 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 4819 const struct bin_attribute *attr, 4820 int idx) 4821 { 4822 struct device *dev = kobj_to_dev(kobj); 4823 struct drm_device *ddev = dev_get_drvdata(dev); 4824 struct amdgpu_device *adev = drm_to_adev(ddev); 4825 4826 return adev->psp.sup_ifwi_up ? 0660 : 0; 4827 } 4828 4829 const struct attribute_group amdgpu_flash_attr_group = { 4830 .attrs = flash_attrs, 4831 .bin_attrs = bin_flash_attrs, 4832 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 4833 .is_visible = amdgpu_flash_attr_is_visible, 4834 }; 4835 4836 #if defined(CONFIG_DEBUG_FS) 4837 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 4838 { 4839 struct amdgpu_device *adev = filp->f_inode->i_private; 4840 struct spirom_bo *bo_triplet; 4841 int ret; 4842 4843 /* serialize the open() file calling */ 4844 if (!mutex_trylock(&adev->psp.mutex)) 4845 return -EBUSY; 4846 4847 /* 4848 * make sure only one userpace process is alive for dumping so that 4849 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 4850 * let's say the case where one process try opening the file while 4851 * another one has proceeded to read or release. In this way, eliminate 4852 * the use of mutex for read() or release() callback as well. 4853 */ 4854 if (adev->psp.spirom_dump_trip) { 4855 mutex_unlock(&adev->psp.mutex); 4856 return -EBUSY; 4857 } 4858 4859 bo_triplet = kzalloc_obj(struct spirom_bo); 4860 if (!bo_triplet) { 4861 mutex_unlock(&adev->psp.mutex); 4862 return -ENOMEM; 4863 } 4864 4865 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 4866 AMDGPU_GPU_PAGE_SIZE, 4867 AMDGPU_GEM_DOMAIN_GTT, 4868 &bo_triplet->bo, 4869 &bo_triplet->mc_addr, 4870 &bo_triplet->cpu_addr); 4871 if (ret) 4872 goto rel_trip; 4873 4874 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 4875 if (ret) 4876 goto rel_bo; 4877 4878 adev->psp.spirom_dump_trip = bo_triplet; 4879 mutex_unlock(&adev->psp.mutex); 4880 return 0; 4881 rel_bo: 4882 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4883 &bo_triplet->cpu_addr); 4884 rel_trip: 4885 kfree(bo_triplet); 4886 mutex_unlock(&adev->psp.mutex); 4887 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 4888 return ret; 4889 } 4890 4891 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 4892 loff_t *pos) 4893 { 4894 struct amdgpu_device *adev = filp->f_inode->i_private; 4895 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4896 4897 if (!bo_triplet) 4898 return -EINVAL; 4899 4900 return simple_read_from_buffer(buf, 4901 size, 4902 pos, bo_triplet->cpu_addr, 4903 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4904 } 4905 4906 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 4907 { 4908 struct amdgpu_device *adev = filp->f_inode->i_private; 4909 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 4910 4911 if (bo_triplet) { 4912 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 4913 &bo_triplet->cpu_addr); 4914 kfree(bo_triplet); 4915 } 4916 4917 adev->psp.spirom_dump_trip = NULL; 4918 return 0; 4919 } 4920 4921 static const struct file_operations psp_dump_spirom_debugfs_ops = { 4922 .owner = THIS_MODULE, 4923 .open = psp_read_spirom_debugfs_open, 4924 .read = psp_read_spirom_debugfs_read, 4925 .release = psp_read_spirom_debugfs_release, 4926 .llseek = default_llseek, 4927 }; 4928 #endif 4929 4930 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 4931 { 4932 #if defined(CONFIG_DEBUG_FS) 4933 struct drm_minor *minor = adev_to_drm(adev)->primary; 4934 4935 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 4936 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 4937 #endif 4938 } 4939 4940 const struct amd_ip_funcs psp_ip_funcs = { 4941 .name = "psp", 4942 .early_init = psp_early_init, 4943 .sw_init = psp_sw_init, 4944 .sw_fini = psp_sw_fini, 4945 .hw_init = psp_hw_init, 4946 .hw_fini = psp_hw_fini, 4947 .suspend = psp_suspend, 4948 .resume = psp_resume, 4949 .set_clockgating_state = psp_set_clockgating_state, 4950 .set_powergating_state = psp_set_powergating_state, 4951 }; 4952 4953 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 4954 .type = AMD_IP_BLOCK_TYPE_PSP, 4955 .major = 3, 4956 .minor = 1, 4957 .rev = 0, 4958 .funcs = &psp_ip_funcs, 4959 }; 4960 4961 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 4962 .type = AMD_IP_BLOCK_TYPE_PSP, 4963 .major = 10, 4964 .minor = 0, 4965 .rev = 0, 4966 .funcs = &psp_ip_funcs, 4967 }; 4968 4969 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 4970 .type = AMD_IP_BLOCK_TYPE_PSP, 4971 .major = 11, 4972 .minor = 0, 4973 .rev = 0, 4974 .funcs = &psp_ip_funcs, 4975 }; 4976 4977 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 4978 .type = AMD_IP_BLOCK_TYPE_PSP, 4979 .major = 11, 4980 .minor = 0, 4981 .rev = 8, 4982 .funcs = &psp_ip_funcs, 4983 }; 4984 4985 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 4986 .type = AMD_IP_BLOCK_TYPE_PSP, 4987 .major = 12, 4988 .minor = 0, 4989 .rev = 0, 4990 .funcs = &psp_ip_funcs, 4991 }; 4992 4993 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 4994 .type = AMD_IP_BLOCK_TYPE_PSP, 4995 .major = 13, 4996 .minor = 0, 4997 .rev = 0, 4998 .funcs = &psp_ip_funcs, 4999 }; 5000 5001 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 5002 .type = AMD_IP_BLOCK_TYPE_PSP, 5003 .major = 13, 5004 .minor = 0, 5005 .rev = 4, 5006 .funcs = &psp_ip_funcs, 5007 }; 5008 5009 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 5010 .type = AMD_IP_BLOCK_TYPE_PSP, 5011 .major = 14, 5012 .minor = 0, 5013 .rev = 0, 5014 .funcs = &psp_ip_funcs, 5015 }; 5016 5017 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 5018 .type = AMD_IP_BLOCK_TYPE_PSP, 5019 .major = 15, 5020 .minor = 0, 5021 .rev = 0, 5022 .funcs = &psp_ip_funcs, 5023 }; 5024 5025 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 5026 .type = AMD_IP_BLOCK_TYPE_PSP, 5027 .major = 15, 5028 .minor = 0, 5029 .rev = 8, 5030 .funcs = &psp_ip_funcs, 5031 }; 5032