1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 59 60 amdgpu_bo_kunmap(bo); 61 62 if (bo->tbo.base.import_attach) 63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 64 drm_gem_object_release(&bo->tbo.base); 65 amdgpu_bo_unref(&bo->parent); 66 kvfree(bo); 67 } 68 69 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 70 { 71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 72 struct amdgpu_bo_user *ubo; 73 74 ubo = to_amdgpu_bo_user(bo); 75 kfree(ubo->metadata); 76 amdgpu_bo_destroy(tbo); 77 } 78 79 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 80 { 81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 82 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; 83 struct amdgpu_bo_vm *vmbo; 84 85 bo = shadow_bo->parent; 86 vmbo = to_amdgpu_bo_vm(bo); 87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 88 if (!list_empty(&vmbo->shadow_list)) { 89 mutex_lock(&adev->shadow_list_lock); 90 list_del_init(&vmbo->shadow_list); 91 mutex_unlock(&adev->shadow_list_lock); 92 } 93 94 amdgpu_bo_destroy(tbo); 95 } 96 97 /** 98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 99 * @bo: buffer object to be checked 100 * 101 * Uses destroy function associated with the object to determine if this is 102 * an &amdgpu_bo. 103 * 104 * Returns: 105 * true if the object belongs to &amdgpu_bo, false if not. 106 */ 107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_bo_destroy || 110 bo->destroy == &amdgpu_bo_user_destroy || 111 bo->destroy == &amdgpu_bo_vm_destroy) 112 return true; 113 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 136 137 if (adev->gmc.mem_partitions && mem_id >= 0) { 138 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 139 /* 140 * memory partition range lpfn is inclusive start + size - 1 141 * TTM place lpfn is exclusive start + size 142 */ 143 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 144 } else { 145 places[c].fpfn = 0; 146 places[c].lpfn = 0; 147 } 148 places[c].mem_type = TTM_PL_VRAM; 149 places[c].flags = 0; 150 151 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 152 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 153 else 154 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 155 156 if (abo->tbo.type == ttm_bo_type_kernel && 157 flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 158 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 159 160 c++; 161 } 162 163 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { 164 places[c].fpfn = 0; 165 places[c].lpfn = 0; 166 places[c].mem_type = AMDGPU_PL_DOORBELL; 167 places[c].flags = 0; 168 c++; 169 } 170 171 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 172 places[c].fpfn = 0; 173 places[c].lpfn = 0; 174 places[c].mem_type = 175 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 176 AMDGPU_PL_PREEMPT : TTM_PL_TT; 177 places[c].flags = 0; 178 /* 179 * When GTT is just an alternative to VRAM make sure that we 180 * only use it as fallback and still try to fill up VRAM first. 181 */ 182 if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) 183 places[c].flags |= TTM_PL_FLAG_FALLBACK; 184 c++; 185 } 186 187 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 188 places[c].fpfn = 0; 189 places[c].lpfn = 0; 190 places[c].mem_type = TTM_PL_SYSTEM; 191 places[c].flags = 0; 192 c++; 193 } 194 195 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 196 places[c].fpfn = 0; 197 places[c].lpfn = 0; 198 places[c].mem_type = AMDGPU_PL_GDS; 199 places[c].flags = 0; 200 c++; 201 } 202 203 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 204 places[c].fpfn = 0; 205 places[c].lpfn = 0; 206 places[c].mem_type = AMDGPU_PL_GWS; 207 places[c].flags = 0; 208 c++; 209 } 210 211 if (domain & AMDGPU_GEM_DOMAIN_OA) { 212 places[c].fpfn = 0; 213 places[c].lpfn = 0; 214 places[c].mem_type = AMDGPU_PL_OA; 215 places[c].flags = 0; 216 c++; 217 } 218 219 if (!c) { 220 places[c].fpfn = 0; 221 places[c].lpfn = 0; 222 places[c].mem_type = TTM_PL_SYSTEM; 223 places[c].flags = 0; 224 c++; 225 } 226 227 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 228 229 placement->num_placement = c; 230 placement->placement = places; 231 } 232 233 /** 234 * amdgpu_bo_create_reserved - create reserved BO for kernel use 235 * 236 * @adev: amdgpu device object 237 * @size: size for the new BO 238 * @align: alignment for the new BO 239 * @domain: where to place it 240 * @bo_ptr: used to initialize BOs in structures 241 * @gpu_addr: GPU addr of the pinned BO 242 * @cpu_addr: optional CPU address mapping 243 * 244 * Allocates and pins a BO for kernel internal use, and returns it still 245 * reserved. 246 * 247 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 248 * 249 * Returns: 250 * 0 on success, negative error code otherwise. 251 */ 252 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 253 unsigned long size, int align, 254 u32 domain, struct amdgpu_bo **bo_ptr, 255 u64 *gpu_addr, void **cpu_addr) 256 { 257 struct amdgpu_bo_param bp; 258 bool free = false; 259 int r; 260 261 if (!size) { 262 amdgpu_bo_unref(bo_ptr); 263 return 0; 264 } 265 266 memset(&bp, 0, sizeof(bp)); 267 bp.size = size; 268 bp.byte_align = align; 269 bp.domain = domain; 270 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 271 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 272 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 273 bp.type = ttm_bo_type_kernel; 274 bp.resv = NULL; 275 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 276 277 if (!*bo_ptr) { 278 r = amdgpu_bo_create(adev, &bp, bo_ptr); 279 if (r) { 280 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 281 r); 282 return r; 283 } 284 free = true; 285 } 286 287 r = amdgpu_bo_reserve(*bo_ptr, false); 288 if (r) { 289 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 290 goto error_free; 291 } 292 293 r = amdgpu_bo_pin(*bo_ptr, domain); 294 if (r) { 295 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 296 goto error_unreserve; 297 } 298 299 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 300 if (r) { 301 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 302 goto error_unpin; 303 } 304 305 if (gpu_addr) 306 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 307 308 if (cpu_addr) { 309 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 310 if (r) { 311 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 312 goto error_unpin; 313 } 314 } 315 316 return 0; 317 318 error_unpin: 319 amdgpu_bo_unpin(*bo_ptr); 320 error_unreserve: 321 amdgpu_bo_unreserve(*bo_ptr); 322 323 error_free: 324 if (free) 325 amdgpu_bo_unref(bo_ptr); 326 327 return r; 328 } 329 330 /** 331 * amdgpu_bo_create_kernel - create BO for kernel use 332 * 333 * @adev: amdgpu device object 334 * @size: size for the new BO 335 * @align: alignment for the new BO 336 * @domain: where to place it 337 * @bo_ptr: used to initialize BOs in structures 338 * @gpu_addr: GPU addr of the pinned BO 339 * @cpu_addr: optional CPU address mapping 340 * 341 * Allocates and pins a BO for kernel internal use. 342 * 343 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 344 * 345 * Returns: 346 * 0 on success, negative error code otherwise. 347 */ 348 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 349 unsigned long size, int align, 350 u32 domain, struct amdgpu_bo **bo_ptr, 351 u64 *gpu_addr, void **cpu_addr) 352 { 353 int r; 354 355 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 356 gpu_addr, cpu_addr); 357 358 if (r) 359 return r; 360 361 if (*bo_ptr) 362 amdgpu_bo_unreserve(*bo_ptr); 363 364 return 0; 365 } 366 367 /** 368 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 369 * 370 * @adev: amdgpu device object 371 * @offset: offset of the BO 372 * @size: size of the BO 373 * @bo_ptr: used to initialize BOs in structures 374 * @cpu_addr: optional CPU address mapping 375 * 376 * Creates a kernel BO at a specific offset in VRAM. 377 * 378 * Returns: 379 * 0 on success, negative error code otherwise. 380 */ 381 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 382 uint64_t offset, uint64_t size, 383 struct amdgpu_bo **bo_ptr, void **cpu_addr) 384 { 385 struct ttm_operation_ctx ctx = { false, false }; 386 unsigned int i; 387 int r; 388 389 offset &= PAGE_MASK; 390 size = ALIGN(size, PAGE_SIZE); 391 392 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 393 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 394 cpu_addr); 395 if (r) 396 return r; 397 398 if ((*bo_ptr) == NULL) 399 return 0; 400 401 /* 402 * Remove the original mem node and create a new one at the request 403 * position. 404 */ 405 if (cpu_addr) 406 amdgpu_bo_kunmap(*bo_ptr); 407 408 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 409 410 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 411 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 412 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 413 } 414 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 415 &(*bo_ptr)->tbo.resource, &ctx); 416 if (r) 417 goto error; 418 419 if (cpu_addr) { 420 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 421 if (r) 422 goto error; 423 } 424 425 amdgpu_bo_unreserve(*bo_ptr); 426 return 0; 427 428 error: 429 amdgpu_bo_unreserve(*bo_ptr); 430 amdgpu_bo_unref(bo_ptr); 431 return r; 432 } 433 434 /** 435 * amdgpu_bo_free_kernel - free BO for kernel use 436 * 437 * @bo: amdgpu BO to free 438 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 439 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 440 * 441 * unmaps and unpin a BO for kernel internal use. 442 */ 443 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 444 void **cpu_addr) 445 { 446 if (*bo == NULL) 447 return; 448 449 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 450 451 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 452 if (cpu_addr) 453 amdgpu_bo_kunmap(*bo); 454 455 amdgpu_bo_unpin(*bo); 456 amdgpu_bo_unreserve(*bo); 457 } 458 amdgpu_bo_unref(bo); 459 460 if (gpu_addr) 461 *gpu_addr = 0; 462 463 if (cpu_addr) 464 *cpu_addr = NULL; 465 } 466 467 /* Validate bo size is bit bigger than the request domain */ 468 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 469 unsigned long size, u32 domain) 470 { 471 struct ttm_resource_manager *man = NULL; 472 473 /* 474 * If GTT is part of requested domains the check must succeed to 475 * allow fall back to GTT. 476 */ 477 if (domain & AMDGPU_GEM_DOMAIN_GTT) 478 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 479 else if (domain & AMDGPU_GEM_DOMAIN_VRAM) 480 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 481 else 482 return true; 483 484 if (!man) { 485 if (domain & AMDGPU_GEM_DOMAIN_GTT) 486 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 487 return false; 488 } 489 490 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */ 491 if (size < man->size) 492 return true; 493 494 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size); 495 return false; 496 } 497 498 bool amdgpu_bo_support_uswc(u64 bo_flags) 499 { 500 501 #ifdef CONFIG_X86_32 502 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 503 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 504 */ 505 return false; 506 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 507 /* Don't try to enable write-combining when it can't work, or things 508 * may be slow 509 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 510 */ 511 512 #ifndef CONFIG_COMPILE_TEST 513 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 514 thanks to write-combining 515 #endif 516 517 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 518 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 519 "better performance thanks to write-combining\n"); 520 return false; 521 #else 522 /* For architectures that don't support WC memory, 523 * mask out the WC flag from the BO 524 */ 525 if (!drm_arch_can_wc_memory()) 526 return false; 527 528 return true; 529 #endif 530 } 531 532 /** 533 * amdgpu_bo_create - create an &amdgpu_bo buffer object 534 * @adev: amdgpu device object 535 * @bp: parameters to be used for the buffer object 536 * @bo_ptr: pointer to the buffer object pointer 537 * 538 * Creates an &amdgpu_bo buffer object. 539 * 540 * Returns: 541 * 0 for success or a negative error code on failure. 542 */ 543 int amdgpu_bo_create(struct amdgpu_device *adev, 544 struct amdgpu_bo_param *bp, 545 struct amdgpu_bo **bo_ptr) 546 { 547 struct ttm_operation_ctx ctx = { 548 .interruptible = (bp->type != ttm_bo_type_kernel), 549 .no_wait_gpu = bp->no_wait_gpu, 550 /* We opt to avoid OOM on system pages allocations */ 551 .gfp_retry_mayfail = true, 552 .allow_res_evict = bp->type != ttm_bo_type_kernel, 553 .resv = bp->resv 554 }; 555 struct amdgpu_bo *bo; 556 unsigned long page_align, size = bp->size; 557 int r; 558 559 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 560 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 561 /* GWS and OA don't need any alignment. */ 562 page_align = bp->byte_align; 563 size <<= PAGE_SHIFT; 564 565 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 566 /* Both size and alignment must be a multiple of 4. */ 567 page_align = ALIGN(bp->byte_align, 4); 568 size = ALIGN(size, 4) << PAGE_SHIFT; 569 } else { 570 /* Memory should be aligned at least to a page size. */ 571 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 572 size = ALIGN(size, PAGE_SIZE); 573 } 574 575 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 576 return -ENOMEM; 577 578 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 579 580 *bo_ptr = NULL; 581 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 582 if (bo == NULL) 583 return -ENOMEM; 584 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 585 bo->vm_bo = NULL; 586 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 587 bp->domain; 588 bo->allowed_domains = bo->preferred_domains; 589 if (bp->type != ttm_bo_type_kernel && 590 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 591 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 592 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 593 594 bo->flags = bp->flags; 595 596 if (adev->gmc.mem_partitions) 597 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 598 bo->xcp_id = bp->xcp_id_plus1 - 1; 599 else 600 /* For GPUs without spatial partitioning */ 601 bo->xcp_id = 0; 602 603 if (!amdgpu_bo_support_uswc(bo->flags)) 604 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 605 606 if (adev->ras_enabled) 607 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 608 609 bo->tbo.bdev = &adev->mman.bdev; 610 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 611 AMDGPU_GEM_DOMAIN_GDS)) 612 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 613 else 614 amdgpu_bo_placement_from_domain(bo, bp->domain); 615 if (bp->type == ttm_bo_type_kernel) 616 bo->tbo.priority = 2; 617 else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE)) 618 bo->tbo.priority = 1; 619 620 if (!bp->destroy) 621 bp->destroy = &amdgpu_bo_destroy; 622 623 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 624 &bo->placement, page_align, &ctx, NULL, 625 bp->resv, bp->destroy); 626 if (unlikely(r != 0)) 627 return r; 628 629 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 630 amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 631 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 632 ctx.bytes_moved); 633 else 634 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 635 636 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 637 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 638 struct dma_fence *fence; 639 640 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence, true); 641 if (unlikely(r)) 642 goto fail_unreserve; 643 644 dma_resv_add_fence(bo->tbo.base.resv, fence, 645 DMA_RESV_USAGE_KERNEL); 646 dma_fence_put(fence); 647 } 648 if (!bp->resv) 649 amdgpu_bo_unreserve(bo); 650 *bo_ptr = bo; 651 652 trace_amdgpu_bo_create(bo); 653 654 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 655 if (bp->type == ttm_bo_type_device) 656 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 657 658 return 0; 659 660 fail_unreserve: 661 if (!bp->resv) 662 dma_resv_unlock(bo->tbo.base.resv); 663 amdgpu_bo_unref(&bo); 664 return r; 665 } 666 667 /** 668 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 669 * @adev: amdgpu device object 670 * @bp: parameters to be used for the buffer object 671 * @ubo_ptr: pointer to the buffer object pointer 672 * 673 * Create a BO to be used by user application; 674 * 675 * Returns: 676 * 0 for success or a negative error code on failure. 677 */ 678 679 int amdgpu_bo_create_user(struct amdgpu_device *adev, 680 struct amdgpu_bo_param *bp, 681 struct amdgpu_bo_user **ubo_ptr) 682 { 683 struct amdgpu_bo *bo_ptr; 684 int r; 685 686 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 687 bp->destroy = &amdgpu_bo_user_destroy; 688 r = amdgpu_bo_create(adev, bp, &bo_ptr); 689 if (r) 690 return r; 691 692 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 693 return r; 694 } 695 696 /** 697 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 698 * @adev: amdgpu device object 699 * @bp: parameters to be used for the buffer object 700 * @vmbo_ptr: pointer to the buffer object pointer 701 * 702 * Create a BO to be for GPUVM. 703 * 704 * Returns: 705 * 0 for success or a negative error code on failure. 706 */ 707 708 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 709 struct amdgpu_bo_param *bp, 710 struct amdgpu_bo_vm **vmbo_ptr) 711 { 712 struct amdgpu_bo *bo_ptr; 713 int r; 714 715 /* bo_ptr_size will be determined by the caller and it depends on 716 * num of amdgpu_vm_pt entries. 717 */ 718 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 719 r = amdgpu_bo_create(adev, bp, &bo_ptr); 720 if (r) 721 return r; 722 723 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 724 return r; 725 } 726 727 /** 728 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 729 * 730 * @vmbo: BO that will be inserted into the shadow list 731 * 732 * Insert a BO to the shadow list. 733 */ 734 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 735 { 736 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 737 738 mutex_lock(&adev->shadow_list_lock); 739 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 740 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); 741 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; 742 mutex_unlock(&adev->shadow_list_lock); 743 } 744 745 /** 746 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 747 * 748 * @shadow: &amdgpu_bo shadow to be restored 749 * @fence: dma_fence associated with the operation 750 * 751 * Copies a buffer object's shadow content back to the object. 752 * This is used for recovering a buffer from its shadow in case of a gpu 753 * reset where vram context may be lost. 754 * 755 * Returns: 756 * 0 for success or a negative error code on failure. 757 */ 758 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 759 760 { 761 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 762 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 763 uint64_t shadow_addr, parent_addr; 764 765 shadow_addr = amdgpu_bo_gpu_offset(shadow); 766 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 767 768 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 769 amdgpu_bo_size(shadow), NULL, fence, 770 true, false, 0); 771 } 772 773 /** 774 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 775 * @bo: &amdgpu_bo buffer object to be mapped 776 * @ptr: kernel virtual address to be returned 777 * 778 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 779 * amdgpu_bo_kptr() to get the kernel virtual address. 780 * 781 * Returns: 782 * 0 for success or a negative error code on failure. 783 */ 784 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 785 { 786 void *kptr; 787 long r; 788 789 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 790 return -EPERM; 791 792 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 793 false, MAX_SCHEDULE_TIMEOUT); 794 if (r < 0) 795 return r; 796 797 kptr = amdgpu_bo_kptr(bo); 798 if (kptr) { 799 if (ptr) 800 *ptr = kptr; 801 return 0; 802 } 803 804 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 805 if (r) 806 return r; 807 808 if (ptr) 809 *ptr = amdgpu_bo_kptr(bo); 810 811 return 0; 812 } 813 814 /** 815 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 816 * @bo: &amdgpu_bo buffer object 817 * 818 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 819 * 820 * Returns: 821 * the virtual address of a buffer object area. 822 */ 823 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 824 { 825 bool is_iomem; 826 827 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 828 } 829 830 /** 831 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 832 * @bo: &amdgpu_bo buffer object to be unmapped 833 * 834 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 835 */ 836 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 837 { 838 if (bo->kmap.bo) 839 ttm_bo_kunmap(&bo->kmap); 840 } 841 842 /** 843 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 844 * @bo: &amdgpu_bo buffer object 845 * 846 * References the contained &ttm_buffer_object. 847 * 848 * Returns: 849 * a refcounted pointer to the &amdgpu_bo buffer object. 850 */ 851 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 852 { 853 if (bo == NULL) 854 return NULL; 855 856 ttm_bo_get(&bo->tbo); 857 return bo; 858 } 859 860 /** 861 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 862 * @bo: &amdgpu_bo buffer object 863 * 864 * Unreferences the contained &ttm_buffer_object and clear the pointer 865 */ 866 void amdgpu_bo_unref(struct amdgpu_bo **bo) 867 { 868 struct ttm_buffer_object *tbo; 869 870 if ((*bo) == NULL) 871 return; 872 873 tbo = &((*bo)->tbo); 874 ttm_bo_put(tbo); 875 *bo = NULL; 876 } 877 878 /** 879 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 880 * @bo: &amdgpu_bo buffer object to be pinned 881 * @domain: domain to be pinned to 882 * @min_offset: the start of requested address range 883 * @max_offset: the end of requested address range 884 * 885 * Pins the buffer object according to requested domain and address range. If 886 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 887 * pin_count and pin_size accordingly. 888 * 889 * Pinning means to lock pages in memory along with keeping them at a fixed 890 * offset. It is required when a buffer can not be moved, for example, when 891 * a display buffer is being scanned out. 892 * 893 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 894 * where to pin a buffer if there are specific restrictions on where a buffer 895 * must be located. 896 * 897 * Returns: 898 * 0 for success or a negative error code on failure. 899 */ 900 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 901 u64 min_offset, u64 max_offset) 902 { 903 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 904 struct ttm_operation_ctx ctx = { false, false }; 905 int r, i; 906 907 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 908 return -EPERM; 909 910 if (WARN_ON_ONCE(min_offset > max_offset)) 911 return -EINVAL; 912 913 /* Check domain to be pinned to against preferred domains */ 914 if (bo->preferred_domains & domain) 915 domain = bo->preferred_domains & domain; 916 917 /* A shared bo cannot be migrated to VRAM */ 918 if (bo->tbo.base.import_attach) { 919 if (domain & AMDGPU_GEM_DOMAIN_GTT) 920 domain = AMDGPU_GEM_DOMAIN_GTT; 921 else 922 return -EINVAL; 923 } 924 925 if (bo->tbo.pin_count) { 926 uint32_t mem_type = bo->tbo.resource->mem_type; 927 uint32_t mem_flags = bo->tbo.resource->placement; 928 929 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 930 return -EINVAL; 931 932 if ((mem_type == TTM_PL_VRAM) && 933 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 934 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 935 return -EINVAL; 936 937 ttm_bo_pin(&bo->tbo); 938 939 if (max_offset != 0) { 940 u64 domain_start = amdgpu_ttm_domain_start(adev, 941 mem_type); 942 WARN_ON_ONCE(max_offset < 943 (amdgpu_bo_gpu_offset(bo) - domain_start)); 944 } 945 946 return 0; 947 } 948 949 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 950 * See function amdgpu_display_supported_domains() 951 */ 952 domain = amdgpu_bo_get_preferred_domain(adev, domain); 953 954 if (bo->tbo.base.import_attach) 955 dma_buf_pin(bo->tbo.base.import_attach); 956 957 /* force to pin into visible video ram */ 958 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 959 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 960 amdgpu_bo_placement_from_domain(bo, domain); 961 for (i = 0; i < bo->placement.num_placement; i++) { 962 unsigned int fpfn, lpfn; 963 964 fpfn = min_offset >> PAGE_SHIFT; 965 lpfn = max_offset >> PAGE_SHIFT; 966 967 if (fpfn > bo->placements[i].fpfn) 968 bo->placements[i].fpfn = fpfn; 969 if (!bo->placements[i].lpfn || 970 (lpfn && lpfn < bo->placements[i].lpfn)) 971 bo->placements[i].lpfn = lpfn; 972 973 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && 974 bo->placements[i].mem_type == TTM_PL_VRAM) 975 bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 976 } 977 978 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 979 if (unlikely(r)) { 980 dev_err(adev->dev, "%p pin failed\n", bo); 981 goto error; 982 } 983 984 ttm_bo_pin(&bo->tbo); 985 986 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 987 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 988 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 989 &adev->visible_pin_size); 990 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 991 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 992 } 993 994 error: 995 return r; 996 } 997 998 /** 999 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 1000 * @bo: &amdgpu_bo buffer object to be pinned 1001 * @domain: domain to be pinned to 1002 * 1003 * A simple wrapper to amdgpu_bo_pin_restricted(). 1004 * Provides a simpler API for buffers that do not have any strict restrictions 1005 * on where a buffer must be located. 1006 * 1007 * Returns: 1008 * 0 for success or a negative error code on failure. 1009 */ 1010 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 1011 { 1012 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1013 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1014 } 1015 1016 /** 1017 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1018 * @bo: &amdgpu_bo buffer object to be unpinned 1019 * 1020 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1021 * Changes placement and pin size accordingly. 1022 * 1023 * Returns: 1024 * 0 for success or a negative error code on failure. 1025 */ 1026 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1027 { 1028 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1029 1030 ttm_bo_unpin(&bo->tbo); 1031 if (bo->tbo.pin_count) 1032 return; 1033 1034 if (bo->tbo.base.import_attach) 1035 dma_buf_unpin(bo->tbo.base.import_attach); 1036 1037 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1038 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1039 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1040 &adev->visible_pin_size); 1041 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1042 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1043 } 1044 1045 } 1046 1047 static const char * const amdgpu_vram_names[] = { 1048 "UNKNOWN", 1049 "GDDR1", 1050 "DDR2", 1051 "GDDR3", 1052 "GDDR4", 1053 "GDDR5", 1054 "HBM", 1055 "DDR3", 1056 "DDR4", 1057 "GDDR6", 1058 "DDR5", 1059 "LPDDR4", 1060 "LPDDR5" 1061 }; 1062 1063 /** 1064 * amdgpu_bo_init - initialize memory manager 1065 * @adev: amdgpu device object 1066 * 1067 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1068 * 1069 * Returns: 1070 * 0 for success or a negative error code on failure. 1071 */ 1072 int amdgpu_bo_init(struct amdgpu_device *adev) 1073 { 1074 /* On A+A platform, VRAM can be mapped as WB */ 1075 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1076 /* reserve PAT memory space to WC for VRAM */ 1077 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1078 adev->gmc.aper_size); 1079 1080 if (r) { 1081 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1082 return r; 1083 } 1084 1085 /* Add an MTRR for the VRAM */ 1086 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1087 adev->gmc.aper_size); 1088 } 1089 1090 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1091 adev->gmc.mc_vram_size >> 20, 1092 (unsigned long long)adev->gmc.aper_size >> 20); 1093 DRM_INFO("RAM width %dbits %s\n", 1094 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1095 return amdgpu_ttm_init(adev); 1096 } 1097 1098 /** 1099 * amdgpu_bo_fini - tear down memory manager 1100 * @adev: amdgpu device object 1101 * 1102 * Reverses amdgpu_bo_init() to tear down memory manager. 1103 */ 1104 void amdgpu_bo_fini(struct amdgpu_device *adev) 1105 { 1106 int idx; 1107 1108 amdgpu_ttm_fini(adev); 1109 1110 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1111 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1112 arch_phys_wc_del(adev->gmc.vram_mtrr); 1113 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1114 } 1115 drm_dev_exit(idx); 1116 } 1117 } 1118 1119 /** 1120 * amdgpu_bo_set_tiling_flags - set tiling flags 1121 * @bo: &amdgpu_bo buffer object 1122 * @tiling_flags: new flags 1123 * 1124 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1125 * kernel driver to set the tiling flags on a buffer. 1126 * 1127 * Returns: 1128 * 0 for success or a negative error code on failure. 1129 */ 1130 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1131 { 1132 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1133 struct amdgpu_bo_user *ubo; 1134 1135 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1136 if (adev->family <= AMDGPU_FAMILY_CZ && 1137 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1138 return -EINVAL; 1139 1140 ubo = to_amdgpu_bo_user(bo); 1141 ubo->tiling_flags = tiling_flags; 1142 return 0; 1143 } 1144 1145 /** 1146 * amdgpu_bo_get_tiling_flags - get tiling flags 1147 * @bo: &amdgpu_bo buffer object 1148 * @tiling_flags: returned flags 1149 * 1150 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1151 * set the tiling flags on a buffer. 1152 */ 1153 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1154 { 1155 struct amdgpu_bo_user *ubo; 1156 1157 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1158 dma_resv_assert_held(bo->tbo.base.resv); 1159 ubo = to_amdgpu_bo_user(bo); 1160 1161 if (tiling_flags) 1162 *tiling_flags = ubo->tiling_flags; 1163 } 1164 1165 /** 1166 * amdgpu_bo_set_metadata - set metadata 1167 * @bo: &amdgpu_bo buffer object 1168 * @metadata: new metadata 1169 * @metadata_size: size of the new metadata 1170 * @flags: flags of the new metadata 1171 * 1172 * Sets buffer object's metadata, its size and flags. 1173 * Used via GEM ioctl. 1174 * 1175 * Returns: 1176 * 0 for success or a negative error code on failure. 1177 */ 1178 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1179 u32 metadata_size, uint64_t flags) 1180 { 1181 struct amdgpu_bo_user *ubo; 1182 void *buffer; 1183 1184 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1185 ubo = to_amdgpu_bo_user(bo); 1186 if (!metadata_size) { 1187 if (ubo->metadata_size) { 1188 kfree(ubo->metadata); 1189 ubo->metadata = NULL; 1190 ubo->metadata_size = 0; 1191 } 1192 return 0; 1193 } 1194 1195 if (metadata == NULL) 1196 return -EINVAL; 1197 1198 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1199 if (buffer == NULL) 1200 return -ENOMEM; 1201 1202 kfree(ubo->metadata); 1203 ubo->metadata_flags = flags; 1204 ubo->metadata = buffer; 1205 ubo->metadata_size = metadata_size; 1206 1207 return 0; 1208 } 1209 1210 /** 1211 * amdgpu_bo_get_metadata - get metadata 1212 * @bo: &amdgpu_bo buffer object 1213 * @buffer: returned metadata 1214 * @buffer_size: size of the buffer 1215 * @metadata_size: size of the returned metadata 1216 * @flags: flags of the returned metadata 1217 * 1218 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1219 * less than metadata_size. 1220 * Used via GEM ioctl. 1221 * 1222 * Returns: 1223 * 0 for success or a negative error code on failure. 1224 */ 1225 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1226 size_t buffer_size, uint32_t *metadata_size, 1227 uint64_t *flags) 1228 { 1229 struct amdgpu_bo_user *ubo; 1230 1231 if (!buffer && !metadata_size) 1232 return -EINVAL; 1233 1234 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1235 ubo = to_amdgpu_bo_user(bo); 1236 if (metadata_size) 1237 *metadata_size = ubo->metadata_size; 1238 1239 if (buffer) { 1240 if (buffer_size < ubo->metadata_size) 1241 return -EINVAL; 1242 1243 if (ubo->metadata_size) 1244 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1245 } 1246 1247 if (flags) 1248 *flags = ubo->metadata_flags; 1249 1250 return 0; 1251 } 1252 1253 /** 1254 * amdgpu_bo_move_notify - notification about a memory move 1255 * @bo: pointer to a buffer object 1256 * @evict: if this move is evicting the buffer from the graphics address space 1257 * @new_mem: new resource for backing the BO 1258 * 1259 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1260 * bookkeeping. 1261 * TTM driver callback which is called when ttm moves a buffer. 1262 */ 1263 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1264 bool evict, 1265 struct ttm_resource *new_mem) 1266 { 1267 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1268 struct ttm_resource *old_mem = bo->resource; 1269 struct amdgpu_bo *abo; 1270 1271 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1272 return; 1273 1274 abo = ttm_to_amdgpu_bo(bo); 1275 amdgpu_vm_bo_invalidate(adev, abo, evict); 1276 1277 amdgpu_bo_kunmap(abo); 1278 1279 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1280 old_mem && old_mem->mem_type != TTM_PL_SYSTEM) 1281 dma_buf_move_notify(abo->tbo.base.dma_buf); 1282 1283 /* move_notify is called before move happens */ 1284 trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, 1285 old_mem ? old_mem->mem_type : -1); 1286 } 1287 1288 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1289 struct amdgpu_mem_stats *stats) 1290 { 1291 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1292 struct ttm_resource *res = bo->tbo.resource; 1293 uint64_t size = amdgpu_bo_size(bo); 1294 struct drm_gem_object *obj; 1295 bool shared; 1296 1297 /* Abort if the BO doesn't currently have a backing store */ 1298 if (!res) 1299 return; 1300 1301 obj = &bo->tbo.base; 1302 shared = drm_gem_object_is_shared_for_memory_stats(obj); 1303 1304 switch (res->mem_type) { 1305 case TTM_PL_VRAM: 1306 stats->vram += size; 1307 if (amdgpu_res_cpu_visible(adev, res)) 1308 stats->visible_vram += size; 1309 if (shared) 1310 stats->vram_shared += size; 1311 break; 1312 case TTM_PL_TT: 1313 stats->gtt += size; 1314 if (shared) 1315 stats->gtt_shared += size; 1316 break; 1317 case TTM_PL_SYSTEM: 1318 default: 1319 stats->cpu += size; 1320 if (shared) 1321 stats->cpu_shared += size; 1322 break; 1323 } 1324 1325 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1326 stats->requested_vram += size; 1327 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1328 stats->requested_visible_vram += size; 1329 1330 if (res->mem_type != TTM_PL_VRAM) { 1331 stats->evicted_vram += size; 1332 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1333 stats->evicted_visible_vram += size; 1334 } 1335 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1336 stats->requested_gtt += size; 1337 } 1338 } 1339 1340 /** 1341 * amdgpu_bo_release_notify - notification about a BO being released 1342 * @bo: pointer to a buffer object 1343 * 1344 * Wipes VRAM buffers whose contents should not be leaked before the 1345 * memory is released. 1346 */ 1347 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1348 { 1349 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1350 struct dma_fence *fence = NULL; 1351 struct amdgpu_bo *abo; 1352 int r; 1353 1354 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1355 return; 1356 1357 abo = ttm_to_amdgpu_bo(bo); 1358 1359 WARN_ON(abo->vm_bo); 1360 1361 if (abo->kfd_bo) 1362 amdgpu_amdkfd_release_notify(abo); 1363 1364 /* We only remove the fence if the resv has individualized. */ 1365 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1366 && bo->base.resv != &bo->base._resv); 1367 if (bo->base.resv == &bo->base._resv) 1368 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1369 1370 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1371 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1372 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1373 return; 1374 1375 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1376 return; 1377 1378 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence, true); 1379 if (!WARN_ON(r)) { 1380 amdgpu_bo_fence(abo, fence, false); 1381 dma_fence_put(fence); 1382 } 1383 1384 dma_resv_unlock(bo->base.resv); 1385 } 1386 1387 /** 1388 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1389 * @bo: pointer to a buffer object 1390 * 1391 * Notifies the driver we are taking a fault on this BO and have reserved it, 1392 * also performs bookkeeping. 1393 * TTM driver callback for dealing with vm faults. 1394 * 1395 * Returns: 1396 * 0 for success or a negative error code on failure. 1397 */ 1398 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1399 { 1400 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1401 struct ttm_operation_ctx ctx = { false, false }; 1402 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1403 int r; 1404 1405 /* Remember that this BO was accessed by the CPU */ 1406 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1407 1408 if (amdgpu_res_cpu_visible(adev, bo->resource)) 1409 return 0; 1410 1411 /* Can't move a pinned BO to visible VRAM */ 1412 if (abo->tbo.pin_count > 0) 1413 return VM_FAULT_SIGBUS; 1414 1415 /* hurrah the memory is not visible ! */ 1416 atomic64_inc(&adev->num_vram_cpu_page_faults); 1417 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1418 AMDGPU_GEM_DOMAIN_GTT); 1419 1420 /* Avoid costly evictions; only set GTT as a busy placement */ 1421 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 1422 1423 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1424 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1425 return VM_FAULT_NOPAGE; 1426 else if (unlikely(r)) 1427 return VM_FAULT_SIGBUS; 1428 1429 /* this should never happen */ 1430 if (bo->resource->mem_type == TTM_PL_VRAM && 1431 !amdgpu_res_cpu_visible(adev, bo->resource)) 1432 return VM_FAULT_SIGBUS; 1433 1434 ttm_bo_move_to_lru_tail_unlocked(bo); 1435 return 0; 1436 } 1437 1438 /** 1439 * amdgpu_bo_fence - add fence to buffer object 1440 * 1441 * @bo: buffer object in question 1442 * @fence: fence to add 1443 * @shared: true if fence should be added shared 1444 * 1445 */ 1446 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1447 bool shared) 1448 { 1449 struct dma_resv *resv = bo->tbo.base.resv; 1450 int r; 1451 1452 r = dma_resv_reserve_fences(resv, 1); 1453 if (r) { 1454 /* As last resort on OOM we block for the fence */ 1455 dma_fence_wait(fence, false); 1456 return; 1457 } 1458 1459 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1460 DMA_RESV_USAGE_WRITE); 1461 } 1462 1463 /** 1464 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1465 * 1466 * @adev: amdgpu device pointer 1467 * @resv: reservation object to sync to 1468 * @sync_mode: synchronization mode 1469 * @owner: fence owner 1470 * @intr: Whether the wait is interruptible 1471 * 1472 * Extract the fences from the reservation object and waits for them to finish. 1473 * 1474 * Returns: 1475 * 0 on success, errno otherwise. 1476 */ 1477 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1478 enum amdgpu_sync_mode sync_mode, void *owner, 1479 bool intr) 1480 { 1481 struct amdgpu_sync sync; 1482 int r; 1483 1484 amdgpu_sync_create(&sync); 1485 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1486 r = amdgpu_sync_wait(&sync, intr); 1487 amdgpu_sync_free(&sync); 1488 return r; 1489 } 1490 1491 /** 1492 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1493 * @bo: buffer object to wait for 1494 * @owner: fence owner 1495 * @intr: Whether the wait is interruptible 1496 * 1497 * Wrapper to wait for fences in a BO. 1498 * Returns: 1499 * 0 on success, errno otherwise. 1500 */ 1501 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1502 { 1503 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1504 1505 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1506 AMDGPU_SYNC_NE_OWNER, owner, intr); 1507 } 1508 1509 /** 1510 * amdgpu_bo_gpu_offset - return GPU offset of bo 1511 * @bo: amdgpu object for which we query the offset 1512 * 1513 * Note: object should either be pinned or reserved when calling this 1514 * function, it might be useful to add check for this for debugging. 1515 * 1516 * Returns: 1517 * current GPU offset of the object. 1518 */ 1519 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1520 { 1521 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1522 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1523 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1524 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1525 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1526 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1527 1528 return amdgpu_bo_gpu_offset_no_check(bo); 1529 } 1530 1531 /** 1532 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1533 * @bo: amdgpu object for which we query the offset 1534 * 1535 * Returns: 1536 * current GPU offset of the object without raising warnings. 1537 */ 1538 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1539 { 1540 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1541 uint64_t offset = AMDGPU_BO_INVALID_OFFSET; 1542 1543 if (bo->tbo.resource->mem_type == TTM_PL_TT) 1544 offset = amdgpu_gmc_agp_addr(&bo->tbo); 1545 1546 if (offset == AMDGPU_BO_INVALID_OFFSET) 1547 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1548 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1549 1550 return amdgpu_gmc_sign_extend(offset); 1551 } 1552 1553 /** 1554 * amdgpu_bo_get_preferred_domain - get preferred domain 1555 * @adev: amdgpu device object 1556 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1557 * 1558 * Returns: 1559 * Which of the allowed domains is preferred for allocating the BO. 1560 */ 1561 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1562 uint32_t domain) 1563 { 1564 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1565 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1566 domain = AMDGPU_GEM_DOMAIN_VRAM; 1567 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1568 domain = AMDGPU_GEM_DOMAIN_GTT; 1569 } 1570 return domain; 1571 } 1572 1573 #if defined(CONFIG_DEBUG_FS) 1574 #define amdgpu_bo_print_flag(m, bo, flag) \ 1575 do { \ 1576 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1577 seq_printf((m), " " #flag); \ 1578 } \ 1579 } while (0) 1580 1581 /** 1582 * amdgpu_bo_print_info - print BO info in debugfs file 1583 * 1584 * @id: Index or Id of the BO 1585 * @bo: Requested BO for printing info 1586 * @m: debugfs file 1587 * 1588 * Print BO information in debugfs file 1589 * 1590 * Returns: 1591 * Size of the BO in bytes. 1592 */ 1593 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1594 { 1595 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1596 struct dma_buf_attachment *attachment; 1597 struct dma_buf *dma_buf; 1598 const char *placement; 1599 unsigned int pin_count; 1600 u64 size; 1601 1602 if (dma_resv_trylock(bo->tbo.base.resv)) { 1603 1604 switch (bo->tbo.resource->mem_type) { 1605 case TTM_PL_VRAM: 1606 if (amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 1607 placement = "VRAM VISIBLE"; 1608 else 1609 placement = "VRAM"; 1610 break; 1611 case TTM_PL_TT: 1612 placement = "GTT"; 1613 break; 1614 case AMDGPU_PL_GDS: 1615 placement = "GDS"; 1616 break; 1617 case AMDGPU_PL_GWS: 1618 placement = "GWS"; 1619 break; 1620 case AMDGPU_PL_OA: 1621 placement = "OA"; 1622 break; 1623 case AMDGPU_PL_PREEMPT: 1624 placement = "PREEMPTIBLE"; 1625 break; 1626 case AMDGPU_PL_DOORBELL: 1627 placement = "DOORBELL"; 1628 break; 1629 case TTM_PL_SYSTEM: 1630 default: 1631 placement = "CPU"; 1632 break; 1633 } 1634 dma_resv_unlock(bo->tbo.base.resv); 1635 } else { 1636 placement = "UNKNOWN"; 1637 } 1638 1639 size = amdgpu_bo_size(bo); 1640 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1641 id, size, placement); 1642 1643 pin_count = READ_ONCE(bo->tbo.pin_count); 1644 if (pin_count) 1645 seq_printf(m, " pin count %d", pin_count); 1646 1647 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1648 attachment = READ_ONCE(bo->tbo.base.import_attach); 1649 1650 if (attachment) 1651 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1652 else if (dma_buf) 1653 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1654 1655 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1656 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1657 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1658 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1659 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1660 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1661 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1662 1663 seq_puts(m, "\n"); 1664 1665 return size; 1666 } 1667 #endif 1668