1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_vram_mgr.h" 43 44 /** 45 * DOC: amdgpu_object 46 * 47 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 48 * represents memory used by driver (VRAM, system memory, etc.). The driver 49 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 50 * to create/destroy/set buffer object which are then managed by the kernel TTM 51 * memory manager. 52 * The interfaces are also used internally by kernel clients, including gfx, 53 * uvd, etc. for kernel managed allocations used by the GPU. 54 * 55 */ 56 57 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 58 { 59 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 60 61 amdgpu_bo_kunmap(bo); 62 63 if (bo->tbo.base.import_attach) 64 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 65 drm_gem_object_release(&bo->tbo.base); 66 amdgpu_bo_unref(&bo->parent); 67 kvfree(bo); 68 } 69 70 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 71 { 72 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 73 struct amdgpu_bo_user *ubo; 74 75 ubo = to_amdgpu_bo_user(bo); 76 kfree(ubo->metadata); 77 amdgpu_bo_destroy(tbo); 78 } 79 80 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 81 { 82 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 83 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; 84 struct amdgpu_bo_vm *vmbo; 85 86 bo = shadow_bo->parent; 87 vmbo = to_amdgpu_bo_vm(bo); 88 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 89 if (!list_empty(&vmbo->shadow_list)) { 90 mutex_lock(&adev->shadow_list_lock); 91 list_del_init(&vmbo->shadow_list); 92 mutex_unlock(&adev->shadow_list_lock); 93 } 94 95 amdgpu_bo_destroy(tbo); 96 } 97 98 /** 99 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 100 * @bo: buffer object to be checked 101 * 102 * Uses destroy function associated with the object to determine if this is 103 * an &amdgpu_bo. 104 * 105 * Returns: 106 * true if the object belongs to &amdgpu_bo, false if not. 107 */ 108 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 109 { 110 if (bo->destroy == &amdgpu_bo_destroy || 111 bo->destroy == &amdgpu_bo_user_destroy || 112 bo->destroy == &amdgpu_bo_vm_destroy) 113 return true; 114 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 137 138 if (adev->gmc.mem_partitions && mem_id >= 0) { 139 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 140 /* 141 * memory partition range lpfn is inclusive start + size - 1 142 * TTM place lpfn is exclusive start + size 143 */ 144 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 145 } else { 146 places[c].fpfn = 0; 147 places[c].lpfn = 0; 148 } 149 places[c].mem_type = TTM_PL_VRAM; 150 places[c].flags = 0; 151 152 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 153 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 154 else 155 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 156 157 if (abo->tbo.type == ttm_bo_type_kernel && 158 flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 159 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 160 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { 165 places[c].fpfn = 0; 166 places[c].lpfn = 0; 167 places[c].mem_type = AMDGPU_PL_DOORBELL; 168 places[c].flags = 0; 169 c++; 170 } 171 172 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 173 places[c].fpfn = 0; 174 places[c].lpfn = 0; 175 places[c].mem_type = 176 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 177 AMDGPU_PL_PREEMPT : TTM_PL_TT; 178 places[c].flags = 0; 179 /* 180 * When GTT is just an alternative to VRAM make sure that we 181 * only use it as fallback and still try to fill up VRAM first. 182 */ 183 if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) 184 places[c].flags |= TTM_PL_FLAG_FALLBACK; 185 c++; 186 } 187 188 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 189 places[c].fpfn = 0; 190 places[c].lpfn = 0; 191 places[c].mem_type = TTM_PL_SYSTEM; 192 places[c].flags = 0; 193 c++; 194 } 195 196 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 197 places[c].fpfn = 0; 198 places[c].lpfn = 0; 199 places[c].mem_type = AMDGPU_PL_GDS; 200 places[c].flags = 0; 201 c++; 202 } 203 204 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 205 places[c].fpfn = 0; 206 places[c].lpfn = 0; 207 places[c].mem_type = AMDGPU_PL_GWS; 208 places[c].flags = 0; 209 c++; 210 } 211 212 if (domain & AMDGPU_GEM_DOMAIN_OA) { 213 places[c].fpfn = 0; 214 places[c].lpfn = 0; 215 places[c].mem_type = AMDGPU_PL_OA; 216 places[c].flags = 0; 217 c++; 218 } 219 220 if (!c) { 221 places[c].fpfn = 0; 222 places[c].lpfn = 0; 223 places[c].mem_type = TTM_PL_SYSTEM; 224 places[c].flags = 0; 225 c++; 226 } 227 228 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 229 230 placement->num_placement = c; 231 placement->placement = places; 232 } 233 234 /** 235 * amdgpu_bo_create_reserved - create reserved BO for kernel use 236 * 237 * @adev: amdgpu device object 238 * @size: size for the new BO 239 * @align: alignment for the new BO 240 * @domain: where to place it 241 * @bo_ptr: used to initialize BOs in structures 242 * @gpu_addr: GPU addr of the pinned BO 243 * @cpu_addr: optional CPU address mapping 244 * 245 * Allocates and pins a BO for kernel internal use, and returns it still 246 * reserved. 247 * 248 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 249 * 250 * Returns: 251 * 0 on success, negative error code otherwise. 252 */ 253 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 254 unsigned long size, int align, 255 u32 domain, struct amdgpu_bo **bo_ptr, 256 u64 *gpu_addr, void **cpu_addr) 257 { 258 struct amdgpu_bo_param bp; 259 bool free = false; 260 int r; 261 262 if (!size) { 263 amdgpu_bo_unref(bo_ptr); 264 return 0; 265 } 266 267 memset(&bp, 0, sizeof(bp)); 268 bp.size = size; 269 bp.byte_align = align; 270 bp.domain = domain; 271 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 272 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 273 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 274 bp.type = ttm_bo_type_kernel; 275 bp.resv = NULL; 276 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 277 278 if (!*bo_ptr) { 279 r = amdgpu_bo_create(adev, &bp, bo_ptr); 280 if (r) { 281 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 282 r); 283 return r; 284 } 285 free = true; 286 } 287 288 r = amdgpu_bo_reserve(*bo_ptr, false); 289 if (r) { 290 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 291 goto error_free; 292 } 293 294 r = amdgpu_bo_pin(*bo_ptr, domain); 295 if (r) { 296 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 297 goto error_unreserve; 298 } 299 300 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 301 if (r) { 302 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 303 goto error_unpin; 304 } 305 306 if (gpu_addr) 307 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 308 309 if (cpu_addr) { 310 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 311 if (r) { 312 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 313 goto error_unpin; 314 } 315 } 316 317 return 0; 318 319 error_unpin: 320 amdgpu_bo_unpin(*bo_ptr); 321 error_unreserve: 322 amdgpu_bo_unreserve(*bo_ptr); 323 324 error_free: 325 if (free) 326 amdgpu_bo_unref(bo_ptr); 327 328 return r; 329 } 330 331 /** 332 * amdgpu_bo_create_kernel - create BO for kernel use 333 * 334 * @adev: amdgpu device object 335 * @size: size for the new BO 336 * @align: alignment for the new BO 337 * @domain: where to place it 338 * @bo_ptr: used to initialize BOs in structures 339 * @gpu_addr: GPU addr of the pinned BO 340 * @cpu_addr: optional CPU address mapping 341 * 342 * Allocates and pins a BO for kernel internal use. 343 * 344 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 345 * 346 * Returns: 347 * 0 on success, negative error code otherwise. 348 */ 349 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 350 unsigned long size, int align, 351 u32 domain, struct amdgpu_bo **bo_ptr, 352 u64 *gpu_addr, void **cpu_addr) 353 { 354 int r; 355 356 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 357 gpu_addr, cpu_addr); 358 359 if (r) 360 return r; 361 362 if (*bo_ptr) 363 amdgpu_bo_unreserve(*bo_ptr); 364 365 return 0; 366 } 367 368 /** 369 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 370 * 371 * @adev: amdgpu device object 372 * @offset: offset of the BO 373 * @size: size of the BO 374 * @bo_ptr: used to initialize BOs in structures 375 * @cpu_addr: optional CPU address mapping 376 * 377 * Creates a kernel BO at a specific offset in VRAM. 378 * 379 * Returns: 380 * 0 on success, negative error code otherwise. 381 */ 382 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 383 uint64_t offset, uint64_t size, 384 struct amdgpu_bo **bo_ptr, void **cpu_addr) 385 { 386 struct ttm_operation_ctx ctx = { false, false }; 387 unsigned int i; 388 int r; 389 390 offset &= PAGE_MASK; 391 size = ALIGN(size, PAGE_SIZE); 392 393 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 394 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 395 cpu_addr); 396 if (r) 397 return r; 398 399 if ((*bo_ptr) == NULL) 400 return 0; 401 402 /* 403 * Remove the original mem node and create a new one at the request 404 * position. 405 */ 406 if (cpu_addr) 407 amdgpu_bo_kunmap(*bo_ptr); 408 409 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 410 411 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 412 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 413 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 414 } 415 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 416 &(*bo_ptr)->tbo.resource, &ctx); 417 if (r) 418 goto error; 419 420 if (cpu_addr) { 421 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 422 if (r) 423 goto error; 424 } 425 426 amdgpu_bo_unreserve(*bo_ptr); 427 return 0; 428 429 error: 430 amdgpu_bo_unreserve(*bo_ptr); 431 amdgpu_bo_unref(bo_ptr); 432 return r; 433 } 434 435 /** 436 * amdgpu_bo_free_kernel - free BO for kernel use 437 * 438 * @bo: amdgpu BO to free 439 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 440 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 441 * 442 * unmaps and unpin a BO for kernel internal use. 443 */ 444 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 445 void **cpu_addr) 446 { 447 if (*bo == NULL) 448 return; 449 450 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 451 452 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 453 if (cpu_addr) 454 amdgpu_bo_kunmap(*bo); 455 456 amdgpu_bo_unpin(*bo); 457 amdgpu_bo_unreserve(*bo); 458 } 459 amdgpu_bo_unref(bo); 460 461 if (gpu_addr) 462 *gpu_addr = 0; 463 464 if (cpu_addr) 465 *cpu_addr = NULL; 466 } 467 468 /* Validate bo size is bit bigger than the request domain */ 469 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 470 unsigned long size, u32 domain) 471 { 472 struct ttm_resource_manager *man = NULL; 473 474 /* 475 * If GTT is part of requested domains the check must succeed to 476 * allow fall back to GTT. 477 */ 478 if (domain & AMDGPU_GEM_DOMAIN_GTT) 479 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 480 else if (domain & AMDGPU_GEM_DOMAIN_VRAM) 481 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 482 else 483 return true; 484 485 if (!man) { 486 if (domain & AMDGPU_GEM_DOMAIN_GTT) 487 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 488 return false; 489 } 490 491 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */ 492 if (size < man->size) 493 return true; 494 495 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size); 496 return false; 497 } 498 499 bool amdgpu_bo_support_uswc(u64 bo_flags) 500 { 501 502 #ifdef CONFIG_X86_32 503 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 504 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 505 */ 506 return false; 507 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 508 /* Don't try to enable write-combining when it can't work, or things 509 * may be slow 510 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 511 */ 512 513 #ifndef CONFIG_COMPILE_TEST 514 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 515 thanks to write-combining 516 #endif 517 518 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 519 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 520 "better performance thanks to write-combining\n"); 521 return false; 522 #else 523 /* For architectures that don't support WC memory, 524 * mask out the WC flag from the BO 525 */ 526 if (!drm_arch_can_wc_memory()) 527 return false; 528 529 return true; 530 #endif 531 } 532 533 /** 534 * amdgpu_bo_create - create an &amdgpu_bo buffer object 535 * @adev: amdgpu device object 536 * @bp: parameters to be used for the buffer object 537 * @bo_ptr: pointer to the buffer object pointer 538 * 539 * Creates an &amdgpu_bo buffer object. 540 * 541 * Returns: 542 * 0 for success or a negative error code on failure. 543 */ 544 int amdgpu_bo_create(struct amdgpu_device *adev, 545 struct amdgpu_bo_param *bp, 546 struct amdgpu_bo **bo_ptr) 547 { 548 struct ttm_operation_ctx ctx = { 549 .interruptible = (bp->type != ttm_bo_type_kernel), 550 .no_wait_gpu = bp->no_wait_gpu, 551 /* We opt to avoid OOM on system pages allocations */ 552 .gfp_retry_mayfail = true, 553 .allow_res_evict = bp->type != ttm_bo_type_kernel, 554 .resv = bp->resv 555 }; 556 struct amdgpu_bo *bo; 557 unsigned long page_align, size = bp->size; 558 int r; 559 560 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 561 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 562 /* GWS and OA don't need any alignment. */ 563 page_align = bp->byte_align; 564 size <<= PAGE_SHIFT; 565 566 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 567 /* Both size and alignment must be a multiple of 4. */ 568 page_align = ALIGN(bp->byte_align, 4); 569 size = ALIGN(size, 4) << PAGE_SHIFT; 570 } else { 571 /* Memory should be aligned at least to a page size. */ 572 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 573 size = ALIGN(size, PAGE_SIZE); 574 } 575 576 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 577 return -ENOMEM; 578 579 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 580 581 *bo_ptr = NULL; 582 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 583 if (bo == NULL) 584 return -ENOMEM; 585 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 586 bo->vm_bo = NULL; 587 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 588 bp->domain; 589 bo->allowed_domains = bo->preferred_domains; 590 if (bp->type != ttm_bo_type_kernel && 591 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 592 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 593 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 594 595 bo->flags = bp->flags; 596 597 if (adev->gmc.mem_partitions) 598 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 599 bo->xcp_id = bp->xcp_id_plus1 - 1; 600 else 601 /* For GPUs without spatial partitioning */ 602 bo->xcp_id = 0; 603 604 if (!amdgpu_bo_support_uswc(bo->flags)) 605 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 606 607 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 608 609 bo->tbo.bdev = &adev->mman.bdev; 610 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 611 AMDGPU_GEM_DOMAIN_GDS)) 612 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 613 else 614 amdgpu_bo_placement_from_domain(bo, bp->domain); 615 if (bp->type == ttm_bo_type_kernel) 616 bo->tbo.priority = 2; 617 else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE)) 618 bo->tbo.priority = 1; 619 620 if (!bp->destroy) 621 bp->destroy = &amdgpu_bo_destroy; 622 623 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 624 &bo->placement, page_align, &ctx, NULL, 625 bp->resv, bp->destroy); 626 if (unlikely(r != 0)) 627 return r; 628 629 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 630 amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 631 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 632 ctx.bytes_moved); 633 else 634 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 635 636 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 637 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 638 struct dma_fence *fence; 639 640 r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); 641 if (unlikely(r)) 642 goto fail_unreserve; 643 644 dma_resv_add_fence(bo->tbo.base.resv, fence, 645 DMA_RESV_USAGE_KERNEL); 646 dma_fence_put(fence); 647 } 648 if (!bp->resv) 649 amdgpu_bo_unreserve(bo); 650 *bo_ptr = bo; 651 652 trace_amdgpu_bo_create(bo); 653 654 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 655 if (bp->type == ttm_bo_type_device) 656 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 657 658 return 0; 659 660 fail_unreserve: 661 if (!bp->resv) 662 dma_resv_unlock(bo->tbo.base.resv); 663 amdgpu_bo_unref(&bo); 664 return r; 665 } 666 667 /** 668 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 669 * @adev: amdgpu device object 670 * @bp: parameters to be used for the buffer object 671 * @ubo_ptr: pointer to the buffer object pointer 672 * 673 * Create a BO to be used by user application; 674 * 675 * Returns: 676 * 0 for success or a negative error code on failure. 677 */ 678 679 int amdgpu_bo_create_user(struct amdgpu_device *adev, 680 struct amdgpu_bo_param *bp, 681 struct amdgpu_bo_user **ubo_ptr) 682 { 683 struct amdgpu_bo *bo_ptr; 684 int r; 685 686 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 687 bp->destroy = &amdgpu_bo_user_destroy; 688 r = amdgpu_bo_create(adev, bp, &bo_ptr); 689 if (r) 690 return r; 691 692 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 693 return r; 694 } 695 696 /** 697 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 698 * @adev: amdgpu device object 699 * @bp: parameters to be used for the buffer object 700 * @vmbo_ptr: pointer to the buffer object pointer 701 * 702 * Create a BO to be for GPUVM. 703 * 704 * Returns: 705 * 0 for success or a negative error code on failure. 706 */ 707 708 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 709 struct amdgpu_bo_param *bp, 710 struct amdgpu_bo_vm **vmbo_ptr) 711 { 712 struct amdgpu_bo *bo_ptr; 713 int r; 714 715 /* bo_ptr_size will be determined by the caller and it depends on 716 * num of amdgpu_vm_pt entries. 717 */ 718 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 719 r = amdgpu_bo_create(adev, bp, &bo_ptr); 720 if (r) 721 return r; 722 723 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 724 return r; 725 } 726 727 /** 728 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 729 * 730 * @vmbo: BO that will be inserted into the shadow list 731 * 732 * Insert a BO to the shadow list. 733 */ 734 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 735 { 736 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 737 738 mutex_lock(&adev->shadow_list_lock); 739 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 740 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); 741 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; 742 mutex_unlock(&adev->shadow_list_lock); 743 } 744 745 /** 746 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 747 * 748 * @shadow: &amdgpu_bo shadow to be restored 749 * @fence: dma_fence associated with the operation 750 * 751 * Copies a buffer object's shadow content back to the object. 752 * This is used for recovering a buffer from its shadow in case of a gpu 753 * reset where vram context may be lost. 754 * 755 * Returns: 756 * 0 for success or a negative error code on failure. 757 */ 758 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 759 760 { 761 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 762 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 763 uint64_t shadow_addr, parent_addr; 764 765 shadow_addr = amdgpu_bo_gpu_offset(shadow); 766 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 767 768 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 769 amdgpu_bo_size(shadow), NULL, fence, 770 true, false, 0); 771 } 772 773 /** 774 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 775 * @bo: &amdgpu_bo buffer object to be mapped 776 * @ptr: kernel virtual address to be returned 777 * 778 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 779 * amdgpu_bo_kptr() to get the kernel virtual address. 780 * 781 * Returns: 782 * 0 for success or a negative error code on failure. 783 */ 784 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 785 { 786 void *kptr; 787 long r; 788 789 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 790 return -EPERM; 791 792 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 793 false, MAX_SCHEDULE_TIMEOUT); 794 if (r < 0) 795 return r; 796 797 kptr = amdgpu_bo_kptr(bo); 798 if (kptr) { 799 if (ptr) 800 *ptr = kptr; 801 return 0; 802 } 803 804 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 805 if (r) 806 return r; 807 808 if (ptr) 809 *ptr = amdgpu_bo_kptr(bo); 810 811 return 0; 812 } 813 814 /** 815 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 816 * @bo: &amdgpu_bo buffer object 817 * 818 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 819 * 820 * Returns: 821 * the virtual address of a buffer object area. 822 */ 823 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 824 { 825 bool is_iomem; 826 827 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 828 } 829 830 /** 831 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 832 * @bo: &amdgpu_bo buffer object to be unmapped 833 * 834 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 835 */ 836 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 837 { 838 if (bo->kmap.bo) 839 ttm_bo_kunmap(&bo->kmap); 840 } 841 842 /** 843 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 844 * @bo: &amdgpu_bo buffer object 845 * 846 * References the contained &ttm_buffer_object. 847 * 848 * Returns: 849 * a refcounted pointer to the &amdgpu_bo buffer object. 850 */ 851 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 852 { 853 if (bo == NULL) 854 return NULL; 855 856 ttm_bo_get(&bo->tbo); 857 return bo; 858 } 859 860 /** 861 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 862 * @bo: &amdgpu_bo buffer object 863 * 864 * Unreferences the contained &ttm_buffer_object and clear the pointer 865 */ 866 void amdgpu_bo_unref(struct amdgpu_bo **bo) 867 { 868 struct ttm_buffer_object *tbo; 869 870 if ((*bo) == NULL) 871 return; 872 873 tbo = &((*bo)->tbo); 874 ttm_bo_put(tbo); 875 *bo = NULL; 876 } 877 878 /** 879 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 880 * @bo: &amdgpu_bo buffer object to be pinned 881 * @domain: domain to be pinned to 882 * @min_offset: the start of requested address range 883 * @max_offset: the end of requested address range 884 * 885 * Pins the buffer object according to requested domain and address range. If 886 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 887 * pin_count and pin_size accordingly. 888 * 889 * Pinning means to lock pages in memory along with keeping them at a fixed 890 * offset. It is required when a buffer can not be moved, for example, when 891 * a display buffer is being scanned out. 892 * 893 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 894 * where to pin a buffer if there are specific restrictions on where a buffer 895 * must be located. 896 * 897 * Returns: 898 * 0 for success or a negative error code on failure. 899 */ 900 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 901 u64 min_offset, u64 max_offset) 902 { 903 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 904 struct ttm_operation_ctx ctx = { false, false }; 905 int r, i; 906 907 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 908 return -EPERM; 909 910 if (WARN_ON_ONCE(min_offset > max_offset)) 911 return -EINVAL; 912 913 /* Check domain to be pinned to against preferred domains */ 914 if (bo->preferred_domains & domain) 915 domain = bo->preferred_domains & domain; 916 917 /* A shared bo cannot be migrated to VRAM */ 918 if (bo->tbo.base.import_attach) { 919 if (domain & AMDGPU_GEM_DOMAIN_GTT) 920 domain = AMDGPU_GEM_DOMAIN_GTT; 921 else 922 return -EINVAL; 923 } 924 925 if (bo->tbo.pin_count) { 926 uint32_t mem_type = bo->tbo.resource->mem_type; 927 uint32_t mem_flags = bo->tbo.resource->placement; 928 929 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 930 return -EINVAL; 931 932 if ((mem_type == TTM_PL_VRAM) && 933 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 934 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 935 return -EINVAL; 936 937 ttm_bo_pin(&bo->tbo); 938 939 if (max_offset != 0) { 940 u64 domain_start = amdgpu_ttm_domain_start(adev, 941 mem_type); 942 WARN_ON_ONCE(max_offset < 943 (amdgpu_bo_gpu_offset(bo) - domain_start)); 944 } 945 946 return 0; 947 } 948 949 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 950 * See function amdgpu_display_supported_domains() 951 */ 952 domain = amdgpu_bo_get_preferred_domain(adev, domain); 953 954 if (bo->tbo.base.import_attach) 955 dma_buf_pin(bo->tbo.base.import_attach); 956 957 /* force to pin into visible video ram */ 958 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 959 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 960 amdgpu_bo_placement_from_domain(bo, domain); 961 for (i = 0; i < bo->placement.num_placement; i++) { 962 unsigned int fpfn, lpfn; 963 964 fpfn = min_offset >> PAGE_SHIFT; 965 lpfn = max_offset >> PAGE_SHIFT; 966 967 if (fpfn > bo->placements[i].fpfn) 968 bo->placements[i].fpfn = fpfn; 969 if (!bo->placements[i].lpfn || 970 (lpfn && lpfn < bo->placements[i].lpfn)) 971 bo->placements[i].lpfn = lpfn; 972 973 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && 974 bo->placements[i].mem_type == TTM_PL_VRAM) 975 bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 976 } 977 978 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 979 if (unlikely(r)) { 980 dev_err(adev->dev, "%p pin failed\n", bo); 981 goto error; 982 } 983 984 ttm_bo_pin(&bo->tbo); 985 986 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 987 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 988 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 989 &adev->visible_pin_size); 990 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 991 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 992 } 993 994 error: 995 return r; 996 } 997 998 /** 999 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 1000 * @bo: &amdgpu_bo buffer object to be pinned 1001 * @domain: domain to be pinned to 1002 * 1003 * A simple wrapper to amdgpu_bo_pin_restricted(). 1004 * Provides a simpler API for buffers that do not have any strict restrictions 1005 * on where a buffer must be located. 1006 * 1007 * Returns: 1008 * 0 for success or a negative error code on failure. 1009 */ 1010 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 1011 { 1012 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1013 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1014 } 1015 1016 /** 1017 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 1018 * @bo: &amdgpu_bo buffer object to be unpinned 1019 * 1020 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 1021 * Changes placement and pin size accordingly. 1022 * 1023 * Returns: 1024 * 0 for success or a negative error code on failure. 1025 */ 1026 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1027 { 1028 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1029 1030 ttm_bo_unpin(&bo->tbo); 1031 if (bo->tbo.pin_count) 1032 return; 1033 1034 if (bo->tbo.base.import_attach) 1035 dma_buf_unpin(bo->tbo.base.import_attach); 1036 1037 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1038 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1039 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1040 &adev->visible_pin_size); 1041 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1042 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1043 } 1044 1045 } 1046 1047 static const char * const amdgpu_vram_names[] = { 1048 "UNKNOWN", 1049 "GDDR1", 1050 "DDR2", 1051 "GDDR3", 1052 "GDDR4", 1053 "GDDR5", 1054 "HBM", 1055 "DDR3", 1056 "DDR4", 1057 "GDDR6", 1058 "DDR5", 1059 "LPDDR4", 1060 "LPDDR5" 1061 }; 1062 1063 /** 1064 * amdgpu_bo_init - initialize memory manager 1065 * @adev: amdgpu device object 1066 * 1067 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1068 * 1069 * Returns: 1070 * 0 for success or a negative error code on failure. 1071 */ 1072 int amdgpu_bo_init(struct amdgpu_device *adev) 1073 { 1074 /* On A+A platform, VRAM can be mapped as WB */ 1075 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1076 /* reserve PAT memory space to WC for VRAM */ 1077 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1078 adev->gmc.aper_size); 1079 1080 if (r) { 1081 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1082 return r; 1083 } 1084 1085 /* Add an MTRR for the VRAM */ 1086 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1087 adev->gmc.aper_size); 1088 } 1089 1090 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1091 adev->gmc.mc_vram_size >> 20, 1092 (unsigned long long)adev->gmc.aper_size >> 20); 1093 DRM_INFO("RAM width %dbits %s\n", 1094 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1095 return amdgpu_ttm_init(adev); 1096 } 1097 1098 /** 1099 * amdgpu_bo_fini - tear down memory manager 1100 * @adev: amdgpu device object 1101 * 1102 * Reverses amdgpu_bo_init() to tear down memory manager. 1103 */ 1104 void amdgpu_bo_fini(struct amdgpu_device *adev) 1105 { 1106 int idx; 1107 1108 amdgpu_ttm_fini(adev); 1109 1110 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1111 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1112 arch_phys_wc_del(adev->gmc.vram_mtrr); 1113 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1114 } 1115 drm_dev_exit(idx); 1116 } 1117 } 1118 1119 /** 1120 * amdgpu_bo_set_tiling_flags - set tiling flags 1121 * @bo: &amdgpu_bo buffer object 1122 * @tiling_flags: new flags 1123 * 1124 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1125 * kernel driver to set the tiling flags on a buffer. 1126 * 1127 * Returns: 1128 * 0 for success or a negative error code on failure. 1129 */ 1130 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1131 { 1132 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1133 struct amdgpu_bo_user *ubo; 1134 1135 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1136 if (adev->family <= AMDGPU_FAMILY_CZ && 1137 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1138 return -EINVAL; 1139 1140 ubo = to_amdgpu_bo_user(bo); 1141 ubo->tiling_flags = tiling_flags; 1142 return 0; 1143 } 1144 1145 /** 1146 * amdgpu_bo_get_tiling_flags - get tiling flags 1147 * @bo: &amdgpu_bo buffer object 1148 * @tiling_flags: returned flags 1149 * 1150 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1151 * set the tiling flags on a buffer. 1152 */ 1153 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1154 { 1155 struct amdgpu_bo_user *ubo; 1156 1157 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1158 dma_resv_assert_held(bo->tbo.base.resv); 1159 ubo = to_amdgpu_bo_user(bo); 1160 1161 if (tiling_flags) 1162 *tiling_flags = ubo->tiling_flags; 1163 } 1164 1165 /** 1166 * amdgpu_bo_set_metadata - set metadata 1167 * @bo: &amdgpu_bo buffer object 1168 * @metadata: new metadata 1169 * @metadata_size: size of the new metadata 1170 * @flags: flags of the new metadata 1171 * 1172 * Sets buffer object's metadata, its size and flags. 1173 * Used via GEM ioctl. 1174 * 1175 * Returns: 1176 * 0 for success or a negative error code on failure. 1177 */ 1178 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1179 u32 metadata_size, uint64_t flags) 1180 { 1181 struct amdgpu_bo_user *ubo; 1182 void *buffer; 1183 1184 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1185 ubo = to_amdgpu_bo_user(bo); 1186 if (!metadata_size) { 1187 if (ubo->metadata_size) { 1188 kfree(ubo->metadata); 1189 ubo->metadata = NULL; 1190 ubo->metadata_size = 0; 1191 } 1192 return 0; 1193 } 1194 1195 if (metadata == NULL) 1196 return -EINVAL; 1197 1198 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1199 if (buffer == NULL) 1200 return -ENOMEM; 1201 1202 kfree(ubo->metadata); 1203 ubo->metadata_flags = flags; 1204 ubo->metadata = buffer; 1205 ubo->metadata_size = metadata_size; 1206 1207 return 0; 1208 } 1209 1210 /** 1211 * amdgpu_bo_get_metadata - get metadata 1212 * @bo: &amdgpu_bo buffer object 1213 * @buffer: returned metadata 1214 * @buffer_size: size of the buffer 1215 * @metadata_size: size of the returned metadata 1216 * @flags: flags of the returned metadata 1217 * 1218 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1219 * less than metadata_size. 1220 * Used via GEM ioctl. 1221 * 1222 * Returns: 1223 * 0 for success or a negative error code on failure. 1224 */ 1225 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1226 size_t buffer_size, uint32_t *metadata_size, 1227 uint64_t *flags) 1228 { 1229 struct amdgpu_bo_user *ubo; 1230 1231 if (!buffer && !metadata_size) 1232 return -EINVAL; 1233 1234 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1235 ubo = to_amdgpu_bo_user(bo); 1236 if (metadata_size) 1237 *metadata_size = ubo->metadata_size; 1238 1239 if (buffer) { 1240 if (buffer_size < ubo->metadata_size) 1241 return -EINVAL; 1242 1243 if (ubo->metadata_size) 1244 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1245 } 1246 1247 if (flags) 1248 *flags = ubo->metadata_flags; 1249 1250 return 0; 1251 } 1252 1253 /** 1254 * amdgpu_bo_move_notify - notification about a memory move 1255 * @bo: pointer to a buffer object 1256 * @evict: if this move is evicting the buffer from the graphics address space 1257 * @new_mem: new resource for backing the BO 1258 * 1259 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1260 * bookkeeping. 1261 * TTM driver callback which is called when ttm moves a buffer. 1262 */ 1263 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1264 bool evict, 1265 struct ttm_resource *new_mem) 1266 { 1267 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1268 struct ttm_resource *old_mem = bo->resource; 1269 struct amdgpu_bo *abo; 1270 1271 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1272 return; 1273 1274 abo = ttm_to_amdgpu_bo(bo); 1275 amdgpu_vm_bo_invalidate(adev, abo, evict); 1276 1277 amdgpu_bo_kunmap(abo); 1278 1279 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1280 old_mem && old_mem->mem_type != TTM_PL_SYSTEM) 1281 dma_buf_move_notify(abo->tbo.base.dma_buf); 1282 1283 /* move_notify is called before move happens */ 1284 trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, 1285 old_mem ? old_mem->mem_type : -1); 1286 } 1287 1288 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 1289 struct amdgpu_mem_stats *stats) 1290 { 1291 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1292 struct ttm_resource *res = bo->tbo.resource; 1293 uint64_t size = amdgpu_bo_size(bo); 1294 struct drm_gem_object *obj; 1295 bool shared; 1296 1297 /* Abort if the BO doesn't currently have a backing store */ 1298 if (!res) 1299 return; 1300 1301 obj = &bo->tbo.base; 1302 shared = drm_gem_object_is_shared_for_memory_stats(obj); 1303 1304 switch (res->mem_type) { 1305 case TTM_PL_VRAM: 1306 stats->vram += size; 1307 if (amdgpu_res_cpu_visible(adev, res)) 1308 stats->visible_vram += size; 1309 if (shared) 1310 stats->vram_shared += size; 1311 break; 1312 case TTM_PL_TT: 1313 stats->gtt += size; 1314 if (shared) 1315 stats->gtt_shared += size; 1316 break; 1317 case TTM_PL_SYSTEM: 1318 default: 1319 stats->cpu += size; 1320 if (shared) 1321 stats->cpu_shared += size; 1322 break; 1323 } 1324 1325 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1326 stats->requested_vram += size; 1327 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1328 stats->requested_visible_vram += size; 1329 1330 if (res->mem_type != TTM_PL_VRAM) { 1331 stats->evicted_vram += size; 1332 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1333 stats->evicted_visible_vram += size; 1334 } 1335 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1336 stats->requested_gtt += size; 1337 } 1338 } 1339 1340 /** 1341 * amdgpu_bo_release_notify - notification about a BO being released 1342 * @bo: pointer to a buffer object 1343 * 1344 * Wipes VRAM buffers whose contents should not be leaked before the 1345 * memory is released. 1346 */ 1347 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1348 { 1349 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1350 struct dma_fence *fence = NULL; 1351 struct amdgpu_bo *abo; 1352 int r; 1353 1354 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1355 return; 1356 1357 abo = ttm_to_amdgpu_bo(bo); 1358 1359 WARN_ON(abo->vm_bo); 1360 1361 if (abo->kfd_bo) 1362 amdgpu_amdkfd_release_notify(abo); 1363 1364 /* We only remove the fence if the resv has individualized. */ 1365 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1366 && bo->base.resv != &bo->base._resv); 1367 if (bo->base.resv == &bo->base._resv) 1368 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1369 1370 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1371 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1372 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1373 return; 1374 1375 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1376 return; 1377 1378 r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true); 1379 if (!WARN_ON(r)) { 1380 amdgpu_vram_mgr_set_cleared(bo->resource); 1381 amdgpu_bo_fence(abo, fence, false); 1382 dma_fence_put(fence); 1383 } 1384 1385 dma_resv_unlock(bo->base.resv); 1386 } 1387 1388 /** 1389 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1390 * @bo: pointer to a buffer object 1391 * 1392 * Notifies the driver we are taking a fault on this BO and have reserved it, 1393 * also performs bookkeeping. 1394 * TTM driver callback for dealing with vm faults. 1395 * 1396 * Returns: 1397 * 0 for success or a negative error code on failure. 1398 */ 1399 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1400 { 1401 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1402 struct ttm_operation_ctx ctx = { false, false }; 1403 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1404 int r; 1405 1406 /* Remember that this BO was accessed by the CPU */ 1407 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1408 1409 if (amdgpu_res_cpu_visible(adev, bo->resource)) 1410 return 0; 1411 1412 /* Can't move a pinned BO to visible VRAM */ 1413 if (abo->tbo.pin_count > 0) 1414 return VM_FAULT_SIGBUS; 1415 1416 /* hurrah the memory is not visible ! */ 1417 atomic64_inc(&adev->num_vram_cpu_page_faults); 1418 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1419 AMDGPU_GEM_DOMAIN_GTT); 1420 1421 /* Avoid costly evictions; only set GTT as a busy placement */ 1422 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 1423 1424 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1425 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1426 return VM_FAULT_NOPAGE; 1427 else if (unlikely(r)) 1428 return VM_FAULT_SIGBUS; 1429 1430 /* this should never happen */ 1431 if (bo->resource->mem_type == TTM_PL_VRAM && 1432 !amdgpu_res_cpu_visible(adev, bo->resource)) 1433 return VM_FAULT_SIGBUS; 1434 1435 ttm_bo_move_to_lru_tail_unlocked(bo); 1436 return 0; 1437 } 1438 1439 /** 1440 * amdgpu_bo_fence - add fence to buffer object 1441 * 1442 * @bo: buffer object in question 1443 * @fence: fence to add 1444 * @shared: true if fence should be added shared 1445 * 1446 */ 1447 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1448 bool shared) 1449 { 1450 struct dma_resv *resv = bo->tbo.base.resv; 1451 int r; 1452 1453 r = dma_resv_reserve_fences(resv, 1); 1454 if (r) { 1455 /* As last resort on OOM we block for the fence */ 1456 dma_fence_wait(fence, false); 1457 return; 1458 } 1459 1460 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1461 DMA_RESV_USAGE_WRITE); 1462 } 1463 1464 /** 1465 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1466 * 1467 * @adev: amdgpu device pointer 1468 * @resv: reservation object to sync to 1469 * @sync_mode: synchronization mode 1470 * @owner: fence owner 1471 * @intr: Whether the wait is interruptible 1472 * 1473 * Extract the fences from the reservation object and waits for them to finish. 1474 * 1475 * Returns: 1476 * 0 on success, errno otherwise. 1477 */ 1478 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1479 enum amdgpu_sync_mode sync_mode, void *owner, 1480 bool intr) 1481 { 1482 struct amdgpu_sync sync; 1483 int r; 1484 1485 amdgpu_sync_create(&sync); 1486 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1487 r = amdgpu_sync_wait(&sync, intr); 1488 amdgpu_sync_free(&sync); 1489 return r; 1490 } 1491 1492 /** 1493 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1494 * @bo: buffer object to wait for 1495 * @owner: fence owner 1496 * @intr: Whether the wait is interruptible 1497 * 1498 * Wrapper to wait for fences in a BO. 1499 * Returns: 1500 * 0 on success, errno otherwise. 1501 */ 1502 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1503 { 1504 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1505 1506 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1507 AMDGPU_SYNC_NE_OWNER, owner, intr); 1508 } 1509 1510 /** 1511 * amdgpu_bo_gpu_offset - return GPU offset of bo 1512 * @bo: amdgpu object for which we query the offset 1513 * 1514 * Note: object should either be pinned or reserved when calling this 1515 * function, it might be useful to add check for this for debugging. 1516 * 1517 * Returns: 1518 * current GPU offset of the object. 1519 */ 1520 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1521 { 1522 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1523 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1524 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1525 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1526 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1527 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1528 1529 return amdgpu_bo_gpu_offset_no_check(bo); 1530 } 1531 1532 /** 1533 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1534 * @bo: amdgpu object for which we query the offset 1535 * 1536 * Returns: 1537 * current GPU offset of the object without raising warnings. 1538 */ 1539 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1540 { 1541 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1542 uint64_t offset = AMDGPU_BO_INVALID_OFFSET; 1543 1544 if (bo->tbo.resource->mem_type == TTM_PL_TT) 1545 offset = amdgpu_gmc_agp_addr(&bo->tbo); 1546 1547 if (offset == AMDGPU_BO_INVALID_OFFSET) 1548 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1549 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1550 1551 return amdgpu_gmc_sign_extend(offset); 1552 } 1553 1554 /** 1555 * amdgpu_bo_get_preferred_domain - get preferred domain 1556 * @adev: amdgpu device object 1557 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1558 * 1559 * Returns: 1560 * Which of the allowed domains is preferred for allocating the BO. 1561 */ 1562 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1563 uint32_t domain) 1564 { 1565 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1566 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1567 domain = AMDGPU_GEM_DOMAIN_VRAM; 1568 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1569 domain = AMDGPU_GEM_DOMAIN_GTT; 1570 } 1571 return domain; 1572 } 1573 1574 #if defined(CONFIG_DEBUG_FS) 1575 #define amdgpu_bo_print_flag(m, bo, flag) \ 1576 do { \ 1577 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1578 seq_printf((m), " " #flag); \ 1579 } \ 1580 } while (0) 1581 1582 /** 1583 * amdgpu_bo_print_info - print BO info in debugfs file 1584 * 1585 * @id: Index or Id of the BO 1586 * @bo: Requested BO for printing info 1587 * @m: debugfs file 1588 * 1589 * Print BO information in debugfs file 1590 * 1591 * Returns: 1592 * Size of the BO in bytes. 1593 */ 1594 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1595 { 1596 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1597 struct dma_buf_attachment *attachment; 1598 struct dma_buf *dma_buf; 1599 const char *placement; 1600 unsigned int pin_count; 1601 u64 size; 1602 1603 if (dma_resv_trylock(bo->tbo.base.resv)) { 1604 if (!bo->tbo.resource) { 1605 placement = "NONE"; 1606 } else { 1607 switch (bo->tbo.resource->mem_type) { 1608 case TTM_PL_VRAM: 1609 if (amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 1610 placement = "VRAM VISIBLE"; 1611 else 1612 placement = "VRAM"; 1613 break; 1614 case TTM_PL_TT: 1615 placement = "GTT"; 1616 break; 1617 case AMDGPU_PL_GDS: 1618 placement = "GDS"; 1619 break; 1620 case AMDGPU_PL_GWS: 1621 placement = "GWS"; 1622 break; 1623 case AMDGPU_PL_OA: 1624 placement = "OA"; 1625 break; 1626 case AMDGPU_PL_PREEMPT: 1627 placement = "PREEMPTIBLE"; 1628 break; 1629 case AMDGPU_PL_DOORBELL: 1630 placement = "DOORBELL"; 1631 break; 1632 case TTM_PL_SYSTEM: 1633 default: 1634 placement = "CPU"; 1635 break; 1636 } 1637 } 1638 dma_resv_unlock(bo->tbo.base.resv); 1639 } else { 1640 placement = "UNKNOWN"; 1641 } 1642 1643 size = amdgpu_bo_size(bo); 1644 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1645 id, size, placement); 1646 1647 pin_count = READ_ONCE(bo->tbo.pin_count); 1648 if (pin_count) 1649 seq_printf(m, " pin count %d", pin_count); 1650 1651 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1652 attachment = READ_ONCE(bo->tbo.base.import_attach); 1653 1654 if (attachment) 1655 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1656 else if (dma_buf) 1657 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1658 1659 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1660 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1661 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1662 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1663 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1664 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1665 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1666 1667 seq_puts(m, "\n"); 1668 1669 return size; 1670 } 1671 #endif 1672