1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_cache.h> 37 #include "amdgpu.h" 38 #include "amdgpu_trace.h" 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * DOC: amdgpu_object 43 * 44 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 45 * represents memory used by driver (VRAM, system memory, etc.). The driver 46 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 47 * to create/destroy/set buffer object which are then managed by the kernel TTM 48 * memory manager. 49 * The interfaces are also used internally by kernel clients, including gfx, 50 * uvd, etc. for kernel managed allocations used by the GPU. 51 * 52 */ 53 54 /** 55 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 56 * 57 * @bo: &amdgpu_bo buffer object 58 * 59 * This function is called when a BO stops being pinned, and updates the 60 * &amdgpu_device pin_size values accordingly. 61 */ 62 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 63 { 64 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 65 66 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 67 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 68 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 69 &adev->visible_pin_size); 70 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 71 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 72 } 73 } 74 75 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 76 { 77 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 78 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 79 80 if (bo->pin_count > 0) 81 amdgpu_bo_subtract_pin_size(bo); 82 83 amdgpu_bo_kunmap(bo); 84 85 if (bo->tbo.base.import_attach) 86 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 87 drm_gem_object_release(&bo->tbo.base); 88 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 89 if (!list_empty(&bo->shadow_list)) { 90 mutex_lock(&adev->shadow_list_lock); 91 list_del_init(&bo->shadow_list); 92 mutex_unlock(&adev->shadow_list_lock); 93 } 94 amdgpu_bo_unref(&bo->parent); 95 96 kfree(bo->metadata); 97 kfree(bo); 98 } 99 100 /** 101 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 102 * @bo: buffer object to be checked 103 * 104 * Uses destroy function associated with the object to determine if this is 105 * an &amdgpu_bo. 106 * 107 * Returns: 108 * true if the object belongs to &amdgpu_bo, false if not. 109 */ 110 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 111 { 112 if (bo->destroy == &amdgpu_bo_destroy) 113 return true; 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 136 places[c].fpfn = 0; 137 places[c].lpfn = 0; 138 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 139 TTM_PL_FLAG_VRAM; 140 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 places[c].lpfn = visible_pfn; 143 else 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 147 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 148 c++; 149 } 150 151 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].flags = TTM_PL_FLAG_TT; 155 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 156 places[c].flags |= TTM_PL_FLAG_WC | 157 TTM_PL_FLAG_UNCACHED; 158 else 159 places[c].flags |= TTM_PL_FLAG_CACHED; 160 c++; 161 } 162 163 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 164 places[c].fpfn = 0; 165 places[c].lpfn = 0; 166 places[c].flags = TTM_PL_FLAG_SYSTEM; 167 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 168 places[c].flags |= TTM_PL_FLAG_WC | 169 TTM_PL_FLAG_UNCACHED; 170 else 171 places[c].flags |= TTM_PL_FLAG_CACHED; 172 c++; 173 } 174 175 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 176 places[c].fpfn = 0; 177 places[c].lpfn = 0; 178 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 179 c++; 180 } 181 182 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 183 places[c].fpfn = 0; 184 places[c].lpfn = 0; 185 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 186 c++; 187 } 188 189 if (domain & AMDGPU_GEM_DOMAIN_OA) { 190 places[c].fpfn = 0; 191 places[c].lpfn = 0; 192 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 193 c++; 194 } 195 196 if (!c) { 197 places[c].fpfn = 0; 198 places[c].lpfn = 0; 199 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 200 c++; 201 } 202 203 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 204 205 placement->num_placement = c; 206 placement->placement = places; 207 208 placement->num_busy_placement = c; 209 placement->busy_placement = places; 210 } 211 212 /** 213 * amdgpu_bo_create_reserved - create reserved BO for kernel use 214 * 215 * @adev: amdgpu device object 216 * @size: size for the new BO 217 * @align: alignment for the new BO 218 * @domain: where to place it 219 * @bo_ptr: used to initialize BOs in structures 220 * @gpu_addr: GPU addr of the pinned BO 221 * @cpu_addr: optional CPU address mapping 222 * 223 * Allocates and pins a BO for kernel internal use, and returns it still 224 * reserved. 225 * 226 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 227 * 228 * Returns: 229 * 0 on success, negative error code otherwise. 230 */ 231 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 232 unsigned long size, int align, 233 u32 domain, struct amdgpu_bo **bo_ptr, 234 u64 *gpu_addr, void **cpu_addr) 235 { 236 struct amdgpu_bo_param bp; 237 bool free = false; 238 int r; 239 240 if (!size) { 241 amdgpu_bo_unref(bo_ptr); 242 return 0; 243 } 244 245 memset(&bp, 0, sizeof(bp)); 246 bp.size = size; 247 bp.byte_align = align; 248 bp.domain = domain; 249 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 250 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 251 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 252 bp.type = ttm_bo_type_kernel; 253 bp.resv = NULL; 254 255 if (!*bo_ptr) { 256 r = amdgpu_bo_create(adev, &bp, bo_ptr); 257 if (r) { 258 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 259 r); 260 return r; 261 } 262 free = true; 263 } 264 265 r = amdgpu_bo_reserve(*bo_ptr, false); 266 if (r) { 267 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 268 goto error_free; 269 } 270 271 r = amdgpu_bo_pin(*bo_ptr, domain); 272 if (r) { 273 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 274 goto error_unreserve; 275 } 276 277 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 278 if (r) { 279 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 280 goto error_unpin; 281 } 282 283 if (gpu_addr) 284 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 285 286 if (cpu_addr) { 287 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 288 if (r) { 289 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 290 goto error_unpin; 291 } 292 } 293 294 return 0; 295 296 error_unpin: 297 amdgpu_bo_unpin(*bo_ptr); 298 error_unreserve: 299 amdgpu_bo_unreserve(*bo_ptr); 300 301 error_free: 302 if (free) 303 amdgpu_bo_unref(bo_ptr); 304 305 return r; 306 } 307 308 /** 309 * amdgpu_bo_create_kernel - create BO for kernel use 310 * 311 * @adev: amdgpu device object 312 * @size: size for the new BO 313 * @align: alignment for the new BO 314 * @domain: where to place it 315 * @bo_ptr: used to initialize BOs in structures 316 * @gpu_addr: GPU addr of the pinned BO 317 * @cpu_addr: optional CPU address mapping 318 * 319 * Allocates and pins a BO for kernel internal use. 320 * 321 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 322 * 323 * Returns: 324 * 0 on success, negative error code otherwise. 325 */ 326 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 327 unsigned long size, int align, 328 u32 domain, struct amdgpu_bo **bo_ptr, 329 u64 *gpu_addr, void **cpu_addr) 330 { 331 int r; 332 333 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 334 gpu_addr, cpu_addr); 335 336 if (r) 337 return r; 338 339 if (*bo_ptr) 340 amdgpu_bo_unreserve(*bo_ptr); 341 342 return 0; 343 } 344 345 /** 346 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 347 * 348 * @adev: amdgpu device object 349 * @offset: offset of the BO 350 * @size: size of the BO 351 * @domain: where to place it 352 * @bo_ptr: used to initialize BOs in structures 353 * @cpu_addr: optional CPU address mapping 354 * 355 * Creates a kernel BO at a specific offset in the address space of the domain. 356 * 357 * Returns: 358 * 0 on success, negative error code otherwise. 359 */ 360 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 361 uint64_t offset, uint64_t size, uint32_t domain, 362 struct amdgpu_bo **bo_ptr, void **cpu_addr) 363 { 364 struct ttm_operation_ctx ctx = { false, false }; 365 unsigned int i; 366 int r; 367 368 offset &= PAGE_MASK; 369 size = ALIGN(size, PAGE_SIZE); 370 371 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 372 NULL, NULL); 373 if (r) 374 return r; 375 376 /* 377 * Remove the original mem node and create a new one at the request 378 * position. 379 */ 380 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 381 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 382 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 383 } 384 385 ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 386 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 387 &(*bo_ptr)->tbo.mem, &ctx); 388 if (r) 389 goto error; 390 391 if (cpu_addr) { 392 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 393 if (r) 394 goto error; 395 } 396 397 amdgpu_bo_unreserve(*bo_ptr); 398 return 0; 399 400 error: 401 amdgpu_bo_unreserve(*bo_ptr); 402 amdgpu_bo_unref(bo_ptr); 403 return r; 404 } 405 406 /** 407 * amdgpu_bo_free_kernel - free BO for kernel use 408 * 409 * @bo: amdgpu BO to free 410 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 411 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 412 * 413 * unmaps and unpin a BO for kernel internal use. 414 */ 415 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 416 void **cpu_addr) 417 { 418 if (*bo == NULL) 419 return; 420 421 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 422 if (cpu_addr) 423 amdgpu_bo_kunmap(*bo); 424 425 amdgpu_bo_unpin(*bo); 426 amdgpu_bo_unreserve(*bo); 427 } 428 amdgpu_bo_unref(bo); 429 430 if (gpu_addr) 431 *gpu_addr = 0; 432 433 if (cpu_addr) 434 *cpu_addr = NULL; 435 } 436 437 /* Validate bo size is bit bigger then the request domain */ 438 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 439 unsigned long size, u32 domain) 440 { 441 struct ttm_mem_type_manager *man = NULL; 442 443 /* 444 * If GTT is part of requested domains the check must succeed to 445 * allow fall back to GTT 446 */ 447 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 448 man = &adev->mman.bdev.man[TTM_PL_TT]; 449 450 if (size < (man->size << PAGE_SHIFT)) 451 return true; 452 else 453 goto fail; 454 } 455 456 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 457 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 458 459 if (size < (man->size << PAGE_SHIFT)) 460 return true; 461 else 462 goto fail; 463 } 464 465 466 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 467 return true; 468 469 fail: 470 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 471 man->size << PAGE_SHIFT); 472 return false; 473 } 474 475 bool amdgpu_bo_support_uswc(u64 bo_flags) 476 { 477 478 #ifdef CONFIG_X86_32 479 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 480 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 481 */ 482 return false; 483 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 484 /* Don't try to enable write-combining when it can't work, or things 485 * may be slow 486 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 487 */ 488 489 #ifndef CONFIG_COMPILE_TEST 490 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 491 thanks to write-combining 492 #endif 493 494 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 495 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 496 "better performance thanks to write-combining\n"); 497 return false; 498 #else 499 /* For architectures that don't support WC memory, 500 * mask out the WC flag from the BO 501 */ 502 if (!drm_arch_can_wc_memory()) 503 return false; 504 505 return true; 506 #endif 507 } 508 509 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 510 struct amdgpu_bo_param *bp, 511 struct amdgpu_bo **bo_ptr) 512 { 513 struct ttm_operation_ctx ctx = { 514 .interruptible = (bp->type != ttm_bo_type_kernel), 515 .no_wait_gpu = bp->no_wait_gpu, 516 .resv = bp->resv, 517 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT 518 }; 519 struct amdgpu_bo *bo; 520 unsigned long page_align, size = bp->size; 521 size_t acc_size; 522 int r; 523 524 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 525 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 526 /* GWS and OA don't need any alignment. */ 527 page_align = bp->byte_align; 528 size <<= PAGE_SHIFT; 529 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 530 /* Both size and alignment must be a multiple of 4. */ 531 page_align = ALIGN(bp->byte_align, 4); 532 size = ALIGN(size, 4) << PAGE_SHIFT; 533 } else { 534 /* Memory should be aligned at least to a page size. */ 535 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 536 size = ALIGN(size, PAGE_SIZE); 537 } 538 539 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 540 return -ENOMEM; 541 542 *bo_ptr = NULL; 543 544 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 545 sizeof(struct amdgpu_bo)); 546 547 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 548 if (bo == NULL) 549 return -ENOMEM; 550 drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); 551 INIT_LIST_HEAD(&bo->shadow_list); 552 bo->vm_bo = NULL; 553 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 554 bp->domain; 555 bo->allowed_domains = bo->preferred_domains; 556 if (bp->type != ttm_bo_type_kernel && 557 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 558 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 559 560 bo->flags = bp->flags; 561 562 if (!amdgpu_bo_support_uswc(bo->flags)) 563 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 564 565 bo->tbo.bdev = &adev->mman.bdev; 566 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 567 AMDGPU_GEM_DOMAIN_GDS)) 568 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 569 else 570 amdgpu_bo_placement_from_domain(bo, bp->domain); 571 if (bp->type == ttm_bo_type_kernel) 572 bo->tbo.priority = 1; 573 574 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 575 &bo->placement, page_align, &ctx, acc_size, 576 NULL, bp->resv, &amdgpu_bo_destroy); 577 if (unlikely(r != 0)) 578 return r; 579 580 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 581 bo->tbo.mem.mem_type == TTM_PL_VRAM && 582 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 583 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 584 ctx.bytes_moved); 585 else 586 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 587 588 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 589 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 590 struct dma_fence *fence; 591 592 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 593 if (unlikely(r)) 594 goto fail_unreserve; 595 596 amdgpu_bo_fence(bo, fence, false); 597 dma_fence_put(bo->tbo.moving); 598 bo->tbo.moving = dma_fence_get(fence); 599 dma_fence_put(fence); 600 } 601 if (!bp->resv) 602 amdgpu_bo_unreserve(bo); 603 *bo_ptr = bo; 604 605 trace_amdgpu_bo_create(bo); 606 607 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 608 if (bp->type == ttm_bo_type_device) 609 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 610 611 return 0; 612 613 fail_unreserve: 614 if (!bp->resv) 615 dma_resv_unlock(bo->tbo.base.resv); 616 amdgpu_bo_unref(&bo); 617 return r; 618 } 619 620 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 621 unsigned long size, 622 struct amdgpu_bo *bo) 623 { 624 struct amdgpu_bo_param bp; 625 int r; 626 627 if (bo->shadow) 628 return 0; 629 630 memset(&bp, 0, sizeof(bp)); 631 bp.size = size; 632 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 633 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 634 AMDGPU_GEM_CREATE_SHADOW; 635 bp.type = ttm_bo_type_kernel; 636 bp.resv = bo->tbo.base.resv; 637 638 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 639 if (!r) { 640 bo->shadow->parent = amdgpu_bo_ref(bo); 641 mutex_lock(&adev->shadow_list_lock); 642 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 643 mutex_unlock(&adev->shadow_list_lock); 644 } 645 646 return r; 647 } 648 649 /** 650 * amdgpu_bo_create - create an &amdgpu_bo buffer object 651 * @adev: amdgpu device object 652 * @bp: parameters to be used for the buffer object 653 * @bo_ptr: pointer to the buffer object pointer 654 * 655 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 656 * shadow object. 657 * Shadow object is used to backup the original buffer object, and is always 658 * in GTT. 659 * 660 * Returns: 661 * 0 for success or a negative error code on failure. 662 */ 663 int amdgpu_bo_create(struct amdgpu_device *adev, 664 struct amdgpu_bo_param *bp, 665 struct amdgpu_bo **bo_ptr) 666 { 667 u64 flags = bp->flags; 668 int r; 669 670 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 671 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 672 if (r) 673 return r; 674 675 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 676 if (!bp->resv) 677 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 678 NULL)); 679 680 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 681 682 if (!bp->resv) 683 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 684 685 if (r) 686 amdgpu_bo_unref(bo_ptr); 687 } 688 689 return r; 690 } 691 692 /** 693 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 694 * @bo: pointer to the buffer object 695 * 696 * Sets placement according to domain; and changes placement and caching 697 * policy of the buffer object according to the placement. 698 * This is used for validating shadow bos. It calls ttm_bo_validate() to 699 * make sure the buffer is resident where it needs to be. 700 * 701 * Returns: 702 * 0 for success or a negative error code on failure. 703 */ 704 int amdgpu_bo_validate(struct amdgpu_bo *bo) 705 { 706 struct ttm_operation_ctx ctx = { false, false }; 707 uint32_t domain; 708 int r; 709 710 if (bo->pin_count) 711 return 0; 712 713 domain = bo->preferred_domains; 714 715 retry: 716 amdgpu_bo_placement_from_domain(bo, domain); 717 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 718 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 719 domain = bo->allowed_domains; 720 goto retry; 721 } 722 723 return r; 724 } 725 726 /** 727 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 728 * 729 * @shadow: &amdgpu_bo shadow to be restored 730 * @fence: dma_fence associated with the operation 731 * 732 * Copies a buffer object's shadow content back to the object. 733 * This is used for recovering a buffer from its shadow in case of a gpu 734 * reset where vram context may be lost. 735 * 736 * Returns: 737 * 0 for success or a negative error code on failure. 738 */ 739 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 740 741 { 742 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 743 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 744 uint64_t shadow_addr, parent_addr; 745 746 shadow_addr = amdgpu_bo_gpu_offset(shadow); 747 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 748 749 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 750 amdgpu_bo_size(shadow), NULL, fence, 751 true, false); 752 } 753 754 /** 755 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 756 * @bo: &amdgpu_bo buffer object to be mapped 757 * @ptr: kernel virtual address to be returned 758 * 759 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 760 * amdgpu_bo_kptr() to get the kernel virtual address. 761 * 762 * Returns: 763 * 0 for success or a negative error code on failure. 764 */ 765 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 766 { 767 void *kptr; 768 long r; 769 770 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 771 return -EPERM; 772 773 kptr = amdgpu_bo_kptr(bo); 774 if (kptr) { 775 if (ptr) 776 *ptr = kptr; 777 return 0; 778 } 779 780 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 781 MAX_SCHEDULE_TIMEOUT); 782 if (r < 0) 783 return r; 784 785 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 786 if (r) 787 return r; 788 789 if (ptr) 790 *ptr = amdgpu_bo_kptr(bo); 791 792 return 0; 793 } 794 795 /** 796 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 797 * @bo: &amdgpu_bo buffer object 798 * 799 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 800 * 801 * Returns: 802 * the virtual address of a buffer object area. 803 */ 804 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 805 { 806 bool is_iomem; 807 808 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 809 } 810 811 /** 812 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 813 * @bo: &amdgpu_bo buffer object to be unmapped 814 * 815 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 816 */ 817 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 818 { 819 if (bo->kmap.bo) 820 ttm_bo_kunmap(&bo->kmap); 821 } 822 823 /** 824 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 825 * @bo: &amdgpu_bo buffer object 826 * 827 * References the contained &ttm_buffer_object. 828 * 829 * Returns: 830 * a refcounted pointer to the &amdgpu_bo buffer object. 831 */ 832 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 833 { 834 if (bo == NULL) 835 return NULL; 836 837 ttm_bo_get(&bo->tbo); 838 return bo; 839 } 840 841 /** 842 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 843 * @bo: &amdgpu_bo buffer object 844 * 845 * Unreferences the contained &ttm_buffer_object and clear the pointer 846 */ 847 void amdgpu_bo_unref(struct amdgpu_bo **bo) 848 { 849 struct ttm_buffer_object *tbo; 850 851 if ((*bo) == NULL) 852 return; 853 854 tbo = &((*bo)->tbo); 855 ttm_bo_put(tbo); 856 *bo = NULL; 857 } 858 859 /** 860 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 861 * @bo: &amdgpu_bo buffer object to be pinned 862 * @domain: domain to be pinned to 863 * @min_offset: the start of requested address range 864 * @max_offset: the end of requested address range 865 * 866 * Pins the buffer object according to requested domain and address range. If 867 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 868 * pin_count and pin_size accordingly. 869 * 870 * Pinning means to lock pages in memory along with keeping them at a fixed 871 * offset. It is required when a buffer can not be moved, for example, when 872 * a display buffer is being scanned out. 873 * 874 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 875 * where to pin a buffer if there are specific restrictions on where a buffer 876 * must be located. 877 * 878 * Returns: 879 * 0 for success or a negative error code on failure. 880 */ 881 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 882 u64 min_offset, u64 max_offset) 883 { 884 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 885 struct ttm_operation_ctx ctx = { false, false }; 886 int r, i; 887 888 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 889 return -EPERM; 890 891 if (WARN_ON_ONCE(min_offset > max_offset)) 892 return -EINVAL; 893 894 /* A shared bo cannot be migrated to VRAM */ 895 if (bo->prime_shared_count) { 896 if (domain & AMDGPU_GEM_DOMAIN_GTT) 897 domain = AMDGPU_GEM_DOMAIN_GTT; 898 else 899 return -EINVAL; 900 } 901 902 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 903 * See function amdgpu_display_supported_domains() 904 */ 905 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 906 907 if (bo->pin_count) { 908 uint32_t mem_type = bo->tbo.mem.mem_type; 909 910 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 911 return -EINVAL; 912 913 bo->pin_count++; 914 915 if (max_offset != 0) { 916 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 917 WARN_ON_ONCE(max_offset < 918 (amdgpu_bo_gpu_offset(bo) - domain_start)); 919 } 920 921 return 0; 922 } 923 924 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 925 /* force to pin into visible video ram */ 926 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 927 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 928 amdgpu_bo_placement_from_domain(bo, domain); 929 for (i = 0; i < bo->placement.num_placement; i++) { 930 unsigned fpfn, lpfn; 931 932 fpfn = min_offset >> PAGE_SHIFT; 933 lpfn = max_offset >> PAGE_SHIFT; 934 935 if (fpfn > bo->placements[i].fpfn) 936 bo->placements[i].fpfn = fpfn; 937 if (!bo->placements[i].lpfn || 938 (lpfn && lpfn < bo->placements[i].lpfn)) 939 bo->placements[i].lpfn = lpfn; 940 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 941 } 942 943 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 944 if (unlikely(r)) { 945 dev_err(adev->dev, "%p pin failed\n", bo); 946 goto error; 947 } 948 949 bo->pin_count = 1; 950 951 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 952 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 953 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 954 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 955 &adev->visible_pin_size); 956 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 957 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 958 } 959 960 error: 961 return r; 962 } 963 964 /** 965 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 966 * @bo: &amdgpu_bo buffer object to be pinned 967 * @domain: domain to be pinned to 968 * 969 * A simple wrapper to amdgpu_bo_pin_restricted(). 970 * Provides a simpler API for buffers that do not have any strict restrictions 971 * on where a buffer must be located. 972 * 973 * Returns: 974 * 0 for success or a negative error code on failure. 975 */ 976 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 977 { 978 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 979 } 980 981 /** 982 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 983 * @bo: &amdgpu_bo buffer object to be unpinned 984 * 985 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 986 * Changes placement and pin size accordingly. 987 * 988 * Returns: 989 * 0 for success or a negative error code on failure. 990 */ 991 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 992 { 993 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 994 struct ttm_operation_ctx ctx = { false, false }; 995 int r, i; 996 997 if (WARN_ON_ONCE(!bo->pin_count)) { 998 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 999 return 0; 1000 } 1001 bo->pin_count--; 1002 if (bo->pin_count) 1003 return 0; 1004 1005 amdgpu_bo_subtract_pin_size(bo); 1006 1007 for (i = 0; i < bo->placement.num_placement; i++) { 1008 bo->placements[i].lpfn = 0; 1009 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1010 } 1011 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1012 if (unlikely(r)) 1013 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1014 1015 return r; 1016 } 1017 1018 /** 1019 * amdgpu_bo_evict_vram - evict VRAM buffers 1020 * @adev: amdgpu device object 1021 * 1022 * Evicts all VRAM buffers on the lru list of the memory type. 1023 * Mainly used for evicting vram at suspend time. 1024 * 1025 * Returns: 1026 * 0 for success or a negative error code on failure. 1027 */ 1028 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1029 { 1030 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1031 #ifndef CONFIG_HIBERNATION 1032 if (adev->flags & AMD_IS_APU) { 1033 /* Useless to evict on IGP chips */ 1034 return 0; 1035 } 1036 #endif 1037 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1038 } 1039 1040 static const char *amdgpu_vram_names[] = { 1041 "UNKNOWN", 1042 "GDDR1", 1043 "DDR2", 1044 "GDDR3", 1045 "GDDR4", 1046 "GDDR5", 1047 "HBM", 1048 "DDR3", 1049 "DDR4", 1050 "GDDR6", 1051 }; 1052 1053 /** 1054 * amdgpu_bo_init - initialize memory manager 1055 * @adev: amdgpu device object 1056 * 1057 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1058 * 1059 * Returns: 1060 * 0 for success or a negative error code on failure. 1061 */ 1062 int amdgpu_bo_init(struct amdgpu_device *adev) 1063 { 1064 /* reserve PAT memory space to WC for VRAM */ 1065 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1066 adev->gmc.aper_size); 1067 1068 /* Add an MTRR for the VRAM */ 1069 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1070 adev->gmc.aper_size); 1071 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1072 adev->gmc.mc_vram_size >> 20, 1073 (unsigned long long)adev->gmc.aper_size >> 20); 1074 DRM_INFO("RAM width %dbits %s\n", 1075 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1076 return amdgpu_ttm_init(adev); 1077 } 1078 1079 /** 1080 * amdgpu_bo_late_init - late init 1081 * @adev: amdgpu device object 1082 * 1083 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1084 * initialization. 1085 * 1086 * Returns: 1087 * 0 for success or a negative error code on failure. 1088 */ 1089 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1090 { 1091 amdgpu_ttm_late_init(adev); 1092 1093 return 0; 1094 } 1095 1096 /** 1097 * amdgpu_bo_fini - tear down memory manager 1098 * @adev: amdgpu device object 1099 * 1100 * Reverses amdgpu_bo_init() to tear down memory manager. 1101 */ 1102 void amdgpu_bo_fini(struct amdgpu_device *adev) 1103 { 1104 amdgpu_ttm_fini(adev); 1105 arch_phys_wc_del(adev->gmc.vram_mtrr); 1106 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1107 } 1108 1109 /** 1110 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1111 * @bo: &amdgpu_bo buffer object 1112 * @vma: vma as input from the fbdev mmap method 1113 * 1114 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1115 * 1116 * Returns: 1117 * 0 for success or a negative error code on failure. 1118 */ 1119 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1120 struct vm_area_struct *vma) 1121 { 1122 return ttm_fbdev_mmap(vma, &bo->tbo); 1123 } 1124 1125 /** 1126 * amdgpu_bo_set_tiling_flags - set tiling flags 1127 * @bo: &amdgpu_bo buffer object 1128 * @tiling_flags: new flags 1129 * 1130 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1131 * kernel driver to set the tiling flags on a buffer. 1132 * 1133 * Returns: 1134 * 0 for success or a negative error code on failure. 1135 */ 1136 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1137 { 1138 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1139 1140 if (adev->family <= AMDGPU_FAMILY_CZ && 1141 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1142 return -EINVAL; 1143 1144 bo->tiling_flags = tiling_flags; 1145 return 0; 1146 } 1147 1148 /** 1149 * amdgpu_bo_get_tiling_flags - get tiling flags 1150 * @bo: &amdgpu_bo buffer object 1151 * @tiling_flags: returned flags 1152 * 1153 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1154 * set the tiling flags on a buffer. 1155 */ 1156 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1157 { 1158 dma_resv_assert_held(bo->tbo.base.resv); 1159 1160 if (tiling_flags) 1161 *tiling_flags = bo->tiling_flags; 1162 } 1163 1164 /** 1165 * amdgpu_bo_set_metadata - set metadata 1166 * @bo: &amdgpu_bo buffer object 1167 * @metadata: new metadata 1168 * @metadata_size: size of the new metadata 1169 * @flags: flags of the new metadata 1170 * 1171 * Sets buffer object's metadata, its size and flags. 1172 * Used via GEM ioctl. 1173 * 1174 * Returns: 1175 * 0 for success or a negative error code on failure. 1176 */ 1177 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1178 uint32_t metadata_size, uint64_t flags) 1179 { 1180 void *buffer; 1181 1182 if (!metadata_size) { 1183 if (bo->metadata_size) { 1184 kfree(bo->metadata); 1185 bo->metadata = NULL; 1186 bo->metadata_size = 0; 1187 } 1188 return 0; 1189 } 1190 1191 if (metadata == NULL) 1192 return -EINVAL; 1193 1194 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1195 if (buffer == NULL) 1196 return -ENOMEM; 1197 1198 kfree(bo->metadata); 1199 bo->metadata_flags = flags; 1200 bo->metadata = buffer; 1201 bo->metadata_size = metadata_size; 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * amdgpu_bo_get_metadata - get metadata 1208 * @bo: &amdgpu_bo buffer object 1209 * @buffer: returned metadata 1210 * @buffer_size: size of the buffer 1211 * @metadata_size: size of the returned metadata 1212 * @flags: flags of the returned metadata 1213 * 1214 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1215 * less than metadata_size. 1216 * Used via GEM ioctl. 1217 * 1218 * Returns: 1219 * 0 for success or a negative error code on failure. 1220 */ 1221 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1222 size_t buffer_size, uint32_t *metadata_size, 1223 uint64_t *flags) 1224 { 1225 if (!buffer && !metadata_size) 1226 return -EINVAL; 1227 1228 if (buffer) { 1229 if (buffer_size < bo->metadata_size) 1230 return -EINVAL; 1231 1232 if (bo->metadata_size) 1233 memcpy(buffer, bo->metadata, bo->metadata_size); 1234 } 1235 1236 if (metadata_size) 1237 *metadata_size = bo->metadata_size; 1238 if (flags) 1239 *flags = bo->metadata_flags; 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * amdgpu_bo_move_notify - notification about a memory move 1246 * @bo: pointer to a buffer object 1247 * @evict: if this move is evicting the buffer from the graphics address space 1248 * @new_mem: new information of the bufer object 1249 * 1250 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1251 * bookkeeping. 1252 * TTM driver callback which is called when ttm moves a buffer. 1253 */ 1254 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1255 bool evict, 1256 struct ttm_mem_reg *new_mem) 1257 { 1258 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1259 struct amdgpu_bo *abo; 1260 struct ttm_mem_reg *old_mem = &bo->mem; 1261 1262 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1263 return; 1264 1265 abo = ttm_to_amdgpu_bo(bo); 1266 amdgpu_vm_bo_invalidate(adev, abo, evict); 1267 1268 amdgpu_bo_kunmap(abo); 1269 1270 /* remember the eviction */ 1271 if (evict) 1272 atomic64_inc(&adev->num_evictions); 1273 1274 /* update statistics */ 1275 if (!new_mem) 1276 return; 1277 1278 /* move_notify is called before move happens */ 1279 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1280 } 1281 1282 /** 1283 * amdgpu_bo_move_notify - notification about a BO being released 1284 * @bo: pointer to a buffer object 1285 * 1286 * Wipes VRAM buffers whose contents should not be leaked before the 1287 * memory is released. 1288 */ 1289 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1290 { 1291 struct dma_fence *fence = NULL; 1292 struct amdgpu_bo *abo; 1293 int r; 1294 1295 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1296 return; 1297 1298 abo = ttm_to_amdgpu_bo(bo); 1299 1300 if (abo->kfd_bo) 1301 amdgpu_amdkfd_unreserve_memory_limit(abo); 1302 1303 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1304 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1305 return; 1306 1307 dma_resv_lock(bo->base.resv, NULL); 1308 1309 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1310 if (!WARN_ON(r)) { 1311 amdgpu_bo_fence(abo, fence, false); 1312 dma_fence_put(fence); 1313 } 1314 1315 dma_resv_unlock(bo->base.resv); 1316 } 1317 1318 /** 1319 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1320 * @bo: pointer to a buffer object 1321 * 1322 * Notifies the driver we are taking a fault on this BO and have reserved it, 1323 * also performs bookkeeping. 1324 * TTM driver callback for dealing with vm faults. 1325 * 1326 * Returns: 1327 * 0 for success or a negative error code on failure. 1328 */ 1329 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1330 { 1331 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1332 struct ttm_operation_ctx ctx = { false, false }; 1333 struct amdgpu_bo *abo; 1334 unsigned long offset, size; 1335 int r; 1336 1337 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1338 return 0; 1339 1340 abo = ttm_to_amdgpu_bo(bo); 1341 1342 /* Remember that this BO was accessed by the CPU */ 1343 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1344 1345 if (bo->mem.mem_type != TTM_PL_VRAM) 1346 return 0; 1347 1348 size = bo->mem.num_pages << PAGE_SHIFT; 1349 offset = bo->mem.start << PAGE_SHIFT; 1350 if ((offset + size) <= adev->gmc.visible_vram_size) 1351 return 0; 1352 1353 /* Can't move a pinned BO to visible VRAM */ 1354 if (abo->pin_count > 0) 1355 return -EINVAL; 1356 1357 /* hurrah the memory is not visible ! */ 1358 atomic64_inc(&adev->num_vram_cpu_page_faults); 1359 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1360 AMDGPU_GEM_DOMAIN_GTT); 1361 1362 /* Avoid costly evictions; only set GTT as a busy placement */ 1363 abo->placement.num_busy_placement = 1; 1364 abo->placement.busy_placement = &abo->placements[1]; 1365 1366 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1367 if (unlikely(r != 0)) 1368 return r; 1369 1370 offset = bo->mem.start << PAGE_SHIFT; 1371 /* this should never happen */ 1372 if (bo->mem.mem_type == TTM_PL_VRAM && 1373 (offset + size) > adev->gmc.visible_vram_size) 1374 return -EINVAL; 1375 1376 return 0; 1377 } 1378 1379 /** 1380 * amdgpu_bo_fence - add fence to buffer object 1381 * 1382 * @bo: buffer object in question 1383 * @fence: fence to add 1384 * @shared: true if fence should be added shared 1385 * 1386 */ 1387 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1388 bool shared) 1389 { 1390 struct dma_resv *resv = bo->tbo.base.resv; 1391 1392 if (shared) 1393 dma_resv_add_shared_fence(resv, fence); 1394 else 1395 dma_resv_add_excl_fence(resv, fence); 1396 } 1397 1398 /** 1399 * amdgpu_sync_wait_resv - Wait for BO reservation fences 1400 * 1401 * @bo: buffer object 1402 * @owner: fence owner 1403 * @intr: Whether the wait is interruptible 1404 * 1405 * Returns: 1406 * 0 on success, errno otherwise. 1407 */ 1408 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1409 { 1410 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1411 struct amdgpu_sync sync; 1412 int r; 1413 1414 amdgpu_sync_create(&sync); 1415 amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false); 1416 r = amdgpu_sync_wait(&sync, intr); 1417 amdgpu_sync_free(&sync); 1418 1419 return r; 1420 } 1421 1422 /** 1423 * amdgpu_bo_gpu_offset - return GPU offset of bo 1424 * @bo: amdgpu object for which we query the offset 1425 * 1426 * Note: object should either be pinned or reserved when calling this 1427 * function, it might be useful to add check for this for debugging. 1428 * 1429 * Returns: 1430 * current GPU offset of the object. 1431 */ 1432 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1433 { 1434 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1435 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1436 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1437 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1438 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1439 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1440 1441 return amdgpu_gmc_sign_extend(bo->tbo.offset); 1442 } 1443 1444 /** 1445 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1446 * @adev: amdgpu device object 1447 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1448 * 1449 * Returns: 1450 * Which of the allowed domains is preferred for pinning the BO for scanout. 1451 */ 1452 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1453 uint32_t domain) 1454 { 1455 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1456 domain = AMDGPU_GEM_DOMAIN_VRAM; 1457 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1458 domain = AMDGPU_GEM_DOMAIN_GTT; 1459 } 1460 return domain; 1461 } 1462