1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_vram_mgr.h" 43 #include "amdgpu_vm.h" 44 45 /** 46 * DOC: amdgpu_object 47 * 48 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 49 * represents memory used by driver (VRAM, system memory, etc.). The driver 50 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 51 * to create/destroy/set buffer object which are then managed by the kernel TTM 52 * memory manager. 53 * The interfaces are also used internally by kernel clients, including gfx, 54 * uvd, etc. for kernel managed allocations used by the GPU. 55 * 56 */ 57 58 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 59 { 60 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 61 62 amdgpu_bo_kunmap(bo); 63 64 if (bo->tbo.base.import_attach) 65 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 66 drm_gem_object_release(&bo->tbo.base); 67 amdgpu_bo_unref(&bo->parent); 68 kvfree(bo); 69 } 70 71 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 72 { 73 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 74 struct amdgpu_bo_user *ubo; 75 76 ubo = to_amdgpu_bo_user(bo); 77 kfree(ubo->metadata); 78 amdgpu_bo_destroy(tbo); 79 } 80 81 /** 82 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 83 * @bo: buffer object to be checked 84 * 85 * Uses destroy function associated with the object to determine if this is 86 * an &amdgpu_bo. 87 * 88 * Returns: 89 * true if the object belongs to &amdgpu_bo, false if not. 90 */ 91 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 92 { 93 if (bo->destroy == &amdgpu_bo_destroy || 94 bo->destroy == &amdgpu_bo_user_destroy) 95 return true; 96 97 return false; 98 } 99 100 /** 101 * amdgpu_bo_placement_from_domain - set buffer's placement 102 * @abo: &amdgpu_bo buffer object whose placement is to be set 103 * @domain: requested domain 104 * 105 * Sets buffer's placement according to requested domain and the buffer's 106 * flags. 107 */ 108 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 109 { 110 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 111 struct ttm_placement *placement = &abo->placement; 112 struct ttm_place *places = abo->placements; 113 u64 flags = abo->flags; 114 u32 c = 0; 115 116 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 117 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 118 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); 119 120 if (adev->gmc.mem_partitions && mem_id >= 0) { 121 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn; 122 /* 123 * memory partition range lpfn is inclusive start + size - 1 124 * TTM place lpfn is exclusive start + size 125 */ 126 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1; 127 } else { 128 places[c].fpfn = 0; 129 places[c].lpfn = 0; 130 } 131 places[c].mem_type = TTM_PL_VRAM; 132 places[c].flags = 0; 133 134 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 135 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); 136 else 137 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 138 139 if (abo->tbo.type == ttm_bo_type_kernel && 140 flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 141 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 142 143 c++; 144 } 145 146 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) { 147 places[c].fpfn = 0; 148 places[c].lpfn = 0; 149 places[c].mem_type = AMDGPU_PL_DOORBELL; 150 places[c].flags = 0; 151 c++; 152 } 153 154 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 155 places[c].fpfn = 0; 156 places[c].lpfn = 0; 157 places[c].mem_type = 158 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 159 AMDGPU_PL_PREEMPT : TTM_PL_TT; 160 places[c].flags = 0; 161 /* 162 * When GTT is just an alternative to VRAM make sure that we 163 * only use it as fallback and still try to fill up VRAM first. 164 */ 165 if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && 166 !(adev->flags & AMD_IS_APU)) 167 places[c].flags |= TTM_PL_FLAG_FALLBACK; 168 c++; 169 } 170 171 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 172 places[c].fpfn = 0; 173 places[c].lpfn = 0; 174 places[c].mem_type = TTM_PL_SYSTEM; 175 places[c].flags = 0; 176 c++; 177 } 178 179 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 180 places[c].fpfn = 0; 181 places[c].lpfn = 0; 182 places[c].mem_type = AMDGPU_PL_GDS; 183 places[c].flags = 0; 184 c++; 185 } 186 187 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 188 places[c].fpfn = 0; 189 places[c].lpfn = 0; 190 places[c].mem_type = AMDGPU_PL_GWS; 191 places[c].flags = 0; 192 c++; 193 } 194 195 if (domain & AMDGPU_GEM_DOMAIN_OA) { 196 places[c].fpfn = 0; 197 places[c].lpfn = 0; 198 places[c].mem_type = AMDGPU_PL_OA; 199 places[c].flags = 0; 200 c++; 201 } 202 203 if (!c) { 204 places[c].fpfn = 0; 205 places[c].lpfn = 0; 206 places[c].mem_type = TTM_PL_SYSTEM; 207 places[c].flags = 0; 208 c++; 209 } 210 211 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 212 213 placement->num_placement = c; 214 placement->placement = places; 215 } 216 217 /** 218 * amdgpu_bo_create_reserved - create reserved BO for kernel use 219 * 220 * @adev: amdgpu device object 221 * @size: size for the new BO 222 * @align: alignment for the new BO 223 * @domain: where to place it 224 * @bo_ptr: used to initialize BOs in structures 225 * @gpu_addr: GPU addr of the pinned BO 226 * @cpu_addr: optional CPU address mapping 227 * 228 * Allocates and pins a BO for kernel internal use, and returns it still 229 * reserved. 230 * 231 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 232 * 233 * Returns: 234 * 0 on success, negative error code otherwise. 235 */ 236 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 237 unsigned long size, int align, 238 u32 domain, struct amdgpu_bo **bo_ptr, 239 u64 *gpu_addr, void **cpu_addr) 240 { 241 struct amdgpu_bo_param bp; 242 bool free = false; 243 int r; 244 245 if (!size) { 246 amdgpu_bo_unref(bo_ptr); 247 return 0; 248 } 249 250 memset(&bp, 0, sizeof(bp)); 251 bp.size = size; 252 bp.byte_align = align; 253 bp.domain = domain; 254 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 255 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 256 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 257 bp.type = ttm_bo_type_kernel; 258 bp.resv = NULL; 259 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 260 261 if (!*bo_ptr) { 262 r = amdgpu_bo_create(adev, &bp, bo_ptr); 263 if (r) { 264 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 265 r); 266 return r; 267 } 268 free = true; 269 } 270 271 r = amdgpu_bo_reserve(*bo_ptr, false); 272 if (r) { 273 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 274 goto error_free; 275 } 276 277 r = amdgpu_bo_pin(*bo_ptr, domain); 278 if (r) { 279 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 280 goto error_unreserve; 281 } 282 283 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 284 if (r) { 285 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 286 goto error_unpin; 287 } 288 289 if (gpu_addr) 290 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 291 292 if (cpu_addr) { 293 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 294 if (r) { 295 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 296 goto error_unpin; 297 } 298 } 299 300 return 0; 301 302 error_unpin: 303 amdgpu_bo_unpin(*bo_ptr); 304 error_unreserve: 305 amdgpu_bo_unreserve(*bo_ptr); 306 307 error_free: 308 if (free) 309 amdgpu_bo_unref(bo_ptr); 310 311 return r; 312 } 313 314 /** 315 * amdgpu_bo_create_kernel - create BO for kernel use 316 * 317 * @adev: amdgpu device object 318 * @size: size for the new BO 319 * @align: alignment for the new BO 320 * @domain: where to place it 321 * @bo_ptr: used to initialize BOs in structures 322 * @gpu_addr: GPU addr of the pinned BO 323 * @cpu_addr: optional CPU address mapping 324 * 325 * Allocates and pins a BO for kernel internal use. 326 * 327 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 328 * 329 * Returns: 330 * 0 on success, negative error code otherwise. 331 */ 332 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 333 unsigned long size, int align, 334 u32 domain, struct amdgpu_bo **bo_ptr, 335 u64 *gpu_addr, void **cpu_addr) 336 { 337 int r; 338 339 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 340 gpu_addr, cpu_addr); 341 342 if (r) 343 return r; 344 345 if (*bo_ptr) 346 amdgpu_bo_unreserve(*bo_ptr); 347 348 return 0; 349 } 350 351 /** 352 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 353 * 354 * @adev: amdgpu device object 355 * @offset: offset of the BO 356 * @size: size of the BO 357 * @bo_ptr: used to initialize BOs in structures 358 * @cpu_addr: optional CPU address mapping 359 * 360 * Creates a kernel BO at a specific offset in VRAM. 361 * 362 * Returns: 363 * 0 on success, negative error code otherwise. 364 */ 365 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 366 uint64_t offset, uint64_t size, 367 struct amdgpu_bo **bo_ptr, void **cpu_addr) 368 { 369 struct ttm_operation_ctx ctx = { false, false }; 370 unsigned int i; 371 int r; 372 373 offset &= PAGE_MASK; 374 size = ALIGN(size, PAGE_SIZE); 375 376 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, 377 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL, 378 cpu_addr); 379 if (r) 380 return r; 381 382 if ((*bo_ptr) == NULL) 383 return 0; 384 385 /* 386 * Remove the original mem node and create a new one at the request 387 * position. 388 */ 389 if (cpu_addr) 390 amdgpu_bo_kunmap(*bo_ptr); 391 392 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 393 394 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 395 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 396 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 397 } 398 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 399 &(*bo_ptr)->tbo.resource, &ctx); 400 if (r) 401 goto error; 402 403 if (cpu_addr) { 404 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 405 if (r) 406 goto error; 407 } 408 409 amdgpu_bo_unreserve(*bo_ptr); 410 return 0; 411 412 error: 413 amdgpu_bo_unreserve(*bo_ptr); 414 amdgpu_bo_unref(bo_ptr); 415 return r; 416 } 417 418 /** 419 * amdgpu_bo_free_kernel - free BO for kernel use 420 * 421 * @bo: amdgpu BO to free 422 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 423 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 424 * 425 * unmaps and unpin a BO for kernel internal use. 426 */ 427 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 428 void **cpu_addr) 429 { 430 if (*bo == NULL) 431 return; 432 433 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend); 434 435 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 436 if (cpu_addr) 437 amdgpu_bo_kunmap(*bo); 438 439 amdgpu_bo_unpin(*bo); 440 amdgpu_bo_unreserve(*bo); 441 } 442 amdgpu_bo_unref(bo); 443 444 if (gpu_addr) 445 *gpu_addr = 0; 446 447 if (cpu_addr) 448 *cpu_addr = NULL; 449 } 450 451 /* Validate bo size is bit bigger than the request domain */ 452 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 453 unsigned long size, u32 domain) 454 { 455 struct ttm_resource_manager *man = NULL; 456 457 /* 458 * If GTT is part of requested domains the check must succeed to 459 * allow fall back to GTT. 460 */ 461 if (domain & AMDGPU_GEM_DOMAIN_GTT) 462 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 463 else if (domain & AMDGPU_GEM_DOMAIN_VRAM) 464 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 465 else 466 return true; 467 468 if (!man) { 469 if (domain & AMDGPU_GEM_DOMAIN_GTT) 470 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 471 return false; 472 } 473 474 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */ 475 if (size < man->size) 476 return true; 477 478 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size); 479 return false; 480 } 481 482 bool amdgpu_bo_support_uswc(u64 bo_flags) 483 { 484 485 #ifdef CONFIG_X86_32 486 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 487 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 488 */ 489 return false; 490 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 491 /* Don't try to enable write-combining when it can't work, or things 492 * may be slow 493 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 494 */ 495 496 #ifndef CONFIG_COMPILE_TEST 497 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 498 thanks to write-combining 499 #endif 500 501 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 502 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 503 "better performance thanks to write-combining\n"); 504 return false; 505 #else 506 /* For architectures that don't support WC memory, 507 * mask out the WC flag from the BO 508 */ 509 if (!drm_arch_can_wc_memory()) 510 return false; 511 512 return true; 513 #endif 514 } 515 516 /** 517 * amdgpu_bo_create - create an &amdgpu_bo buffer object 518 * @adev: amdgpu device object 519 * @bp: parameters to be used for the buffer object 520 * @bo_ptr: pointer to the buffer object pointer 521 * 522 * Creates an &amdgpu_bo buffer object. 523 * 524 * Returns: 525 * 0 for success or a negative error code on failure. 526 */ 527 int amdgpu_bo_create(struct amdgpu_device *adev, 528 struct amdgpu_bo_param *bp, 529 struct amdgpu_bo **bo_ptr) 530 { 531 struct ttm_operation_ctx ctx = { 532 .interruptible = (bp->type != ttm_bo_type_kernel), 533 .no_wait_gpu = bp->no_wait_gpu, 534 /* We opt to avoid OOM on system pages allocations */ 535 .gfp_retry_mayfail = true, 536 .allow_res_evict = bp->type != ttm_bo_type_kernel, 537 .resv = bp->resv 538 }; 539 struct amdgpu_bo *bo; 540 unsigned long page_align, size = bp->size; 541 int r; 542 543 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 544 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 545 /* GWS and OA don't need any alignment. */ 546 page_align = bp->byte_align; 547 size <<= PAGE_SHIFT; 548 549 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 550 /* Both size and alignment must be a multiple of 4. */ 551 page_align = ALIGN(bp->byte_align, 4); 552 size = ALIGN(size, 4) << PAGE_SHIFT; 553 } else { 554 /* Memory should be aligned at least to a page size. */ 555 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 556 size = ALIGN(size, PAGE_SIZE); 557 } 558 559 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 560 return -ENOMEM; 561 562 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 563 564 *bo_ptr = NULL; 565 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 566 if (bo == NULL) 567 return -ENOMEM; 568 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 569 bo->tbo.base.funcs = &amdgpu_gem_object_funcs; 570 bo->vm_bo = NULL; 571 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 572 bp->domain; 573 bo->allowed_domains = bo->preferred_domains; 574 if (bp->type != ttm_bo_type_kernel && 575 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 576 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 577 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 578 579 bo->flags = bp->flags; 580 581 if (adev->gmc.mem_partitions) 582 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */ 583 bo->xcp_id = bp->xcp_id_plus1 - 1; 584 else 585 /* For GPUs without spatial partitioning */ 586 bo->xcp_id = 0; 587 588 if (!amdgpu_bo_support_uswc(bo->flags)) 589 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 590 591 bo->tbo.bdev = &adev->mman.bdev; 592 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 593 AMDGPU_GEM_DOMAIN_GDS)) 594 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 595 else 596 amdgpu_bo_placement_from_domain(bo, bp->domain); 597 if (bp->type == ttm_bo_type_kernel) 598 bo->tbo.priority = 2; 599 else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE)) 600 bo->tbo.priority = 1; 601 602 if (!bp->destroy) 603 bp->destroy = &amdgpu_bo_destroy; 604 605 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 606 &bo->placement, page_align, &ctx, NULL, 607 bp->resv, bp->destroy); 608 if (unlikely(r != 0)) 609 return r; 610 611 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 612 amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 613 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 614 ctx.bytes_moved); 615 else 616 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 617 618 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 619 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 620 struct dma_fence *fence; 621 622 r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); 623 if (unlikely(r)) 624 goto fail_unreserve; 625 626 dma_resv_add_fence(bo->tbo.base.resv, fence, 627 DMA_RESV_USAGE_KERNEL); 628 dma_fence_put(fence); 629 } 630 if (!bp->resv) 631 amdgpu_bo_unreserve(bo); 632 *bo_ptr = bo; 633 634 trace_amdgpu_bo_create(bo); 635 636 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 637 if (bp->type == ttm_bo_type_device) 638 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 639 640 return 0; 641 642 fail_unreserve: 643 if (!bp->resv) 644 dma_resv_unlock(bo->tbo.base.resv); 645 amdgpu_bo_unref(&bo); 646 return r; 647 } 648 649 /** 650 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 651 * @adev: amdgpu device object 652 * @bp: parameters to be used for the buffer object 653 * @ubo_ptr: pointer to the buffer object pointer 654 * 655 * Create a BO to be used by user application; 656 * 657 * Returns: 658 * 0 for success or a negative error code on failure. 659 */ 660 661 int amdgpu_bo_create_user(struct amdgpu_device *adev, 662 struct amdgpu_bo_param *bp, 663 struct amdgpu_bo_user **ubo_ptr) 664 { 665 struct amdgpu_bo *bo_ptr; 666 int r; 667 668 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 669 bp->destroy = &amdgpu_bo_user_destroy; 670 r = amdgpu_bo_create(adev, bp, &bo_ptr); 671 if (r) 672 return r; 673 674 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 675 return r; 676 } 677 678 /** 679 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 680 * @adev: amdgpu device object 681 * @bp: parameters to be used for the buffer object 682 * @vmbo_ptr: pointer to the buffer object pointer 683 * 684 * Create a BO to be for GPUVM. 685 * 686 * Returns: 687 * 0 for success or a negative error code on failure. 688 */ 689 690 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 691 struct amdgpu_bo_param *bp, 692 struct amdgpu_bo_vm **vmbo_ptr) 693 { 694 struct amdgpu_bo *bo_ptr; 695 int r; 696 697 /* bo_ptr_size will be determined by the caller and it depends on 698 * num of amdgpu_vm_pt entries. 699 */ 700 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 701 r = amdgpu_bo_create(adev, bp, &bo_ptr); 702 if (r) 703 return r; 704 705 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 706 return r; 707 } 708 709 /** 710 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 711 * @bo: &amdgpu_bo buffer object to be mapped 712 * @ptr: kernel virtual address to be returned 713 * 714 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 715 * amdgpu_bo_kptr() to get the kernel virtual address. 716 * 717 * Returns: 718 * 0 for success or a negative error code on failure. 719 */ 720 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 721 { 722 void *kptr; 723 long r; 724 725 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 726 return -EPERM; 727 728 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 729 false, MAX_SCHEDULE_TIMEOUT); 730 if (r < 0) 731 return r; 732 733 kptr = amdgpu_bo_kptr(bo); 734 if (kptr) { 735 if (ptr) 736 *ptr = kptr; 737 return 0; 738 } 739 740 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 741 if (r) 742 return r; 743 744 if (ptr) 745 *ptr = amdgpu_bo_kptr(bo); 746 747 return 0; 748 } 749 750 /** 751 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 752 * @bo: &amdgpu_bo buffer object 753 * 754 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 755 * 756 * Returns: 757 * the virtual address of a buffer object area. 758 */ 759 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 760 { 761 bool is_iomem; 762 763 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 764 } 765 766 /** 767 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 768 * @bo: &amdgpu_bo buffer object to be unmapped 769 * 770 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 771 */ 772 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 773 { 774 if (bo->kmap.bo) 775 ttm_bo_kunmap(&bo->kmap); 776 } 777 778 /** 779 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 780 * @bo: &amdgpu_bo buffer object 781 * 782 * References the contained &ttm_buffer_object. 783 * 784 * Returns: 785 * a refcounted pointer to the &amdgpu_bo buffer object. 786 */ 787 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 788 { 789 if (bo == NULL) 790 return NULL; 791 792 drm_gem_object_get(&bo->tbo.base); 793 return bo; 794 } 795 796 /** 797 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 798 * @bo: &amdgpu_bo buffer object 799 * 800 * Unreferences the contained &ttm_buffer_object and clear the pointer 801 */ 802 void amdgpu_bo_unref(struct amdgpu_bo **bo) 803 { 804 if ((*bo) == NULL) 805 return; 806 807 drm_gem_object_put(&(*bo)->tbo.base); 808 *bo = NULL; 809 } 810 811 /** 812 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 813 * @bo: &amdgpu_bo buffer object to be pinned 814 * @domain: domain to be pinned to 815 * 816 * Pins the buffer object according to requested domain. If the memory is 817 * unbound gart memory, binds the pages into gart table. Adjusts pin_count and 818 * pin_size accordingly. 819 * 820 * Pinning means to lock pages in memory along with keeping them at a fixed 821 * offset. It is required when a buffer can not be moved, for example, when 822 * a display buffer is being scanned out. 823 * 824 * Returns: 825 * 0 for success or a negative error code on failure. 826 */ 827 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 828 { 829 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 830 struct ttm_operation_ctx ctx = { false, false }; 831 int r, i; 832 833 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 834 return -EPERM; 835 836 /* Check domain to be pinned to against preferred domains */ 837 if (bo->preferred_domains & domain) 838 domain = bo->preferred_domains & domain; 839 840 /* A shared bo cannot be migrated to VRAM */ 841 if (bo->tbo.base.import_attach) { 842 if (domain & AMDGPU_GEM_DOMAIN_GTT) 843 domain = AMDGPU_GEM_DOMAIN_GTT; 844 else 845 return -EINVAL; 846 } 847 848 if (bo->tbo.pin_count) { 849 uint32_t mem_type = bo->tbo.resource->mem_type; 850 uint32_t mem_flags = bo->tbo.resource->placement; 851 852 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 853 return -EINVAL; 854 855 if ((mem_type == TTM_PL_VRAM) && 856 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 857 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 858 return -EINVAL; 859 860 ttm_bo_pin(&bo->tbo); 861 return 0; 862 } 863 864 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 865 * See function amdgpu_display_supported_domains() 866 */ 867 domain = amdgpu_bo_get_preferred_domain(adev, domain); 868 869 if (bo->tbo.base.import_attach) 870 dma_buf_pin(bo->tbo.base.import_attach); 871 872 /* force to pin into visible video ram */ 873 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 874 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 875 amdgpu_bo_placement_from_domain(bo, domain); 876 for (i = 0; i < bo->placement.num_placement; i++) { 877 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && 878 bo->placements[i].mem_type == TTM_PL_VRAM) 879 bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; 880 } 881 882 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 883 if (unlikely(r)) { 884 dev_err(adev->dev, "%p pin failed\n", bo); 885 goto error; 886 } 887 888 ttm_bo_pin(&bo->tbo); 889 890 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 891 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 892 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 893 &adev->visible_pin_size); 894 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 895 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 896 } 897 898 error: 899 return r; 900 } 901 902 /** 903 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 904 * @bo: &amdgpu_bo buffer object to be unpinned 905 * 906 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 907 * Changes placement and pin size accordingly. 908 * 909 * Returns: 910 * 0 for success or a negative error code on failure. 911 */ 912 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 913 { 914 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 915 916 ttm_bo_unpin(&bo->tbo); 917 if (bo->tbo.pin_count) 918 return; 919 920 if (bo->tbo.base.import_attach) 921 dma_buf_unpin(bo->tbo.base.import_attach); 922 923 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 924 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 925 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 926 &adev->visible_pin_size); 927 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 928 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 929 } 930 931 } 932 933 static const char * const amdgpu_vram_names[] = { 934 "UNKNOWN", 935 "GDDR1", 936 "DDR2", 937 "GDDR3", 938 "GDDR4", 939 "GDDR5", 940 "HBM", 941 "DDR3", 942 "DDR4", 943 "GDDR6", 944 "DDR5", 945 "LPDDR4", 946 "LPDDR5" 947 }; 948 949 /** 950 * amdgpu_bo_init - initialize memory manager 951 * @adev: amdgpu device object 952 * 953 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 954 * 955 * Returns: 956 * 0 for success or a negative error code on failure. 957 */ 958 int amdgpu_bo_init(struct amdgpu_device *adev) 959 { 960 /* On A+A platform, VRAM can be mapped as WB */ 961 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 962 /* reserve PAT memory space to WC for VRAM */ 963 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 964 adev->gmc.aper_size); 965 966 if (r) { 967 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 968 return r; 969 } 970 971 /* Add an MTRR for the VRAM */ 972 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 973 adev->gmc.aper_size); 974 } 975 976 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 977 adev->gmc.mc_vram_size >> 20, 978 (unsigned long long)adev->gmc.aper_size >> 20); 979 DRM_INFO("RAM width %dbits %s\n", 980 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 981 return amdgpu_ttm_init(adev); 982 } 983 984 /** 985 * amdgpu_bo_fini - tear down memory manager 986 * @adev: amdgpu device object 987 * 988 * Reverses amdgpu_bo_init() to tear down memory manager. 989 */ 990 void amdgpu_bo_fini(struct amdgpu_device *adev) 991 { 992 int idx; 993 994 amdgpu_ttm_fini(adev); 995 996 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 997 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 998 arch_phys_wc_del(adev->gmc.vram_mtrr); 999 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1000 } 1001 drm_dev_exit(idx); 1002 } 1003 } 1004 1005 /** 1006 * amdgpu_bo_set_tiling_flags - set tiling flags 1007 * @bo: &amdgpu_bo buffer object 1008 * @tiling_flags: new flags 1009 * 1010 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1011 * kernel driver to set the tiling flags on a buffer. 1012 * 1013 * Returns: 1014 * 0 for success or a negative error code on failure. 1015 */ 1016 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1017 { 1018 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1019 struct amdgpu_bo_user *ubo; 1020 1021 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1022 if (adev->family <= AMDGPU_FAMILY_CZ && 1023 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1024 return -EINVAL; 1025 1026 ubo = to_amdgpu_bo_user(bo); 1027 ubo->tiling_flags = tiling_flags; 1028 return 0; 1029 } 1030 1031 /** 1032 * amdgpu_bo_get_tiling_flags - get tiling flags 1033 * @bo: &amdgpu_bo buffer object 1034 * @tiling_flags: returned flags 1035 * 1036 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1037 * set the tiling flags on a buffer. 1038 */ 1039 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1040 { 1041 struct amdgpu_bo_user *ubo; 1042 1043 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1044 dma_resv_assert_held(bo->tbo.base.resv); 1045 ubo = to_amdgpu_bo_user(bo); 1046 1047 if (tiling_flags) 1048 *tiling_flags = ubo->tiling_flags; 1049 } 1050 1051 /** 1052 * amdgpu_bo_set_metadata - set metadata 1053 * @bo: &amdgpu_bo buffer object 1054 * @metadata: new metadata 1055 * @metadata_size: size of the new metadata 1056 * @flags: flags of the new metadata 1057 * 1058 * Sets buffer object's metadata, its size and flags. 1059 * Used via GEM ioctl. 1060 * 1061 * Returns: 1062 * 0 for success or a negative error code on failure. 1063 */ 1064 int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata, 1065 u32 metadata_size, uint64_t flags) 1066 { 1067 struct amdgpu_bo_user *ubo; 1068 void *buffer; 1069 1070 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1071 ubo = to_amdgpu_bo_user(bo); 1072 if (!metadata_size) { 1073 if (ubo->metadata_size) { 1074 kfree(ubo->metadata); 1075 ubo->metadata = NULL; 1076 ubo->metadata_size = 0; 1077 } 1078 return 0; 1079 } 1080 1081 if (metadata == NULL) 1082 return -EINVAL; 1083 1084 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1085 if (buffer == NULL) 1086 return -ENOMEM; 1087 1088 kfree(ubo->metadata); 1089 ubo->metadata_flags = flags; 1090 ubo->metadata = buffer; 1091 ubo->metadata_size = metadata_size; 1092 1093 return 0; 1094 } 1095 1096 /** 1097 * amdgpu_bo_get_metadata - get metadata 1098 * @bo: &amdgpu_bo buffer object 1099 * @buffer: returned metadata 1100 * @buffer_size: size of the buffer 1101 * @metadata_size: size of the returned metadata 1102 * @flags: flags of the returned metadata 1103 * 1104 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1105 * less than metadata_size. 1106 * Used via GEM ioctl. 1107 * 1108 * Returns: 1109 * 0 for success or a negative error code on failure. 1110 */ 1111 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1112 size_t buffer_size, uint32_t *metadata_size, 1113 uint64_t *flags) 1114 { 1115 struct amdgpu_bo_user *ubo; 1116 1117 if (!buffer && !metadata_size) 1118 return -EINVAL; 1119 1120 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1121 ubo = to_amdgpu_bo_user(bo); 1122 if (metadata_size) 1123 *metadata_size = ubo->metadata_size; 1124 1125 if (buffer) { 1126 if (buffer_size < ubo->metadata_size) 1127 return -EINVAL; 1128 1129 if (ubo->metadata_size) 1130 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1131 } 1132 1133 if (flags) 1134 *flags = ubo->metadata_flags; 1135 1136 return 0; 1137 } 1138 1139 /** 1140 * amdgpu_bo_move_notify - notification about a memory move 1141 * @bo: pointer to a buffer object 1142 * @evict: if this move is evicting the buffer from the graphics address space 1143 * @new_mem: new resource for backing the BO 1144 * 1145 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1146 * bookkeeping. 1147 * TTM driver callback which is called when ttm moves a buffer. 1148 */ 1149 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1150 bool evict, 1151 struct ttm_resource *new_mem) 1152 { 1153 struct ttm_resource *old_mem = bo->resource; 1154 struct amdgpu_bo *abo; 1155 1156 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1157 return; 1158 1159 abo = ttm_to_amdgpu_bo(bo); 1160 amdgpu_vm_bo_move(abo, new_mem, evict); 1161 1162 amdgpu_bo_kunmap(abo); 1163 1164 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1165 old_mem && old_mem->mem_type != TTM_PL_SYSTEM) 1166 dma_buf_move_notify(abo->tbo.base.dma_buf); 1167 1168 /* move_notify is called before move happens */ 1169 trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, 1170 old_mem ? old_mem->mem_type : -1); 1171 } 1172 1173 /** 1174 * amdgpu_bo_release_notify - notification about a BO being released 1175 * @bo: pointer to a buffer object 1176 * 1177 * Wipes VRAM buffers whose contents should not be leaked before the 1178 * memory is released. 1179 */ 1180 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1181 { 1182 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1183 struct dma_fence *fence = NULL; 1184 struct amdgpu_bo *abo; 1185 int r; 1186 1187 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1188 return; 1189 1190 abo = ttm_to_amdgpu_bo(bo); 1191 1192 WARN_ON(abo->vm_bo); 1193 1194 if (abo->kfd_bo) 1195 amdgpu_amdkfd_release_notify(abo); 1196 1197 /* We only remove the fence if the resv has individualized. */ 1198 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1199 && bo->base.resv != &bo->base._resv); 1200 if (bo->base.resv == &bo->base._resv) 1201 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1202 1203 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1204 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1205 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1206 return; 1207 1208 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1209 return; 1210 1211 r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true); 1212 if (!WARN_ON(r)) { 1213 amdgpu_vram_mgr_set_cleared(bo->resource); 1214 amdgpu_bo_fence(abo, fence, false); 1215 dma_fence_put(fence); 1216 } 1217 1218 dma_resv_unlock(bo->base.resv); 1219 } 1220 1221 /** 1222 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1223 * @bo: pointer to a buffer object 1224 * 1225 * Notifies the driver we are taking a fault on this BO and have reserved it, 1226 * also performs bookkeeping. 1227 * TTM driver callback for dealing with vm faults. 1228 * 1229 * Returns: 1230 * 0 for success or a negative error code on failure. 1231 */ 1232 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1233 { 1234 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1235 struct ttm_operation_ctx ctx = { false, false }; 1236 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1237 int r; 1238 1239 /* Remember that this BO was accessed by the CPU */ 1240 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1241 1242 if (amdgpu_res_cpu_visible(adev, bo->resource)) 1243 return 0; 1244 1245 /* Can't move a pinned BO to visible VRAM */ 1246 if (abo->tbo.pin_count > 0) 1247 return VM_FAULT_SIGBUS; 1248 1249 /* hurrah the memory is not visible ! */ 1250 atomic64_inc(&adev->num_vram_cpu_page_faults); 1251 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1252 AMDGPU_GEM_DOMAIN_GTT); 1253 1254 /* Avoid costly evictions; only set GTT as a busy placement */ 1255 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 1256 1257 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1258 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1259 return VM_FAULT_NOPAGE; 1260 else if (unlikely(r)) 1261 return VM_FAULT_SIGBUS; 1262 1263 /* this should never happen */ 1264 if (bo->resource->mem_type == TTM_PL_VRAM && 1265 !amdgpu_res_cpu_visible(adev, bo->resource)) 1266 return VM_FAULT_SIGBUS; 1267 1268 ttm_bo_move_to_lru_tail_unlocked(bo); 1269 return 0; 1270 } 1271 1272 /** 1273 * amdgpu_bo_fence - add fence to buffer object 1274 * 1275 * @bo: buffer object in question 1276 * @fence: fence to add 1277 * @shared: true if fence should be added shared 1278 * 1279 */ 1280 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1281 bool shared) 1282 { 1283 struct dma_resv *resv = bo->tbo.base.resv; 1284 int r; 1285 1286 r = dma_resv_reserve_fences(resv, 1); 1287 if (r) { 1288 /* As last resort on OOM we block for the fence */ 1289 dma_fence_wait(fence, false); 1290 return; 1291 } 1292 1293 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1294 DMA_RESV_USAGE_WRITE); 1295 } 1296 1297 /** 1298 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1299 * 1300 * @adev: amdgpu device pointer 1301 * @resv: reservation object to sync to 1302 * @sync_mode: synchronization mode 1303 * @owner: fence owner 1304 * @intr: Whether the wait is interruptible 1305 * 1306 * Extract the fences from the reservation object and waits for them to finish. 1307 * 1308 * Returns: 1309 * 0 on success, errno otherwise. 1310 */ 1311 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1312 enum amdgpu_sync_mode sync_mode, void *owner, 1313 bool intr) 1314 { 1315 struct amdgpu_sync sync; 1316 int r; 1317 1318 amdgpu_sync_create(&sync); 1319 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1320 r = amdgpu_sync_wait(&sync, intr); 1321 amdgpu_sync_free(&sync); 1322 return r; 1323 } 1324 1325 /** 1326 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1327 * @bo: buffer object to wait for 1328 * @owner: fence owner 1329 * @intr: Whether the wait is interruptible 1330 * 1331 * Wrapper to wait for fences in a BO. 1332 * Returns: 1333 * 0 on success, errno otherwise. 1334 */ 1335 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1336 { 1337 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1338 1339 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1340 AMDGPU_SYNC_NE_OWNER, owner, intr); 1341 } 1342 1343 /** 1344 * amdgpu_bo_gpu_offset - return GPU offset of bo 1345 * @bo: amdgpu object for which we query the offset 1346 * 1347 * Note: object should either be pinned or reserved when calling this 1348 * function, it might be useful to add check for this for debugging. 1349 * 1350 * Returns: 1351 * current GPU offset of the object. 1352 */ 1353 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1354 { 1355 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1356 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1357 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1358 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1359 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1360 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1361 1362 return amdgpu_bo_gpu_offset_no_check(bo); 1363 } 1364 1365 /** 1366 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1367 * @bo: amdgpu object for which we query the offset 1368 * 1369 * Returns: 1370 * current GPU offset of the object without raising warnings. 1371 */ 1372 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1373 { 1374 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1375 uint64_t offset = AMDGPU_BO_INVALID_OFFSET; 1376 1377 if (bo->tbo.resource->mem_type == TTM_PL_TT) 1378 offset = amdgpu_gmc_agp_addr(&bo->tbo); 1379 1380 if (offset == AMDGPU_BO_INVALID_OFFSET) 1381 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1382 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1383 1384 return amdgpu_gmc_sign_extend(offset); 1385 } 1386 1387 /** 1388 * amdgpu_bo_mem_stats_placement - bo placement for memory accounting 1389 * @bo: the buffer object we should look at 1390 * 1391 * BO can have multiple preferred placements, to avoid double counting we want 1392 * to file it under a single placement for memory stats. 1393 * Luckily, if we take the highest set bit in preferred_domains the result is 1394 * quite sensible. 1395 * 1396 * Returns: 1397 * Which of the placements should the BO be accounted under. 1398 */ 1399 uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo) 1400 { 1401 uint32_t domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK; 1402 1403 if (!domain) 1404 return TTM_PL_SYSTEM; 1405 1406 switch (rounddown_pow_of_two(domain)) { 1407 case AMDGPU_GEM_DOMAIN_CPU: 1408 return TTM_PL_SYSTEM; 1409 case AMDGPU_GEM_DOMAIN_GTT: 1410 return TTM_PL_TT; 1411 case AMDGPU_GEM_DOMAIN_VRAM: 1412 return TTM_PL_VRAM; 1413 case AMDGPU_GEM_DOMAIN_GDS: 1414 return AMDGPU_PL_GDS; 1415 case AMDGPU_GEM_DOMAIN_GWS: 1416 return AMDGPU_PL_GWS; 1417 case AMDGPU_GEM_DOMAIN_OA: 1418 return AMDGPU_PL_OA; 1419 case AMDGPU_GEM_DOMAIN_DOORBELL: 1420 return AMDGPU_PL_DOORBELL; 1421 default: 1422 return TTM_PL_SYSTEM; 1423 } 1424 } 1425 1426 /** 1427 * amdgpu_bo_get_preferred_domain - get preferred domain 1428 * @adev: amdgpu device object 1429 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1430 * 1431 * Returns: 1432 * Which of the allowed domains is preferred for allocating the BO. 1433 */ 1434 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1435 uint32_t domain) 1436 { 1437 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1438 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1439 domain = AMDGPU_GEM_DOMAIN_VRAM; 1440 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1441 domain = AMDGPU_GEM_DOMAIN_GTT; 1442 } 1443 return domain; 1444 } 1445 1446 #if defined(CONFIG_DEBUG_FS) 1447 #define amdgpu_bo_print_flag(m, bo, flag) \ 1448 do { \ 1449 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1450 seq_printf((m), " " #flag); \ 1451 } \ 1452 } while (0) 1453 1454 /** 1455 * amdgpu_bo_print_info - print BO info in debugfs file 1456 * 1457 * @id: Index or Id of the BO 1458 * @bo: Requested BO for printing info 1459 * @m: debugfs file 1460 * 1461 * Print BO information in debugfs file 1462 * 1463 * Returns: 1464 * Size of the BO in bytes. 1465 */ 1466 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1467 { 1468 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1469 struct dma_buf_attachment *attachment; 1470 struct dma_buf *dma_buf; 1471 const char *placement; 1472 unsigned int pin_count; 1473 u64 size; 1474 1475 if (dma_resv_trylock(bo->tbo.base.resv)) { 1476 if (!bo->tbo.resource) { 1477 placement = "NONE"; 1478 } else { 1479 switch (bo->tbo.resource->mem_type) { 1480 case TTM_PL_VRAM: 1481 if (amdgpu_res_cpu_visible(adev, bo->tbo.resource)) 1482 placement = "VRAM VISIBLE"; 1483 else 1484 placement = "VRAM"; 1485 break; 1486 case TTM_PL_TT: 1487 placement = "GTT"; 1488 break; 1489 case AMDGPU_PL_GDS: 1490 placement = "GDS"; 1491 break; 1492 case AMDGPU_PL_GWS: 1493 placement = "GWS"; 1494 break; 1495 case AMDGPU_PL_OA: 1496 placement = "OA"; 1497 break; 1498 case AMDGPU_PL_PREEMPT: 1499 placement = "PREEMPTIBLE"; 1500 break; 1501 case AMDGPU_PL_DOORBELL: 1502 placement = "DOORBELL"; 1503 break; 1504 case TTM_PL_SYSTEM: 1505 default: 1506 placement = "CPU"; 1507 break; 1508 } 1509 } 1510 dma_resv_unlock(bo->tbo.base.resv); 1511 } else { 1512 placement = "UNKNOWN"; 1513 } 1514 1515 size = amdgpu_bo_size(bo); 1516 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1517 id, size, placement); 1518 1519 pin_count = READ_ONCE(bo->tbo.pin_count); 1520 if (pin_count) 1521 seq_printf(m, " pin count %d", pin_count); 1522 1523 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1524 attachment = READ_ONCE(bo->tbo.base.import_attach); 1525 1526 if (attachment) 1527 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino); 1528 else if (dma_buf) 1529 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino); 1530 1531 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1532 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1533 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1534 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1535 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1536 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1537 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1538 1539 seq_puts(m, "\n"); 1540 1541 return size; 1542 } 1543 #endif 1544