1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <drm/drm_fb_helper.h> 42 #include <linux/i2c.h> 43 #include <linux/i2c-algo-bit.h> 44 #include <linux/hrtimer.h> 45 #include "amdgpu_irq.h" 46 47 #include <drm/drm_dp_mst_helper.h> 48 #include "modules/inc/mod_freesync.h" 49 50 struct amdgpu_bo; 51 struct amdgpu_device; 52 struct amdgpu_encoder; 53 struct amdgpu_router; 54 struct amdgpu_hpd; 55 56 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 57 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 58 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 59 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 60 61 #define AMDGPU_MAX_HPD_PINS 6 62 #define AMDGPU_MAX_CRTCS 6 63 #define AMDGPU_MAX_AFMT_BLOCKS 9 64 65 enum amdgpu_rmx_type { 66 RMX_OFF, 67 RMX_FULL, 68 RMX_CENTER, 69 RMX_ASPECT 70 }; 71 72 enum amdgpu_underscan_type { 73 UNDERSCAN_OFF, 74 UNDERSCAN_ON, 75 UNDERSCAN_AUTO, 76 }; 77 78 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 79 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 80 81 enum amdgpu_hpd_id { 82 AMDGPU_HPD_1 = 0, 83 AMDGPU_HPD_2, 84 AMDGPU_HPD_3, 85 AMDGPU_HPD_4, 86 AMDGPU_HPD_5, 87 AMDGPU_HPD_6, 88 AMDGPU_HPD_LAST, 89 AMDGPU_HPD_NONE = 0xff, 90 }; 91 92 enum amdgpu_crtc_irq { 93 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 94 AMDGPU_CRTC_IRQ_VBLANK2, 95 AMDGPU_CRTC_IRQ_VBLANK3, 96 AMDGPU_CRTC_IRQ_VBLANK4, 97 AMDGPU_CRTC_IRQ_VBLANK5, 98 AMDGPU_CRTC_IRQ_VBLANK6, 99 AMDGPU_CRTC_IRQ_VLINE1, 100 AMDGPU_CRTC_IRQ_VLINE2, 101 AMDGPU_CRTC_IRQ_VLINE3, 102 AMDGPU_CRTC_IRQ_VLINE4, 103 AMDGPU_CRTC_IRQ_VLINE5, 104 AMDGPU_CRTC_IRQ_VLINE6, 105 AMDGPU_CRTC_IRQ_LAST, 106 AMDGPU_CRTC_IRQ_NONE = 0xff 107 }; 108 109 enum amdgpu_pageflip_irq { 110 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 111 AMDGPU_PAGEFLIP_IRQ_D2, 112 AMDGPU_PAGEFLIP_IRQ_D3, 113 AMDGPU_PAGEFLIP_IRQ_D4, 114 AMDGPU_PAGEFLIP_IRQ_D5, 115 AMDGPU_PAGEFLIP_IRQ_D6, 116 AMDGPU_PAGEFLIP_IRQ_LAST, 117 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 118 }; 119 120 enum amdgpu_flip_status { 121 AMDGPU_FLIP_NONE, 122 AMDGPU_FLIP_PENDING, 123 AMDGPU_FLIP_SUBMITTED 124 }; 125 126 #define AMDGPU_MAX_I2C_BUS 16 127 128 /* amdgpu gpio-based i2c 129 * 1. "mask" reg and bits 130 * grabs the gpio pins for software use 131 * 0=not held 1=held 132 * 2. "a" reg and bits 133 * output pin value 134 * 0=low 1=high 135 * 3. "en" reg and bits 136 * sets the pin direction 137 * 0=input 1=output 138 * 4. "y" reg and bits 139 * input pin value 140 * 0=low 1=high 141 */ 142 struct amdgpu_i2c_bus_rec { 143 bool valid; 144 /* id used by atom */ 145 uint8_t i2c_id; 146 /* id used by atom */ 147 enum amdgpu_hpd_id hpd; 148 /* can be used with hw i2c engine */ 149 bool hw_capable; 150 /* uses multi-media i2c engine */ 151 bool mm_i2c; 152 /* regs and bits */ 153 uint32_t mask_clk_reg; 154 uint32_t mask_data_reg; 155 uint32_t a_clk_reg; 156 uint32_t a_data_reg; 157 uint32_t en_clk_reg; 158 uint32_t en_data_reg; 159 uint32_t y_clk_reg; 160 uint32_t y_data_reg; 161 uint32_t mask_clk_mask; 162 uint32_t mask_data_mask; 163 uint32_t a_clk_mask; 164 uint32_t a_data_mask; 165 uint32_t en_clk_mask; 166 uint32_t en_data_mask; 167 uint32_t y_clk_mask; 168 uint32_t y_data_mask; 169 }; 170 171 #define AMDGPU_MAX_BIOS_CONNECTOR 16 172 173 /* pll flags */ 174 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 175 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 176 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 177 #define AMDGPU_PLL_LEGACY (1 << 3) 178 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 179 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 180 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 181 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 182 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 183 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 184 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 185 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 186 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 187 #define AMDGPU_PLL_IS_LCD (1 << 13) 188 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 189 190 struct amdgpu_pll { 191 /* reference frequency */ 192 uint32_t reference_freq; 193 194 /* fixed dividers */ 195 uint32_t reference_div; 196 uint32_t post_div; 197 198 /* pll in/out limits */ 199 uint32_t pll_in_min; 200 uint32_t pll_in_max; 201 uint32_t pll_out_min; 202 uint32_t pll_out_max; 203 uint32_t lcd_pll_out_min; 204 uint32_t lcd_pll_out_max; 205 uint32_t best_vco; 206 207 /* divider limits */ 208 uint32_t min_ref_div; 209 uint32_t max_ref_div; 210 uint32_t min_post_div; 211 uint32_t max_post_div; 212 uint32_t min_feedback_div; 213 uint32_t max_feedback_div; 214 uint32_t min_frac_feedback_div; 215 uint32_t max_frac_feedback_div; 216 217 /* flags for the current clock */ 218 uint32_t flags; 219 220 /* pll id */ 221 uint32_t id; 222 }; 223 224 struct amdgpu_i2c_chan { 225 struct i2c_adapter adapter; 226 struct drm_device *dev; 227 struct i2c_algo_bit_data bit; 228 struct amdgpu_i2c_bus_rec rec; 229 struct drm_dp_aux aux; 230 bool has_aux; 231 struct mutex mutex; 232 }; 233 234 struct amdgpu_fbdev; 235 236 struct amdgpu_afmt { 237 bool enabled; 238 int offset; 239 bool last_buffer_filled_status; 240 int id; 241 struct amdgpu_audio_pin *pin; 242 }; 243 244 /* 245 * Audio 246 */ 247 struct amdgpu_audio_pin { 248 int channels; 249 int rate; 250 int bits_per_sample; 251 u8 status_bits; 252 u8 category_code; 253 u32 offset; 254 bool connected; 255 u32 id; 256 }; 257 258 struct amdgpu_audio { 259 bool enabled; 260 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 261 int num_pins; 262 }; 263 264 struct amdgpu_display_funcs { 265 /* display watermarks */ 266 void (*bandwidth_update)(struct amdgpu_device *adev); 267 /* get frame count */ 268 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 269 /* wait for vblank */ 270 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 271 /* set backlight level */ 272 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 273 u8 level); 274 /* get backlight level */ 275 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 276 /* hotplug detect */ 277 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 278 void (*hpd_set_polarity)(struct amdgpu_device *adev, 279 enum amdgpu_hpd_id hpd); 280 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 281 /* pageflipping */ 282 void (*page_flip)(struct amdgpu_device *adev, 283 int crtc_id, u64 crtc_base, bool async); 284 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 285 u32 *vbl, u32 *position); 286 /* display topology setup */ 287 void (*add_encoder)(struct amdgpu_device *adev, 288 uint32_t encoder_enum, 289 uint32_t supported_device, 290 u16 caps); 291 void (*add_connector)(struct amdgpu_device *adev, 292 uint32_t connector_id, 293 uint32_t supported_device, 294 int connector_type, 295 struct amdgpu_i2c_bus_rec *i2c_bus, 296 uint16_t connector_object_id, 297 struct amdgpu_hpd *hpd, 298 struct amdgpu_router *router); 299 /* it is used to enter or exit into free sync mode */ 300 int (*notify_freesync)(struct drm_device *dev, void *data, 301 struct drm_file *filp); 302 /* it is used to allow enablement of freesync mode */ 303 int (*set_freesync_property)(struct drm_connector *connector, 304 struct drm_property *property, 305 uint64_t val); 306 307 308 }; 309 310 struct amdgpu_framebuffer { 311 struct drm_framebuffer base; 312 struct drm_gem_object *obj; 313 314 /* caching for later use */ 315 uint64_t address; 316 }; 317 318 struct amdgpu_fbdev { 319 struct drm_fb_helper helper; 320 struct amdgpu_framebuffer rfb; 321 struct list_head fbdev_list; 322 struct amdgpu_device *adev; 323 }; 324 325 struct amdgpu_mode_info { 326 struct atom_context *atom_context; 327 struct card_info *atom_card_info; 328 bool mode_config_initialized; 329 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 330 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 331 /* DVI-I properties */ 332 struct drm_property *coherent_mode_property; 333 /* DAC enable load detect */ 334 struct drm_property *load_detect_property; 335 /* underscan */ 336 struct drm_property *underscan_property; 337 struct drm_property *underscan_hborder_property; 338 struct drm_property *underscan_vborder_property; 339 /* audio */ 340 struct drm_property *audio_property; 341 /* FMT dithering */ 342 struct drm_property *dither_property; 343 /* hardcoded DFP edid from BIOS */ 344 struct edid *bios_hardcoded_edid; 345 int bios_hardcoded_edid_size; 346 347 /* pointer to fbdev info structure */ 348 struct amdgpu_fbdev *rfbdev; 349 /* firmware flags */ 350 u16 firmware_flags; 351 /* pointer to backlight encoder */ 352 struct amdgpu_encoder *bl_encoder; 353 struct amdgpu_audio audio; /* audio stuff */ 354 int num_crtc; /* number of crtcs */ 355 int num_hpd; /* number of hpd pins */ 356 int num_dig; /* number of dig blocks */ 357 int disp_priority; 358 const struct amdgpu_display_funcs *funcs; 359 }; 360 361 #define AMDGPU_MAX_BL_LEVEL 0xFF 362 363 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 364 365 struct amdgpu_backlight_privdata { 366 struct amdgpu_encoder *encoder; 367 uint8_t negative; 368 }; 369 370 #endif 371 372 struct amdgpu_atom_ss { 373 uint16_t percentage; 374 uint16_t percentage_divider; 375 uint8_t type; 376 uint16_t step; 377 uint8_t delay; 378 uint8_t range; 379 uint8_t refdiv; 380 /* asic_ss */ 381 uint16_t rate; 382 uint16_t amount; 383 }; 384 385 struct amdgpu_crtc { 386 struct drm_crtc base; 387 int crtc_id; 388 bool enabled; 389 bool can_tile; 390 uint32_t crtc_offset; 391 struct drm_gem_object *cursor_bo; 392 uint64_t cursor_addr; 393 int cursor_x; 394 int cursor_y; 395 int cursor_hot_x; 396 int cursor_hot_y; 397 int cursor_width; 398 int cursor_height; 399 int max_cursor_width; 400 int max_cursor_height; 401 enum amdgpu_rmx_type rmx_type; 402 u8 h_border; 403 u8 v_border; 404 fixed20_12 vsc; 405 fixed20_12 hsc; 406 struct drm_display_mode native_mode; 407 u32 pll_id; 408 /* page flipping */ 409 struct amdgpu_flip_work *pflip_works; 410 enum amdgpu_flip_status pflip_status; 411 int deferred_flip_completion; 412 /* pll sharing */ 413 struct amdgpu_atom_ss ss; 414 bool ss_enabled; 415 u32 adjusted_clock; 416 int bpc; 417 u32 pll_reference_div; 418 u32 pll_post_div; 419 u32 pll_flags; 420 struct drm_encoder *encoder; 421 struct drm_connector *connector; 422 /* for dpm */ 423 u32 line_time; 424 u32 wm_low; 425 u32 wm_high; 426 u32 lb_vblank_lead_lines; 427 struct drm_display_mode hw_mode; 428 /* for virtual dce */ 429 struct hrtimer vblank_timer; 430 enum amdgpu_interrupt_state vsync_timer_enabled; 431 432 int otg_inst; 433 uint32_t flip_flags; 434 /* After Set Mode stream will be non-NULL */ 435 const struct dc_stream *stream; 436 struct drm_pending_vblank_event *event; 437 }; 438 439 struct amdgpu_encoder_atom_dig { 440 bool linkb; 441 /* atom dig */ 442 bool coherent_mode; 443 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 444 /* atom lvds/edp */ 445 uint32_t lcd_misc; 446 uint16_t panel_pwr_delay; 447 uint32_t lcd_ss_id; 448 /* panel mode */ 449 struct drm_display_mode native_mode; 450 struct backlight_device *bl_dev; 451 int dpms_mode; 452 uint8_t backlight_level; 453 int panel_mode; 454 struct amdgpu_afmt *afmt; 455 }; 456 457 struct amdgpu_encoder { 458 struct drm_encoder base; 459 uint32_t encoder_enum; 460 uint32_t encoder_id; 461 uint32_t devices; 462 uint32_t active_device; 463 uint32_t flags; 464 uint32_t pixel_clock; 465 enum amdgpu_rmx_type rmx_type; 466 enum amdgpu_underscan_type underscan_type; 467 uint32_t underscan_hborder; 468 uint32_t underscan_vborder; 469 struct drm_display_mode native_mode; 470 void *enc_priv; 471 int audio_polling_active; 472 bool is_ext_encoder; 473 u16 caps; 474 }; 475 476 struct amdgpu_connector_atom_dig { 477 /* displayport */ 478 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 479 u8 dp_sink_type; 480 int dp_clock; 481 int dp_lane_count; 482 bool edp_on; 483 }; 484 485 struct amdgpu_gpio_rec { 486 bool valid; 487 u8 id; 488 u32 reg; 489 u32 mask; 490 u32 shift; 491 }; 492 493 struct amdgpu_hpd { 494 enum amdgpu_hpd_id hpd; 495 u8 plugged_state; 496 struct amdgpu_gpio_rec gpio; 497 }; 498 499 struct amdgpu_router { 500 u32 router_id; 501 struct amdgpu_i2c_bus_rec i2c_info; 502 u8 i2c_addr; 503 /* i2c mux */ 504 bool ddc_valid; 505 u8 ddc_mux_type; 506 u8 ddc_mux_control_pin; 507 u8 ddc_mux_state; 508 /* clock/data mux */ 509 bool cd_valid; 510 u8 cd_mux_type; 511 u8 cd_mux_control_pin; 512 u8 cd_mux_state; 513 }; 514 515 enum amdgpu_connector_audio { 516 AMDGPU_AUDIO_DISABLE = 0, 517 AMDGPU_AUDIO_ENABLE = 1, 518 AMDGPU_AUDIO_AUTO = 2 519 }; 520 521 enum amdgpu_connector_dither { 522 AMDGPU_FMT_DITHER_DISABLE = 0, 523 AMDGPU_FMT_DITHER_ENABLE = 1, 524 }; 525 526 struct amdgpu_dm_dp_aux { 527 struct drm_dp_aux aux; 528 uint32_t link_index; 529 }; 530 531 struct amdgpu_i2c_adapter { 532 struct i2c_adapter base; 533 struct amdgpu_display_manager *dm; 534 uint32_t link_index; 535 }; 536 537 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 538 539 struct amdgpu_connector { 540 struct drm_connector base; 541 uint32_t connector_id; 542 uint32_t devices; 543 struct amdgpu_i2c_chan *ddc_bus; 544 /* some systems have an hdmi and vga port with a shared ddc line */ 545 bool shared_ddc; 546 bool use_digital; 547 /* we need to mind the EDID between detect 548 and get modes due to analog/digital/tvencoder */ 549 struct edid *edid; 550 /* number of modes generated from EDID at 'dc_sink' */ 551 int num_modes; 552 /* The 'old' sink - before an HPD. 553 * The 'current' sink is in dc_link->sink. */ 554 const struct dc_sink *dc_sink; 555 const struct dc_link *dc_link; 556 const struct dc_sink *dc_em_sink; 557 const struct dc_stream *stream; 558 void *con_priv; 559 bool dac_load_detect; 560 bool detected_by_load; /* if the connection status was determined by load */ 561 uint16_t connector_object_id; 562 struct amdgpu_hpd hpd; 563 struct amdgpu_router router; 564 struct amdgpu_i2c_chan *router_bus; 565 enum amdgpu_connector_audio audio; 566 enum amdgpu_connector_dither dither; 567 unsigned pixelclock_for_modeset; 568 569 struct drm_dp_mst_topology_mgr mst_mgr; 570 struct amdgpu_dm_dp_aux dm_dp_aux; 571 struct drm_dp_mst_port *port; 572 struct amdgpu_connector *mst_port; 573 struct amdgpu_encoder *mst_encoder; 574 struct semaphore mst_sem; 575 576 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 577 struct amdgpu_i2c_adapter *i2c; 578 579 /* Monitor range limits */ 580 int min_vfreq ; 581 int max_vfreq ; 582 int pixel_clock_mhz; 583 584 /*freesync caps*/ 585 struct mod_freesync_caps caps; 586 587 struct mutex hpd_lock; 588 589 }; 590 591 /* TODO: start to use this struct and remove same field from base one */ 592 struct amdgpu_mst_connector { 593 struct amdgpu_connector base; 594 595 struct drm_dp_mst_topology_mgr mst_mgr; 596 struct amdgpu_dm_dp_aux dm_dp_aux; 597 struct drm_dp_mst_port *port; 598 struct amdgpu_connector *mst_port; 599 bool is_mst_connector; 600 struct amdgpu_encoder *mst_encoder; 601 }; 602 603 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 604 ((em) == ATOM_ENCODER_MODE_DP_MST)) 605 606 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 607 #define DRM_SCANOUTPOS_VALID (1 << 0) 608 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 609 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 610 #define USE_REAL_VBLANKSTART (1 << 30) 611 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 612 613 void amdgpu_link_encoder_connector(struct drm_device *dev); 614 615 struct drm_connector * 616 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 617 struct drm_connector * 618 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 619 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 620 u32 pixel_clock); 621 622 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 623 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 624 625 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); 626 627 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 628 629 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 630 unsigned int flags, int *vpos, int *hpos, 631 ktime_t *stime, ktime_t *etime, 632 const struct drm_display_mode *mode); 633 634 int amdgpu_framebuffer_init(struct drm_device *dev, 635 struct amdgpu_framebuffer *rfb, 636 const struct drm_mode_fb_cmd2 *mode_cmd, 637 struct drm_gem_object *obj); 638 639 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 640 641 void amdgpu_enc_destroy(struct drm_encoder *encoder); 642 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 643 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 644 const struct drm_display_mode *mode, 645 struct drm_display_mode *adjusted_mode); 646 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 647 struct drm_display_mode *adjusted_mode); 648 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 649 650 /* fbdev layer */ 651 int amdgpu_fbdev_init(struct amdgpu_device *adev); 652 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 653 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 654 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 655 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 656 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); 657 658 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); 659 660 661 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 662 663 /* amdgpu_display.c */ 664 void amdgpu_print_display_setup(struct drm_device *dev); 665 int amdgpu_modeset_create_props(struct amdgpu_device *adev); 666 int amdgpu_crtc_set_config(struct drm_mode_set *set, 667 struct drm_modeset_acquire_ctx *ctx); 668 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, 669 struct drm_framebuffer *fb, 670 struct drm_pending_vblank_event *event, 671 uint32_t page_flip_flags, uint32_t target, 672 struct drm_modeset_acquire_ctx *ctx); 673 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 674 675 #endif 676