1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef AMDGPU_MODE_H 31 #define AMDGPU_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <linux/i2c.h> 42 #include <linux/i2c-algo-bit.h> 43 #include <linux/hrtimer.h> 44 #include "amdgpu_irq.h" 45 46 #include <drm/drm_dp_mst_helper.h> 47 #include "modules/inc/mod_freesync.h" 48 49 struct amdgpu_bo; 50 struct amdgpu_device; 51 struct amdgpu_encoder; 52 struct amdgpu_router; 53 struct amdgpu_hpd; 54 55 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 56 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 57 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 58 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 59 60 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base); 61 62 #define AMDGPU_MAX_HPD_PINS 6 63 #define AMDGPU_MAX_CRTCS 6 64 #define AMDGPU_MAX_PLANES 6 65 #define AMDGPU_MAX_AFMT_BLOCKS 9 66 67 enum amdgpu_rmx_type { 68 RMX_OFF, 69 RMX_FULL, 70 RMX_CENTER, 71 RMX_ASPECT 72 }; 73 74 enum amdgpu_underscan_type { 75 UNDERSCAN_OFF, 76 UNDERSCAN_ON, 77 UNDERSCAN_AUTO, 78 }; 79 80 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 81 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 82 83 enum amdgpu_hpd_id { 84 AMDGPU_HPD_1 = 0, 85 AMDGPU_HPD_2, 86 AMDGPU_HPD_3, 87 AMDGPU_HPD_4, 88 AMDGPU_HPD_5, 89 AMDGPU_HPD_6, 90 AMDGPU_HPD_NONE = 0xff, 91 }; 92 93 enum amdgpu_crtc_irq { 94 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 95 AMDGPU_CRTC_IRQ_VBLANK2, 96 AMDGPU_CRTC_IRQ_VBLANK3, 97 AMDGPU_CRTC_IRQ_VBLANK4, 98 AMDGPU_CRTC_IRQ_VBLANK5, 99 AMDGPU_CRTC_IRQ_VBLANK6, 100 AMDGPU_CRTC_IRQ_VLINE1, 101 AMDGPU_CRTC_IRQ_VLINE2, 102 AMDGPU_CRTC_IRQ_VLINE3, 103 AMDGPU_CRTC_IRQ_VLINE4, 104 AMDGPU_CRTC_IRQ_VLINE5, 105 AMDGPU_CRTC_IRQ_VLINE6, 106 AMDGPU_CRTC_IRQ_NONE = 0xff 107 }; 108 109 enum amdgpu_pageflip_irq { 110 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 111 AMDGPU_PAGEFLIP_IRQ_D2, 112 AMDGPU_PAGEFLIP_IRQ_D3, 113 AMDGPU_PAGEFLIP_IRQ_D4, 114 AMDGPU_PAGEFLIP_IRQ_D5, 115 AMDGPU_PAGEFLIP_IRQ_D6, 116 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 117 }; 118 119 enum amdgpu_flip_status { 120 AMDGPU_FLIP_NONE, 121 AMDGPU_FLIP_PENDING, 122 AMDGPU_FLIP_SUBMITTED 123 }; 124 125 #define AMDGPU_MAX_I2C_BUS 16 126 127 /* amdgpu gpio-based i2c 128 * 1. "mask" reg and bits 129 * grabs the gpio pins for software use 130 * 0=not held 1=held 131 * 2. "a" reg and bits 132 * output pin value 133 * 0=low 1=high 134 * 3. "en" reg and bits 135 * sets the pin direction 136 * 0=input 1=output 137 * 4. "y" reg and bits 138 * input pin value 139 * 0=low 1=high 140 */ 141 struct amdgpu_i2c_bus_rec { 142 bool valid; 143 /* id used by atom */ 144 uint8_t i2c_id; 145 /* id used by atom */ 146 enum amdgpu_hpd_id hpd; 147 /* can be used with hw i2c engine */ 148 bool hw_capable; 149 /* uses multi-media i2c engine */ 150 bool mm_i2c; 151 /* regs and bits */ 152 uint32_t mask_clk_reg; 153 uint32_t mask_data_reg; 154 uint32_t a_clk_reg; 155 uint32_t a_data_reg; 156 uint32_t en_clk_reg; 157 uint32_t en_data_reg; 158 uint32_t y_clk_reg; 159 uint32_t y_data_reg; 160 uint32_t mask_clk_mask; 161 uint32_t mask_data_mask; 162 uint32_t a_clk_mask; 163 uint32_t a_data_mask; 164 uint32_t en_clk_mask; 165 uint32_t en_data_mask; 166 uint32_t y_clk_mask; 167 uint32_t y_data_mask; 168 }; 169 170 #define AMDGPU_MAX_BIOS_CONNECTOR 16 171 172 /* pll flags */ 173 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 174 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 175 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 176 #define AMDGPU_PLL_LEGACY (1 << 3) 177 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 178 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 179 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 180 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 181 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 182 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 183 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 184 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 185 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 186 #define AMDGPU_PLL_IS_LCD (1 << 13) 187 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 188 189 struct amdgpu_pll { 190 /* reference frequency */ 191 uint32_t reference_freq; 192 193 /* fixed dividers */ 194 uint32_t reference_div; 195 uint32_t post_div; 196 197 /* pll in/out limits */ 198 uint32_t pll_in_min; 199 uint32_t pll_in_max; 200 uint32_t pll_out_min; 201 uint32_t pll_out_max; 202 uint32_t lcd_pll_out_min; 203 uint32_t lcd_pll_out_max; 204 uint32_t best_vco; 205 206 /* divider limits */ 207 uint32_t min_ref_div; 208 uint32_t max_ref_div; 209 uint32_t min_post_div; 210 uint32_t max_post_div; 211 uint32_t min_feedback_div; 212 uint32_t max_feedback_div; 213 uint32_t min_frac_feedback_div; 214 uint32_t max_frac_feedback_div; 215 216 /* flags for the current clock */ 217 uint32_t flags; 218 219 /* pll id */ 220 uint32_t id; 221 }; 222 223 struct amdgpu_i2c_chan { 224 struct i2c_adapter adapter; 225 struct drm_device *dev; 226 struct i2c_algo_bit_data bit; 227 struct amdgpu_i2c_bus_rec rec; 228 struct drm_dp_aux aux; 229 bool has_aux; 230 struct mutex mutex; 231 }; 232 233 struct amdgpu_fbdev; 234 235 struct amdgpu_afmt { 236 bool enabled; 237 int offset; 238 bool last_buffer_filled_status; 239 int id; 240 struct amdgpu_audio_pin *pin; 241 }; 242 243 /* 244 * Audio 245 */ 246 struct amdgpu_audio_pin { 247 int channels; 248 int rate; 249 int bits_per_sample; 250 u8 status_bits; 251 u8 category_code; 252 u32 offset; 253 bool connected; 254 u32 id; 255 }; 256 257 struct amdgpu_audio { 258 bool enabled; 259 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 260 int num_pins; 261 }; 262 263 struct amdgpu_display_funcs { 264 /* display watermarks */ 265 void (*bandwidth_update)(struct amdgpu_device *adev); 266 /* get frame count */ 267 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 268 /* set backlight level */ 269 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 270 u8 level); 271 /* get backlight level */ 272 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 273 /* hotplug detect */ 274 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 275 void (*hpd_set_polarity)(struct amdgpu_device *adev, 276 enum amdgpu_hpd_id hpd); 277 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 278 /* pageflipping */ 279 void (*page_flip)(struct amdgpu_device *adev, 280 int crtc_id, u64 crtc_base, bool async); 281 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 282 u32 *vbl, u32 *position); 283 /* display topology setup */ 284 void (*add_encoder)(struct amdgpu_device *adev, 285 uint32_t encoder_enum, 286 uint32_t supported_device, 287 u16 caps); 288 void (*add_connector)(struct amdgpu_device *adev, 289 uint32_t connector_id, 290 uint32_t supported_device, 291 int connector_type, 292 struct amdgpu_i2c_bus_rec *i2c_bus, 293 uint16_t connector_object_id, 294 struct amdgpu_hpd *hpd, 295 struct amdgpu_router *router); 296 297 298 }; 299 300 struct amdgpu_framebuffer { 301 struct drm_framebuffer base; 302 303 /* caching for later use */ 304 uint64_t address; 305 }; 306 307 struct amdgpu_fbdev { 308 struct drm_fb_helper helper; 309 struct amdgpu_framebuffer rfb; 310 struct list_head fbdev_list; 311 struct amdgpu_device *adev; 312 }; 313 314 struct amdgpu_mode_info { 315 struct atom_context *atom_context; 316 struct card_info *atom_card_info; 317 bool mode_config_initialized; 318 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 319 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 320 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 321 /* DVI-I properties */ 322 struct drm_property *coherent_mode_property; 323 /* DAC enable load detect */ 324 struct drm_property *load_detect_property; 325 /* underscan */ 326 struct drm_property *underscan_property; 327 struct drm_property *underscan_hborder_property; 328 struct drm_property *underscan_vborder_property; 329 /* audio */ 330 struct drm_property *audio_property; 331 /* FMT dithering */ 332 struct drm_property *dither_property; 333 /* maximum number of bits per channel for monitor color */ 334 struct drm_property *max_bpc_property; 335 /* Adaptive Backlight Modulation (power feature) */ 336 struct drm_property *abm_level_property; 337 /* hardcoded DFP edid from BIOS */ 338 struct edid *bios_hardcoded_edid; 339 int bios_hardcoded_edid_size; 340 341 /* pointer to fbdev info structure */ 342 struct amdgpu_fbdev *rfbdev; 343 /* firmware flags */ 344 u16 firmware_flags; 345 /* pointer to backlight encoder */ 346 struct amdgpu_encoder *bl_encoder; 347 u8 bl_level; /* saved backlight level */ 348 struct amdgpu_audio audio; /* audio stuff */ 349 int num_crtc; /* number of crtcs */ 350 int num_hpd; /* number of hpd pins */ 351 int num_dig; /* number of dig blocks */ 352 int disp_priority; 353 const struct amdgpu_display_funcs *funcs; 354 const enum drm_plane_type *plane_type; 355 }; 356 357 #define AMDGPU_MAX_BL_LEVEL 0xFF 358 359 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 360 361 struct amdgpu_backlight_privdata { 362 struct amdgpu_encoder *encoder; 363 uint8_t negative; 364 }; 365 366 #endif 367 368 struct amdgpu_atom_ss { 369 uint16_t percentage; 370 uint16_t percentage_divider; 371 uint8_t type; 372 uint16_t step; 373 uint8_t delay; 374 uint8_t range; 375 uint8_t refdiv; 376 /* asic_ss */ 377 uint16_t rate; 378 uint16_t amount; 379 }; 380 381 struct amdgpu_crtc { 382 struct drm_crtc base; 383 int crtc_id; 384 bool enabled; 385 bool can_tile; 386 uint32_t crtc_offset; 387 struct drm_gem_object *cursor_bo; 388 uint64_t cursor_addr; 389 int cursor_x; 390 int cursor_y; 391 int cursor_hot_x; 392 int cursor_hot_y; 393 int cursor_width; 394 int cursor_height; 395 int max_cursor_width; 396 int max_cursor_height; 397 enum amdgpu_rmx_type rmx_type; 398 u8 h_border; 399 u8 v_border; 400 fixed20_12 vsc; 401 fixed20_12 hsc; 402 struct drm_display_mode native_mode; 403 u32 pll_id; 404 /* page flipping */ 405 struct amdgpu_flip_work *pflip_works; 406 enum amdgpu_flip_status pflip_status; 407 int deferred_flip_completion; 408 /* pll sharing */ 409 struct amdgpu_atom_ss ss; 410 bool ss_enabled; 411 u32 adjusted_clock; 412 int bpc; 413 u32 pll_reference_div; 414 u32 pll_post_div; 415 u32 pll_flags; 416 struct drm_encoder *encoder; 417 struct drm_connector *connector; 418 /* for dpm */ 419 u32 line_time; 420 u32 wm_low; 421 u32 wm_high; 422 u32 lb_vblank_lead_lines; 423 struct drm_display_mode hw_mode; 424 /* for virtual dce */ 425 struct hrtimer vblank_timer; 426 enum amdgpu_interrupt_state vsync_timer_enabled; 427 428 int otg_inst; 429 struct drm_pending_vblank_event *event; 430 }; 431 432 struct amdgpu_encoder_atom_dig { 433 bool linkb; 434 /* atom dig */ 435 bool coherent_mode; 436 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 437 /* atom lvds/edp */ 438 uint32_t lcd_misc; 439 uint16_t panel_pwr_delay; 440 uint32_t lcd_ss_id; 441 /* panel mode */ 442 struct drm_display_mode native_mode; 443 struct backlight_device *bl_dev; 444 int dpms_mode; 445 uint8_t backlight_level; 446 int panel_mode; 447 struct amdgpu_afmt *afmt; 448 }; 449 450 struct amdgpu_encoder { 451 struct drm_encoder base; 452 uint32_t encoder_enum; 453 uint32_t encoder_id; 454 uint32_t devices; 455 uint32_t active_device; 456 uint32_t flags; 457 uint32_t pixel_clock; 458 enum amdgpu_rmx_type rmx_type; 459 enum amdgpu_underscan_type underscan_type; 460 uint32_t underscan_hborder; 461 uint32_t underscan_vborder; 462 struct drm_display_mode native_mode; 463 void *enc_priv; 464 int audio_polling_active; 465 bool is_ext_encoder; 466 u16 caps; 467 }; 468 469 struct amdgpu_connector_atom_dig { 470 /* displayport */ 471 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 472 u8 dp_sink_type; 473 int dp_clock; 474 int dp_lane_count; 475 bool edp_on; 476 }; 477 478 struct amdgpu_gpio_rec { 479 bool valid; 480 u8 id; 481 u32 reg; 482 u32 mask; 483 u32 shift; 484 }; 485 486 struct amdgpu_hpd { 487 enum amdgpu_hpd_id hpd; 488 u8 plugged_state; 489 struct amdgpu_gpio_rec gpio; 490 }; 491 492 struct amdgpu_router { 493 u32 router_id; 494 struct amdgpu_i2c_bus_rec i2c_info; 495 u8 i2c_addr; 496 /* i2c mux */ 497 bool ddc_valid; 498 u8 ddc_mux_type; 499 u8 ddc_mux_control_pin; 500 u8 ddc_mux_state; 501 /* clock/data mux */ 502 bool cd_valid; 503 u8 cd_mux_type; 504 u8 cd_mux_control_pin; 505 u8 cd_mux_state; 506 }; 507 508 enum amdgpu_connector_audio { 509 AMDGPU_AUDIO_DISABLE = 0, 510 AMDGPU_AUDIO_ENABLE = 1, 511 AMDGPU_AUDIO_AUTO = 2 512 }; 513 514 enum amdgpu_connector_dither { 515 AMDGPU_FMT_DITHER_DISABLE = 0, 516 AMDGPU_FMT_DITHER_ENABLE = 1, 517 }; 518 519 struct amdgpu_dm_dp_aux { 520 struct drm_dp_aux aux; 521 struct ddc_service *ddc_service; 522 }; 523 524 struct amdgpu_i2c_adapter { 525 struct i2c_adapter base; 526 527 struct ddc_service *ddc_service; 528 }; 529 530 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 531 532 struct amdgpu_connector { 533 struct drm_connector base; 534 uint32_t connector_id; 535 uint32_t devices; 536 struct amdgpu_i2c_chan *ddc_bus; 537 /* some systems have an hdmi and vga port with a shared ddc line */ 538 bool shared_ddc; 539 bool use_digital; 540 /* we need to mind the EDID between detect 541 and get modes due to analog/digital/tvencoder */ 542 struct edid *edid; 543 void *con_priv; 544 bool dac_load_detect; 545 bool detected_by_load; /* if the connection status was determined by load */ 546 uint16_t connector_object_id; 547 struct amdgpu_hpd hpd; 548 struct amdgpu_router router; 549 struct amdgpu_i2c_chan *router_bus; 550 enum amdgpu_connector_audio audio; 551 enum amdgpu_connector_dither dither; 552 unsigned pixelclock_for_modeset; 553 }; 554 555 /* TODO: start to use this struct and remove same field from base one */ 556 struct amdgpu_mst_connector { 557 struct amdgpu_connector base; 558 559 struct drm_dp_mst_topology_mgr mst_mgr; 560 struct amdgpu_dm_dp_aux dm_dp_aux; 561 struct drm_dp_mst_port *port; 562 struct amdgpu_connector *mst_port; 563 bool is_mst_connector; 564 struct amdgpu_encoder *mst_encoder; 565 }; 566 567 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 568 ((em) == ATOM_ENCODER_MODE_DP_MST)) 569 570 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 571 #define DRM_SCANOUTPOS_VALID (1 << 0) 572 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 573 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 574 #define USE_REAL_VBLANKSTART (1 << 30) 575 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 576 577 void amdgpu_link_encoder_connector(struct drm_device *dev); 578 579 struct drm_connector * 580 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 581 struct drm_connector * 582 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 583 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 584 u32 pixel_clock); 585 586 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 587 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 588 589 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 590 bool use_aux); 591 592 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 593 594 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 595 unsigned int pipe, unsigned int flags, int *vpos, 596 int *hpos, ktime_t *stime, ktime_t *etime, 597 const struct drm_display_mode *mode); 598 599 int amdgpu_display_framebuffer_init(struct drm_device *dev, 600 struct amdgpu_framebuffer *rfb, 601 const struct drm_mode_fb_cmd2 *mode_cmd, 602 struct drm_gem_object *obj); 603 604 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 605 606 void amdgpu_enc_destroy(struct drm_encoder *encoder); 607 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 608 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 609 const struct drm_display_mode *mode, 610 struct drm_display_mode *adjusted_mode); 611 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 612 struct drm_display_mode *adjusted_mode); 613 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 614 615 /* fbdev layer */ 616 int amdgpu_fbdev_init(struct amdgpu_device *adev); 617 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 618 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 619 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 620 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 621 622 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 623 624 /* amdgpu_display.c */ 625 void amdgpu_display_print_display_setup(struct drm_device *dev); 626 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 627 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 628 struct drm_modeset_acquire_ctx *ctx); 629 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 630 struct drm_framebuffer *fb, 631 struct drm_pending_vblank_event *event, 632 uint32_t page_flip_flags, uint32_t target, 633 struct drm_modeset_acquire_ctx *ctx); 634 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 635 636 #endif 637