1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_MMHUB_H__ 22 #define __AMDGPU_MMHUB_H__ 23 24 struct amdgpu_mmhub_ras { 25 struct amdgpu_ras_block_object ras_block; 26 }; 27 28 struct amdgpu_mmhub_funcs { 29 u64 (*get_fb_location)(struct amdgpu_device *adev); 30 u64 (*get_mc_fb_offset)(struct amdgpu_device *adev); 31 void (*init)(struct amdgpu_device *adev); 32 int (*gart_enable)(struct amdgpu_device *adev); 33 void (*set_fault_enable_default)(struct amdgpu_device *adev, 34 bool value); 35 void (*gart_disable)(struct amdgpu_device *adev); 36 int (*set_clockgating)(struct amdgpu_device *adev, 37 enum amd_clockgating_state state); 38 void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 39 void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 40 uint64_t page_table_base); 41 void (*update_power_gating)(struct amdgpu_device *adev, 42 bool enable); 43 int (*get_xgmi_info)(struct amdgpu_device *adev); 44 }; 45 46 struct amdgpu_mmhub_client_ids { 47 const char * const (*names)[2]; 48 unsigned int size; 49 }; 50 51 struct amdgpu_mmhub { 52 struct ras_common_if *ras_if; 53 const struct amdgpu_mmhub_funcs *funcs; 54 struct amdgpu_mmhub_ras *ras; 55 struct amdgpu_mmhub_client_ids client_ids; 56 }; 57 58 static inline void 59 amdgpu_mmhub_init_client_info(struct amdgpu_mmhub *mmhub, 60 const char * const (*names)[2], 61 unsigned int size) 62 { 63 mmhub->client_ids.names = names; 64 mmhub->client_ids.size = size; 65 } 66 67 static inline const char * 68 amdgpu_mmhub_client_name(struct amdgpu_mmhub *mmhub, 69 u32 cid, bool is_write) 70 { 71 if (cid < mmhub->client_ids.size) 72 return mmhub->client_ids.names[cid][is_write]; 73 74 return NULL; 75 } 76 77 int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); 78 79 #endif 80 81