1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_MMHUB_H__ 22 #define __AMDGPU_MMHUB_H__ 23 24 enum amdgpu_mmhub_ras_memory_id { 25 AMDGPU_MMHUB_WGMI_PAGEMEM = 0, 26 AMDGPU_MMHUB_RGMI_PAGEMEM = 1, 27 AMDGPU_MMHUB_WDRAM_PAGEMEM = 2, 28 AMDGPU_MMHUB_RDRAM_PAGEMEM = 3, 29 AMDGPU_MMHUB_WIO_CMDMEM = 4, 30 AMDGPU_MMHUB_RIO_CMDMEM = 5, 31 AMDGPU_MMHUB_WGMI_CMDMEM = 6, 32 AMDGPU_MMHUB_RGMI_CMDMEM = 7, 33 AMDGPU_MMHUB_WDRAM_CMDMEM = 8, 34 AMDGPU_MMHUB_RDRAM_CMDMEM = 9, 35 AMDGPU_MMHUB_MAM_DMEM0 = 10, 36 AMDGPU_MMHUB_MAM_DMEM1 = 11, 37 AMDGPU_MMHUB_MAM_DMEM2 = 12, 38 AMDGPU_MMHUB_MAM_DMEM3 = 13, 39 AMDGPU_MMHUB_WRET_TAGMEM = 19, 40 AMDGPU_MMHUB_RRET_TAGMEM = 20, 41 AMDGPU_MMHUB_WIO_DATAMEM = 21, 42 AMDGPU_MMHUB_WGMI_DATAMEM = 22, 43 AMDGPU_MMHUB_WDRAM_DATAMEM = 23, 44 AMDGPU_MMHUB_MEMORY_BLOCK_LAST, 45 }; 46 47 struct amdgpu_mmhub_ras { 48 struct amdgpu_ras_block_object ras_block; 49 }; 50 51 struct amdgpu_mmhub_funcs { 52 u64 (*get_fb_location)(struct amdgpu_device *adev); 53 u64 (*get_mc_fb_offset)(struct amdgpu_device *adev); 54 void (*init)(struct amdgpu_device *adev); 55 int (*gart_enable)(struct amdgpu_device *adev); 56 void (*set_fault_enable_default)(struct amdgpu_device *adev, 57 bool value); 58 void (*gart_disable)(struct amdgpu_device *adev); 59 int (*set_clockgating)(struct amdgpu_device *adev, 60 enum amd_clockgating_state state); 61 void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 62 void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 63 uint64_t page_table_base); 64 void (*update_power_gating)(struct amdgpu_device *adev, 65 bool enable); 66 }; 67 68 struct amdgpu_mmhub { 69 struct ras_common_if *ras_if; 70 const struct amdgpu_mmhub_funcs *funcs; 71 struct amdgpu_mmhub_ras *ras; 72 }; 73 74 int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); 75 76 #endif 77 78