1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include <linux/sched/mm.h> 31 32 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 33 #define AMDGPU_MES_MAX_GFX_PIPES 2 34 #define AMDGPU_MES_MAX_SDMA_PIPES 2 35 36 enum amdgpu_mes_priority_level { 37 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 38 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 39 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 40 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 41 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 42 AMDGPU_MES_PRIORITY_NUM_LEVELS 43 }; 44 45 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 46 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 47 48 struct amdgpu_mes_funcs; 49 50 enum admgpu_mes_pipe { 51 AMDGPU_MES_SCHED_PIPE = 0, 52 AMDGPU_MES_KIQ_PIPE, 53 AMDGPU_MAX_MES_PIPES = 2, 54 }; 55 56 struct amdgpu_mes { 57 struct amdgpu_device *adev; 58 59 struct mutex mutex_hidden; 60 61 struct idr pasid_idr; 62 struct idr gang_id_idr; 63 struct idr queue_id_idr; 64 struct ida doorbell_ida; 65 66 spinlock_t queue_id_lock; 67 68 uint32_t total_max_queue; 69 uint32_t doorbell_id_offset; 70 uint32_t max_doorbell_slices; 71 72 uint64_t default_process_quantum; 73 uint64_t default_gang_quantum; 74 75 struct amdgpu_ring ring; 76 77 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 78 79 /* mes ucode */ 80 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 81 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 82 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 83 uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES]; 84 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 85 86 /* mes ucode data */ 87 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 88 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 89 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 90 uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES]; 91 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 92 93 /* eop gpu obj */ 94 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 95 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 96 97 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 98 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 99 100 uint32_t vmid_mask_gfxhub; 101 uint32_t vmid_mask_mmhub; 102 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 103 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 104 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 105 uint32_t agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 106 uint32_t sch_ctx_offs; 107 uint64_t sch_ctx_gpu_addr; 108 uint64_t *sch_ctx_ptr; 109 uint32_t query_status_fence_offs; 110 uint64_t query_status_fence_gpu_addr; 111 uint64_t *query_status_fence_ptr; 112 uint32_t saved_flags; 113 114 /* initialize kiq pipe */ 115 int (*kiq_hw_init)(struct amdgpu_device *adev); 116 int (*kiq_hw_fini)(struct amdgpu_device *adev); 117 118 /* ip specific functions */ 119 const struct amdgpu_mes_funcs *funcs; 120 }; 121 122 struct amdgpu_mes_process { 123 int pasid; 124 struct amdgpu_vm *vm; 125 uint64_t pd_gpu_addr; 126 struct amdgpu_bo *proc_ctx_bo; 127 uint64_t proc_ctx_gpu_addr; 128 void *proc_ctx_cpu_ptr; 129 uint64_t process_quantum; 130 struct list_head gang_list; 131 uint32_t doorbell_index; 132 unsigned long *doorbell_bitmap; 133 struct mutex doorbell_lock; 134 }; 135 136 struct amdgpu_mes_gang { 137 int gang_id; 138 int priority; 139 int inprocess_gang_priority; 140 int global_priority_level; 141 struct list_head list; 142 struct amdgpu_mes_process *process; 143 struct amdgpu_bo *gang_ctx_bo; 144 uint64_t gang_ctx_gpu_addr; 145 void *gang_ctx_cpu_ptr; 146 uint64_t gang_quantum; 147 struct list_head queue_list; 148 }; 149 150 struct amdgpu_mes_queue { 151 struct list_head list; 152 struct amdgpu_mes_gang *gang; 153 int queue_id; 154 uint64_t doorbell_off; 155 struct amdgpu_bo *mqd_obj; 156 void *mqd_cpu_ptr; 157 uint64_t mqd_gpu_addr; 158 uint64_t wptr_gpu_addr; 159 int queue_type; 160 int paging; 161 struct amdgpu_ring *ring; 162 }; 163 164 struct amdgpu_mes_queue_properties { 165 int queue_type; 166 uint64_t hqd_base_gpu_addr; 167 uint64_t rptr_gpu_addr; 168 uint64_t wptr_gpu_addr; 169 uint32_t queue_size; 170 uint64_t eop_gpu_addr; 171 uint32_t hqd_pipe_priority; 172 uint32_t hqd_queue_priority; 173 bool paging; 174 struct amdgpu_ring *ring; 175 /* out */ 176 uint64_t doorbell_off; 177 }; 178 179 struct amdgpu_mes_gang_properties { 180 uint32_t priority; 181 uint32_t gang_quantum; 182 uint32_t inprocess_gang_priority; 183 uint32_t priority_level; 184 int global_priority_level; 185 }; 186 187 struct mes_add_queue_input { 188 uint32_t process_id; 189 uint64_t page_table_base_addr; 190 uint64_t process_va_start; 191 uint64_t process_va_end; 192 uint64_t process_quantum; 193 uint64_t process_context_addr; 194 uint64_t gang_quantum; 195 uint64_t gang_context_addr; 196 uint32_t inprocess_gang_priority; 197 uint32_t gang_global_priority_level; 198 uint32_t doorbell_offset; 199 uint64_t mqd_addr; 200 uint64_t wptr_addr; 201 uint32_t queue_type; 202 uint32_t paging; 203 uint32_t gws_base; 204 uint32_t gws_size; 205 uint64_t tba_addr; 206 uint64_t tma_addr; 207 }; 208 209 struct mes_remove_queue_input { 210 uint32_t doorbell_offset; 211 uint64_t gang_context_addr; 212 }; 213 214 struct mes_unmap_legacy_queue_input { 215 enum amdgpu_unmap_queues_action action; 216 uint32_t queue_type; 217 uint32_t doorbell_offset; 218 uint32_t pipe_id; 219 uint32_t queue_id; 220 uint64_t trail_fence_addr; 221 uint64_t trail_fence_data; 222 }; 223 224 struct mes_suspend_gang_input { 225 bool suspend_all_gangs; 226 uint64_t gang_context_addr; 227 uint64_t suspend_fence_addr; 228 uint32_t suspend_fence_value; 229 }; 230 231 struct mes_resume_gang_input { 232 bool resume_all_gangs; 233 uint64_t gang_context_addr; 234 }; 235 236 struct amdgpu_mes_funcs { 237 int (*add_hw_queue)(struct amdgpu_mes *mes, 238 struct mes_add_queue_input *input); 239 240 int (*remove_hw_queue)(struct amdgpu_mes *mes, 241 struct mes_remove_queue_input *input); 242 243 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 244 struct mes_unmap_legacy_queue_input *input); 245 246 int (*suspend_gang)(struct amdgpu_mes *mes, 247 struct mes_suspend_gang_input *input); 248 249 int (*resume_gang)(struct amdgpu_mes *mes, 250 struct mes_resume_gang_input *input); 251 }; 252 253 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 254 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 255 256 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 257 258 int amdgpu_mes_init(struct amdgpu_device *adev); 259 void amdgpu_mes_fini(struct amdgpu_device *adev); 260 261 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 262 struct amdgpu_vm *vm); 263 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 264 265 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 266 struct amdgpu_mes_gang_properties *gprops, 267 int *gang_id); 268 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 269 270 int amdgpu_mes_suspend(struct amdgpu_device *adev); 271 int amdgpu_mes_resume(struct amdgpu_device *adev); 272 273 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 274 struct amdgpu_mes_queue_properties *qprops, 275 int *queue_id); 276 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 277 278 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 279 struct amdgpu_ring *ring, 280 enum amdgpu_unmap_queues_action action, 281 u64 gpu_addr, u64 seq); 282 283 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 284 int queue_type, int idx, 285 struct amdgpu_mes_ctx_data *ctx_data, 286 struct amdgpu_ring **out); 287 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 288 struct amdgpu_ring *ring); 289 290 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 291 struct amdgpu_mes_ctx_data *ctx_data); 292 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 293 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 294 struct amdgpu_vm *vm, 295 struct amdgpu_mes_ctx_data *ctx_data); 296 297 int amdgpu_mes_self_test(struct amdgpu_device *adev); 298 299 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev, 300 unsigned int *doorbell_index); 301 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev, 302 unsigned int doorbell_index); 303 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar( 304 struct amdgpu_device *adev, 305 uint32_t doorbell_index, 306 unsigned int doorbell_id); 307 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 308 309 /* 310 * MES lock can be taken in MMU notifiers. 311 * 312 * A bit more detail about why to set no-FS reclaim with MES lock: 313 * 314 * The purpose of the MMU notifier is to stop GPU access to memory so 315 * that the Linux VM subsystem can move pages around safely. This is 316 * done by preempting user mode queues for the affected process. When 317 * MES is used, MES lock needs to be taken to preempt the queues. 318 * 319 * The MMU notifier callback entry point in the driver is 320 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 321 * there is: 322 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 323 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 324 * 325 * The last part of the chain is a function pointer where we take the 326 * MES lock. 327 * 328 * The problem with taking locks in the MMU notifier is, that MMU 329 * notifiers can be called in reclaim-FS context. That's where the 330 * kernel frees up pages to make room for new page allocations under 331 * memory pressure. While we are running in reclaim-FS context, we must 332 * not trigger another memory reclaim operation because that would 333 * recursively reenter the reclaim code and cause a deadlock. The 334 * memalloc_nofs_save/restore calls guarantee that. 335 * 336 * In addition we also need to avoid lock dependencies on other locks taken 337 * under the MES lock, for example reservation locks. Here is a possible 338 * scenario of a deadlock: 339 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 340 * MMU notifier | blocks trying to take MES lock 341 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 342 * 343 * In this scenario Thread B gets involved in a deadlock even without 344 * triggering a reclaim-FS operation itself. 345 * To fix this and break the lock dependency chain you'd need to either: 346 * 1. protect reservation locks with memalloc_nofs_save/restore, or 347 * 2. avoid taking reservation locks under the MES lock. 348 * 349 * Reservation locks are taken all over the kernel in different subsystems, we 350 * have no control over them and their lock dependencies.So the only workable 351 * solution is to avoid taking other locks under the MES lock. 352 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 353 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 354 */ 355 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 356 { 357 mutex_lock(&mes->mutex_hidden); 358 mes->saved_flags = memalloc_noreclaim_save(); 359 } 360 361 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 362 { 363 memalloc_noreclaim_restore(mes->saved_flags); 364 mutex_unlock(&mes->mutex_hidden); 365 } 366 #endif /* __AMDGPU_MES_H__ */ 367