1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44 enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51 }; 52 53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 #define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */ 56 57 struct amdgpu_mes_funcs; 58 59 enum admgpu_mes_pipe { 60 AMDGPU_MES_SCHED_PIPE = 0, 61 AMDGPU_MES_KIQ_PIPE, 62 AMDGPU_MAX_MES_PIPES = 2, 63 }; 64 65 struct amdgpu_mes { 66 struct amdgpu_device *adev; 67 68 struct mutex mutex_hidden; 69 70 struct idr pasid_idr; 71 struct idr gang_id_idr; 72 struct idr queue_id_idr; 73 struct ida doorbell_ida; 74 75 spinlock_t queue_id_lock; 76 77 uint32_t sched_version; 78 uint32_t kiq_version; 79 80 uint32_t total_max_queue; 81 uint32_t max_doorbell_slices; 82 83 uint64_t default_process_quantum; 84 uint64_t default_gang_quantum; 85 86 struct amdgpu_ring ring; 87 spinlock_t ring_lock; 88 89 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 90 91 /* mes ucode */ 92 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 93 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 94 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 96 97 /* mes ucode data */ 98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 102 103 /* eop gpu obj */ 104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 106 107 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 109 110 uint32_t vmid_mask_gfxhub; 111 uint32_t vmid_mask_mmhub; 112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 115 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 116 uint32_t sch_ctx_offs; 117 uint64_t sch_ctx_gpu_addr; 118 uint64_t *sch_ctx_ptr; 119 uint32_t query_status_fence_offs; 120 uint64_t query_status_fence_gpu_addr; 121 uint64_t *query_status_fence_ptr; 122 uint32_t read_val_offs; 123 uint64_t read_val_gpu_addr; 124 uint32_t *read_val_ptr; 125 126 uint32_t saved_flags; 127 128 /* initialize kiq pipe */ 129 int (*kiq_hw_init)(struct amdgpu_device *adev); 130 int (*kiq_hw_fini)(struct amdgpu_device *adev); 131 132 /* MES doorbells */ 133 uint32_t db_start_dw_offset; 134 uint32_t num_mes_dbs; 135 unsigned long *doorbell_bitmap; 136 137 /* MES event log buffer */ 138 struct amdgpu_bo *event_log_gpu_obj; 139 uint64_t event_log_gpu_addr; 140 void *event_log_cpu_addr; 141 142 /* ip specific functions */ 143 const struct amdgpu_mes_funcs *funcs; 144 }; 145 146 struct amdgpu_mes_process { 147 int pasid; 148 struct amdgpu_vm *vm; 149 uint64_t pd_gpu_addr; 150 struct amdgpu_bo *proc_ctx_bo; 151 uint64_t proc_ctx_gpu_addr; 152 void *proc_ctx_cpu_ptr; 153 uint64_t process_quantum; 154 struct list_head gang_list; 155 uint32_t doorbell_index; 156 struct mutex doorbell_lock; 157 }; 158 159 struct amdgpu_mes_gang { 160 int gang_id; 161 int priority; 162 int inprocess_gang_priority; 163 int global_priority_level; 164 struct list_head list; 165 struct amdgpu_mes_process *process; 166 struct amdgpu_bo *gang_ctx_bo; 167 uint64_t gang_ctx_gpu_addr; 168 void *gang_ctx_cpu_ptr; 169 uint64_t gang_quantum; 170 struct list_head queue_list; 171 }; 172 173 struct amdgpu_mes_queue { 174 struct list_head list; 175 struct amdgpu_mes_gang *gang; 176 int queue_id; 177 uint64_t doorbell_off; 178 struct amdgpu_bo *mqd_obj; 179 void *mqd_cpu_ptr; 180 uint64_t mqd_gpu_addr; 181 uint64_t wptr_gpu_addr; 182 int queue_type; 183 int paging; 184 struct amdgpu_ring *ring; 185 }; 186 187 struct amdgpu_mes_queue_properties { 188 int queue_type; 189 uint64_t hqd_base_gpu_addr; 190 uint64_t rptr_gpu_addr; 191 uint64_t wptr_gpu_addr; 192 uint64_t wptr_mc_addr; 193 uint32_t queue_size; 194 uint64_t eop_gpu_addr; 195 uint32_t hqd_pipe_priority; 196 uint32_t hqd_queue_priority; 197 bool paging; 198 struct amdgpu_ring *ring; 199 /* out */ 200 uint64_t doorbell_off; 201 }; 202 203 struct amdgpu_mes_gang_properties { 204 uint32_t priority; 205 uint32_t gang_quantum; 206 uint32_t inprocess_gang_priority; 207 uint32_t priority_level; 208 int global_priority_level; 209 }; 210 211 struct mes_add_queue_input { 212 uint32_t process_id; 213 uint64_t page_table_base_addr; 214 uint64_t process_va_start; 215 uint64_t process_va_end; 216 uint64_t process_quantum; 217 uint64_t process_context_addr; 218 uint64_t gang_quantum; 219 uint64_t gang_context_addr; 220 uint32_t inprocess_gang_priority; 221 uint32_t gang_global_priority_level; 222 uint32_t doorbell_offset; 223 uint64_t mqd_addr; 224 uint64_t wptr_addr; 225 uint64_t wptr_mc_addr; 226 uint32_t queue_type; 227 uint32_t paging; 228 uint32_t gws_base; 229 uint32_t gws_size; 230 uint64_t tba_addr; 231 uint64_t tma_addr; 232 uint32_t trap_en; 233 uint32_t skip_process_ctx_clear; 234 uint32_t is_kfd_process; 235 uint32_t is_aql_queue; 236 uint32_t queue_size; 237 uint32_t exclusively_scheduled; 238 }; 239 240 struct mes_remove_queue_input { 241 uint32_t doorbell_offset; 242 uint64_t gang_context_addr; 243 }; 244 245 struct mes_unmap_legacy_queue_input { 246 enum amdgpu_unmap_queues_action action; 247 uint32_t queue_type; 248 uint32_t doorbell_offset; 249 uint32_t pipe_id; 250 uint32_t queue_id; 251 uint64_t trail_fence_addr; 252 uint64_t trail_fence_data; 253 }; 254 255 struct mes_suspend_gang_input { 256 bool suspend_all_gangs; 257 uint64_t gang_context_addr; 258 uint64_t suspend_fence_addr; 259 uint32_t suspend_fence_value; 260 }; 261 262 struct mes_resume_gang_input { 263 bool resume_all_gangs; 264 uint64_t gang_context_addr; 265 }; 266 267 enum mes_misc_opcode { 268 MES_MISC_OP_WRITE_REG, 269 MES_MISC_OP_READ_REG, 270 MES_MISC_OP_WRM_REG_WAIT, 271 MES_MISC_OP_WRM_REG_WR_WAIT, 272 MES_MISC_OP_SET_SHADER_DEBUGGER, 273 }; 274 275 struct mes_misc_op_input { 276 enum mes_misc_opcode op; 277 278 union { 279 struct { 280 uint32_t reg_offset; 281 uint64_t buffer_addr; 282 } read_reg; 283 284 struct { 285 uint32_t reg_offset; 286 uint32_t reg_value; 287 } write_reg; 288 289 struct { 290 uint32_t ref; 291 uint32_t mask; 292 uint32_t reg0; 293 uint32_t reg1; 294 } wrm_reg; 295 296 struct { 297 uint64_t process_context_addr; 298 union { 299 struct { 300 uint32_t single_memop : 1; 301 uint32_t single_alu_op : 1; 302 uint32_t reserved: 29; 303 uint32_t process_ctx_flush: 1; 304 }; 305 uint32_t u32all; 306 } flags; 307 uint32_t spi_gdbg_per_vmid_cntl; 308 uint32_t tcp_watch_cntl[4]; 309 uint32_t trap_en; 310 } set_shader_debugger; 311 }; 312 }; 313 314 struct amdgpu_mes_funcs { 315 int (*add_hw_queue)(struct amdgpu_mes *mes, 316 struct mes_add_queue_input *input); 317 318 int (*remove_hw_queue)(struct amdgpu_mes *mes, 319 struct mes_remove_queue_input *input); 320 321 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 322 struct mes_unmap_legacy_queue_input *input); 323 324 int (*suspend_gang)(struct amdgpu_mes *mes, 325 struct mes_suspend_gang_input *input); 326 327 int (*resume_gang)(struct amdgpu_mes *mes, 328 struct mes_resume_gang_input *input); 329 330 int (*misc_op)(struct amdgpu_mes *mes, 331 struct mes_misc_op_input *input); 332 }; 333 334 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 335 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 336 337 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 338 339 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 340 int amdgpu_mes_init(struct amdgpu_device *adev); 341 void amdgpu_mes_fini(struct amdgpu_device *adev); 342 343 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 344 struct amdgpu_vm *vm); 345 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 346 347 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 348 struct amdgpu_mes_gang_properties *gprops, 349 int *gang_id); 350 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 351 352 int amdgpu_mes_suspend(struct amdgpu_device *adev); 353 int amdgpu_mes_resume(struct amdgpu_device *adev); 354 355 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 356 struct amdgpu_mes_queue_properties *qprops, 357 int *queue_id); 358 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 359 360 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 361 struct amdgpu_ring *ring, 362 enum amdgpu_unmap_queues_action action, 363 u64 gpu_addr, u64 seq); 364 365 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 366 int amdgpu_mes_wreg(struct amdgpu_device *adev, 367 uint32_t reg, uint32_t val); 368 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 369 uint32_t val, uint32_t mask); 370 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 371 uint32_t reg0, uint32_t reg1, 372 uint32_t ref, uint32_t mask); 373 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 374 uint64_t process_context_addr, 375 uint32_t spi_gdbg_per_vmid_cntl, 376 const uint32_t *tcp_watch_cntl, 377 uint32_t flags, 378 bool trap_en); 379 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 380 uint64_t process_context_addr); 381 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 382 int queue_type, int idx, 383 struct amdgpu_mes_ctx_data *ctx_data, 384 struct amdgpu_ring **out); 385 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 386 struct amdgpu_ring *ring); 387 388 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 389 enum amdgpu_mes_priority_level prio); 390 391 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 392 struct amdgpu_mes_ctx_data *ctx_data); 393 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 394 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 395 struct amdgpu_vm *vm, 396 struct amdgpu_mes_ctx_data *ctx_data); 397 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 398 struct amdgpu_mes_ctx_data *ctx_data); 399 400 int amdgpu_mes_self_test(struct amdgpu_device *adev); 401 402 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 403 404 /* 405 * MES lock can be taken in MMU notifiers. 406 * 407 * A bit more detail about why to set no-FS reclaim with MES lock: 408 * 409 * The purpose of the MMU notifier is to stop GPU access to memory so 410 * that the Linux VM subsystem can move pages around safely. This is 411 * done by preempting user mode queues for the affected process. When 412 * MES is used, MES lock needs to be taken to preempt the queues. 413 * 414 * The MMU notifier callback entry point in the driver is 415 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 416 * there is: 417 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 418 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 419 * 420 * The last part of the chain is a function pointer where we take the 421 * MES lock. 422 * 423 * The problem with taking locks in the MMU notifier is, that MMU 424 * notifiers can be called in reclaim-FS context. That's where the 425 * kernel frees up pages to make room for new page allocations under 426 * memory pressure. While we are running in reclaim-FS context, we must 427 * not trigger another memory reclaim operation because that would 428 * recursively reenter the reclaim code and cause a deadlock. The 429 * memalloc_nofs_save/restore calls guarantee that. 430 * 431 * In addition we also need to avoid lock dependencies on other locks taken 432 * under the MES lock, for example reservation locks. Here is a possible 433 * scenario of a deadlock: 434 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 435 * MMU notifier | blocks trying to take MES lock 436 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 437 * 438 * In this scenario Thread B gets involved in a deadlock even without 439 * triggering a reclaim-FS operation itself. 440 * To fix this and break the lock dependency chain you'd need to either: 441 * 1. protect reservation locks with memalloc_nofs_save/restore, or 442 * 2. avoid taking reservation locks under the MES lock. 443 * 444 * Reservation locks are taken all over the kernel in different subsystems, we 445 * have no control over them and their lock dependencies.So the only workable 446 * solution is to avoid taking other locks under the MES lock. 447 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 448 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 449 */ 450 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 451 { 452 mutex_lock(&mes->mutex_hidden); 453 mes->saved_flags = memalloc_noreclaim_save(); 454 } 455 456 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 457 { 458 memalloc_noreclaim_restore(mes->saved_flags); 459 mutex_unlock(&mes->mutex_hidden); 460 } 461 #endif /* __AMDGPU_MES_H__ */ 462