1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44 enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51 }; 52 53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 56 struct amdgpu_mes_funcs; 57 58 enum admgpu_mes_pipe { 59 AMDGPU_MES_SCHED_PIPE = 0, 60 AMDGPU_MES_KIQ_PIPE, 61 AMDGPU_MAX_MES_PIPES = 2, 62 }; 63 64 struct amdgpu_mes { 65 struct amdgpu_device *adev; 66 67 struct mutex mutex_hidden; 68 69 struct idr pasid_idr; 70 struct idr gang_id_idr; 71 struct idr queue_id_idr; 72 struct ida doorbell_ida; 73 74 spinlock_t queue_id_lock; 75 76 uint32_t sched_version; 77 uint32_t kiq_version; 78 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 79 bool enable_legacy_queue_map; 80 81 uint32_t total_max_queue; 82 uint32_t max_doorbell_slices; 83 84 uint64_t default_process_quantum; 85 uint64_t default_gang_quantum; 86 87 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 88 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 89 90 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 91 92 /* mes ucode */ 93 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 94 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 95 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 96 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 97 98 /* mes ucode data */ 99 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 100 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 101 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 102 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 103 104 /* eop gpu obj */ 105 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 106 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 107 108 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 109 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 110 111 uint32_t vmid_mask_gfxhub; 112 uint32_t vmid_mask_mmhub; 113 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 114 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 115 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 116 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 117 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 118 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 119 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 120 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 121 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 122 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 123 124 uint32_t saved_flags; 125 126 /* initialize kiq pipe */ 127 int (*kiq_hw_init)(struct amdgpu_device *adev); 128 int (*kiq_hw_fini)(struct amdgpu_device *adev); 129 130 /* MES doorbells */ 131 uint32_t db_start_dw_offset; 132 uint32_t num_mes_dbs; 133 unsigned long *doorbell_bitmap; 134 135 /* MES event log buffer */ 136 uint32_t event_log_size; 137 struct amdgpu_bo *event_log_gpu_obj; 138 uint64_t event_log_gpu_addr; 139 void *event_log_cpu_addr; 140 141 /* ip specific functions */ 142 const struct amdgpu_mes_funcs *funcs; 143 144 /* mes resource_1 bo*/ 145 struct amdgpu_bo *resource_1; 146 uint64_t resource_1_gpu_addr; 147 void *resource_1_addr; 148 149 }; 150 151 struct amdgpu_mes_process { 152 int pasid; 153 struct amdgpu_vm *vm; 154 uint64_t pd_gpu_addr; 155 struct amdgpu_bo *proc_ctx_bo; 156 uint64_t proc_ctx_gpu_addr; 157 void *proc_ctx_cpu_ptr; 158 uint64_t process_quantum; 159 struct list_head gang_list; 160 uint32_t doorbell_index; 161 struct mutex doorbell_lock; 162 }; 163 164 struct amdgpu_mes_gang { 165 int gang_id; 166 int priority; 167 int inprocess_gang_priority; 168 int global_priority_level; 169 struct list_head list; 170 struct amdgpu_mes_process *process; 171 struct amdgpu_bo *gang_ctx_bo; 172 uint64_t gang_ctx_gpu_addr; 173 void *gang_ctx_cpu_ptr; 174 uint64_t gang_quantum; 175 struct list_head queue_list; 176 }; 177 178 struct amdgpu_mes_queue { 179 struct list_head list; 180 struct amdgpu_mes_gang *gang; 181 int queue_id; 182 uint64_t doorbell_off; 183 struct amdgpu_bo *mqd_obj; 184 void *mqd_cpu_ptr; 185 uint64_t mqd_gpu_addr; 186 uint64_t wptr_gpu_addr; 187 int queue_type; 188 int paging; 189 struct amdgpu_ring *ring; 190 }; 191 192 struct amdgpu_mes_queue_properties { 193 int queue_type; 194 uint64_t hqd_base_gpu_addr; 195 uint64_t rptr_gpu_addr; 196 uint64_t wptr_gpu_addr; 197 uint64_t wptr_mc_addr; 198 uint32_t queue_size; 199 uint64_t eop_gpu_addr; 200 uint32_t hqd_pipe_priority; 201 uint32_t hqd_queue_priority; 202 bool paging; 203 struct amdgpu_ring *ring; 204 /* out */ 205 uint64_t doorbell_off; 206 }; 207 208 struct amdgpu_mes_gang_properties { 209 uint32_t priority; 210 uint32_t gang_quantum; 211 uint32_t inprocess_gang_priority; 212 uint32_t priority_level; 213 int global_priority_level; 214 }; 215 216 struct mes_add_queue_input { 217 uint32_t process_id; 218 uint64_t page_table_base_addr; 219 uint64_t process_va_start; 220 uint64_t process_va_end; 221 uint64_t process_quantum; 222 uint64_t process_context_addr; 223 uint64_t gang_quantum; 224 uint64_t gang_context_addr; 225 uint32_t inprocess_gang_priority; 226 uint32_t gang_global_priority_level; 227 uint32_t doorbell_offset; 228 uint64_t mqd_addr; 229 uint64_t wptr_addr; 230 uint64_t wptr_mc_addr; 231 uint32_t queue_type; 232 uint32_t paging; 233 uint32_t gws_base; 234 uint32_t gws_size; 235 uint64_t tba_addr; 236 uint64_t tma_addr; 237 uint32_t trap_en; 238 uint32_t skip_process_ctx_clear; 239 uint32_t is_kfd_process; 240 uint32_t is_aql_queue; 241 uint32_t queue_size; 242 uint32_t exclusively_scheduled; 243 }; 244 245 struct mes_remove_queue_input { 246 uint32_t doorbell_offset; 247 uint64_t gang_context_addr; 248 }; 249 250 struct mes_reset_queue_input { 251 uint32_t doorbell_offset; 252 uint64_t gang_context_addr; 253 bool use_mmio; 254 uint32_t queue_type; 255 uint32_t me_id; 256 uint32_t pipe_id; 257 uint32_t queue_id; 258 uint32_t xcc_id; 259 uint32_t vmid; 260 }; 261 262 struct mes_map_legacy_queue_input { 263 uint32_t queue_type; 264 uint32_t doorbell_offset; 265 uint32_t pipe_id; 266 uint32_t queue_id; 267 uint64_t mqd_addr; 268 uint64_t wptr_addr; 269 }; 270 271 struct mes_unmap_legacy_queue_input { 272 enum amdgpu_unmap_queues_action action; 273 uint32_t queue_type; 274 uint32_t doorbell_offset; 275 uint32_t pipe_id; 276 uint32_t queue_id; 277 uint64_t trail_fence_addr; 278 uint64_t trail_fence_data; 279 }; 280 281 struct mes_suspend_gang_input { 282 bool suspend_all_gangs; 283 uint64_t gang_context_addr; 284 uint64_t suspend_fence_addr; 285 uint32_t suspend_fence_value; 286 }; 287 288 struct mes_resume_gang_input { 289 bool resume_all_gangs; 290 uint64_t gang_context_addr; 291 }; 292 293 struct mes_reset_legacy_queue_input { 294 uint32_t queue_type; 295 uint32_t doorbell_offset; 296 bool use_mmio; 297 uint32_t me_id; 298 uint32_t pipe_id; 299 uint32_t queue_id; 300 uint64_t mqd_addr; 301 uint64_t wptr_addr; 302 uint32_t vmid; 303 }; 304 305 enum mes_misc_opcode { 306 MES_MISC_OP_WRITE_REG, 307 MES_MISC_OP_READ_REG, 308 MES_MISC_OP_WRM_REG_WAIT, 309 MES_MISC_OP_WRM_REG_WR_WAIT, 310 MES_MISC_OP_SET_SHADER_DEBUGGER, 311 }; 312 313 struct mes_misc_op_input { 314 enum mes_misc_opcode op; 315 316 union { 317 struct { 318 uint32_t reg_offset; 319 uint64_t buffer_addr; 320 } read_reg; 321 322 struct { 323 uint32_t reg_offset; 324 uint32_t reg_value; 325 } write_reg; 326 327 struct { 328 uint32_t ref; 329 uint32_t mask; 330 uint32_t reg0; 331 uint32_t reg1; 332 } wrm_reg; 333 334 struct { 335 uint64_t process_context_addr; 336 union { 337 struct { 338 uint32_t single_memop : 1; 339 uint32_t single_alu_op : 1; 340 uint32_t reserved: 29; 341 uint32_t process_ctx_flush: 1; 342 }; 343 uint32_t u32all; 344 } flags; 345 uint32_t spi_gdbg_per_vmid_cntl; 346 uint32_t tcp_watch_cntl[4]; 347 uint32_t trap_en; 348 } set_shader_debugger; 349 }; 350 }; 351 352 struct amdgpu_mes_funcs { 353 int (*add_hw_queue)(struct amdgpu_mes *mes, 354 struct mes_add_queue_input *input); 355 356 int (*remove_hw_queue)(struct amdgpu_mes *mes, 357 struct mes_remove_queue_input *input); 358 359 int (*map_legacy_queue)(struct amdgpu_mes *mes, 360 struct mes_map_legacy_queue_input *input); 361 362 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 363 struct mes_unmap_legacy_queue_input *input); 364 365 int (*suspend_gang)(struct amdgpu_mes *mes, 366 struct mes_suspend_gang_input *input); 367 368 int (*resume_gang)(struct amdgpu_mes *mes, 369 struct mes_resume_gang_input *input); 370 371 int (*misc_op)(struct amdgpu_mes *mes, 372 struct mes_misc_op_input *input); 373 374 int (*reset_legacy_queue)(struct amdgpu_mes *mes, 375 struct mes_reset_legacy_queue_input *input); 376 377 int (*reset_hw_queue)(struct amdgpu_mes *mes, 378 struct mes_reset_queue_input *input); 379 }; 380 381 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 382 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 383 384 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 385 386 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 387 int amdgpu_mes_init(struct amdgpu_device *adev); 388 void amdgpu_mes_fini(struct amdgpu_device *adev); 389 390 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 391 struct amdgpu_vm *vm); 392 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 393 394 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 395 struct amdgpu_mes_gang_properties *gprops, 396 int *gang_id); 397 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 398 399 int amdgpu_mes_suspend(struct amdgpu_device *adev); 400 int amdgpu_mes_resume(struct amdgpu_device *adev); 401 402 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 403 struct amdgpu_mes_queue_properties *qprops, 404 int *queue_id); 405 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 406 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); 407 int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, 408 int me_id, int pipe_id, int queue_id, int vmid); 409 410 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 411 struct amdgpu_ring *ring); 412 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 413 struct amdgpu_ring *ring, 414 enum amdgpu_unmap_queues_action action, 415 u64 gpu_addr, u64 seq); 416 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 417 struct amdgpu_ring *ring, 418 unsigned int vmid, 419 bool use_mmio); 420 421 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 422 int amdgpu_mes_wreg(struct amdgpu_device *adev, 423 uint32_t reg, uint32_t val); 424 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 425 uint32_t val, uint32_t mask); 426 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 427 uint32_t reg0, uint32_t reg1, 428 uint32_t ref, uint32_t mask); 429 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 430 uint64_t process_context_addr, 431 uint32_t spi_gdbg_per_vmid_cntl, 432 const uint32_t *tcp_watch_cntl, 433 uint32_t flags, 434 bool trap_en); 435 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 436 uint64_t process_context_addr); 437 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 438 int queue_type, int idx, 439 struct amdgpu_mes_ctx_data *ctx_data, 440 struct amdgpu_ring **out); 441 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 442 struct amdgpu_ring *ring); 443 444 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 445 enum amdgpu_mes_priority_level prio); 446 447 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 448 struct amdgpu_mes_ctx_data *ctx_data); 449 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 450 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 451 struct amdgpu_vm *vm, 452 struct amdgpu_mes_ctx_data *ctx_data); 453 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 454 struct amdgpu_mes_ctx_data *ctx_data); 455 456 int amdgpu_mes_self_test(struct amdgpu_device *adev); 457 458 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 459 460 /* 461 * MES lock can be taken in MMU notifiers. 462 * 463 * A bit more detail about why to set no-FS reclaim with MES lock: 464 * 465 * The purpose of the MMU notifier is to stop GPU access to memory so 466 * that the Linux VM subsystem can move pages around safely. This is 467 * done by preempting user mode queues for the affected process. When 468 * MES is used, MES lock needs to be taken to preempt the queues. 469 * 470 * The MMU notifier callback entry point in the driver is 471 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 472 * there is: 473 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 474 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 475 * 476 * The last part of the chain is a function pointer where we take the 477 * MES lock. 478 * 479 * The problem with taking locks in the MMU notifier is, that MMU 480 * notifiers can be called in reclaim-FS context. That's where the 481 * kernel frees up pages to make room for new page allocations under 482 * memory pressure. While we are running in reclaim-FS context, we must 483 * not trigger another memory reclaim operation because that would 484 * recursively reenter the reclaim code and cause a deadlock. The 485 * memalloc_nofs_save/restore calls guarantee that. 486 * 487 * In addition we also need to avoid lock dependencies on other locks taken 488 * under the MES lock, for example reservation locks. Here is a possible 489 * scenario of a deadlock: 490 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 491 * MMU notifier | blocks trying to take MES lock 492 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 493 * 494 * In this scenario Thread B gets involved in a deadlock even without 495 * triggering a reclaim-FS operation itself. 496 * To fix this and break the lock dependency chain you'd need to either: 497 * 1. protect reservation locks with memalloc_nofs_save/restore, or 498 * 2. avoid taking reservation locks under the MES lock. 499 * 500 * Reservation locks are taken all over the kernel in different subsystems, we 501 * have no control over them and their lock dependencies.So the only workable 502 * solution is to avoid taking other locks under the MES lock. 503 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 504 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 505 */ 506 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 507 { 508 mutex_lock(&mes->mutex_hidden); 509 mes->saved_flags = memalloc_noreclaim_save(); 510 } 511 512 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 513 { 514 memalloc_noreclaim_restore(mes->saved_flags); 515 mutex_unlock(&mes->mutex_hidden); 516 } 517 518 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 519 #endif /* __AMDGPU_MES_H__ */ 520