1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_PIPE_0 = 0, 62 AMDGPU_MES_PIPE_1, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 69 #define AMDGPU_MAX_MES_INST_PIPES \ 70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 72 #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 74 75 struct amdgpu_mes { 76 struct amdgpu_device *adev; 77 78 struct mutex mutex_hidden; 79 80 struct ida doorbell_ida; 81 82 spinlock_t queue_id_lock; 83 84 uint32_t sched_version; 85 uint32_t kiq_version; 86 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 87 bool enable_legacy_queue_map; 88 89 uint32_t total_max_queue; 90 uint32_t max_doorbell_slices; 91 92 uint64_t default_process_quantum; 93 uint64_t default_gang_quantum; 94 95 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 96 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 97 98 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 99 100 /* mes ucode */ 101 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 102 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 103 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 104 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 105 106 /* mes ucode data */ 107 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 108 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 109 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 110 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 111 112 /* eop gpu obj */ 113 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 114 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 115 116 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 117 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 118 119 uint32_t vmid_mask_gfxhub; 120 uint32_t vmid_mask_mmhub; 121 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 122 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 123 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 124 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 125 126 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 127 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 128 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 129 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 130 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 132 133 uint32_t saved_flags; 134 135 /* initialize kiq pipe */ 136 int (*kiq_hw_init)(struct amdgpu_device *adev, 137 uint32_t xcc_id); 138 int (*kiq_hw_fini)(struct amdgpu_device *adev, 139 uint32_t xcc_id); 140 141 /* MES doorbells */ 142 uint32_t db_start_dw_offset; 143 uint32_t num_mes_dbs; 144 unsigned long *doorbell_bitmap; 145 146 /* MES event log buffer */ 147 uint32_t event_log_size; 148 struct amdgpu_bo *event_log_gpu_obj; 149 uint64_t event_log_gpu_addr; 150 void *event_log_cpu_addr; 151 152 /* ip specific functions */ 153 const struct amdgpu_mes_funcs *funcs; 154 155 /* mes resource_1 bo*/ 156 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 157 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 158 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 159 160 int hung_queue_db_array_size; 161 int hung_queue_hqd_info_offset; 162 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 163 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 164 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 165 166 /* cooperative dispatch */ 167 bool enable_coop_mode; 168 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 169 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 170 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 171 172 bool compute_pipe_reset_enabled; 173 bool gfx_pipe_reset_enabled; 174 }; 175 176 struct amdgpu_mes_hung_queue_hqd_info { 177 union { 178 struct { 179 u32 queue_type: 3; // queue type 180 u32 pipe_index: 4; // pipe index 181 u32 queue_index: 8; // queue index 182 u32 reserved: 17; 183 }; 184 185 u32 bit0_31; 186 }; 187 }; 188 189 struct amdgpu_mes_gang { 190 int gang_id; 191 int priority; 192 int inprocess_gang_priority; 193 int global_priority_level; 194 struct list_head list; 195 struct amdgpu_mes_process *process; 196 struct amdgpu_bo *gang_ctx_bo; 197 uint64_t gang_ctx_gpu_addr; 198 void *gang_ctx_cpu_ptr; 199 uint64_t gang_quantum; 200 struct list_head queue_list; 201 }; 202 203 struct amdgpu_mes_queue { 204 struct list_head list; 205 struct amdgpu_mes_gang *gang; 206 int queue_id; 207 uint64_t doorbell_off; 208 struct amdgpu_bo *mqd_obj; 209 void *mqd_cpu_ptr; 210 uint64_t mqd_gpu_addr; 211 uint64_t wptr_gpu_addr; 212 int queue_type; 213 int paging; 214 struct amdgpu_ring *ring; 215 }; 216 217 struct amdgpu_mes_queue_properties { 218 int queue_type; 219 uint64_t hqd_base_gpu_addr; 220 uint64_t rptr_gpu_addr; 221 uint64_t wptr_gpu_addr; 222 uint64_t wptr_mc_addr; 223 uint32_t queue_size; 224 uint64_t eop_gpu_addr; 225 uint32_t hqd_pipe_priority; 226 uint32_t hqd_queue_priority; 227 bool paging; 228 struct amdgpu_ring *ring; 229 /* out */ 230 uint64_t doorbell_off; 231 }; 232 233 struct amdgpu_mes_gang_properties { 234 uint32_t priority; 235 uint32_t gang_quantum; 236 uint32_t inprocess_gang_priority; 237 uint32_t priority_level; 238 int global_priority_level; 239 }; 240 241 struct mes_add_queue_input { 242 uint32_t xcc_id; 243 uint32_t process_id; 244 uint64_t page_table_base_addr; 245 uint64_t process_va_start; 246 uint64_t process_va_end; 247 uint64_t process_quantum; 248 uint64_t process_context_addr; 249 uint64_t gang_quantum; 250 uint64_t gang_context_addr; 251 uint32_t inprocess_gang_priority; 252 uint32_t gang_global_priority_level; 253 uint32_t doorbell_offset; 254 uint64_t mqd_addr; 255 uint64_t wptr_addr; 256 uint64_t wptr_mc_addr; 257 uint32_t queue_type; 258 uint32_t paging; 259 uint32_t gws_base; 260 uint32_t gws_size; 261 uint64_t tba_addr; 262 uint64_t tma_addr; 263 uint32_t trap_en; 264 uint32_t skip_process_ctx_clear; 265 uint32_t is_kfd_process; 266 uint32_t is_aql_queue; 267 uint32_t queue_size; 268 uint32_t exclusively_scheduled; 269 uint32_t sh_mem_config_data; 270 uint32_t vm_cntx_cntl; 271 }; 272 273 struct mes_remove_queue_input { 274 uint32_t xcc_id; 275 uint32_t doorbell_offset; 276 uint64_t gang_context_addr; 277 uint32_t queue_type; 278 bool remove_queue_after_reset; 279 }; 280 281 struct mes_map_legacy_queue_input { 282 uint32_t xcc_id; 283 uint32_t queue_type; 284 uint32_t doorbell_offset; 285 uint32_t pipe_id; 286 uint32_t queue_id; 287 uint64_t mqd_addr; 288 uint64_t wptr_addr; 289 }; 290 291 struct mes_unmap_legacy_queue_input { 292 uint32_t xcc_id; 293 enum amdgpu_unmap_queues_action action; 294 uint32_t queue_type; 295 uint32_t doorbell_offset; 296 uint32_t pipe_id; 297 uint32_t queue_id; 298 uint64_t trail_fence_addr; 299 uint64_t trail_fence_data; 300 }; 301 302 struct mes_suspend_gang_input { 303 uint32_t xcc_id; 304 bool suspend_all_gangs; 305 bool suspend_all_sdma_gangs; 306 uint64_t gang_context_addr; 307 uint64_t suspend_fence_addr; 308 uint32_t suspend_fence_value; 309 uint32_t doorbell_offset; 310 }; 311 312 struct mes_resume_gang_input { 313 uint32_t xcc_id; 314 bool resume_all_gangs; 315 uint64_t gang_context_addr; 316 uint32_t doorbell_offset; 317 }; 318 319 struct mes_reset_queue_input { 320 uint32_t xcc_id; 321 uint32_t queue_type; 322 uint32_t doorbell_offset; 323 bool use_mmio; 324 uint32_t me_id; 325 uint32_t pipe_id; 326 uint32_t queue_id; 327 uint64_t mqd_addr; 328 uint64_t wptr_addr; 329 uint32_t vmid; 330 bool legacy_gfx; 331 bool is_kq; 332 }; 333 334 struct mes_detect_and_reset_queue_input { 335 u32 queue_type; 336 bool detect_only; 337 u32 xcc_id; 338 }; 339 340 struct mes_inv_tlbs_pasid_input { 341 uint32_t xcc_id; 342 uint16_t pasid; 343 uint8_t hub_id; 344 uint8_t flush_type; 345 }; 346 347 enum mes_misc_opcode { 348 MES_MISC_OP_WRITE_REG, 349 MES_MISC_OP_READ_REG, 350 MES_MISC_OP_WRM_REG_WAIT, 351 MES_MISC_OP_WRM_REG_WR_WAIT, 352 MES_MISC_OP_SET_SHADER_DEBUGGER, 353 MES_MISC_OP_CHANGE_CONFIG, 354 }; 355 356 struct mes_misc_op_input { 357 uint32_t xcc_id; 358 enum mes_misc_opcode op; 359 360 union { 361 struct { 362 uint32_t reg_offset; 363 uint64_t buffer_addr; 364 } read_reg; 365 366 struct { 367 uint32_t reg_offset; 368 uint32_t reg_value; 369 } write_reg; 370 371 struct { 372 uint32_t ref; 373 uint32_t mask; 374 uint32_t reg0; 375 uint32_t reg1; 376 } wrm_reg; 377 378 struct { 379 uint64_t process_context_addr; 380 union { 381 struct { 382 uint32_t single_memop : 1; 383 uint32_t single_alu_op : 1; 384 uint32_t reserved: 29; 385 uint32_t process_ctx_flush: 1; 386 }; 387 uint32_t u32all; 388 } flags; 389 uint32_t spi_gdbg_per_vmid_cntl; 390 uint32_t tcp_watch_cntl[4]; 391 uint32_t trap_en; 392 } set_shader_debugger; 393 394 struct { 395 union { 396 struct { 397 uint32_t limit_single_process : 1; 398 uint32_t enable_hws_logging_buffer : 1; 399 uint32_t reserved : 30; 400 }; 401 uint32_t all; 402 } option; 403 struct { 404 uint32_t tdr_level; 405 uint32_t tdr_delay; 406 } tdr_config; 407 } change_config; 408 }; 409 }; 410 411 struct amdgpu_mes_funcs { 412 int (*add_hw_queue)(struct amdgpu_mes *mes, 413 struct mes_add_queue_input *input); 414 415 int (*remove_hw_queue)(struct amdgpu_mes *mes, 416 struct mes_remove_queue_input *input); 417 418 int (*map_legacy_queue)(struct amdgpu_mes *mes, 419 struct mes_map_legacy_queue_input *input); 420 421 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 422 struct mes_unmap_legacy_queue_input *input); 423 424 int (*suspend_gang)(struct amdgpu_mes *mes, 425 struct mes_suspend_gang_input *input); 426 427 int (*resume_gang)(struct amdgpu_mes *mes, 428 struct mes_resume_gang_input *input); 429 430 int (*misc_op)(struct amdgpu_mes *mes, 431 struct mes_misc_op_input *input); 432 433 int (*reset_hw_queue)(struct amdgpu_mes *mes, 434 struct mes_reset_queue_input *input); 435 436 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 437 struct mes_detect_and_reset_queue_input *input); 438 439 440 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 441 struct mes_inv_tlbs_pasid_input *input); 442 }; 443 444 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 445 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 446 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 447 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 448 449 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 450 void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev); 451 int amdgpu_mes_init(struct amdgpu_device *adev); 452 void amdgpu_mes_fini(struct amdgpu_device *adev); 453 454 int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); 455 int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); 456 457 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 458 struct amdgpu_ring *ring, uint32_t xcc_id); 459 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 460 struct amdgpu_ring *ring, 461 enum amdgpu_unmap_queues_action action, 462 u64 gpu_addr, u64 seq, uint32_t xcc_id); 463 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 464 struct amdgpu_ring *ring, 465 unsigned int vmid, 466 bool use_mmio, 467 uint32_t xcc_id); 468 int amdgpu_mes_reset_queue_mmio(struct amdgpu_device *adev, 469 int queue_type, 470 unsigned int vmid, 471 unsigned int me, 472 unsigned int pipe, 473 unsigned int queue, 474 uint32_t xcc_id); 475 int amdgpu_mes_reset_user_queue(struct amdgpu_device *adev, 476 int queue_type, 477 unsigned int doorbell_index, 478 unsigned int xcc_id); 479 480 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 481 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 482 int queue_type, 483 bool detect_only, 484 unsigned int *hung_db_num, 485 u32 *hung_db_array, 486 uint32_t xcc_id); 487 488 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 489 uint32_t xcc_id); 490 int amdgpu_mes_wreg(struct amdgpu_device *adev, 491 uint32_t reg, uint32_t val, uint32_t xcc_id); 492 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 493 uint32_t reg0, uint32_t reg1, 494 uint32_t ref, uint32_t mask, uint32_t xcc_id); 495 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 496 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 497 uint64_t process_context_addr, 498 uint32_t spi_gdbg_per_vmid_cntl, 499 const uint32_t *tcp_watch_cntl, 500 uint32_t flags, 501 bool trap_en, 502 uint32_t xcc_id); 503 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 504 uint64_t process_context_addr, uint32_t xcc_id); 505 506 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 507 enum amdgpu_mes_priority_level prio); 508 509 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 510 511 /* 512 * MES lock can be taken in MMU notifiers. 513 * 514 * A bit more detail about why to set no-FS reclaim with MES lock: 515 * 516 * The purpose of the MMU notifier is to stop GPU access to memory so 517 * that the Linux VM subsystem can move pages around safely. This is 518 * done by preempting user mode queues for the affected process. When 519 * MES is used, MES lock needs to be taken to preempt the queues. 520 * 521 * The MMU notifier callback entry point in the driver is 522 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 523 * there is: 524 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 525 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 526 * 527 * The last part of the chain is a function pointer where we take the 528 * MES lock. 529 * 530 * The problem with taking locks in the MMU notifier is, that MMU 531 * notifiers can be called in reclaim-FS context. That's where the 532 * kernel frees up pages to make room for new page allocations under 533 * memory pressure. While we are running in reclaim-FS context, we must 534 * not trigger another memory reclaim operation because that would 535 * recursively reenter the reclaim code and cause a deadlock. The 536 * memalloc_nofs_save/restore calls guarantee that. 537 * 538 * In addition we also need to avoid lock dependencies on other locks taken 539 * under the MES lock, for example reservation locks. Here is a possible 540 * scenario of a deadlock: 541 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 542 * MMU notifier | blocks trying to take MES lock 543 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 544 * 545 * In this scenario Thread B gets involved in a deadlock even without 546 * triggering a reclaim-FS operation itself. 547 * To fix this and break the lock dependency chain you'd need to either: 548 * 1. protect reservation locks with memalloc_nofs_save/restore, or 549 * 2. avoid taking reservation locks under the MES lock. 550 * 551 * Reservation locks are taken all over the kernel in different subsystems, we 552 * have no control over them and their lock dependencies.So the only workable 553 * solution is to avoid taking other locks under the MES lock. 554 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 555 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 556 */ 557 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 558 { 559 mutex_lock(&mes->mutex_hidden); 560 mes->saved_flags = memalloc_noreclaim_save(); 561 } 562 563 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 564 { 565 memalloc_noreclaim_restore(mes->saved_flags); 566 mutex_unlock(&mes->mutex_hidden); 567 } 568 569 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 570 bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); 571 572 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 573 574 #endif /* __AMDGPU_MES_H__ */ 575