1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_PIPE_0 = 0, 62 AMDGPU_MES_PIPE_1, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 69 #define AMDGPU_MAX_MES_INST_PIPES \ 70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 72 #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 74 75 struct amdgpu_mes { 76 struct amdgpu_device *adev; 77 78 struct mutex mutex_hidden; 79 80 struct idr pasid_idr; 81 struct idr gang_id_idr; 82 struct idr queue_id_idr; 83 struct ida doorbell_ida; 84 85 spinlock_t queue_id_lock; 86 87 uint32_t sched_version; 88 uint32_t kiq_version; 89 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 90 bool enable_legacy_queue_map; 91 92 uint32_t total_max_queue; 93 uint32_t max_doorbell_slices; 94 95 uint64_t default_process_quantum; 96 uint64_t default_gang_quantum; 97 98 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 99 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 100 101 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 102 103 /* mes ucode */ 104 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 105 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 106 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 107 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 108 109 /* mes ucode data */ 110 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 111 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 112 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 113 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 114 115 /* eop gpu obj */ 116 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 117 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 118 119 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 120 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 121 122 uint32_t vmid_mask_gfxhub; 123 uint32_t vmid_mask_mmhub; 124 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 125 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 126 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 127 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 128 129 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 130 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 132 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 133 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 134 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 135 136 uint32_t saved_flags; 137 138 /* initialize kiq pipe */ 139 int (*kiq_hw_init)(struct amdgpu_device *adev, 140 uint32_t xcc_id); 141 int (*kiq_hw_fini)(struct amdgpu_device *adev, 142 uint32_t xcc_id); 143 144 /* MES doorbells */ 145 uint32_t db_start_dw_offset; 146 uint32_t num_mes_dbs; 147 unsigned long *doorbell_bitmap; 148 149 /* MES event log buffer */ 150 uint32_t event_log_size; 151 struct amdgpu_bo *event_log_gpu_obj; 152 uint64_t event_log_gpu_addr; 153 void *event_log_cpu_addr; 154 155 /* ip specific functions */ 156 const struct amdgpu_mes_funcs *funcs; 157 158 /* mes resource_1 bo*/ 159 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 160 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 161 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 162 163 int hung_queue_db_array_size; 164 int hung_queue_hqd_info_offset; 165 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES]; 166 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES]; 167 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES]; 168 }; 169 170 struct amdgpu_mes_gang { 171 int gang_id; 172 int priority; 173 int inprocess_gang_priority; 174 int global_priority_level; 175 struct list_head list; 176 struct amdgpu_mes_process *process; 177 struct amdgpu_bo *gang_ctx_bo; 178 uint64_t gang_ctx_gpu_addr; 179 void *gang_ctx_cpu_ptr; 180 uint64_t gang_quantum; 181 struct list_head queue_list; 182 }; 183 184 struct amdgpu_mes_queue { 185 struct list_head list; 186 struct amdgpu_mes_gang *gang; 187 int queue_id; 188 uint64_t doorbell_off; 189 struct amdgpu_bo *mqd_obj; 190 void *mqd_cpu_ptr; 191 uint64_t mqd_gpu_addr; 192 uint64_t wptr_gpu_addr; 193 int queue_type; 194 int paging; 195 struct amdgpu_ring *ring; 196 }; 197 198 struct amdgpu_mes_queue_properties { 199 int queue_type; 200 uint64_t hqd_base_gpu_addr; 201 uint64_t rptr_gpu_addr; 202 uint64_t wptr_gpu_addr; 203 uint64_t wptr_mc_addr; 204 uint32_t queue_size; 205 uint64_t eop_gpu_addr; 206 uint32_t hqd_pipe_priority; 207 uint32_t hqd_queue_priority; 208 bool paging; 209 struct amdgpu_ring *ring; 210 /* out */ 211 uint64_t doorbell_off; 212 }; 213 214 struct amdgpu_mes_gang_properties { 215 uint32_t priority; 216 uint32_t gang_quantum; 217 uint32_t inprocess_gang_priority; 218 uint32_t priority_level; 219 int global_priority_level; 220 }; 221 222 struct mes_add_queue_input { 223 uint32_t xcc_id; 224 uint32_t process_id; 225 uint64_t page_table_base_addr; 226 uint64_t process_va_start; 227 uint64_t process_va_end; 228 uint64_t process_quantum; 229 uint64_t process_context_addr; 230 uint64_t gang_quantum; 231 uint64_t gang_context_addr; 232 uint32_t inprocess_gang_priority; 233 uint32_t gang_global_priority_level; 234 uint32_t doorbell_offset; 235 uint64_t mqd_addr; 236 uint64_t wptr_addr; 237 uint64_t wptr_mc_addr; 238 uint32_t queue_type; 239 uint32_t paging; 240 uint32_t gws_base; 241 uint32_t gws_size; 242 uint64_t tba_addr; 243 uint64_t tma_addr; 244 uint32_t trap_en; 245 uint32_t skip_process_ctx_clear; 246 uint32_t is_kfd_process; 247 uint32_t is_aql_queue; 248 uint32_t queue_size; 249 uint32_t exclusively_scheduled; 250 }; 251 252 struct mes_remove_queue_input { 253 uint32_t xcc_id; 254 uint32_t doorbell_offset; 255 uint64_t gang_context_addr; 256 bool remove_queue_after_reset; 257 }; 258 259 struct mes_map_legacy_queue_input { 260 uint32_t xcc_id; 261 uint32_t queue_type; 262 uint32_t doorbell_offset; 263 uint32_t pipe_id; 264 uint32_t queue_id; 265 uint64_t mqd_addr; 266 uint64_t wptr_addr; 267 }; 268 269 struct mes_unmap_legacy_queue_input { 270 uint32_t xcc_id; 271 enum amdgpu_unmap_queues_action action; 272 uint32_t queue_type; 273 uint32_t doorbell_offset; 274 uint32_t pipe_id; 275 uint32_t queue_id; 276 uint64_t trail_fence_addr; 277 uint64_t trail_fence_data; 278 }; 279 280 struct mes_suspend_gang_input { 281 uint32_t xcc_id; 282 bool suspend_all_gangs; 283 uint64_t gang_context_addr; 284 uint64_t suspend_fence_addr; 285 uint32_t suspend_fence_value; 286 }; 287 288 struct mes_resume_gang_input { 289 uint32_t xcc_id; 290 bool resume_all_gangs; 291 uint64_t gang_context_addr; 292 }; 293 294 struct mes_reset_queue_input { 295 uint32_t xcc_id; 296 uint32_t queue_type; 297 uint32_t doorbell_offset; 298 bool use_mmio; 299 uint32_t me_id; 300 uint32_t pipe_id; 301 uint32_t queue_id; 302 uint64_t mqd_addr; 303 uint64_t wptr_addr; 304 uint32_t vmid; 305 bool legacy_gfx; 306 bool is_kq; 307 }; 308 309 struct mes_detect_and_reset_queue_input { 310 uint32_t queue_type; 311 bool detect_only; 312 }; 313 314 struct mes_inv_tlbs_pasid_input { 315 uint32_t xcc_id; 316 uint16_t pasid; 317 uint8_t hub_id; 318 uint8_t flush_type; 319 }; 320 321 enum mes_misc_opcode { 322 MES_MISC_OP_WRITE_REG, 323 MES_MISC_OP_READ_REG, 324 MES_MISC_OP_WRM_REG_WAIT, 325 MES_MISC_OP_WRM_REG_WR_WAIT, 326 MES_MISC_OP_SET_SHADER_DEBUGGER, 327 MES_MISC_OP_CHANGE_CONFIG, 328 }; 329 330 struct mes_misc_op_input { 331 uint32_t xcc_id; 332 enum mes_misc_opcode op; 333 334 union { 335 struct { 336 uint32_t reg_offset; 337 uint64_t buffer_addr; 338 } read_reg; 339 340 struct { 341 uint32_t reg_offset; 342 uint32_t reg_value; 343 } write_reg; 344 345 struct { 346 uint32_t ref; 347 uint32_t mask; 348 uint32_t reg0; 349 uint32_t reg1; 350 } wrm_reg; 351 352 struct { 353 uint64_t process_context_addr; 354 union { 355 struct { 356 uint32_t single_memop : 1; 357 uint32_t single_alu_op : 1; 358 uint32_t reserved: 29; 359 uint32_t process_ctx_flush: 1; 360 }; 361 uint32_t u32all; 362 } flags; 363 uint32_t spi_gdbg_per_vmid_cntl; 364 uint32_t tcp_watch_cntl[4]; 365 uint32_t trap_en; 366 } set_shader_debugger; 367 368 struct { 369 union { 370 struct { 371 uint32_t limit_single_process : 1; 372 uint32_t enable_hws_logging_buffer : 1; 373 uint32_t reserved : 30; 374 }; 375 uint32_t all; 376 } option; 377 struct { 378 uint32_t tdr_level; 379 uint32_t tdr_delay; 380 } tdr_config; 381 } change_config; 382 }; 383 }; 384 385 struct amdgpu_mes_funcs { 386 int (*add_hw_queue)(struct amdgpu_mes *mes, 387 struct mes_add_queue_input *input); 388 389 int (*remove_hw_queue)(struct amdgpu_mes *mes, 390 struct mes_remove_queue_input *input); 391 392 int (*map_legacy_queue)(struct amdgpu_mes *mes, 393 struct mes_map_legacy_queue_input *input); 394 395 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 396 struct mes_unmap_legacy_queue_input *input); 397 398 int (*suspend_gang)(struct amdgpu_mes *mes, 399 struct mes_suspend_gang_input *input); 400 401 int (*resume_gang)(struct amdgpu_mes *mes, 402 struct mes_resume_gang_input *input); 403 404 int (*misc_op)(struct amdgpu_mes *mes, 405 struct mes_misc_op_input *input); 406 407 int (*reset_hw_queue)(struct amdgpu_mes *mes, 408 struct mes_reset_queue_input *input); 409 410 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 411 struct mes_detect_and_reset_queue_input *input); 412 413 414 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 415 struct mes_inv_tlbs_pasid_input *input); 416 }; 417 418 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 419 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 420 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 421 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 422 423 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 424 int amdgpu_mes_init(struct amdgpu_device *adev); 425 void amdgpu_mes_fini(struct amdgpu_device *adev); 426 427 int amdgpu_mes_suspend(struct amdgpu_device *adev); 428 int amdgpu_mes_resume(struct amdgpu_device *adev); 429 430 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 431 struct amdgpu_ring *ring, uint32_t xcc_id); 432 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 433 struct amdgpu_ring *ring, 434 enum amdgpu_unmap_queues_action action, 435 u64 gpu_addr, u64 seq, uint32_t xcc_id); 436 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 437 struct amdgpu_ring *ring, 438 unsigned int vmid, 439 bool use_mmio, 440 uint32_t xcc_id); 441 442 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 443 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 444 int queue_type, 445 bool detect_only, 446 unsigned int *hung_db_num, 447 u32 *hung_db_array, 448 uint32_t xcc_id); 449 450 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 451 uint32_t xcc_id); 452 int amdgpu_mes_wreg(struct amdgpu_device *adev, 453 uint32_t reg, uint32_t val, uint32_t xcc_id); 454 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 455 uint32_t reg0, uint32_t reg1, 456 uint32_t ref, uint32_t mask, uint32_t xcc_id); 457 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 458 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 459 uint64_t process_context_addr, 460 uint32_t spi_gdbg_per_vmid_cntl, 461 const uint32_t *tcp_watch_cntl, 462 uint32_t flags, 463 bool trap_en, 464 uint32_t xcc_id); 465 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 466 uint64_t process_context_addr, uint32_t xcc_id); 467 468 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 469 enum amdgpu_mes_priority_level prio); 470 471 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 472 473 /* 474 * MES lock can be taken in MMU notifiers. 475 * 476 * A bit more detail about why to set no-FS reclaim with MES lock: 477 * 478 * The purpose of the MMU notifier is to stop GPU access to memory so 479 * that the Linux VM subsystem can move pages around safely. This is 480 * done by preempting user mode queues for the affected process. When 481 * MES is used, MES lock needs to be taken to preempt the queues. 482 * 483 * The MMU notifier callback entry point in the driver is 484 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 485 * there is: 486 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 487 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 488 * 489 * The last part of the chain is a function pointer where we take the 490 * MES lock. 491 * 492 * The problem with taking locks in the MMU notifier is, that MMU 493 * notifiers can be called in reclaim-FS context. That's where the 494 * kernel frees up pages to make room for new page allocations under 495 * memory pressure. While we are running in reclaim-FS context, we must 496 * not trigger another memory reclaim operation because that would 497 * recursively reenter the reclaim code and cause a deadlock. The 498 * memalloc_nofs_save/restore calls guarantee that. 499 * 500 * In addition we also need to avoid lock dependencies on other locks taken 501 * under the MES lock, for example reservation locks. Here is a possible 502 * scenario of a deadlock: 503 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 504 * MMU notifier | blocks trying to take MES lock 505 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 506 * 507 * In this scenario Thread B gets involved in a deadlock even without 508 * triggering a reclaim-FS operation itself. 509 * To fix this and break the lock dependency chain you'd need to either: 510 * 1. protect reservation locks with memalloc_nofs_save/restore, or 511 * 2. avoid taking reservation locks under the MES lock. 512 * 513 * Reservation locks are taken all over the kernel in different subsystems, we 514 * have no control over them and their lock dependencies.So the only workable 515 * solution is to avoid taking other locks under the MES lock. 516 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 517 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 518 */ 519 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 520 { 521 mutex_lock(&mes->mutex_hidden); 522 mes->saved_flags = memalloc_noreclaim_save(); 523 } 524 525 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 526 { 527 memalloc_noreclaim_restore(mes->saved_flags); 528 mutex_unlock(&mes->mutex_hidden); 529 } 530 531 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 532 533 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 534 535 #endif /* __AMDGPU_MES_H__ */ 536