1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 45 enum amdgpu_mes_priority_level { 46 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 47 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 48 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 49 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 50 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 51 AMDGPU_MES_PRIORITY_NUM_LEVELS 52 }; 53 54 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 55 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 56 57 struct amdgpu_mes_funcs; 58 59 enum amdgpu_mes_pipe { 60 AMDGPU_MES_SCHED_PIPE = 0, 61 AMDGPU_MES_KIQ_PIPE, 62 AMDGPU_MAX_MES_PIPES = 2, 63 }; 64 65 struct amdgpu_mes { 66 struct amdgpu_device *adev; 67 68 struct mutex mutex_hidden; 69 70 struct idr pasid_idr; 71 struct idr gang_id_idr; 72 struct idr queue_id_idr; 73 struct ida doorbell_ida; 74 75 spinlock_t queue_id_lock; 76 77 uint32_t sched_version; 78 uint32_t kiq_version; 79 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 80 bool enable_legacy_queue_map; 81 82 uint32_t total_max_queue; 83 uint32_t max_doorbell_slices; 84 85 uint64_t default_process_quantum; 86 uint64_t default_gang_quantum; 87 88 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 89 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 90 91 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 92 93 /* mes ucode */ 94 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 95 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 96 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 97 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 98 99 /* mes ucode data */ 100 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 101 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 102 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 103 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 104 105 /* eop gpu obj */ 106 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 107 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 108 109 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 110 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 111 112 uint32_t vmid_mask_gfxhub; 113 uint32_t vmid_mask_mmhub; 114 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 115 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 116 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 117 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 118 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 119 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 120 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 121 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 122 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 123 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 124 125 uint32_t saved_flags; 126 127 /* initialize kiq pipe */ 128 int (*kiq_hw_init)(struct amdgpu_device *adev); 129 int (*kiq_hw_fini)(struct amdgpu_device *adev); 130 131 /* MES doorbells */ 132 uint32_t db_start_dw_offset; 133 uint32_t num_mes_dbs; 134 unsigned long *doorbell_bitmap; 135 136 /* MES event log buffer */ 137 uint32_t event_log_size; 138 struct amdgpu_bo *event_log_gpu_obj; 139 uint64_t event_log_gpu_addr; 140 void *event_log_cpu_addr; 141 142 /* ip specific functions */ 143 const struct amdgpu_mes_funcs *funcs; 144 145 /* mes resource_1 bo*/ 146 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 147 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 148 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 149 150 }; 151 152 struct amdgpu_mes_gang { 153 int gang_id; 154 int priority; 155 int inprocess_gang_priority; 156 int global_priority_level; 157 struct list_head list; 158 struct amdgpu_mes_process *process; 159 struct amdgpu_bo *gang_ctx_bo; 160 uint64_t gang_ctx_gpu_addr; 161 void *gang_ctx_cpu_ptr; 162 uint64_t gang_quantum; 163 struct list_head queue_list; 164 }; 165 166 struct amdgpu_mes_queue { 167 struct list_head list; 168 struct amdgpu_mes_gang *gang; 169 int queue_id; 170 uint64_t doorbell_off; 171 struct amdgpu_bo *mqd_obj; 172 void *mqd_cpu_ptr; 173 uint64_t mqd_gpu_addr; 174 uint64_t wptr_gpu_addr; 175 int queue_type; 176 int paging; 177 struct amdgpu_ring *ring; 178 }; 179 180 struct amdgpu_mes_queue_properties { 181 int queue_type; 182 uint64_t hqd_base_gpu_addr; 183 uint64_t rptr_gpu_addr; 184 uint64_t wptr_gpu_addr; 185 uint64_t wptr_mc_addr; 186 uint32_t queue_size; 187 uint64_t eop_gpu_addr; 188 uint32_t hqd_pipe_priority; 189 uint32_t hqd_queue_priority; 190 bool paging; 191 struct amdgpu_ring *ring; 192 /* out */ 193 uint64_t doorbell_off; 194 }; 195 196 struct amdgpu_mes_gang_properties { 197 uint32_t priority; 198 uint32_t gang_quantum; 199 uint32_t inprocess_gang_priority; 200 uint32_t priority_level; 201 int global_priority_level; 202 }; 203 204 struct mes_add_queue_input { 205 uint32_t process_id; 206 uint64_t page_table_base_addr; 207 uint64_t process_va_start; 208 uint64_t process_va_end; 209 uint64_t process_quantum; 210 uint64_t process_context_addr; 211 uint64_t gang_quantum; 212 uint64_t gang_context_addr; 213 uint32_t inprocess_gang_priority; 214 uint32_t gang_global_priority_level; 215 uint32_t doorbell_offset; 216 uint64_t mqd_addr; 217 uint64_t wptr_addr; 218 uint64_t wptr_mc_addr; 219 uint32_t queue_type; 220 uint32_t paging; 221 uint32_t gws_base; 222 uint32_t gws_size; 223 uint64_t tba_addr; 224 uint64_t tma_addr; 225 uint32_t trap_en; 226 uint32_t skip_process_ctx_clear; 227 uint32_t is_kfd_process; 228 uint32_t is_aql_queue; 229 uint32_t queue_size; 230 uint32_t exclusively_scheduled; 231 }; 232 233 struct mes_remove_queue_input { 234 uint32_t doorbell_offset; 235 uint64_t gang_context_addr; 236 }; 237 238 struct mes_reset_queue_input { 239 uint32_t doorbell_offset; 240 uint64_t gang_context_addr; 241 bool use_mmio; 242 uint32_t queue_type; 243 uint32_t me_id; 244 uint32_t pipe_id; 245 uint32_t queue_id; 246 uint32_t xcc_id; 247 uint32_t vmid; 248 }; 249 250 struct mes_map_legacy_queue_input { 251 uint32_t queue_type; 252 uint32_t doorbell_offset; 253 uint32_t pipe_id; 254 uint32_t queue_id; 255 uint64_t mqd_addr; 256 uint64_t wptr_addr; 257 }; 258 259 struct mes_unmap_legacy_queue_input { 260 enum amdgpu_unmap_queues_action action; 261 uint32_t queue_type; 262 uint32_t doorbell_offset; 263 uint32_t pipe_id; 264 uint32_t queue_id; 265 uint64_t trail_fence_addr; 266 uint64_t trail_fence_data; 267 }; 268 269 struct mes_suspend_gang_input { 270 bool suspend_all_gangs; 271 uint64_t gang_context_addr; 272 uint64_t suspend_fence_addr; 273 uint32_t suspend_fence_value; 274 }; 275 276 struct mes_resume_gang_input { 277 bool resume_all_gangs; 278 uint64_t gang_context_addr; 279 }; 280 281 struct mes_reset_legacy_queue_input { 282 uint32_t queue_type; 283 uint32_t doorbell_offset; 284 bool use_mmio; 285 uint32_t me_id; 286 uint32_t pipe_id; 287 uint32_t queue_id; 288 uint64_t mqd_addr; 289 uint64_t wptr_addr; 290 uint32_t vmid; 291 }; 292 293 enum mes_misc_opcode { 294 MES_MISC_OP_WRITE_REG, 295 MES_MISC_OP_READ_REG, 296 MES_MISC_OP_WRM_REG_WAIT, 297 MES_MISC_OP_WRM_REG_WR_WAIT, 298 MES_MISC_OP_SET_SHADER_DEBUGGER, 299 MES_MISC_OP_CHANGE_CONFIG, 300 }; 301 302 struct mes_misc_op_input { 303 enum mes_misc_opcode op; 304 305 union { 306 struct { 307 uint32_t reg_offset; 308 uint64_t buffer_addr; 309 } read_reg; 310 311 struct { 312 uint32_t reg_offset; 313 uint32_t reg_value; 314 } write_reg; 315 316 struct { 317 uint32_t ref; 318 uint32_t mask; 319 uint32_t reg0; 320 uint32_t reg1; 321 } wrm_reg; 322 323 struct { 324 uint64_t process_context_addr; 325 union { 326 struct { 327 uint32_t single_memop : 1; 328 uint32_t single_alu_op : 1; 329 uint32_t reserved: 29; 330 uint32_t process_ctx_flush: 1; 331 }; 332 uint32_t u32all; 333 } flags; 334 uint32_t spi_gdbg_per_vmid_cntl; 335 uint32_t tcp_watch_cntl[4]; 336 uint32_t trap_en; 337 } set_shader_debugger; 338 339 struct { 340 union { 341 struct { 342 uint32_t limit_single_process : 1; 343 uint32_t enable_hws_logging_buffer : 1; 344 uint32_t reserved : 30; 345 }; 346 uint32_t all; 347 } option; 348 struct { 349 uint32_t tdr_level; 350 uint32_t tdr_delay; 351 } tdr_config; 352 } change_config; 353 }; 354 }; 355 356 struct amdgpu_mes_funcs { 357 int (*add_hw_queue)(struct amdgpu_mes *mes, 358 struct mes_add_queue_input *input); 359 360 int (*remove_hw_queue)(struct amdgpu_mes *mes, 361 struct mes_remove_queue_input *input); 362 363 int (*map_legacy_queue)(struct amdgpu_mes *mes, 364 struct mes_map_legacy_queue_input *input); 365 366 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 367 struct mes_unmap_legacy_queue_input *input); 368 369 int (*suspend_gang)(struct amdgpu_mes *mes, 370 struct mes_suspend_gang_input *input); 371 372 int (*resume_gang)(struct amdgpu_mes *mes, 373 struct mes_resume_gang_input *input); 374 375 int (*misc_op)(struct amdgpu_mes *mes, 376 struct mes_misc_op_input *input); 377 378 int (*reset_legacy_queue)(struct amdgpu_mes *mes, 379 struct mes_reset_legacy_queue_input *input); 380 381 int (*reset_hw_queue)(struct amdgpu_mes *mes, 382 struct mes_reset_queue_input *input); 383 }; 384 385 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 386 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 387 388 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 389 390 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 391 int amdgpu_mes_init(struct amdgpu_device *adev); 392 void amdgpu_mes_fini(struct amdgpu_device *adev); 393 394 int amdgpu_mes_suspend(struct amdgpu_device *adev); 395 int amdgpu_mes_resume(struct amdgpu_device *adev); 396 397 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); 398 int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, 399 int me_id, int pipe_id, int queue_id, int vmid); 400 401 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 402 struct amdgpu_ring *ring); 403 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 404 struct amdgpu_ring *ring, 405 enum amdgpu_unmap_queues_action action, 406 u64 gpu_addr, u64 seq); 407 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 408 struct amdgpu_ring *ring, 409 unsigned int vmid, 410 bool use_mmio); 411 412 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 413 int amdgpu_mes_wreg(struct amdgpu_device *adev, 414 uint32_t reg, uint32_t val); 415 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 416 uint32_t val, uint32_t mask); 417 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 418 uint32_t reg0, uint32_t reg1, 419 uint32_t ref, uint32_t mask); 420 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 421 uint64_t process_context_addr, 422 uint32_t spi_gdbg_per_vmid_cntl, 423 const uint32_t *tcp_watch_cntl, 424 uint32_t flags, 425 bool trap_en); 426 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 427 uint64_t process_context_addr); 428 429 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 430 enum amdgpu_mes_priority_level prio); 431 432 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 433 434 /* 435 * MES lock can be taken in MMU notifiers. 436 * 437 * A bit more detail about why to set no-FS reclaim with MES lock: 438 * 439 * The purpose of the MMU notifier is to stop GPU access to memory so 440 * that the Linux VM subsystem can move pages around safely. This is 441 * done by preempting user mode queues for the affected process. When 442 * MES is used, MES lock needs to be taken to preempt the queues. 443 * 444 * The MMU notifier callback entry point in the driver is 445 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 446 * there is: 447 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 448 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 449 * 450 * The last part of the chain is a function pointer where we take the 451 * MES lock. 452 * 453 * The problem with taking locks in the MMU notifier is, that MMU 454 * notifiers can be called in reclaim-FS context. That's where the 455 * kernel frees up pages to make room for new page allocations under 456 * memory pressure. While we are running in reclaim-FS context, we must 457 * not trigger another memory reclaim operation because that would 458 * recursively reenter the reclaim code and cause a deadlock. The 459 * memalloc_nofs_save/restore calls guarantee that. 460 * 461 * In addition we also need to avoid lock dependencies on other locks taken 462 * under the MES lock, for example reservation locks. Here is a possible 463 * scenario of a deadlock: 464 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 465 * MMU notifier | blocks trying to take MES lock 466 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 467 * 468 * In this scenario Thread B gets involved in a deadlock even without 469 * triggering a reclaim-FS operation itself. 470 * To fix this and break the lock dependency chain you'd need to either: 471 * 1. protect reservation locks with memalloc_nofs_save/restore, or 472 * 2. avoid taking reservation locks under the MES lock. 473 * 474 * Reservation locks are taken all over the kernel in different subsystems, we 475 * have no control over them and their lock dependencies.So the only workable 476 * solution is to avoid taking other locks under the MES lock. 477 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 478 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 479 */ 480 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 481 { 482 mutex_lock(&mes->mutex_hidden); 483 mes->saved_flags = memalloc_noreclaim_save(); 484 } 485 486 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 487 { 488 memalloc_noreclaim_restore(mes->saved_flags); 489 mutex_unlock(&mes->mutex_hidden); 490 } 491 492 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 493 494 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 495 496 #endif /* __AMDGPU_MES_H__ */ 497