1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_PIPE_0 = 0, 62 AMDGPU_MES_PIPE_1, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 69 #define AMDGPU_MAX_MES_INST_PIPES \ 70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 72 #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 74 75 struct amdgpu_mes { 76 struct amdgpu_device *adev; 77 78 struct mutex mutex_hidden; 79 80 struct idr pasid_idr; 81 struct idr gang_id_idr; 82 struct idr queue_id_idr; 83 struct ida doorbell_ida; 84 85 spinlock_t queue_id_lock; 86 87 uint32_t sched_version; 88 uint32_t kiq_version; 89 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 90 bool enable_legacy_queue_map; 91 92 uint32_t total_max_queue; 93 uint32_t max_doorbell_slices; 94 95 uint64_t default_process_quantum; 96 uint64_t default_gang_quantum; 97 98 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 99 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 100 101 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 102 103 /* mes ucode */ 104 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 105 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 106 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 107 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 108 109 /* mes ucode data */ 110 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 111 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 112 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 113 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 114 115 /* eop gpu obj */ 116 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 117 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 118 119 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 120 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 121 122 uint32_t vmid_mask_gfxhub; 123 uint32_t vmid_mask_mmhub; 124 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 125 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 126 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 127 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 128 129 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 130 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 132 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 133 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 134 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 135 136 uint32_t saved_flags; 137 138 /* initialize kiq pipe */ 139 int (*kiq_hw_init)(struct amdgpu_device *adev, 140 uint32_t xcc_id); 141 int (*kiq_hw_fini)(struct amdgpu_device *adev, 142 uint32_t xcc_id); 143 144 /* MES doorbells */ 145 uint32_t db_start_dw_offset; 146 uint32_t num_mes_dbs; 147 unsigned long *doorbell_bitmap; 148 149 /* MES event log buffer */ 150 uint32_t event_log_size; 151 struct amdgpu_bo *event_log_gpu_obj; 152 uint64_t event_log_gpu_addr; 153 void *event_log_cpu_addr; 154 155 /* ip specific functions */ 156 const struct amdgpu_mes_funcs *funcs; 157 158 /* mes resource_1 bo*/ 159 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 160 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 161 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 162 163 int hung_queue_db_array_size; 164 int hung_queue_hqd_info_offset; 165 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES]; 166 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES]; 167 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES]; 168 169 /* cooperative dispatch */ 170 bool enable_coop_mode; 171 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 172 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 173 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 174 }; 175 176 struct amdgpu_mes_gang { 177 int gang_id; 178 int priority; 179 int inprocess_gang_priority; 180 int global_priority_level; 181 struct list_head list; 182 struct amdgpu_mes_process *process; 183 struct amdgpu_bo *gang_ctx_bo; 184 uint64_t gang_ctx_gpu_addr; 185 void *gang_ctx_cpu_ptr; 186 uint64_t gang_quantum; 187 struct list_head queue_list; 188 }; 189 190 struct amdgpu_mes_queue { 191 struct list_head list; 192 struct amdgpu_mes_gang *gang; 193 int queue_id; 194 uint64_t doorbell_off; 195 struct amdgpu_bo *mqd_obj; 196 void *mqd_cpu_ptr; 197 uint64_t mqd_gpu_addr; 198 uint64_t wptr_gpu_addr; 199 int queue_type; 200 int paging; 201 struct amdgpu_ring *ring; 202 }; 203 204 struct amdgpu_mes_queue_properties { 205 int queue_type; 206 uint64_t hqd_base_gpu_addr; 207 uint64_t rptr_gpu_addr; 208 uint64_t wptr_gpu_addr; 209 uint64_t wptr_mc_addr; 210 uint32_t queue_size; 211 uint64_t eop_gpu_addr; 212 uint32_t hqd_pipe_priority; 213 uint32_t hqd_queue_priority; 214 bool paging; 215 struct amdgpu_ring *ring; 216 /* out */ 217 uint64_t doorbell_off; 218 }; 219 220 struct amdgpu_mes_gang_properties { 221 uint32_t priority; 222 uint32_t gang_quantum; 223 uint32_t inprocess_gang_priority; 224 uint32_t priority_level; 225 int global_priority_level; 226 }; 227 228 struct mes_add_queue_input { 229 uint32_t xcc_id; 230 uint32_t process_id; 231 uint64_t page_table_base_addr; 232 uint64_t process_va_start; 233 uint64_t process_va_end; 234 uint64_t process_quantum; 235 uint64_t process_context_addr; 236 uint64_t gang_quantum; 237 uint64_t gang_context_addr; 238 uint32_t inprocess_gang_priority; 239 uint32_t gang_global_priority_level; 240 uint32_t doorbell_offset; 241 uint64_t mqd_addr; 242 uint64_t wptr_addr; 243 uint64_t wptr_mc_addr; 244 uint32_t queue_type; 245 uint32_t paging; 246 uint32_t gws_base; 247 uint32_t gws_size; 248 uint64_t tba_addr; 249 uint64_t tma_addr; 250 uint32_t trap_en; 251 uint32_t skip_process_ctx_clear; 252 uint32_t is_kfd_process; 253 uint32_t is_aql_queue; 254 uint32_t queue_size; 255 uint32_t exclusively_scheduled; 256 uint32_t sh_mem_config_data; 257 uint32_t vm_cntx_cntl; 258 }; 259 260 struct mes_remove_queue_input { 261 uint32_t xcc_id; 262 uint32_t doorbell_offset; 263 uint64_t gang_context_addr; 264 bool remove_queue_after_reset; 265 }; 266 267 struct mes_map_legacy_queue_input { 268 uint32_t xcc_id; 269 uint32_t queue_type; 270 uint32_t doorbell_offset; 271 uint32_t pipe_id; 272 uint32_t queue_id; 273 uint64_t mqd_addr; 274 uint64_t wptr_addr; 275 }; 276 277 struct mes_unmap_legacy_queue_input { 278 uint32_t xcc_id; 279 enum amdgpu_unmap_queues_action action; 280 uint32_t queue_type; 281 uint32_t doorbell_offset; 282 uint32_t pipe_id; 283 uint32_t queue_id; 284 uint64_t trail_fence_addr; 285 uint64_t trail_fence_data; 286 }; 287 288 struct mes_suspend_gang_input { 289 uint32_t xcc_id; 290 bool suspend_all_gangs; 291 uint64_t gang_context_addr; 292 uint64_t suspend_fence_addr; 293 uint32_t suspend_fence_value; 294 }; 295 296 struct mes_resume_gang_input { 297 uint32_t xcc_id; 298 bool resume_all_gangs; 299 uint64_t gang_context_addr; 300 }; 301 302 struct mes_reset_queue_input { 303 uint32_t xcc_id; 304 uint32_t queue_type; 305 uint32_t doorbell_offset; 306 bool use_mmio; 307 uint32_t me_id; 308 uint32_t pipe_id; 309 uint32_t queue_id; 310 uint64_t mqd_addr; 311 uint64_t wptr_addr; 312 uint32_t vmid; 313 bool legacy_gfx; 314 bool is_kq; 315 }; 316 317 struct mes_detect_and_reset_queue_input { 318 uint32_t queue_type; 319 bool detect_only; 320 }; 321 322 struct mes_inv_tlbs_pasid_input { 323 uint32_t xcc_id; 324 uint16_t pasid; 325 uint8_t hub_id; 326 uint8_t flush_type; 327 }; 328 329 enum mes_misc_opcode { 330 MES_MISC_OP_WRITE_REG, 331 MES_MISC_OP_READ_REG, 332 MES_MISC_OP_WRM_REG_WAIT, 333 MES_MISC_OP_WRM_REG_WR_WAIT, 334 MES_MISC_OP_SET_SHADER_DEBUGGER, 335 MES_MISC_OP_CHANGE_CONFIG, 336 }; 337 338 struct mes_misc_op_input { 339 uint32_t xcc_id; 340 enum mes_misc_opcode op; 341 342 union { 343 struct { 344 uint32_t reg_offset; 345 uint64_t buffer_addr; 346 } read_reg; 347 348 struct { 349 uint32_t reg_offset; 350 uint32_t reg_value; 351 } write_reg; 352 353 struct { 354 uint32_t ref; 355 uint32_t mask; 356 uint32_t reg0; 357 uint32_t reg1; 358 } wrm_reg; 359 360 struct { 361 uint64_t process_context_addr; 362 union { 363 struct { 364 uint32_t single_memop : 1; 365 uint32_t single_alu_op : 1; 366 uint32_t reserved: 29; 367 uint32_t process_ctx_flush: 1; 368 }; 369 uint32_t u32all; 370 } flags; 371 uint32_t spi_gdbg_per_vmid_cntl; 372 uint32_t tcp_watch_cntl[4]; 373 uint32_t trap_en; 374 } set_shader_debugger; 375 376 struct { 377 union { 378 struct { 379 uint32_t limit_single_process : 1; 380 uint32_t enable_hws_logging_buffer : 1; 381 uint32_t reserved : 30; 382 }; 383 uint32_t all; 384 } option; 385 struct { 386 uint32_t tdr_level; 387 uint32_t tdr_delay; 388 } tdr_config; 389 } change_config; 390 }; 391 }; 392 393 struct amdgpu_mes_funcs { 394 int (*add_hw_queue)(struct amdgpu_mes *mes, 395 struct mes_add_queue_input *input); 396 397 int (*remove_hw_queue)(struct amdgpu_mes *mes, 398 struct mes_remove_queue_input *input); 399 400 int (*map_legacy_queue)(struct amdgpu_mes *mes, 401 struct mes_map_legacy_queue_input *input); 402 403 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 404 struct mes_unmap_legacy_queue_input *input); 405 406 int (*suspend_gang)(struct amdgpu_mes *mes, 407 struct mes_suspend_gang_input *input); 408 409 int (*resume_gang)(struct amdgpu_mes *mes, 410 struct mes_resume_gang_input *input); 411 412 int (*misc_op)(struct amdgpu_mes *mes, 413 struct mes_misc_op_input *input); 414 415 int (*reset_hw_queue)(struct amdgpu_mes *mes, 416 struct mes_reset_queue_input *input); 417 418 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 419 struct mes_detect_and_reset_queue_input *input); 420 421 422 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 423 struct mes_inv_tlbs_pasid_input *input); 424 }; 425 426 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 427 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 428 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 429 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 430 431 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 432 int amdgpu_mes_init(struct amdgpu_device *adev); 433 void amdgpu_mes_fini(struct amdgpu_device *adev); 434 435 int amdgpu_mes_suspend(struct amdgpu_device *adev); 436 int amdgpu_mes_resume(struct amdgpu_device *adev); 437 438 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 439 struct amdgpu_ring *ring, uint32_t xcc_id); 440 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 441 struct amdgpu_ring *ring, 442 enum amdgpu_unmap_queues_action action, 443 u64 gpu_addr, u64 seq, uint32_t xcc_id); 444 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 445 struct amdgpu_ring *ring, 446 unsigned int vmid, 447 bool use_mmio, 448 uint32_t xcc_id); 449 450 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 451 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 452 int queue_type, 453 bool detect_only, 454 unsigned int *hung_db_num, 455 u32 *hung_db_array, 456 uint32_t xcc_id); 457 458 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 459 uint32_t xcc_id); 460 int amdgpu_mes_wreg(struct amdgpu_device *adev, 461 uint32_t reg, uint32_t val, uint32_t xcc_id); 462 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 463 uint32_t reg0, uint32_t reg1, 464 uint32_t ref, uint32_t mask, uint32_t xcc_id); 465 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 466 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 467 uint64_t process_context_addr, 468 uint32_t spi_gdbg_per_vmid_cntl, 469 const uint32_t *tcp_watch_cntl, 470 uint32_t flags, 471 bool trap_en, 472 uint32_t xcc_id); 473 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 474 uint64_t process_context_addr, uint32_t xcc_id); 475 476 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 477 enum amdgpu_mes_priority_level prio); 478 479 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 480 481 /* 482 * MES lock can be taken in MMU notifiers. 483 * 484 * A bit more detail about why to set no-FS reclaim with MES lock: 485 * 486 * The purpose of the MMU notifier is to stop GPU access to memory so 487 * that the Linux VM subsystem can move pages around safely. This is 488 * done by preempting user mode queues for the affected process. When 489 * MES is used, MES lock needs to be taken to preempt the queues. 490 * 491 * The MMU notifier callback entry point in the driver is 492 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 493 * there is: 494 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 495 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 496 * 497 * The last part of the chain is a function pointer where we take the 498 * MES lock. 499 * 500 * The problem with taking locks in the MMU notifier is, that MMU 501 * notifiers can be called in reclaim-FS context. That's where the 502 * kernel frees up pages to make room for new page allocations under 503 * memory pressure. While we are running in reclaim-FS context, we must 504 * not trigger another memory reclaim operation because that would 505 * recursively reenter the reclaim code and cause a deadlock. The 506 * memalloc_nofs_save/restore calls guarantee that. 507 * 508 * In addition we also need to avoid lock dependencies on other locks taken 509 * under the MES lock, for example reservation locks. Here is a possible 510 * scenario of a deadlock: 511 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 512 * MMU notifier | blocks trying to take MES lock 513 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 514 * 515 * In this scenario Thread B gets involved in a deadlock even without 516 * triggering a reclaim-FS operation itself. 517 * To fix this and break the lock dependency chain you'd need to either: 518 * 1. protect reservation locks with memalloc_nofs_save/restore, or 519 * 2. avoid taking reservation locks under the MES lock. 520 * 521 * Reservation locks are taken all over the kernel in different subsystems, we 522 * have no control over them and their lock dependencies.So the only workable 523 * solution is to avoid taking other locks under the MES lock. 524 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 525 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 526 */ 527 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 528 { 529 mutex_lock(&mes->mutex_hidden); 530 mes->saved_flags = memalloc_noreclaim_save(); 531 } 532 533 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 534 { 535 memalloc_noreclaim_restore(mes->saved_flags); 536 mutex_unlock(&mes->mutex_hidden); 537 } 538 539 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 540 541 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 542 543 #endif /* __AMDGPU_MES_H__ */ 544