1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_PIPE_0 = 0, 62 AMDGPU_MES_PIPE_1, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 69 #define AMDGPU_MAX_MES_INST_PIPES \ 70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 72 #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 74 75 struct amdgpu_mes { 76 struct amdgpu_device *adev; 77 78 struct mutex mutex_hidden; 79 80 struct ida doorbell_ida; 81 82 spinlock_t queue_id_lock; 83 84 uint32_t sched_version; 85 uint32_t kiq_version; 86 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 87 bool enable_legacy_queue_map; 88 89 uint32_t total_max_queue; 90 uint32_t max_doorbell_slices; 91 92 uint64_t default_process_quantum; 93 uint64_t default_gang_quantum; 94 95 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 96 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 97 98 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 99 100 /* mes ucode */ 101 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 102 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 103 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 104 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 105 106 /* mes ucode data */ 107 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 108 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 109 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 110 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 111 112 /* eop gpu obj */ 113 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 114 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 115 116 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 117 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 118 119 uint32_t vmid_mask_gfxhub; 120 uint32_t vmid_mask_mmhub; 121 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 122 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 123 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 124 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 125 126 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 127 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 128 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 129 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 130 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 132 133 uint32_t saved_flags; 134 135 /* initialize kiq pipe */ 136 int (*kiq_hw_init)(struct amdgpu_device *adev, 137 uint32_t xcc_id); 138 int (*kiq_hw_fini)(struct amdgpu_device *adev, 139 uint32_t xcc_id); 140 141 /* MES doorbells */ 142 uint32_t db_start_dw_offset; 143 uint32_t num_mes_dbs; 144 unsigned long *doorbell_bitmap; 145 146 /* MES event log buffer */ 147 uint32_t event_log_size; 148 struct amdgpu_bo *event_log_gpu_obj; 149 uint64_t event_log_gpu_addr; 150 void *event_log_cpu_addr; 151 152 /* ip specific functions */ 153 const struct amdgpu_mes_funcs *funcs; 154 155 /* mes resource_1 bo*/ 156 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 157 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 158 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 159 160 int hung_queue_db_array_size; 161 int hung_queue_hqd_info_offset; 162 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 163 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 164 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 165 166 /* cooperative dispatch */ 167 bool enable_coop_mode; 168 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 169 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 170 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 171 }; 172 173 struct amdgpu_mes_hung_queue_hqd_info { 174 union { 175 struct { 176 u32 queue_type: 3; // queue type 177 u32 pipe_index: 4; // pipe index 178 u32 queue_index: 8; // queue index 179 u32 reserved: 17; 180 }; 181 182 u32 bit0_31; 183 }; 184 }; 185 186 struct amdgpu_mes_gang { 187 int gang_id; 188 int priority; 189 int inprocess_gang_priority; 190 int global_priority_level; 191 struct list_head list; 192 struct amdgpu_mes_process *process; 193 struct amdgpu_bo *gang_ctx_bo; 194 uint64_t gang_ctx_gpu_addr; 195 void *gang_ctx_cpu_ptr; 196 uint64_t gang_quantum; 197 struct list_head queue_list; 198 }; 199 200 struct amdgpu_mes_queue { 201 struct list_head list; 202 struct amdgpu_mes_gang *gang; 203 int queue_id; 204 uint64_t doorbell_off; 205 struct amdgpu_bo *mqd_obj; 206 void *mqd_cpu_ptr; 207 uint64_t mqd_gpu_addr; 208 uint64_t wptr_gpu_addr; 209 int queue_type; 210 int paging; 211 struct amdgpu_ring *ring; 212 }; 213 214 struct amdgpu_mes_queue_properties { 215 int queue_type; 216 uint64_t hqd_base_gpu_addr; 217 uint64_t rptr_gpu_addr; 218 uint64_t wptr_gpu_addr; 219 uint64_t wptr_mc_addr; 220 uint32_t queue_size; 221 uint64_t eop_gpu_addr; 222 uint32_t hqd_pipe_priority; 223 uint32_t hqd_queue_priority; 224 bool paging; 225 struct amdgpu_ring *ring; 226 /* out */ 227 uint64_t doorbell_off; 228 }; 229 230 struct amdgpu_mes_gang_properties { 231 uint32_t priority; 232 uint32_t gang_quantum; 233 uint32_t inprocess_gang_priority; 234 uint32_t priority_level; 235 int global_priority_level; 236 }; 237 238 struct mes_add_queue_input { 239 uint32_t xcc_id; 240 uint32_t process_id; 241 uint64_t page_table_base_addr; 242 uint64_t process_va_start; 243 uint64_t process_va_end; 244 uint64_t process_quantum; 245 uint64_t process_context_addr; 246 uint64_t gang_quantum; 247 uint64_t gang_context_addr; 248 uint32_t inprocess_gang_priority; 249 uint32_t gang_global_priority_level; 250 uint32_t doorbell_offset; 251 uint64_t mqd_addr; 252 uint64_t wptr_addr; 253 uint64_t wptr_mc_addr; 254 uint32_t queue_type; 255 uint32_t paging; 256 uint32_t gws_base; 257 uint32_t gws_size; 258 uint64_t tba_addr; 259 uint64_t tma_addr; 260 uint32_t trap_en; 261 uint32_t skip_process_ctx_clear; 262 uint32_t is_kfd_process; 263 uint32_t is_aql_queue; 264 uint32_t queue_size; 265 uint32_t exclusively_scheduled; 266 uint32_t sh_mem_config_data; 267 uint32_t vm_cntx_cntl; 268 }; 269 270 struct mes_remove_queue_input { 271 uint32_t xcc_id; 272 uint32_t doorbell_offset; 273 uint64_t gang_context_addr; 274 bool remove_queue_after_reset; 275 }; 276 277 struct mes_map_legacy_queue_input { 278 uint32_t xcc_id; 279 uint32_t queue_type; 280 uint32_t doorbell_offset; 281 uint32_t pipe_id; 282 uint32_t queue_id; 283 uint64_t mqd_addr; 284 uint64_t wptr_addr; 285 }; 286 287 struct mes_unmap_legacy_queue_input { 288 uint32_t xcc_id; 289 enum amdgpu_unmap_queues_action action; 290 uint32_t queue_type; 291 uint32_t doorbell_offset; 292 uint32_t pipe_id; 293 uint32_t queue_id; 294 uint64_t trail_fence_addr; 295 uint64_t trail_fence_data; 296 }; 297 298 struct mes_suspend_gang_input { 299 uint32_t xcc_id; 300 bool suspend_all_gangs; 301 uint64_t gang_context_addr; 302 uint64_t suspend_fence_addr; 303 uint32_t suspend_fence_value; 304 }; 305 306 struct mes_resume_gang_input { 307 uint32_t xcc_id; 308 bool resume_all_gangs; 309 uint64_t gang_context_addr; 310 }; 311 312 struct mes_reset_queue_input { 313 uint32_t xcc_id; 314 uint32_t queue_type; 315 uint32_t doorbell_offset; 316 bool use_mmio; 317 uint32_t me_id; 318 uint32_t pipe_id; 319 uint32_t queue_id; 320 uint64_t mqd_addr; 321 uint64_t wptr_addr; 322 uint32_t vmid; 323 bool legacy_gfx; 324 bool is_kq; 325 }; 326 327 struct mes_detect_and_reset_queue_input { 328 uint32_t queue_type; 329 bool detect_only; 330 }; 331 332 struct mes_inv_tlbs_pasid_input { 333 uint32_t xcc_id; 334 uint16_t pasid; 335 uint8_t hub_id; 336 uint8_t flush_type; 337 }; 338 339 enum mes_misc_opcode { 340 MES_MISC_OP_WRITE_REG, 341 MES_MISC_OP_READ_REG, 342 MES_MISC_OP_WRM_REG_WAIT, 343 MES_MISC_OP_WRM_REG_WR_WAIT, 344 MES_MISC_OP_SET_SHADER_DEBUGGER, 345 MES_MISC_OP_CHANGE_CONFIG, 346 }; 347 348 struct mes_misc_op_input { 349 uint32_t xcc_id; 350 enum mes_misc_opcode op; 351 352 union { 353 struct { 354 uint32_t reg_offset; 355 uint64_t buffer_addr; 356 } read_reg; 357 358 struct { 359 uint32_t reg_offset; 360 uint32_t reg_value; 361 } write_reg; 362 363 struct { 364 uint32_t ref; 365 uint32_t mask; 366 uint32_t reg0; 367 uint32_t reg1; 368 } wrm_reg; 369 370 struct { 371 uint64_t process_context_addr; 372 union { 373 struct { 374 uint32_t single_memop : 1; 375 uint32_t single_alu_op : 1; 376 uint32_t reserved: 29; 377 uint32_t process_ctx_flush: 1; 378 }; 379 uint32_t u32all; 380 } flags; 381 uint32_t spi_gdbg_per_vmid_cntl; 382 uint32_t tcp_watch_cntl[4]; 383 uint32_t trap_en; 384 } set_shader_debugger; 385 386 struct { 387 union { 388 struct { 389 uint32_t limit_single_process : 1; 390 uint32_t enable_hws_logging_buffer : 1; 391 uint32_t reserved : 30; 392 }; 393 uint32_t all; 394 } option; 395 struct { 396 uint32_t tdr_level; 397 uint32_t tdr_delay; 398 } tdr_config; 399 } change_config; 400 }; 401 }; 402 403 struct amdgpu_mes_funcs { 404 int (*add_hw_queue)(struct amdgpu_mes *mes, 405 struct mes_add_queue_input *input); 406 407 int (*remove_hw_queue)(struct amdgpu_mes *mes, 408 struct mes_remove_queue_input *input); 409 410 int (*map_legacy_queue)(struct amdgpu_mes *mes, 411 struct mes_map_legacy_queue_input *input); 412 413 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 414 struct mes_unmap_legacy_queue_input *input); 415 416 int (*suspend_gang)(struct amdgpu_mes *mes, 417 struct mes_suspend_gang_input *input); 418 419 int (*resume_gang)(struct amdgpu_mes *mes, 420 struct mes_resume_gang_input *input); 421 422 int (*misc_op)(struct amdgpu_mes *mes, 423 struct mes_misc_op_input *input); 424 425 int (*reset_hw_queue)(struct amdgpu_mes *mes, 426 struct mes_reset_queue_input *input); 427 428 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 429 struct mes_detect_and_reset_queue_input *input); 430 431 432 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 433 struct mes_inv_tlbs_pasid_input *input); 434 }; 435 436 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 437 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 438 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 439 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 440 441 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 442 int amdgpu_mes_init(struct amdgpu_device *adev); 443 void amdgpu_mes_fini(struct amdgpu_device *adev); 444 445 int amdgpu_mes_suspend(struct amdgpu_device *adev); 446 int amdgpu_mes_resume(struct amdgpu_device *adev); 447 448 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 449 struct amdgpu_ring *ring, uint32_t xcc_id); 450 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 451 struct amdgpu_ring *ring, 452 enum amdgpu_unmap_queues_action action, 453 u64 gpu_addr, u64 seq, uint32_t xcc_id); 454 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 455 struct amdgpu_ring *ring, 456 unsigned int vmid, 457 bool use_mmio, 458 uint32_t xcc_id); 459 460 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 461 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 462 int queue_type, 463 bool detect_only, 464 unsigned int *hung_db_num, 465 u32 *hung_db_array, 466 uint32_t xcc_id); 467 468 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 469 uint32_t xcc_id); 470 int amdgpu_mes_wreg(struct amdgpu_device *adev, 471 uint32_t reg, uint32_t val, uint32_t xcc_id); 472 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 473 uint32_t reg0, uint32_t reg1, 474 uint32_t ref, uint32_t mask, uint32_t xcc_id); 475 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 476 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 477 uint64_t process_context_addr, 478 uint32_t spi_gdbg_per_vmid_cntl, 479 const uint32_t *tcp_watch_cntl, 480 uint32_t flags, 481 bool trap_en, 482 uint32_t xcc_id); 483 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 484 uint64_t process_context_addr, uint32_t xcc_id); 485 486 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 487 enum amdgpu_mes_priority_level prio); 488 489 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 490 491 /* 492 * MES lock can be taken in MMU notifiers. 493 * 494 * A bit more detail about why to set no-FS reclaim with MES lock: 495 * 496 * The purpose of the MMU notifier is to stop GPU access to memory so 497 * that the Linux VM subsystem can move pages around safely. This is 498 * done by preempting user mode queues for the affected process. When 499 * MES is used, MES lock needs to be taken to preempt the queues. 500 * 501 * The MMU notifier callback entry point in the driver is 502 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 503 * there is: 504 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 505 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 506 * 507 * The last part of the chain is a function pointer where we take the 508 * MES lock. 509 * 510 * The problem with taking locks in the MMU notifier is, that MMU 511 * notifiers can be called in reclaim-FS context. That's where the 512 * kernel frees up pages to make room for new page allocations under 513 * memory pressure. While we are running in reclaim-FS context, we must 514 * not trigger another memory reclaim operation because that would 515 * recursively reenter the reclaim code and cause a deadlock. The 516 * memalloc_nofs_save/restore calls guarantee that. 517 * 518 * In addition we also need to avoid lock dependencies on other locks taken 519 * under the MES lock, for example reservation locks. Here is a possible 520 * scenario of a deadlock: 521 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 522 * MMU notifier | blocks trying to take MES lock 523 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 524 * 525 * In this scenario Thread B gets involved in a deadlock even without 526 * triggering a reclaim-FS operation itself. 527 * To fix this and break the lock dependency chain you'd need to either: 528 * 1. protect reservation locks with memalloc_nofs_save/restore, or 529 * 2. avoid taking reservation locks under the MES lock. 530 * 531 * Reservation locks are taken all over the kernel in different subsystems, we 532 * have no control over them and their lock dependencies.So the only workable 533 * solution is to avoid taking other locks under the MES lock. 534 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 535 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 536 */ 537 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 538 { 539 mutex_lock(&mes->mutex_hidden); 540 mes->saved_flags = memalloc_noreclaim_save(); 541 } 542 543 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 544 { 545 memalloc_noreclaim_restore(mes->saved_flags); 546 mutex_unlock(&mes->mutex_hidden); 547 } 548 549 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 550 551 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 552 553 #endif /* __AMDGPU_MES_H__ */ 554