1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 #define AMDGPU_MES_PROC_CTX_ARRAY_MAX 128 58 #define AMDGPU_MES_GANG_CTX_ARRAY_MAX 512 59 struct amdgpu_mes_funcs; 60 61 enum amdgpu_mes_pipe { 62 AMDGPU_MES_PIPE_0 = 0, 63 AMDGPU_MES_PIPE_1, 64 AMDGPU_MAX_MES_PIPES = 2, 65 }; 66 67 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 68 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 69 70 #define AMDGPU_MAX_MES_INST_PIPES \ 71 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 72 73 #define MES_PIPE_INST(xcc_id, pipe_id) \ 74 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 75 76 struct amdgpu_mes { 77 struct amdgpu_device *adev; 78 79 struct mutex mutex_hidden; 80 81 struct ida doorbell_ida; 82 83 spinlock_t queue_id_lock; 84 85 uint32_t sched_version; 86 uint32_t kiq_version; 87 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 88 bool enable_legacy_queue_map; 89 90 uint32_t total_max_queue; 91 uint32_t max_doorbell_slices; 92 93 uint64_t default_process_quantum; 94 uint64_t default_gang_quantum; 95 96 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 97 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 98 99 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 100 101 /* mes ucode */ 102 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 103 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 104 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 105 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 106 107 /* mes ucode data */ 108 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 109 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 110 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 111 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 112 113 /* eop gpu obj */ 114 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 115 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 116 117 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 118 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 119 120 uint32_t vmid_mask_gfxhub; 121 uint32_t vmid_mask_mmhub; 122 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 123 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 124 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 125 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 126 127 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 128 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 129 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 130 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 132 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 133 134 uint32_t saved_flags; 135 136 /* initialize kiq pipe */ 137 int (*kiq_hw_init)(struct amdgpu_device *adev, 138 uint32_t xcc_id); 139 int (*kiq_hw_fini)(struct amdgpu_device *adev, 140 uint32_t xcc_id); 141 142 /* MES doorbells */ 143 uint32_t db_start_dw_offset; 144 uint32_t num_mes_dbs; 145 unsigned long *doorbell_bitmap; 146 147 /* MES event log buffer */ 148 uint32_t event_log_size; 149 struct amdgpu_bo *event_log_gpu_obj; 150 uint64_t event_log_gpu_addr; 151 void *event_log_cpu_addr; 152 153 /* ip specific functions */ 154 const struct amdgpu_mes_funcs *funcs; 155 156 /* mes resource_1 bo*/ 157 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 158 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 159 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 160 161 int hung_queue_db_array_size; 162 int hung_queue_hqd_info_offset; 163 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 164 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 165 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 166 167 /* cooperative dispatch */ 168 bool enable_coop_mode; 169 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 170 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 171 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 172 173 bool compute_pipe_reset_enabled; 174 bool gfx_pipe_reset_enabled; 175 176 bool use_rs64mem; 177 struct amdgpu_bo *ctx_array_size_bo; 178 uint64_t ctx_array_size_gpu_addr; 179 uint32_t *ctx_array_size_cpu_ptr; 180 181 uint32_t proc_ctx_array_size; 182 unsigned long *proc_ctx_bitmap; 183 uint32_t gang_ctx_array_size; 184 unsigned long *gang_ctx_bitmap; 185 }; 186 187 struct amdgpu_mes_hung_queue_hqd_info { 188 union { 189 struct { 190 u32 queue_type: 3; // queue type 191 u32 pipe_index: 4; // pipe index 192 u32 queue_index: 8; // queue index 193 u32 reserved: 17; 194 }; 195 196 u32 bit0_31; 197 }; 198 }; 199 200 struct amdgpu_mes_gang { 201 int gang_id; 202 int priority; 203 int inprocess_gang_priority; 204 int global_priority_level; 205 struct list_head list; 206 struct amdgpu_mes_process *process; 207 struct amdgpu_bo *gang_ctx_bo; 208 uint64_t gang_ctx_gpu_addr; 209 void *gang_ctx_cpu_ptr; 210 uint64_t gang_quantum; 211 struct list_head queue_list; 212 }; 213 214 struct amdgpu_mes_queue { 215 struct list_head list; 216 struct amdgpu_mes_gang *gang; 217 int queue_id; 218 uint64_t doorbell_off; 219 struct amdgpu_bo *mqd_obj; 220 void *mqd_cpu_ptr; 221 uint64_t mqd_gpu_addr; 222 uint64_t wptr_gpu_addr; 223 int queue_type; 224 int paging; 225 struct amdgpu_ring *ring; 226 }; 227 228 struct amdgpu_mes_queue_properties { 229 int queue_type; 230 uint64_t hqd_base_gpu_addr; 231 uint64_t rptr_gpu_addr; 232 uint64_t wptr_gpu_addr; 233 uint64_t wptr_mc_addr; 234 uint32_t queue_size; 235 uint64_t eop_gpu_addr; 236 uint32_t hqd_pipe_priority; 237 uint32_t hqd_queue_priority; 238 bool paging; 239 struct amdgpu_ring *ring; 240 /* out */ 241 uint64_t doorbell_off; 242 }; 243 244 struct amdgpu_mes_gang_properties { 245 uint32_t priority; 246 uint32_t gang_quantum; 247 uint32_t inprocess_gang_priority; 248 uint32_t priority_level; 249 int global_priority_level; 250 }; 251 252 struct mes_add_queue_input { 253 uint32_t xcc_id; 254 uint32_t process_id; 255 uint64_t page_table_base_addr; 256 uint64_t process_va_start; 257 uint64_t process_va_end; 258 uint64_t process_quantum; 259 uint64_t process_context_addr; 260 uint64_t gang_quantum; 261 uint64_t gang_context_addr; 262 uint32_t inprocess_gang_priority; 263 uint32_t gang_global_priority_level; 264 uint32_t doorbell_offset; 265 uint64_t mqd_addr; 266 uint64_t wptr_addr; 267 uint64_t wptr_mc_addr; 268 uint32_t queue_type; 269 uint32_t paging; 270 uint32_t gws_base; 271 uint32_t gws_size; 272 uint64_t tba_addr; 273 uint64_t tma_addr; 274 uint32_t trap_en; 275 uint32_t skip_process_ctx_clear; 276 uint32_t is_kfd_process; 277 uint32_t is_aql_queue; 278 uint32_t queue_size; 279 uint32_t exclusively_scheduled; 280 uint32_t sh_mem_config_data; 281 uint32_t vm_cntx_cntl; 282 uint32_t process_context_array_index; 283 }; 284 285 struct mes_remove_queue_input { 286 uint32_t xcc_id; 287 uint32_t doorbell_offset; 288 uint64_t gang_context_addr; 289 uint32_t queue_type; 290 bool remove_queue_after_reset; 291 }; 292 293 struct mes_map_legacy_queue_input { 294 uint32_t xcc_id; 295 uint32_t queue_type; 296 uint32_t doorbell_offset; 297 uint32_t pipe_id; 298 uint32_t queue_id; 299 uint64_t mqd_addr; 300 uint64_t wptr_addr; 301 }; 302 303 struct mes_unmap_legacy_queue_input { 304 uint32_t xcc_id; 305 enum amdgpu_unmap_queues_action action; 306 uint32_t queue_type; 307 uint32_t doorbell_offset; 308 uint32_t pipe_id; 309 uint32_t queue_id; 310 uint64_t trail_fence_addr; 311 uint64_t trail_fence_data; 312 }; 313 314 struct mes_suspend_gang_input { 315 uint32_t xcc_id; 316 bool suspend_all_gangs; 317 bool suspend_all_sdma_gangs; 318 uint64_t gang_context_addr; 319 uint64_t suspend_fence_addr; 320 uint32_t suspend_fence_value; 321 uint32_t doorbell_offset; 322 }; 323 324 struct mes_resume_gang_input { 325 uint32_t xcc_id; 326 bool resume_all_gangs; 327 uint64_t gang_context_addr; 328 uint32_t doorbell_offset; 329 }; 330 331 struct mes_reset_queue_input { 332 uint32_t xcc_id; 333 uint32_t queue_type; 334 uint32_t doorbell_offset; 335 bool use_mmio; 336 uint32_t me_id; 337 uint32_t pipe_id; 338 uint32_t queue_id; 339 uint64_t mqd_addr; 340 uint64_t wptr_addr; 341 uint32_t vmid; 342 bool legacy_gfx; 343 bool is_kq; 344 }; 345 346 struct mes_detect_and_reset_queue_input { 347 u32 queue_type; 348 bool detect_only; 349 u32 xcc_id; 350 }; 351 352 struct mes_inv_tlbs_pasid_input { 353 uint32_t xcc_id; 354 uint16_t pasid; 355 uint8_t hub_id; 356 uint8_t flush_type; 357 }; 358 359 enum mes_misc_opcode { 360 MES_MISC_OP_WRITE_REG, 361 MES_MISC_OP_READ_REG, 362 MES_MISC_OP_WRM_REG_WAIT, 363 MES_MISC_OP_WRM_REG_WR_WAIT, 364 MES_MISC_OP_SET_SHADER_DEBUGGER, 365 MES_MISC_OP_CHANGE_CONFIG, 366 }; 367 368 struct mes_misc_op_input { 369 uint32_t xcc_id; 370 enum mes_misc_opcode op; 371 372 union { 373 struct { 374 uint32_t reg_offset; 375 uint64_t buffer_addr; 376 } read_reg; 377 378 struct { 379 uint32_t reg_offset; 380 uint32_t reg_value; 381 } write_reg; 382 383 struct { 384 uint32_t ref; 385 uint32_t mask; 386 uint32_t reg0; 387 uint32_t reg1; 388 } wrm_reg; 389 390 struct { 391 uint64_t process_context_addr; 392 union { 393 struct { 394 uint32_t single_memop : 1; 395 uint32_t single_alu_op : 1; 396 uint32_t reserved: 29; 397 uint32_t process_ctx_flush: 1; 398 }; 399 uint32_t u32all; 400 } flags; 401 uint32_t spi_gdbg_per_vmid_cntl; 402 uint32_t tcp_watch_cntl[4]; 403 uint32_t trap_en; 404 } set_shader_debugger; 405 406 struct { 407 union { 408 struct { 409 uint32_t limit_single_process : 1; 410 uint32_t enable_hws_logging_buffer : 1; 411 uint32_t reserved : 30; 412 }; 413 uint32_t all; 414 } option; 415 struct { 416 uint32_t tdr_level; 417 uint32_t tdr_delay; 418 } tdr_config; 419 } change_config; 420 }; 421 }; 422 423 struct amdgpu_mes_funcs { 424 int (*add_hw_queue)(struct amdgpu_mes *mes, 425 struct mes_add_queue_input *input); 426 427 int (*remove_hw_queue)(struct amdgpu_mes *mes, 428 struct mes_remove_queue_input *input); 429 430 int (*map_legacy_queue)(struct amdgpu_mes *mes, 431 struct mes_map_legacy_queue_input *input); 432 433 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 434 struct mes_unmap_legacy_queue_input *input); 435 436 int (*suspend_gang)(struct amdgpu_mes *mes, 437 struct mes_suspend_gang_input *input); 438 439 int (*resume_gang)(struct amdgpu_mes *mes, 440 struct mes_resume_gang_input *input); 441 442 int (*misc_op)(struct amdgpu_mes *mes, 443 struct mes_misc_op_input *input); 444 445 int (*reset_hw_queue)(struct amdgpu_mes *mes, 446 struct mes_reset_queue_input *input); 447 448 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 449 struct mes_detect_and_reset_queue_input *input); 450 451 452 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 453 struct mes_inv_tlbs_pasid_input *input); 454 }; 455 456 enum amdgpu_mqd_update_flag { 457 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 458 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 459 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 460 }; 461 462 struct amdgpu_mqd_prop { 463 uint64_t mqd_gpu_addr; 464 uint64_t hqd_base_gpu_addr; 465 uint64_t rptr_gpu_addr; 466 uint64_t wptr_gpu_addr; 467 uint32_t queue_size; 468 bool use_doorbell; 469 uint32_t doorbell_index; 470 uint64_t eop_gpu_addr; 471 uint32_t hqd_pipe_priority; 472 uint32_t hqd_queue_priority; 473 uint32_t mqd_stride_size; 474 bool allow_tunneling; 475 bool hqd_active; 476 uint64_t shadow_addr; 477 uint64_t gds_bkup_addr; 478 uint64_t csa_addr; 479 uint64_t fence_address; 480 bool tmz_queue; 481 bool kernel_queue; 482 uint32_t *cu_mask; 483 uint32_t cu_mask_count; 484 uint32_t cu_flags; 485 bool is_user_cu_masked; 486 }; 487 488 struct amdgpu_mqd { 489 unsigned mqd_size; 490 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 491 struct amdgpu_mqd_prop *p); 492 }; 493 494 /* 495 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 496 * as fence address and writes a 32 bit fence value to this address. 497 * Driver needs to allocate at least 4 DWs extra memory in addition to 498 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 499 */ 500 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 501 502 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 503 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 504 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 505 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 506 507 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 508 void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev); 509 int amdgpu_mes_init(struct amdgpu_device *adev); 510 void amdgpu_mes_fini(struct amdgpu_device *adev); 511 512 int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); 513 int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); 514 515 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 516 struct amdgpu_ring *ring, uint32_t xcc_id); 517 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 518 struct amdgpu_ring *ring, 519 enum amdgpu_unmap_queues_action action, 520 u64 gpu_addr, u64 seq, uint32_t xcc_id); 521 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 522 struct amdgpu_ring *ring, 523 unsigned int vmid, 524 bool use_mmio, 525 uint32_t xcc_id); 526 int amdgpu_mes_reset_queue_mmio(struct amdgpu_device *adev, 527 int queue_type, 528 unsigned int vmid, 529 unsigned int me, 530 unsigned int pipe, 531 unsigned int queue, 532 uint32_t xcc_id); 533 int amdgpu_mes_reset_user_queue(struct amdgpu_device *adev, 534 int queue_type, 535 unsigned int doorbell_index, 536 unsigned int xcc_id); 537 538 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 539 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 540 int queue_type, 541 bool detect_only, 542 unsigned int *hung_db_num, 543 u32 *hung_db_array, 544 uint32_t xcc_id); 545 546 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 547 uint32_t xcc_id); 548 int amdgpu_mes_wreg(struct amdgpu_device *adev, 549 uint32_t reg, uint32_t val, uint32_t xcc_id); 550 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 551 uint32_t reg0, uint32_t reg1, 552 uint32_t ref, uint32_t mask, uint32_t xcc_id); 553 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 554 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 555 uint64_t process_context_addr, 556 uint32_t spi_gdbg_per_vmid_cntl, 557 const uint32_t *tcp_watch_cntl, 558 uint32_t flags, 559 bool trap_en, 560 uint32_t xcc_id); 561 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 562 uint64_t process_context_addr, uint32_t xcc_id); 563 564 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 565 enum amdgpu_mes_priority_level prio); 566 567 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 568 569 /* 570 * MES lock can be taken in MMU notifiers. 571 * 572 * A bit more detail about why to set no-FS reclaim with MES lock: 573 * 574 * The purpose of the MMU notifier is to stop GPU access to memory so 575 * that the Linux VM subsystem can move pages around safely. This is 576 * done by preempting user mode queues for the affected process. When 577 * MES is used, MES lock needs to be taken to preempt the queues. 578 * 579 * The MMU notifier callback entry point in the driver is 580 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 581 * there is: 582 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 583 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 584 * 585 * The last part of the chain is a function pointer where we take the 586 * MES lock. 587 * 588 * The problem with taking locks in the MMU notifier is, that MMU 589 * notifiers can be called in reclaim-FS context. That's where the 590 * kernel frees up pages to make room for new page allocations under 591 * memory pressure. While we are running in reclaim-FS context, we must 592 * not trigger another memory reclaim operation because that would 593 * recursively reenter the reclaim code and cause a deadlock. The 594 * memalloc_nofs_save/restore calls guarantee that. 595 * 596 * In addition we also need to avoid lock dependencies on other locks taken 597 * under the MES lock, for example reservation locks. Here is a possible 598 * scenario of a deadlock: 599 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 600 * MMU notifier | blocks trying to take MES lock 601 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 602 * 603 * In this scenario Thread B gets involved in a deadlock even without 604 * triggering a reclaim-FS operation itself. 605 * To fix this and break the lock dependency chain you'd need to either: 606 * 1. protect reservation locks with memalloc_nofs_save/restore, or 607 * 2. avoid taking reservation locks under the MES lock. 608 * 609 * Reservation locks are taken all over the kernel in different subsystems, we 610 * have no control over them and their lock dependencies.So the only workable 611 * solution is to avoid taking other locks under the MES lock. 612 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 613 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 614 */ 615 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 616 { 617 mutex_lock(&mes->mutex_hidden); 618 mes->saved_flags = memalloc_noreclaim_save(); 619 } 620 621 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 622 { 623 memalloc_noreclaim_restore(mes->saved_flags); 624 mutex_unlock(&mes->mutex_hidden); 625 } 626 627 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 628 bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); 629 630 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 631 632 int amdgpu_mes_rs64mem_init(struct amdgpu_mes *mes); 633 void amdgpu_mes_rs64mem_fini(struct amdgpu_mes *mes); 634 int amdgpu_mes_rs64mem_setup_bitmaps(struct amdgpu_mes *mes); 635 int amdgpu_mes_alloc_proc_ctx_index(struct amdgpu_mes *mes, 636 struct amdgpu_usermode_queue *queue); 637 void amdgpu_mes_free_proc_ctx_index(struct amdgpu_mes *mes, 638 struct amdgpu_usermode_queue *queue); 639 #endif /* __AMDGPU_MES_H__ */ 640