1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44 enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51 }; 52 53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 56 struct amdgpu_mes_funcs; 57 58 enum admgpu_mes_pipe { 59 AMDGPU_MES_SCHED_PIPE = 0, 60 AMDGPU_MES_KIQ_PIPE, 61 AMDGPU_MAX_MES_PIPES = 2, 62 }; 63 64 struct amdgpu_mes { 65 struct amdgpu_device *adev; 66 67 struct mutex mutex_hidden; 68 69 struct idr pasid_idr; 70 struct idr gang_id_idr; 71 struct idr queue_id_idr; 72 struct ida doorbell_ida; 73 74 spinlock_t queue_id_lock; 75 76 uint32_t sched_version; 77 uint32_t kiq_version; 78 79 uint32_t total_max_queue; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring; 86 spinlock_t ring_lock; 87 88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 89 90 /* mes ucode */ 91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 94 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 95 96 /* mes ucode data */ 97 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 98 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 99 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 100 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 101 102 /* eop gpu obj */ 103 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 104 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 105 106 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 107 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 108 109 uint32_t vmid_mask_gfxhub; 110 uint32_t vmid_mask_mmhub; 111 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 112 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 113 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 114 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 115 uint32_t sch_ctx_offs; 116 uint64_t sch_ctx_gpu_addr; 117 uint64_t *sch_ctx_ptr; 118 uint32_t query_status_fence_offs; 119 uint64_t query_status_fence_gpu_addr; 120 uint64_t *query_status_fence_ptr; 121 uint32_t read_val_offs; 122 uint64_t read_val_gpu_addr; 123 uint32_t *read_val_ptr; 124 125 uint32_t saved_flags; 126 127 /* initialize kiq pipe */ 128 int (*kiq_hw_init)(struct amdgpu_device *adev); 129 int (*kiq_hw_fini)(struct amdgpu_device *adev); 130 131 /* MES doorbells */ 132 uint32_t db_start_dw_offset; 133 uint32_t num_mes_dbs; 134 unsigned long *doorbell_bitmap; 135 136 /* MES event log buffer */ 137 struct amdgpu_bo *event_log_gpu_obj; 138 uint64_t event_log_gpu_addr; 139 void *event_log_cpu_addr; 140 141 /* ip specific functions */ 142 const struct amdgpu_mes_funcs *funcs; 143 }; 144 145 struct amdgpu_mes_process { 146 int pasid; 147 struct amdgpu_vm *vm; 148 uint64_t pd_gpu_addr; 149 struct amdgpu_bo *proc_ctx_bo; 150 uint64_t proc_ctx_gpu_addr; 151 void *proc_ctx_cpu_ptr; 152 uint64_t process_quantum; 153 struct list_head gang_list; 154 uint32_t doorbell_index; 155 struct mutex doorbell_lock; 156 }; 157 158 struct amdgpu_mes_gang { 159 int gang_id; 160 int priority; 161 int inprocess_gang_priority; 162 int global_priority_level; 163 struct list_head list; 164 struct amdgpu_mes_process *process; 165 struct amdgpu_bo *gang_ctx_bo; 166 uint64_t gang_ctx_gpu_addr; 167 void *gang_ctx_cpu_ptr; 168 uint64_t gang_quantum; 169 struct list_head queue_list; 170 }; 171 172 struct amdgpu_mes_queue { 173 struct list_head list; 174 struct amdgpu_mes_gang *gang; 175 int queue_id; 176 uint64_t doorbell_off; 177 struct amdgpu_bo *mqd_obj; 178 void *mqd_cpu_ptr; 179 uint64_t mqd_gpu_addr; 180 uint64_t wptr_gpu_addr; 181 int queue_type; 182 int paging; 183 struct amdgpu_ring *ring; 184 }; 185 186 struct amdgpu_mes_queue_properties { 187 int queue_type; 188 uint64_t hqd_base_gpu_addr; 189 uint64_t rptr_gpu_addr; 190 uint64_t wptr_gpu_addr; 191 uint64_t wptr_mc_addr; 192 uint32_t queue_size; 193 uint64_t eop_gpu_addr; 194 uint32_t hqd_pipe_priority; 195 uint32_t hqd_queue_priority; 196 bool paging; 197 struct amdgpu_ring *ring; 198 /* out */ 199 uint64_t doorbell_off; 200 }; 201 202 struct amdgpu_mes_gang_properties { 203 uint32_t priority; 204 uint32_t gang_quantum; 205 uint32_t inprocess_gang_priority; 206 uint32_t priority_level; 207 int global_priority_level; 208 }; 209 210 struct mes_add_queue_input { 211 uint32_t process_id; 212 uint64_t page_table_base_addr; 213 uint64_t process_va_start; 214 uint64_t process_va_end; 215 uint64_t process_quantum; 216 uint64_t process_context_addr; 217 uint64_t gang_quantum; 218 uint64_t gang_context_addr; 219 uint32_t inprocess_gang_priority; 220 uint32_t gang_global_priority_level; 221 uint32_t doorbell_offset; 222 uint64_t mqd_addr; 223 uint64_t wptr_addr; 224 uint64_t wptr_mc_addr; 225 uint32_t queue_type; 226 uint32_t paging; 227 uint32_t gws_base; 228 uint32_t gws_size; 229 uint64_t tba_addr; 230 uint64_t tma_addr; 231 uint32_t trap_en; 232 uint32_t skip_process_ctx_clear; 233 uint32_t is_kfd_process; 234 uint32_t is_aql_queue; 235 uint32_t queue_size; 236 uint32_t exclusively_scheduled; 237 }; 238 239 struct mes_remove_queue_input { 240 uint32_t doorbell_offset; 241 uint64_t gang_context_addr; 242 }; 243 244 struct mes_unmap_legacy_queue_input { 245 enum amdgpu_unmap_queues_action action; 246 uint32_t queue_type; 247 uint32_t doorbell_offset; 248 uint32_t pipe_id; 249 uint32_t queue_id; 250 uint64_t trail_fence_addr; 251 uint64_t trail_fence_data; 252 }; 253 254 struct mes_suspend_gang_input { 255 bool suspend_all_gangs; 256 uint64_t gang_context_addr; 257 uint64_t suspend_fence_addr; 258 uint32_t suspend_fence_value; 259 }; 260 261 struct mes_resume_gang_input { 262 bool resume_all_gangs; 263 uint64_t gang_context_addr; 264 }; 265 266 enum mes_misc_opcode { 267 MES_MISC_OP_WRITE_REG, 268 MES_MISC_OP_READ_REG, 269 MES_MISC_OP_WRM_REG_WAIT, 270 MES_MISC_OP_WRM_REG_WR_WAIT, 271 MES_MISC_OP_SET_SHADER_DEBUGGER, 272 }; 273 274 struct mes_misc_op_input { 275 enum mes_misc_opcode op; 276 277 union { 278 struct { 279 uint32_t reg_offset; 280 uint64_t buffer_addr; 281 } read_reg; 282 283 struct { 284 uint32_t reg_offset; 285 uint32_t reg_value; 286 } write_reg; 287 288 struct { 289 uint32_t ref; 290 uint32_t mask; 291 uint32_t reg0; 292 uint32_t reg1; 293 } wrm_reg; 294 295 struct { 296 uint64_t process_context_addr; 297 union { 298 struct { 299 uint32_t single_memop : 1; 300 uint32_t single_alu_op : 1; 301 uint32_t reserved: 29; 302 uint32_t process_ctx_flush: 1; 303 }; 304 uint32_t u32all; 305 } flags; 306 uint32_t spi_gdbg_per_vmid_cntl; 307 uint32_t tcp_watch_cntl[4]; 308 uint32_t trap_en; 309 } set_shader_debugger; 310 }; 311 }; 312 313 struct amdgpu_mes_funcs { 314 int (*add_hw_queue)(struct amdgpu_mes *mes, 315 struct mes_add_queue_input *input); 316 317 int (*remove_hw_queue)(struct amdgpu_mes *mes, 318 struct mes_remove_queue_input *input); 319 320 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 321 struct mes_unmap_legacy_queue_input *input); 322 323 int (*suspend_gang)(struct amdgpu_mes *mes, 324 struct mes_suspend_gang_input *input); 325 326 int (*resume_gang)(struct amdgpu_mes *mes, 327 struct mes_resume_gang_input *input); 328 329 int (*misc_op)(struct amdgpu_mes *mes, 330 struct mes_misc_op_input *input); 331 }; 332 333 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 334 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 335 336 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 337 338 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 339 int amdgpu_mes_init(struct amdgpu_device *adev); 340 void amdgpu_mes_fini(struct amdgpu_device *adev); 341 342 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 343 struct amdgpu_vm *vm); 344 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 345 346 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 347 struct amdgpu_mes_gang_properties *gprops, 348 int *gang_id); 349 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 350 351 int amdgpu_mes_suspend(struct amdgpu_device *adev); 352 int amdgpu_mes_resume(struct amdgpu_device *adev); 353 354 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 355 struct amdgpu_mes_queue_properties *qprops, 356 int *queue_id); 357 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 358 359 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 360 struct amdgpu_ring *ring, 361 enum amdgpu_unmap_queues_action action, 362 u64 gpu_addr, u64 seq); 363 364 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 365 int amdgpu_mes_wreg(struct amdgpu_device *adev, 366 uint32_t reg, uint32_t val); 367 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 368 uint32_t val, uint32_t mask); 369 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 370 uint32_t reg0, uint32_t reg1, 371 uint32_t ref, uint32_t mask); 372 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 373 uint64_t process_context_addr, 374 uint32_t spi_gdbg_per_vmid_cntl, 375 const uint32_t *tcp_watch_cntl, 376 uint32_t flags, 377 bool trap_en); 378 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 379 uint64_t process_context_addr); 380 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 381 int queue_type, int idx, 382 struct amdgpu_mes_ctx_data *ctx_data, 383 struct amdgpu_ring **out); 384 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 385 struct amdgpu_ring *ring); 386 387 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 388 enum amdgpu_mes_priority_level prio); 389 390 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 391 struct amdgpu_mes_ctx_data *ctx_data); 392 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 393 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 394 struct amdgpu_vm *vm, 395 struct amdgpu_mes_ctx_data *ctx_data); 396 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 397 struct amdgpu_mes_ctx_data *ctx_data); 398 399 int amdgpu_mes_self_test(struct amdgpu_device *adev); 400 401 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 402 403 /* 404 * MES lock can be taken in MMU notifiers. 405 * 406 * A bit more detail about why to set no-FS reclaim with MES lock: 407 * 408 * The purpose of the MMU notifier is to stop GPU access to memory so 409 * that the Linux VM subsystem can move pages around safely. This is 410 * done by preempting user mode queues for the affected process. When 411 * MES is used, MES lock needs to be taken to preempt the queues. 412 * 413 * The MMU notifier callback entry point in the driver is 414 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 415 * there is: 416 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 417 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 418 * 419 * The last part of the chain is a function pointer where we take the 420 * MES lock. 421 * 422 * The problem with taking locks in the MMU notifier is, that MMU 423 * notifiers can be called in reclaim-FS context. That's where the 424 * kernel frees up pages to make room for new page allocations under 425 * memory pressure. While we are running in reclaim-FS context, we must 426 * not trigger another memory reclaim operation because that would 427 * recursively reenter the reclaim code and cause a deadlock. The 428 * memalloc_nofs_save/restore calls guarantee that. 429 * 430 * In addition we also need to avoid lock dependencies on other locks taken 431 * under the MES lock, for example reservation locks. Here is a possible 432 * scenario of a deadlock: 433 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 434 * MMU notifier | blocks trying to take MES lock 435 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 436 * 437 * In this scenario Thread B gets involved in a deadlock even without 438 * triggering a reclaim-FS operation itself. 439 * To fix this and break the lock dependency chain you'd need to either: 440 * 1. protect reservation locks with memalloc_nofs_save/restore, or 441 * 2. avoid taking reservation locks under the MES lock. 442 * 443 * Reservation locks are taken all over the kernel in different subsystems, we 444 * have no control over them and their lock dependencies.So the only workable 445 * solution is to avoid taking other locks under the MES lock. 446 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 447 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 448 */ 449 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 450 { 451 mutex_lock(&mes->mutex_hidden); 452 mes->saved_flags = memalloc_noreclaim_save(); 453 } 454 455 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 456 { 457 memalloc_noreclaim_restore(mes->saved_flags); 458 mutex_unlock(&mes->mutex_hidden); 459 } 460 #endif /* __AMDGPU_MES_H__ */ 461