1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_SCHED_PIPE = 0, 62 AMDGPU_MES_KIQ_PIPE, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 struct amdgpu_mes { 67 struct amdgpu_device *adev; 68 69 struct mutex mutex_hidden; 70 71 struct idr pasid_idr; 72 struct idr gang_id_idr; 73 struct idr queue_id_idr; 74 struct ida doorbell_ida; 75 76 spinlock_t queue_id_lock; 77 78 uint32_t sched_version; 79 uint32_t kiq_version; 80 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 81 bool enable_legacy_queue_map; 82 83 uint32_t total_max_queue; 84 uint32_t max_doorbell_slices; 85 86 uint64_t default_process_quantum; 87 uint64_t default_gang_quantum; 88 89 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 90 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 91 92 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 93 94 /* mes ucode */ 95 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 96 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 97 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 98 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 99 100 /* mes ucode data */ 101 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 102 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 103 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 104 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 105 106 /* eop gpu obj */ 107 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 108 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 109 110 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 111 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 112 113 uint32_t vmid_mask_gfxhub; 114 uint32_t vmid_mask_mmhub; 115 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 116 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 117 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 118 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 119 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 120 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 121 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 122 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 123 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 124 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 125 126 uint32_t saved_flags; 127 128 /* initialize kiq pipe */ 129 int (*kiq_hw_init)(struct amdgpu_device *adev); 130 int (*kiq_hw_fini)(struct amdgpu_device *adev); 131 132 /* MES doorbells */ 133 uint32_t db_start_dw_offset; 134 uint32_t num_mes_dbs; 135 unsigned long *doorbell_bitmap; 136 137 /* MES event log buffer */ 138 uint32_t event_log_size; 139 struct amdgpu_bo *event_log_gpu_obj; 140 uint64_t event_log_gpu_addr; 141 void *event_log_cpu_addr; 142 143 /* ip specific functions */ 144 const struct amdgpu_mes_funcs *funcs; 145 146 /* mes resource_1 bo*/ 147 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 148 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 149 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 150 151 int hung_queue_db_array_size; 152 struct amdgpu_bo *hung_queue_db_array_gpu_obj; 153 uint64_t hung_queue_db_array_gpu_addr; 154 void *hung_queue_db_array_cpu_addr; 155 }; 156 157 struct amdgpu_mes_gang { 158 int gang_id; 159 int priority; 160 int inprocess_gang_priority; 161 int global_priority_level; 162 struct list_head list; 163 struct amdgpu_mes_process *process; 164 struct amdgpu_bo *gang_ctx_bo; 165 uint64_t gang_ctx_gpu_addr; 166 void *gang_ctx_cpu_ptr; 167 uint64_t gang_quantum; 168 struct list_head queue_list; 169 }; 170 171 struct amdgpu_mes_queue { 172 struct list_head list; 173 struct amdgpu_mes_gang *gang; 174 int queue_id; 175 uint64_t doorbell_off; 176 struct amdgpu_bo *mqd_obj; 177 void *mqd_cpu_ptr; 178 uint64_t mqd_gpu_addr; 179 uint64_t wptr_gpu_addr; 180 int queue_type; 181 int paging; 182 struct amdgpu_ring *ring; 183 }; 184 185 struct amdgpu_mes_queue_properties { 186 int queue_type; 187 uint64_t hqd_base_gpu_addr; 188 uint64_t rptr_gpu_addr; 189 uint64_t wptr_gpu_addr; 190 uint64_t wptr_mc_addr; 191 uint32_t queue_size; 192 uint64_t eop_gpu_addr; 193 uint32_t hqd_pipe_priority; 194 uint32_t hqd_queue_priority; 195 bool paging; 196 struct amdgpu_ring *ring; 197 /* out */ 198 uint64_t doorbell_off; 199 }; 200 201 struct amdgpu_mes_gang_properties { 202 uint32_t priority; 203 uint32_t gang_quantum; 204 uint32_t inprocess_gang_priority; 205 uint32_t priority_level; 206 int global_priority_level; 207 }; 208 209 struct mes_add_queue_input { 210 uint32_t process_id; 211 uint64_t page_table_base_addr; 212 uint64_t process_va_start; 213 uint64_t process_va_end; 214 uint64_t process_quantum; 215 uint64_t process_context_addr; 216 uint64_t gang_quantum; 217 uint64_t gang_context_addr; 218 uint32_t inprocess_gang_priority; 219 uint32_t gang_global_priority_level; 220 uint32_t doorbell_offset; 221 uint64_t mqd_addr; 222 uint64_t wptr_addr; 223 uint64_t wptr_mc_addr; 224 uint32_t queue_type; 225 uint32_t paging; 226 uint32_t gws_base; 227 uint32_t gws_size; 228 uint64_t tba_addr; 229 uint64_t tma_addr; 230 uint32_t trap_en; 231 uint32_t skip_process_ctx_clear; 232 uint32_t is_kfd_process; 233 uint32_t is_aql_queue; 234 uint32_t queue_size; 235 uint32_t exclusively_scheduled; 236 }; 237 238 struct mes_remove_queue_input { 239 uint32_t doorbell_offset; 240 uint64_t gang_context_addr; 241 }; 242 243 struct mes_map_legacy_queue_input { 244 uint32_t queue_type; 245 uint32_t doorbell_offset; 246 uint32_t pipe_id; 247 uint32_t queue_id; 248 uint64_t mqd_addr; 249 uint64_t wptr_addr; 250 }; 251 252 struct mes_unmap_legacy_queue_input { 253 enum amdgpu_unmap_queues_action action; 254 uint32_t queue_type; 255 uint32_t doorbell_offset; 256 uint32_t pipe_id; 257 uint32_t queue_id; 258 uint64_t trail_fence_addr; 259 uint64_t trail_fence_data; 260 }; 261 262 struct mes_suspend_gang_input { 263 bool suspend_all_gangs; 264 uint64_t gang_context_addr; 265 uint64_t suspend_fence_addr; 266 uint32_t suspend_fence_value; 267 }; 268 269 struct mes_resume_gang_input { 270 bool resume_all_gangs; 271 uint64_t gang_context_addr; 272 }; 273 274 struct mes_reset_queue_input { 275 uint32_t queue_type; 276 uint32_t doorbell_offset; 277 bool use_mmio; 278 uint32_t me_id; 279 uint32_t pipe_id; 280 uint32_t queue_id; 281 uint64_t mqd_addr; 282 uint64_t wptr_addr; 283 uint32_t vmid; 284 bool legacy_gfx; 285 bool is_kq; 286 }; 287 288 struct mes_detect_and_reset_queue_input { 289 uint32_t queue_type; 290 bool detect_only; 291 }; 292 293 struct mes_inv_tlbs_pasid_input { 294 uint32_t xcc_id; 295 uint16_t pasid; 296 uint8_t hub_id; 297 uint8_t flush_type; 298 }; 299 300 enum mes_misc_opcode { 301 MES_MISC_OP_WRITE_REG, 302 MES_MISC_OP_READ_REG, 303 MES_MISC_OP_WRM_REG_WAIT, 304 MES_MISC_OP_WRM_REG_WR_WAIT, 305 MES_MISC_OP_SET_SHADER_DEBUGGER, 306 MES_MISC_OP_CHANGE_CONFIG, 307 }; 308 309 struct mes_misc_op_input { 310 enum mes_misc_opcode op; 311 312 union { 313 struct { 314 uint32_t reg_offset; 315 uint64_t buffer_addr; 316 } read_reg; 317 318 struct { 319 uint32_t reg_offset; 320 uint32_t reg_value; 321 } write_reg; 322 323 struct { 324 uint32_t ref; 325 uint32_t mask; 326 uint32_t reg0; 327 uint32_t reg1; 328 } wrm_reg; 329 330 struct { 331 uint64_t process_context_addr; 332 union { 333 struct { 334 uint32_t single_memop : 1; 335 uint32_t single_alu_op : 1; 336 uint32_t reserved: 29; 337 uint32_t process_ctx_flush: 1; 338 }; 339 uint32_t u32all; 340 } flags; 341 uint32_t spi_gdbg_per_vmid_cntl; 342 uint32_t tcp_watch_cntl[4]; 343 uint32_t trap_en; 344 } set_shader_debugger; 345 346 struct { 347 union { 348 struct { 349 uint32_t limit_single_process : 1; 350 uint32_t enable_hws_logging_buffer : 1; 351 uint32_t reserved : 30; 352 }; 353 uint32_t all; 354 } option; 355 struct { 356 uint32_t tdr_level; 357 uint32_t tdr_delay; 358 } tdr_config; 359 } change_config; 360 }; 361 }; 362 363 struct amdgpu_mes_funcs { 364 int (*add_hw_queue)(struct amdgpu_mes *mes, 365 struct mes_add_queue_input *input); 366 367 int (*remove_hw_queue)(struct amdgpu_mes *mes, 368 struct mes_remove_queue_input *input); 369 370 int (*map_legacy_queue)(struct amdgpu_mes *mes, 371 struct mes_map_legacy_queue_input *input); 372 373 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 374 struct mes_unmap_legacy_queue_input *input); 375 376 int (*suspend_gang)(struct amdgpu_mes *mes, 377 struct mes_suspend_gang_input *input); 378 379 int (*resume_gang)(struct amdgpu_mes *mes, 380 struct mes_resume_gang_input *input); 381 382 int (*misc_op)(struct amdgpu_mes *mes, 383 struct mes_misc_op_input *input); 384 385 int (*reset_hw_queue)(struct amdgpu_mes *mes, 386 struct mes_reset_queue_input *input); 387 388 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 389 struct mes_detect_and_reset_queue_input *input); 390 391 392 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 393 struct mes_inv_tlbs_pasid_input *input); 394 }; 395 396 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 397 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 398 399 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 400 int amdgpu_mes_init(struct amdgpu_device *adev); 401 void amdgpu_mes_fini(struct amdgpu_device *adev); 402 403 int amdgpu_mes_suspend(struct amdgpu_device *adev); 404 int amdgpu_mes_resume(struct amdgpu_device *adev); 405 406 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 407 struct amdgpu_ring *ring); 408 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 409 struct amdgpu_ring *ring, 410 enum amdgpu_unmap_queues_action action, 411 u64 gpu_addr, u64 seq); 412 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 413 struct amdgpu_ring *ring, 414 unsigned int vmid, 415 bool use_mmio); 416 417 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 418 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 419 int queue_type, 420 bool detect_only, 421 unsigned int *hung_db_num, 422 u32 *hung_db_array); 423 424 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 425 int amdgpu_mes_wreg(struct amdgpu_device *adev, 426 uint32_t reg, uint32_t val); 427 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 428 uint32_t reg0, uint32_t reg1, 429 uint32_t ref, uint32_t mask); 430 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 431 uint64_t process_context_addr, 432 uint32_t spi_gdbg_per_vmid_cntl, 433 const uint32_t *tcp_watch_cntl, 434 uint32_t flags, 435 bool trap_en); 436 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 437 uint64_t process_context_addr); 438 439 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 440 enum amdgpu_mes_priority_level prio); 441 442 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 443 444 /* 445 * MES lock can be taken in MMU notifiers. 446 * 447 * A bit more detail about why to set no-FS reclaim with MES lock: 448 * 449 * The purpose of the MMU notifier is to stop GPU access to memory so 450 * that the Linux VM subsystem can move pages around safely. This is 451 * done by preempting user mode queues for the affected process. When 452 * MES is used, MES lock needs to be taken to preempt the queues. 453 * 454 * The MMU notifier callback entry point in the driver is 455 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 456 * there is: 457 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 458 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 459 * 460 * The last part of the chain is a function pointer where we take the 461 * MES lock. 462 * 463 * The problem with taking locks in the MMU notifier is, that MMU 464 * notifiers can be called in reclaim-FS context. That's where the 465 * kernel frees up pages to make room for new page allocations under 466 * memory pressure. While we are running in reclaim-FS context, we must 467 * not trigger another memory reclaim operation because that would 468 * recursively reenter the reclaim code and cause a deadlock. The 469 * memalloc_nofs_save/restore calls guarantee that. 470 * 471 * In addition we also need to avoid lock dependencies on other locks taken 472 * under the MES lock, for example reservation locks. Here is a possible 473 * scenario of a deadlock: 474 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 475 * MMU notifier | blocks trying to take MES lock 476 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 477 * 478 * In this scenario Thread B gets involved in a deadlock even without 479 * triggering a reclaim-FS operation itself. 480 * To fix this and break the lock dependency chain you'd need to either: 481 * 1. protect reservation locks with memalloc_nofs_save/restore, or 482 * 2. avoid taking reservation locks under the MES lock. 483 * 484 * Reservation locks are taken all over the kernel in different subsystems, we 485 * have no control over them and their lock dependencies.So the only workable 486 * solution is to avoid taking other locks under the MES lock. 487 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 488 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 489 */ 490 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 491 { 492 mutex_lock(&mes->mutex_hidden); 493 mes->saved_flags = memalloc_noreclaim_save(); 494 } 495 496 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 497 { 498 memalloc_noreclaim_restore(mes->saved_flags); 499 mutex_unlock(&mes->mutex_hidden); 500 } 501 502 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 503 504 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 505 506 #endif /* __AMDGPU_MES_H__ */ 507