1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_exec.h> 26 27 #include "amdgpu_mes.h" 28 #include "amdgpu.h" 29 #include "soc15_common.h" 30 #include "amdgpu_mes_ctx.h" 31 32 #define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 33 #define AMDGPU_ONE_DOORBELL_SIZE 8 34 35 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev) 36 { 37 return roundup(AMDGPU_ONE_DOORBELL_SIZE * 38 AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS, 39 PAGE_SIZE); 40 } 41 42 static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev) 43 { 44 int i; 45 struct amdgpu_mes *mes = &adev->mes; 46 47 /* Bitmap for dynamic allocation of kernel doorbells */ 48 mes->doorbell_bitmap = bitmap_zalloc(PAGE_SIZE / sizeof(u32), GFP_KERNEL); 49 if (!mes->doorbell_bitmap) { 50 dev_err(adev->dev, "Failed to allocate MES doorbell bitmap\n"); 51 return -ENOMEM; 52 } 53 54 mes->num_mes_dbs = PAGE_SIZE / AMDGPU_ONE_DOORBELL_SIZE; 55 for (i = 0; i < AMDGPU_MES_PRIORITY_NUM_LEVELS; i++) { 56 adev->mes.aggregated_doorbells[i] = mes->db_start_dw_offset + i * 2; 57 set_bit(i, mes->doorbell_bitmap); 58 } 59 60 return 0; 61 } 62 63 static int amdgpu_mes_event_log_init(struct amdgpu_device *adev) 64 { 65 int r; 66 67 if (!amdgpu_mes_log_enable) 68 return 0; 69 70 r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE, 71 AMDGPU_GEM_DOMAIN_VRAM, 72 &adev->mes.event_log_gpu_obj, 73 &adev->mes.event_log_gpu_addr, 74 &adev->mes.event_log_cpu_addr); 75 if (r) { 76 dev_warn(adev->dev, "failed to create MES event log buffer (%d)", r); 77 return r; 78 } 79 80 memset(adev->mes.event_log_cpu_addr, 0, adev->mes.event_log_size); 81 82 return 0; 83 84 } 85 86 static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev) 87 { 88 bitmap_free(adev->mes.doorbell_bitmap); 89 } 90 91 static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe, 92 u32 num_hqd_per_pipe, 93 u32 num_reserved_hqd) 94 { 95 if (num_pipe == 0) 96 return 0; 97 98 u32 total_hqd_mask = (u32)((1ULL << num_hqd_per_pipe) - 1); 99 u32 reserved_hqd_mask = (u32)((1ULL << DIV_ROUND_UP(num_reserved_hqd, num_pipe)) - 1); 100 101 return (total_hqd_mask & ~reserved_hqd_mask); 102 } 103 104 int amdgpu_mes_init(struct amdgpu_device *adev) 105 { 106 int i, r, num_pipes, num_queues = 0; 107 u32 total_vmid_mask, reserved_vmid_mask; 108 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 109 u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, 110 adev->gfx.me.num_queue_per_pipe, 111 adev->gfx.disable_kq ? 0 : adev->gfx.num_gfx_rings); 112 u32 compute_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.mec.num_pipe_per_mec, 113 adev->gfx.mec.num_queue_per_pipe, 114 adev->gfx.disable_kq ? 0 : adev->gfx.num_compute_rings); 115 116 adev->mes.adev = adev; 117 118 ida_init(&adev->mes.doorbell_ida); 119 spin_lock_init(&adev->mes.queue_id_lock); 120 mutex_init(&adev->mes.mutex_hidden); 121 122 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) 123 spin_lock_init(&adev->mes.ring_lock[i]); 124 125 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; 126 total_vmid_mask = (u32)((1UL << 16) - 1); 127 reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid) - 1); 128 129 adev->mes.vmid_mask_mmhub = 0xFF00; 130 adev->mes.vmid_mask_gfxhub = total_vmid_mask & ~reserved_vmid_mask; 131 132 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; 133 if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) 134 dev_warn(adev->dev, "more gfx pipes than supported by MES! (%d vs %d)\n", 135 num_pipes, AMDGPU_MES_MAX_GFX_PIPES); 136 137 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) { 138 if (i >= num_pipes) 139 break; 140 141 adev->mes.gfx_hqd_mask[i] = gfx_hqd_mask; 142 } 143 144 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; 145 if (num_pipes > AMDGPU_MES_MAX_COMPUTE_PIPES) 146 dev_warn(adev->dev, "more compute pipes than supported by MES! (%d vs %d)\n", 147 num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES); 148 149 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) { 150 /* 151 * Currently, only MEC1 is used for both kernel and user compute queue. 152 * To enable other MEC, we need to redistribute queues per pipe and 153 * adjust queue resource shared with kfd that needs a separate patch. 154 * Skip other MEC for now to avoid potential issues. 155 */ 156 if (i >= adev->gfx.mec.num_pipe_per_mec) 157 break; 158 159 adev->mes.compute_hqd_mask[i] = compute_hqd_mask; 160 } 161 162 num_pipes = adev->sdma.num_inst_per_xcc ? 163 adev->sdma.num_inst_per_xcc : adev->sdma.num_instances; 164 if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES) 165 dev_warn(adev->dev, "more SDMA pipes than supported by MES! (%d vs %d)\n", 166 num_pipes, AMDGPU_MES_MAX_SDMA_PIPES); 167 168 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { 169 if (i >= num_pipes) 170 break; 171 adev->mes.sdma_hqd_mask[i] = 0xfc; 172 } 173 174 dev_info(adev->dev, 175 "MES: vmid_mask_mmhub 0x%08x, vmid_mask_gfxhub 0x%08x\n", 176 adev->mes.vmid_mask_mmhub, 177 adev->mes.vmid_mask_gfxhub); 178 179 dev_info(adev->dev, 180 "MES: gfx_hqd_mask 0x%08x, compute_hqd_mask 0x%08x, sdma_hqd_mask 0x%08x\n", 181 adev->mes.gfx_hqd_mask[0], 182 adev->mes.compute_hqd_mask[0], 183 adev->mes.sdma_hqd_mask[0]); 184 185 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 186 r = amdgpu_wb_get(adev, &adev->mes.sch_ctx_offs[i]); 187 if (r) { 188 dev_err(adev->dev, 189 "(%d) ring trail_fence_offs wb alloc failed\n", 190 r); 191 goto error; 192 } 193 adev->mes.sch_ctx_gpu_addr[i] = 194 adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4); 195 adev->mes.sch_ctx_ptr[i] = 196 (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]]; 197 198 r = amdgpu_wb_get(adev, 199 &adev->mes.query_status_fence_offs[i]); 200 if (r) { 201 dev_err(adev->dev, 202 "(%d) query_status_fence_offs wb alloc failed\n", 203 r); 204 goto error; 205 } 206 adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr + 207 (adev->mes.query_status_fence_offs[i] * 4); 208 adev->mes.query_status_fence_ptr[i] = 209 (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]]; 210 } 211 212 r = amdgpu_mes_doorbell_init(adev); 213 if (r) 214 goto error; 215 216 r = amdgpu_mes_event_log_init(adev); 217 if (r) 218 goto error_doorbell; 219 220 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { 221 /* When queue/pipe reset is done in MES instead of in the 222 * driver, MES passes hung queues information to the driver in 223 * hung_queue_hqd_info. Calculate required space to store this 224 * information. 225 */ 226 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 227 num_queues += hweight32(adev->mes.gfx_hqd_mask[i]); 228 229 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 230 num_queues += hweight32(adev->mes.compute_hqd_mask[i]); 231 232 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 233 num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc; 234 235 adev->mes.hung_queue_hqd_info_offset = num_queues; 236 adev->mes.hung_queue_db_array_size = num_queues * 2; 237 } 238 239 if (adev->mes.hung_queue_db_array_size) { 240 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 241 r = amdgpu_bo_create_kernel(adev, 242 adev->mes.hung_queue_db_array_size * sizeof(u32), 243 PAGE_SIZE, 244 AMDGPU_GEM_DOMAIN_GTT, 245 &adev->mes.hung_queue_db_array_gpu_obj[i], 246 &adev->mes.hung_queue_db_array_gpu_addr[i], 247 &adev->mes.hung_queue_db_array_cpu_addr[i]); 248 if (r) { 249 dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); 250 goto error_doorbell; 251 } 252 } 253 254 adev->gfx.mec.mes_hung_db_array = 255 kcalloc(amdgpu_mes_get_hung_queue_db_array_size(adev), 256 sizeof(u32), GFP_KERNEL); 257 258 if (!adev->gfx.mec.mes_hung_db_array) { 259 r = -ENOMEM; 260 goto error_doorbell; 261 } 262 } 263 264 return 0; 265 266 error_doorbell: 267 amdgpu_mes_doorbell_free(adev); 268 error: 269 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 270 if (adev->mes.sch_ctx_ptr[i]) 271 amdgpu_wb_free(adev, adev->mes.sch_ctx_offs[i]); 272 if (adev->mes.query_status_fence_ptr[i]) 273 amdgpu_wb_free(adev, 274 adev->mes.query_status_fence_offs[i]); 275 if (adev->mes.hung_queue_db_array_gpu_obj[i]) 276 amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], 277 &adev->mes.hung_queue_db_array_gpu_addr[i], 278 &adev->mes.hung_queue_db_array_cpu_addr[i]); 279 } 280 281 ida_destroy(&adev->mes.doorbell_ida); 282 mutex_destroy(&adev->mes.mutex_hidden); 283 return r; 284 } 285 286 void amdgpu_mes_fini(struct amdgpu_device *adev) 287 { 288 int i; 289 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 290 291 kfree(adev->gfx.mec.mes_hung_db_array); 292 293 amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, 294 &adev->mes.event_log_gpu_addr, 295 &adev->mes.event_log_cpu_addr); 296 297 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 298 if (adev->mes.hung_queue_db_array_gpu_obj[i]) 299 amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], 300 &adev->mes.hung_queue_db_array_gpu_addr[i], 301 &adev->mes.hung_queue_db_array_cpu_addr[i]); 302 if (adev->mes.sch_ctx_ptr[i]) 303 amdgpu_wb_free(adev, adev->mes.sch_ctx_offs[i]); 304 if (adev->mes.query_status_fence_ptr[i]) 305 amdgpu_wb_free(adev, 306 adev->mes.query_status_fence_offs[i]); 307 } 308 309 amdgpu_mes_doorbell_free(adev); 310 311 if (adev->mes.use_rs64mem) 312 amdgpu_mes_rs64mem_fini(&adev->mes); 313 314 ida_destroy(&adev->mes.doorbell_ida); 315 mutex_destroy(&adev->mes.mutex_hidden); 316 317 } 318 319 int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id) 320 { 321 struct mes_suspend_gang_input input; 322 int r; 323 324 if (!amdgpu_mes_suspend_resume_all_supported(adev)) 325 return 0; 326 327 memset(&input, 0x0, sizeof(struct mes_suspend_gang_input)); 328 input.suspend_all_gangs = 1; 329 input.xcc_id = xcc_id; 330 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) && 331 ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x71)) 332 input.suspend_all_sdma_gangs = 1; 333 334 /* 335 * Avoid taking any other locks under MES lock to avoid circular 336 * lock dependencies. 337 */ 338 amdgpu_mes_lock(&adev->mes); 339 r = adev->mes.funcs->suspend_gang(&adev->mes, &input); 340 amdgpu_mes_unlock(&adev->mes); 341 if (r) 342 dev_err(adev->dev, "failed to suspend all gangs"); 343 344 return r; 345 } 346 347 int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id) 348 { 349 struct mes_resume_gang_input input; 350 int r; 351 352 if (!amdgpu_mes_suspend_resume_all_supported(adev)) 353 return 0; 354 355 memset(&input, 0x0, sizeof(struct mes_resume_gang_input)); 356 input.resume_all_gangs = 1; 357 input.xcc_id = xcc_id; 358 359 /* 360 * Avoid taking any other locks under MES lock to avoid circular 361 * lock dependencies. 362 */ 363 amdgpu_mes_lock(&adev->mes); 364 r = adev->mes.funcs->resume_gang(&adev->mes, &input); 365 amdgpu_mes_unlock(&adev->mes); 366 if (r) 367 dev_err(adev->dev, "failed to resume all gangs"); 368 369 return r; 370 } 371 372 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 373 struct amdgpu_ring *ring, uint32_t xcc_id) 374 { 375 struct mes_map_legacy_queue_input queue_input; 376 int r; 377 378 memset(&queue_input, 0, sizeof(queue_input)); 379 380 queue_input.xcc_id = xcc_id; 381 queue_input.queue_type = ring->funcs->type; 382 queue_input.doorbell_offset = ring->doorbell_index; 383 queue_input.pipe_id = ring->pipe; 384 queue_input.queue_id = ring->queue; 385 queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 386 queue_input.wptr_addr = ring->wptr_gpu_addr; 387 388 amdgpu_mes_lock(&adev->mes); 389 r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input); 390 amdgpu_mes_unlock(&adev->mes); 391 if (r) 392 dev_err(adev->dev, "failed to map legacy queue\n"); 393 394 return r; 395 } 396 397 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 398 struct amdgpu_ring *ring, 399 enum amdgpu_unmap_queues_action action, 400 u64 gpu_addr, u64 seq, uint32_t xcc_id) 401 { 402 struct mes_unmap_legacy_queue_input queue_input; 403 int r; 404 405 queue_input.xcc_id = xcc_id; 406 queue_input.action = action; 407 queue_input.queue_type = ring->funcs->type; 408 queue_input.doorbell_offset = ring->doorbell_index; 409 queue_input.pipe_id = ring->pipe; 410 queue_input.queue_id = ring->queue; 411 queue_input.trail_fence_addr = gpu_addr; 412 queue_input.trail_fence_data = seq; 413 414 amdgpu_mes_lock(&adev->mes); 415 r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input); 416 amdgpu_mes_unlock(&adev->mes); 417 if (r) 418 dev_err(adev->dev, "failed to unmap legacy queue\n"); 419 420 return r; 421 } 422 423 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 424 struct amdgpu_ring *ring, 425 unsigned int vmid, 426 bool use_mmio, 427 uint32_t xcc_id) 428 { 429 struct mes_reset_queue_input queue_input; 430 int r; 431 432 memset(&queue_input, 0, sizeof(queue_input)); 433 434 queue_input.xcc_id = xcc_id; 435 queue_input.queue_type = ring->funcs->type; 436 queue_input.doorbell_offset = ring->doorbell_index; 437 queue_input.me_id = ring->me; 438 queue_input.pipe_id = ring->pipe; 439 queue_input.queue_id = ring->queue; 440 queue_input.mqd_addr = ring->mqd_obj ? amdgpu_bo_gpu_offset(ring->mqd_obj) : 0; 441 queue_input.wptr_addr = ring->wptr_gpu_addr; 442 queue_input.vmid = vmid; 443 queue_input.use_mmio = use_mmio; 444 queue_input.is_kq = true; 445 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) 446 queue_input.legacy_gfx = true; 447 448 amdgpu_mes_lock(&adev->mes); 449 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 450 amdgpu_mes_unlock(&adev->mes); 451 if (r) 452 dev_err(adev->dev, "failed to reset legacy queue\n"); 453 454 return r; 455 } 456 457 int amdgpu_mes_reset_queue_mmio(struct amdgpu_device *adev, 458 int queue_type, 459 unsigned int vmid, 460 unsigned int me, 461 unsigned int pipe, 462 unsigned int queue, 463 uint32_t xcc_id) 464 { 465 struct mes_reset_queue_input queue_input; 466 int r; 467 468 memset(&queue_input, 0, sizeof(queue_input)); 469 470 queue_input.xcc_id = xcc_id; 471 queue_input.me_id = me; 472 queue_input.pipe_id = pipe; 473 queue_input.queue_id = queue; 474 queue_input.vmid = vmid; 475 queue_input.queue_type = queue_type; 476 queue_input.use_mmio = true; 477 478 amdgpu_mes_lock(&adev->mes); 479 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 480 amdgpu_mes_unlock(&adev->mes); 481 if (r) 482 dev_err(adev->dev, "failed to reset legacy queue\n"); 483 484 return r; 485 } 486 487 int amdgpu_mes_reset_user_queue(struct amdgpu_device *adev, 488 int queue_type, 489 unsigned int doorbell_index, 490 unsigned int xcc_id) 491 { 492 struct mes_reset_queue_input queue_input; 493 int r; 494 495 memset(&queue_input, 0, sizeof(queue_input)); 496 497 queue_input.xcc_id = xcc_id; 498 queue_input.queue_type = queue_type; 499 queue_input.doorbell_offset = doorbell_index; 500 501 amdgpu_mes_lock(&adev->mes); 502 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 503 amdgpu_mes_unlock(&adev->mes); 504 if (r) 505 dev_err(adev->dev, "failed to reset user queue\n"); 506 507 return r; 508 } 509 510 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev) 511 { 512 return adev->mes.hung_queue_db_array_size; 513 } 514 515 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 516 int queue_type, 517 bool detect_only, 518 unsigned int *hung_db_num, 519 u32 *hung_db_array, 520 uint32_t xcc_id) 521 { 522 struct mes_detect_and_reset_queue_input input; 523 u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; 524 int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i; 525 526 if (!hung_db_num || !hung_db_array) 527 return -EINVAL; 528 529 if ((queue_type != AMDGPU_RING_TYPE_GFX) && 530 (queue_type != AMDGPU_RING_TYPE_COMPUTE) && 531 (queue_type != AMDGPU_RING_TYPE_SDMA)) 532 return -EINVAL; 533 534 /* Clear the doorbell array before detection */ 535 memset(adev->mes.hung_queue_db_array_cpu_addr[xcc_id], AMDGPU_MES_INVALID_DB_OFFSET, 536 adev->mes.hung_queue_db_array_size * sizeof(u32)); 537 input.queue_type = queue_type; 538 input.detect_only = detect_only; 539 input.xcc_id = xcc_id; 540 541 r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes, 542 &input); 543 544 if (r && detect_only) { 545 dev_err(adev->dev, "Failed to detect hung queues\n"); 546 return r; 547 } 548 549 *hung_db_num = 0; 550 /* MES passes hung queues' doorbell to driver */ 551 for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { 552 /* Finding hung queues where db_array[i] is a valid doorbell */ 553 if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { 554 hung_db_array[i] = db_array[i]; 555 *hung_db_num += 1; 556 } 557 } 558 559 if (r && !(*hung_db_num)) { 560 dev_err(adev->dev, "Failed to detect and reset hung queues\n"); 561 return r; 562 } 563 564 for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++) 565 hung_db_array[i] = db_array[i]; 566 567 return r; 568 } 569 570 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 571 uint32_t xcc_id) 572 { 573 struct mes_misc_op_input op_input; 574 int r, val = 0; 575 uint32_t addr_offset = 0; 576 uint64_t read_val_gpu_addr; 577 uint32_t *read_val_ptr; 578 579 if (amdgpu_wb_get(adev, &addr_offset)) { 580 dev_err(adev->dev, "critical bug! too many mes readers\n"); 581 goto error; 582 } 583 read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4); 584 read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset]; 585 op_input.xcc_id = xcc_id; 586 op_input.op = MES_MISC_OP_READ_REG; 587 op_input.read_reg.reg_offset = reg; 588 op_input.read_reg.buffer_addr = read_val_gpu_addr; 589 590 if (!adev->mes.funcs->misc_op) { 591 dev_err(adev->dev, "mes rreg is not supported!\n"); 592 goto error; 593 } 594 595 amdgpu_mes_lock(&adev->mes); 596 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 597 amdgpu_mes_unlock(&adev->mes); 598 if (r) 599 dev_err(adev->dev, "failed to read reg (0x%x)\n", reg); 600 else 601 val = *(read_val_ptr); 602 603 error: 604 if (addr_offset) 605 amdgpu_wb_free(adev, addr_offset); 606 return val; 607 } 608 609 int amdgpu_mes_wreg(struct amdgpu_device *adev, uint32_t reg, 610 uint32_t val, uint32_t xcc_id) 611 { 612 struct mes_misc_op_input op_input; 613 int r; 614 615 op_input.xcc_id = xcc_id; 616 op_input.op = MES_MISC_OP_WRITE_REG; 617 op_input.write_reg.reg_offset = reg; 618 op_input.write_reg.reg_value = val; 619 620 if (!adev->mes.funcs->misc_op) { 621 dev_err(adev->dev, "mes wreg is not supported!\n"); 622 r = -EINVAL; 623 goto error; 624 } 625 626 amdgpu_mes_lock(&adev->mes); 627 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 628 amdgpu_mes_unlock(&adev->mes); 629 if (r) 630 dev_err(adev->dev, "failed to write reg (0x%x)\n", reg); 631 632 error: 633 return r; 634 } 635 636 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 637 uint32_t reg0, uint32_t reg1, 638 uint32_t ref, uint32_t mask, 639 uint32_t xcc_id) 640 { 641 struct mes_misc_op_input op_input; 642 int r; 643 644 op_input.xcc_id = xcc_id; 645 op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; 646 op_input.wrm_reg.reg0 = reg0; 647 op_input.wrm_reg.reg1 = reg1; 648 op_input.wrm_reg.ref = ref; 649 op_input.wrm_reg.mask = mask; 650 651 if (!adev->mes.funcs->misc_op) { 652 dev_err(adev->dev, "mes reg_write_reg_wait is not supported!\n"); 653 r = -EINVAL; 654 goto error; 655 } 656 657 amdgpu_mes_lock(&adev->mes); 658 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 659 amdgpu_mes_unlock(&adev->mes); 660 if (r) 661 dev_err(adev->dev, "failed to reg_write_reg_wait\n"); 662 663 error: 664 return r; 665 } 666 667 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev) 668 { 669 uint32_t hdp_flush_req_offset, hdp_flush_done_offset; 670 struct amdgpu_ring *mes_ring; 671 uint32_t ref_and_mask = 0, reg_mem_engine = 0; 672 673 if (!adev->gfx.funcs->get_hdp_flush_mask) { 674 dev_err(adev->dev, "mes hdp flush is not supported.\n"); 675 return -EINVAL; 676 } 677 678 mes_ring = &adev->mes.ring[0]; 679 hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev); 680 hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev); 681 682 adev->gfx.funcs->get_hdp_flush_mask(mes_ring, &ref_and_mask, ®_mem_engine); 683 684 return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset, 685 ref_and_mask, ref_and_mask, 0); 686 } 687 688 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 689 uint64_t process_context_addr, 690 uint32_t spi_gdbg_per_vmid_cntl, 691 const uint32_t *tcp_watch_cntl, 692 uint32_t flags, 693 bool trap_en, 694 uint32_t xcc_id) 695 { 696 struct mes_misc_op_input op_input = {0}; 697 int r; 698 699 if (!adev->mes.funcs->misc_op) { 700 dev_err(adev->dev, 701 "mes set shader debugger is not supported!\n"); 702 return -EINVAL; 703 } 704 705 op_input.xcc_id = xcc_id; 706 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; 707 op_input.set_shader_debugger.process_context_addr = process_context_addr; 708 op_input.set_shader_debugger.flags.u32all = flags; 709 710 /* use amdgpu mes_flush_shader_debugger instead */ 711 if (op_input.set_shader_debugger.flags.process_ctx_flush) 712 return -EINVAL; 713 714 op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl; 715 memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl, 716 sizeof(op_input.set_shader_debugger.tcp_watch_cntl)); 717 718 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 719 AMDGPU_MES_API_VERSION_SHIFT) >= 14) 720 op_input.set_shader_debugger.trap_en = trap_en; 721 722 amdgpu_mes_lock(&adev->mes); 723 724 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 725 if (r) 726 dev_err(adev->dev, "failed to set_shader_debugger\n"); 727 728 amdgpu_mes_unlock(&adev->mes); 729 730 return r; 731 } 732 733 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 734 uint64_t process_context_addr, 735 uint32_t xcc_id) 736 { 737 struct mes_misc_op_input op_input = {0}; 738 int r; 739 740 if (!adev->mes.funcs->misc_op) { 741 dev_err(adev->dev, 742 "mes flush shader debugger is not supported!\n"); 743 return -EINVAL; 744 } 745 746 op_input.xcc_id = xcc_id; 747 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; 748 op_input.set_shader_debugger.process_context_addr = process_context_addr; 749 op_input.set_shader_debugger.flags.process_ctx_flush = true; 750 751 amdgpu_mes_lock(&adev->mes); 752 753 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 754 if (r) 755 dev_err(adev->dev, "failed to set_shader_debugger\n"); 756 757 amdgpu_mes_unlock(&adev->mes); 758 759 return r; 760 } 761 762 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 763 enum amdgpu_mes_priority_level prio) 764 { 765 return adev->mes.aggregated_doorbells[prio]; 766 } 767 768 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) 769 { 770 const struct mes_firmware_header_v1_0 *mes_hdr; 771 struct amdgpu_firmware_info *info; 772 char ucode_prefix[30]; 773 char fw_name[50]; 774 bool need_retry = false; 775 u32 *ucode_ptr; 776 int r; 777 778 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, 779 sizeof(ucode_prefix)); 780 if (adev->enable_uni_mes) { 781 snprintf(fw_name, sizeof(fw_name), 782 "amdgpu/%s_uni_mes.bin", ucode_prefix); 783 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && 784 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { 785 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", 786 ucode_prefix, 787 pipe == AMDGPU_MES_SCHED_PIPE ? "_2" : "1"); 788 need_retry = true; 789 } else { 790 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin", 791 ucode_prefix, 792 pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1"); 793 } 794 795 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], AMDGPU_UCODE_REQUIRED, 796 "%s", fw_name); 797 if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) { 798 dev_info(adev->dev, "try to fall back to %s_mes.bin\n", ucode_prefix); 799 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], 800 AMDGPU_UCODE_REQUIRED, 801 "amdgpu/%s_mes.bin", ucode_prefix); 802 } 803 804 if (r) 805 goto out; 806 807 mes_hdr = (const struct mes_firmware_header_v1_0 *) 808 adev->mes.fw[pipe]->data; 809 adev->mes.uc_start_addr[pipe] = 810 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 811 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 812 adev->mes.data_start_addr[pipe] = 813 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 814 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 815 ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data + 816 sizeof(union amdgpu_firmware_header)); 817 adev->mes.fw_version[pipe] = 818 le32_to_cpu(ucode_ptr[24]) & AMDGPU_MES_VERSION_MASK; 819 820 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 821 int ucode, ucode_data; 822 823 if (pipe == AMDGPU_MES_SCHED_PIPE) { 824 ucode = AMDGPU_UCODE_ID_CP_MES; 825 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 826 } else { 827 ucode = AMDGPU_UCODE_ID_CP_MES1; 828 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 829 } 830 831 info = &adev->firmware.ucode[ucode]; 832 info->ucode_id = ucode; 833 info->fw = adev->mes.fw[pipe]; 834 adev->firmware.fw_size += 835 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 836 PAGE_SIZE); 837 838 info = &adev->firmware.ucode[ucode_data]; 839 info->ucode_id = ucode_data; 840 info->fw = adev->mes.fw[pipe]; 841 adev->firmware.fw_size += 842 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 843 PAGE_SIZE); 844 } 845 846 return 0; 847 out: 848 amdgpu_ucode_release(&adev->mes.fw[pipe]); 849 return r; 850 } 851 852 void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev) 853 { 854 u32 fw_from_ucode = adev->mes.fw_version[AMDGPU_MES_SCHED_PIPE]; 855 u32 fw_from_reg = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 856 857 if (fw_from_ucode != fw_from_reg) 858 dev_info(adev->dev, 859 "MES firmware reports incorrect version in ucode binary (0x%x vs 0x%x)\n", 860 fw_from_ucode, fw_from_reg); 861 } 862 863 864 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) 865 { 866 uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 867 868 return ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && 869 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && 870 mes_rev >= 0x63) || 871 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); 872 } 873 874 bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev) 875 { 876 u32 ip_maj = IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)); 877 u32 ip_min = IP_VERSION_MIN(amdgpu_ip_version(adev, GC_HWIP, 0)); 878 u32 mes_sched = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 879 880 return (ip_maj == 11 && mes_sched >= 0x8c) || 881 ((ip_maj == 12 && ip_min == 0) && mes_sched >= 0x8d) || 882 ((ip_maj == 12 && ip_min == 1) && mes_sched >= 0x73); 883 } 884 885 /* Fix me -- node_id is used to identify the correct MES instances in the future */ 886 static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, 887 uint32_t node_id, bool enable) 888 { 889 struct mes_misc_op_input op_input = {0}; 890 int r; 891 892 op_input.op = MES_MISC_OP_CHANGE_CONFIG; 893 op_input.change_config.option.limit_single_process = enable ? 1 : 0; 894 895 if (!adev->mes.funcs->misc_op) { 896 dev_err(adev->dev, "mes change config is not supported!\n"); 897 r = -EINVAL; 898 goto error; 899 } 900 901 amdgpu_mes_lock(&adev->mes); 902 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); 903 amdgpu_mes_unlock(&adev->mes); 904 if (r) 905 dev_err(adev->dev, "failed to change_config.\n"); 906 907 error: 908 return r; 909 } 910 911 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev) 912 { 913 int i, r = 0; 914 915 if (adev->enable_mes && adev->gfx.enable_cleaner_shader) { 916 mutex_lock(&adev->enforce_isolation_mutex); 917 for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) { 918 if (adev->enforce_isolation[i] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 919 r |= amdgpu_mes_set_enforce_isolation(adev, i, true); 920 else 921 r |= amdgpu_mes_set_enforce_isolation(adev, i, false); 922 } 923 mutex_unlock(&adev->enforce_isolation_mutex); 924 } 925 return r; 926 } 927 928 /** 929 * amdgpu_mes_rs64mem_init - initialize RS64 local memory context arrays 930 * 931 * @mes: MES instance 932 * 933 * Returns 0 on success, negative errno on failure. 934 */ 935 int amdgpu_mes_rs64mem_init(struct amdgpu_mes *mes) 936 { 937 struct amdgpu_device *adev = container_of(mes, struct amdgpu_device, mes); 938 int r; 939 940 if (!mes->use_rs64mem) 941 return 0; 942 943 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 944 AMDGPU_GEM_DOMAIN_GTT, 945 &mes->ctx_array_size_bo, 946 &mes->ctx_array_size_gpu_addr, 947 (void **)&mes->ctx_array_size_cpu_ptr); 948 if (r) { 949 dev_err(adev->dev, 950 "Failed to allocate ctx array size BO, r=%d\n", r); 951 return r; 952 } 953 954 memset(mes->ctx_array_size_cpu_ptr, 0, PAGE_SIZE); 955 956 return 0; 957 } 958 959 /** 960 * amdgpu_mes_rs64mem_fini - tear down RS64 local memory management 961 * 962 * @mes: MES instance 963 */ 964 void amdgpu_mes_rs64mem_fini(struct amdgpu_mes *mes) 965 { 966 if (mes->ctx_array_size_bo) { 967 amdgpu_bo_free_kernel(&mes->ctx_array_size_bo, 968 &mes->ctx_array_size_gpu_addr, 969 (void **)&mes->ctx_array_size_cpu_ptr); 970 } 971 bitmap_free(mes->proc_ctx_bitmap); 972 bitmap_free(mes->gang_ctx_bitmap); 973 mes->use_rs64mem = false; 974 } 975 976 /** 977 * amdgpu_mes_rs64mem_setup_bitmaps - allocate bitmaps after querying MES 978 * 979 * Called after QUERY_SCHEDULER_STATUS returns and MES has written 980 * the array sizes to the GPU buffer. Reads the sizes and allocates 981 * the tracking bitmaps. 982 * 983 * @mes: MES instance 984 * 985 * Returns 0 on success, negative errno on failure. 986 */ 987 int amdgpu_mes_rs64mem_setup_bitmaps(struct amdgpu_mes *mes) 988 { 989 struct amdgpu_device *adev = container_of(mes, struct amdgpu_device, mes); 990 991 if (!mes->use_rs64mem || !mes->ctx_array_size_cpu_ptr) 992 return 0; 993 994 /* 995 * MES FW wrote the sizes to the GPU buffer: 996 * ctx_array_size_cpu_ptr[0] = proc_ctx_array_size (N) 997 * ctx_array_size_cpu_ptr[1] = gang_ctx_array_size (M) 998 */ 999 mes->proc_ctx_array_size = mes->ctx_array_size_cpu_ptr[0]; 1000 mes->gang_ctx_array_size = mes->ctx_array_size_cpu_ptr[1]; 1001 1002 /* Sanity check - MES FW typically returns N=50, M=300 */ 1003 if (mes->proc_ctx_array_size == 0 || mes->gang_ctx_array_size == 0) { 1004 dev_warn(adev->dev, 1005 "MES returned zero ctx array sizes (proc=%u, gang=%u), " 1006 "disabling RS64 local memory optimization\n", 1007 mes->proc_ctx_array_size, mes->gang_ctx_array_size); 1008 mes->use_rs64mem = false; 1009 return 0; 1010 } 1011 1012 /* Cap to safety limits */ 1013 if (mes->proc_ctx_array_size > AMDGPU_MES_PROC_CTX_ARRAY_MAX) 1014 mes->proc_ctx_array_size = AMDGPU_MES_PROC_CTX_ARRAY_MAX; 1015 if (mes->gang_ctx_array_size > AMDGPU_MES_GANG_CTX_ARRAY_MAX) 1016 mes->gang_ctx_array_size = AMDGPU_MES_GANG_CTX_ARRAY_MAX; 1017 1018 dev_info(adev->dev, 1019 "MES RS64 local memory: proc_ctx_array_size:%u, " 1020 "gang_ctx_array_size:%u\n", 1021 mes->proc_ctx_array_size, mes->gang_ctx_array_size); 1022 1023 /* Allocate bitmaps */ 1024 mes->proc_ctx_bitmap = bitmap_zalloc(mes->proc_ctx_array_size, 1025 GFP_KERNEL); 1026 if (!mes->proc_ctx_bitmap) { 1027 mes->use_rs64mem = false; 1028 return -ENOMEM; 1029 } 1030 1031 mes->gang_ctx_bitmap = bitmap_zalloc(mes->gang_ctx_array_size, 1032 GFP_KERNEL); 1033 if (!mes->gang_ctx_bitmap) { 1034 bitmap_free(mes->proc_ctx_bitmap); 1035 mes->proc_ctx_bitmap = NULL; 1036 mes->use_rs64mem = false; 1037 return -ENOMEM; 1038 } 1039 1040 return 0; 1041 } 1042 1043 /** 1044 * amdgpu_mes_alloc_proc_ctx_index - allocate a process context slot 1045 * 1046 * @mes: MES instance 1047 * @index: the allocated process context index 1048 * 1049 * Returns 0 on success, -ENOSPC if all slots are used, or 1050 * -EOPNOTSUPP if RS64 local memory is unavailable. 1051 */ 1052 int amdgpu_mes_alloc_proc_ctx_index(struct amdgpu_mes *mes, 1053 uint32_t *index) 1054 { 1055 unsigned long bit; 1056 1057 if (!mes->use_rs64mem || !mes->proc_ctx_bitmap) 1058 return -EOPNOTSUPP; 1059 1060 amdgpu_mes_lock(mes); 1061 bit = find_first_zero_bit(mes->proc_ctx_bitmap, 1062 mes->proc_ctx_array_size); 1063 if (bit >= mes->proc_ctx_array_size) { 1064 amdgpu_mes_unlock(mes); 1065 return -ENOSPC; 1066 } 1067 set_bit(bit, mes->proc_ctx_bitmap); 1068 *index = (uint32_t)bit; 1069 amdgpu_mes_unlock(mes); 1070 1071 return 0; 1072 } 1073 1074 /** 1075 * amdgpu_mes_free_proc_ctx_index - free a process context slot 1076 * 1077 * @mes: MES instance 1078 * @index: process context index is released 1079 */ 1080 void amdgpu_mes_free_proc_ctx_index(struct amdgpu_mes *mes, 1081 uint32_t index) 1082 { 1083 if (!mes->use_rs64mem || !mes->proc_ctx_bitmap) 1084 return; 1085 if (index >= mes->proc_ctx_array_size) 1086 return; 1087 1088 amdgpu_mes_lock(mes); 1089 clear_bit(index, mes->proc_ctx_bitmap); 1090 amdgpu_mes_unlock(mes); 1091 } 1092 1093 /** 1094 * amdgpu_mes_alloc_gang_ctx_index - allocate a gang context slot 1095 * 1096 * @mes: MES instance 1097 * @index: the allocated gang context index 1098 * 1099 * Returns 0 on success, -ENOSPC if all slots are used, or 1100 * -EOPNOTSUPP if RS64 local memory is unavailable. 1101 */ 1102 int amdgpu_mes_alloc_gang_ctx_index(struct amdgpu_mes *mes, 1103 uint32_t *index) 1104 { 1105 unsigned long bit; 1106 1107 if (!mes->use_rs64mem || !mes->gang_ctx_bitmap) 1108 return -EOPNOTSUPP; 1109 1110 amdgpu_mes_lock(mes); 1111 bit = find_first_zero_bit(mes->gang_ctx_bitmap, 1112 mes->gang_ctx_array_size); 1113 if (bit >= mes->gang_ctx_array_size) { 1114 amdgpu_mes_unlock(mes); 1115 return -ENOSPC; 1116 } 1117 set_bit(bit, mes->gang_ctx_bitmap); 1118 *index = bit; 1119 amdgpu_mes_unlock(mes); 1120 1121 return 0; 1122 } 1123 1124 /** 1125 * amdgpu_mes_free_gang_ctx_index - free a gang context slot 1126 * 1127 * @mes: MES instance 1128 * @index: gang context index is released 1129 */ 1130 void amdgpu_mes_free_gang_ctx_index(struct amdgpu_mes *mes, 1131 uint32_t index) 1132 { 1133 if (!mes->use_rs64mem || !mes->gang_ctx_bitmap) 1134 return; 1135 if (index >= mes->gang_ctx_array_size) 1136 return; 1137 1138 amdgpu_mes_lock(mes); 1139 clear_bit(index, mes->gang_ctx_bitmap); 1140 amdgpu_mes_unlock(mes); 1141 } 1142 1143 #if defined(CONFIG_DEBUG_FS) 1144 1145 static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused) 1146 { 1147 struct amdgpu_device *adev = m->private; 1148 uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr); 1149 1150 seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4, 1151 mem, adev->mes.event_log_size, false); 1152 1153 return 0; 1154 } 1155 1156 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_mes_event_log); 1157 1158 #endif 1159 1160 void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev) 1161 { 1162 1163 #if defined(CONFIG_DEBUG_FS) 1164 struct drm_minor *minor = adev_to_drm(adev)->primary; 1165 struct dentry *root = minor->debugfs_root; 1166 if (adev->enable_mes && amdgpu_mes_log_enable) 1167 debugfs_create_file("amdgpu_mes_event_log", 0444, root, 1168 adev, &amdgpu_debugfs_mes_event_log_fops); 1169 1170 #endif 1171 } 1172