1 /* 2 * Copyright (C) 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_MCA_H__ 22 #define __AMDGPU_MCA_H__ 23 24 #include "amdgpu_ras.h" 25 26 #define MCA_MAX_REGS_COUNT (16) 27 28 enum amdgpu_mca_ip { 29 AMDGPU_MCA_IP_UNKNOW = -1, 30 AMDGPU_MCA_IP_PSP = 0, 31 AMDGPU_MCA_IP_SDMA, 32 AMDGPU_MCA_IP_GC, 33 AMDGPU_MCA_IP_SMU, 34 AMDGPU_MCA_IP_MP5, 35 AMDGPU_MCA_IP_UMC, 36 AMDGPU_MCA_IP_COUNT, 37 }; 38 39 enum amdgpu_mca_error_type { 40 AMDGPU_MCA_ERROR_TYPE_UE = 0, 41 AMDGPU_MCA_ERROR_TYPE_CE, 42 }; 43 44 struct amdgpu_mca_ras_block { 45 struct amdgpu_ras_block_object ras_block; 46 }; 47 48 struct amdgpu_mca_ras { 49 struct ras_common_if *ras_if; 50 struct amdgpu_mca_ras_block *ras; 51 }; 52 53 struct amdgpu_mca { 54 struct amdgpu_mca_ras mp0; 55 struct amdgpu_mca_ras mp1; 56 struct amdgpu_mca_ras mpio; 57 const struct amdgpu_mca_smu_funcs *mca_funcs; 58 }; 59 60 struct mca_bank_info { 61 int socket_id; 62 int aid; 63 int hwid; 64 int mcatype; 65 }; 66 67 struct mca_bank_entry { 68 int idx; 69 enum amdgpu_mca_error_type type; 70 enum amdgpu_mca_ip ip; 71 struct mca_bank_info info; 72 uint64_t regs[MCA_MAX_REGS_COUNT]; 73 }; 74 75 struct amdgpu_mca_smu_funcs { 76 int max_ue_count; 77 int max_ce_count; 78 int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable); 79 int (*mca_get_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 80 enum amdgpu_mca_error_type type, uint32_t *count); 81 int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 82 uint32_t *count); 83 int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 84 int idx, struct mca_bank_entry *entry); 85 int (*mca_get_ras_mca_idx_array)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 86 enum amdgpu_mca_error_type type, int *idx_array, int *idx_array_size); 87 }; 88 89 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, 90 uint64_t mc_status_addr, 91 unsigned long *error_count); 92 93 void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev, 94 uint64_t mc_status_addr, 95 unsigned long *error_count); 96 97 void amdgpu_mca_reset_error_count(struct amdgpu_device *adev, 98 uint64_t mc_status_addr); 99 100 void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, 101 uint64_t mc_status_addr, 102 void *ras_error_status); 103 int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev); 104 int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev); 105 int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev); 106 107 void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs); 108 int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable); 109 int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count); 110 int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 111 enum amdgpu_mca_error_type type, uint32_t *count); 112 int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 113 int idx, struct mca_bank_entry *entry); 114 115 void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root); 116 117 #endif 118