1 /* 2 * Copyright (C) 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef __AMDGPU_MCA_H__ 22 #define __AMDGPU_MCA_H__ 23 24 #include "amdgpu_ras.h" 25 26 enum amdgpu_mca_error_type { 27 AMDGPU_MCA_ERROR_TYPE_UE = 0, 28 AMDGPU_MCA_ERROR_TYPE_CE, 29 AMDGPU_MCA_ERROR_TYPE_DE, 30 }; 31 32 struct amdgpu_mca_ras_block { 33 struct amdgpu_ras_block_object ras_block; 34 }; 35 36 struct amdgpu_mca_ras { 37 struct ras_common_if *ras_if; 38 struct amdgpu_mca_ras_block *ras; 39 }; 40 41 struct amdgpu_mca { 42 struct amdgpu_mca_ras mp0; 43 struct amdgpu_mca_ras mp1; 44 struct amdgpu_mca_ras mpio; 45 }; 46 47 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, 48 uint64_t mc_status_addr, 49 unsigned long *error_count); 50 void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev, 51 uint64_t mc_status_addr, 52 unsigned long *error_count); 53 void amdgpu_mca_reset_error_count(struct amdgpu_device *adev, 54 uint64_t mc_status_addr); 55 void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, 56 uint64_t mc_status_addr, 57 void *ras_error_status); 58 int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev); 59 int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev); 60 int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev); 61 62 #endif 63