1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu_ras.h" 24 #include "amdgpu.h" 25 #include "amdgpu_mca.h" 26 27 #include "umc/umc_6_7_0_offset.h" 28 #include "umc/umc_6_7_0_sh_mask.h" 29 30 static bool amdgpu_mca_is_deferred_error(struct amdgpu_device *adev, 31 uint64_t mc_status) 32 { 33 if (adev->umc.ras->check_ecc_err_status) 34 return adev->umc.ras->check_ecc_err_status(adev, 35 AMDGPU_MCA_ERROR_TYPE_DE, &mc_status); 36 37 return false; 38 } 39 40 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, 41 uint64_t mc_status_addr, 42 unsigned long *error_count) 43 { 44 uint64_t mc_status = RREG64_PCIE(mc_status_addr); 45 46 if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 47 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 48 *error_count += 1; 49 } 50 51 void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev, 52 uint64_t mc_status_addr, 53 unsigned long *error_count) 54 { 55 uint64_t mc_status = RREG64_PCIE(mc_status_addr); 56 57 if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 58 (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 59 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 60 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 61 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 62 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 63 *error_count += 1; 64 } 65 66 void amdgpu_mca_reset_error_count(struct amdgpu_device *adev, 67 uint64_t mc_status_addr) 68 { 69 WREG64_PCIE(mc_status_addr, 0x0ULL); 70 } 71 72 void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, 73 uint64_t mc_status_addr, 74 void *ras_error_status) 75 { 76 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 77 78 amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count)); 79 amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count)); 80 81 amdgpu_mca_reset_error_count(adev, mc_status_addr); 82 } 83 84 int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev) 85 { 86 int err; 87 struct amdgpu_mca_ras_block *ras; 88 89 if (!adev->mca.mp0.ras) 90 return 0; 91 92 ras = adev->mca.mp0.ras; 93 94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 95 if (err) { 96 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n"); 97 return err; 98 } 99 100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); 101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; 102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; 104 105 return 0; 106 } 107 108 int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev) 109 { 110 int err; 111 struct amdgpu_mca_ras_block *ras; 112 113 if (!adev->mca.mp1.ras) 114 return 0; 115 116 ras = adev->mca.mp1.ras; 117 118 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 119 if (err) { 120 dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n"); 121 return err; 122 } 123 124 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); 125 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; 126 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 127 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; 128 129 return 0; 130 } 131 132 int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev) 133 { 134 int err; 135 struct amdgpu_mca_ras_block *ras; 136 137 if (!adev->mca.mpio.ras) 138 return 0; 139 140 ras = adev->mca.mpio.ras; 141 142 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 143 if (err) { 144 dev_err(adev->dev, "Failed to register mca.mpio ras block!\n"); 145 return err; 146 } 147 148 strcpy(ras->ras_block.ras_comm.name, "mca.mpio"); 149 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; 150 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 151 adev->mca.mpio.ras_if = &ras->ras_block.ras_comm; 152 153 return 0; 154 } 155 156 static void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set) 157 { 158 if (!mca_set) 159 return; 160 161 memset(mca_set, 0, sizeof(*mca_set)); 162 INIT_LIST_HEAD(&mca_set->list); 163 } 164 165 static int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry) 166 { 167 struct mca_bank_node *node; 168 169 if (!entry) 170 return -EINVAL; 171 172 node = kvzalloc(sizeof(*node), GFP_KERNEL); 173 if (!node) 174 return -ENOMEM; 175 176 memcpy(&node->entry, entry, sizeof(*entry)); 177 178 INIT_LIST_HEAD(&node->node); 179 list_add_tail(&node->node, &mca_set->list); 180 181 mca_set->nr_entries++; 182 183 return 0; 184 } 185 186 static void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set) 187 { 188 struct mca_bank_node *node, *tmp; 189 190 list_for_each_entry_safe(node, tmp, &mca_set->list, node) { 191 list_del(&node->node); 192 kvfree(node); 193 } 194 } 195 196 void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs) 197 { 198 struct amdgpu_mca *mca = &adev->mca; 199 200 mca->mca_funcs = mca_funcs; 201 } 202 203 int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) 204 { 205 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 206 207 if (mca_funcs && mca_funcs->mca_set_debug_mode) 208 return mca_funcs->mca_set_debug_mode(adev, enable); 209 210 return -EOPNOTSUPP; 211 } 212 213 static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry, 214 struct ras_query_context *qctx) 215 { 216 u64 event_id = qctx->event_id; 217 218 RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n"); 219 RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n", 220 idx, entry->regs[MCA_REG_IDX_STATUS]); 221 RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].ADDR=0x%016llx\n", 222 idx, entry->regs[MCA_REG_IDX_ADDR]); 223 RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].MISC0=0x%016llx\n", 224 idx, entry->regs[MCA_REG_IDX_MISC0]); 225 RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].IPID=0x%016llx\n", 226 idx, entry->regs[MCA_REG_IDX_IPID]); 227 RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].SYND=0x%016llx\n", 228 idx, entry->regs[MCA_REG_IDX_SYND]); 229 } 230 231 static int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count) 232 { 233 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 234 235 if (!count) 236 return -EINVAL; 237 238 if (mca_funcs && mca_funcs->mca_get_valid_mca_count) 239 return mca_funcs->mca_get_valid_mca_count(adev, type, count); 240 241 return -EOPNOTSUPP; 242 } 243 244 static int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 245 int idx, struct mca_bank_entry *entry) 246 { 247 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 248 int count; 249 250 if (!mca_funcs || !mca_funcs->mca_get_mca_entry) 251 return -EOPNOTSUPP; 252 253 switch (type) { 254 case AMDGPU_MCA_ERROR_TYPE_UE: 255 count = mca_funcs->max_ue_count; 256 break; 257 case AMDGPU_MCA_ERROR_TYPE_CE: 258 count = mca_funcs->max_ce_count; 259 break; 260 default: 261 return -EINVAL; 262 } 263 264 if (idx >= count) 265 return -EINVAL; 266 267 return mca_funcs->mca_get_mca_entry(adev, type, idx, entry); 268 } 269 270 static int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set) 271 { 272 struct mca_bank_entry entry; 273 uint32_t count = 0, i; 274 int ret; 275 276 if (!mca_set) 277 return -EINVAL; 278 279 ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &count); 280 if (ret) 281 return ret; 282 283 for (i = 0; i < count; i++) { 284 memset(&entry, 0, sizeof(entry)); 285 ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, &entry); 286 if (ret) 287 return ret; 288 289 amdgpu_mca_bank_set_add_entry(mca_set, &entry); 290 } 291 292 return 0; 293 } 294 295 static int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 296 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count) 297 { 298 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 299 300 if (!count || !entry) 301 return -EINVAL; 302 303 if (!mca_funcs || !mca_funcs->mca_parse_mca_error_count) 304 return -EOPNOTSUPP; 305 306 return mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, count); 307 } 308 309 int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, 310 struct ras_err_data *err_data, struct ras_query_context *qctx) 311 { 312 struct amdgpu_smuio_mcm_config_info mcm_info; 313 struct ras_err_addr err_addr = {0}; 314 struct mca_bank_set mca_set; 315 struct mca_bank_node *node; 316 struct mca_bank_entry *entry; 317 uint32_t count; 318 int ret, i = 0; 319 320 amdgpu_mca_bank_set_init(&mca_set); 321 322 ret = amdgpu_mca_smu_get_mca_set(adev, type, &mca_set); 323 if (ret) 324 goto out_mca_release; 325 326 list_for_each_entry(node, &mca_set.list, node) { 327 entry = &node->entry; 328 329 amdgpu_mca_smu_mca_bank_dump(adev, i++, entry, qctx); 330 331 count = 0; 332 ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &count); 333 if (ret) 334 goto out_mca_release; 335 336 if (!count) 337 continue; 338 339 mcm_info.socket_id = entry->info.socket_id; 340 mcm_info.die_id = entry->info.aid; 341 342 if (blk == AMDGPU_RAS_BLOCK__UMC) { 343 err_addr.err_status = entry->regs[MCA_REG_IDX_STATUS]; 344 err_addr.err_ipid = entry->regs[MCA_REG_IDX_IPID]; 345 err_addr.err_addr = entry->regs[MCA_REG_IDX_ADDR]; 346 } 347 348 if (type == AMDGPU_MCA_ERROR_TYPE_UE) 349 amdgpu_ras_error_statistic_ue_count(err_data, 350 &mcm_info, &err_addr, (uint64_t)count); 351 else { 352 if (amdgpu_mca_is_deferred_error(adev, entry->regs[MCA_REG_IDX_STATUS])) 353 amdgpu_ras_error_statistic_de_count(err_data, 354 &mcm_info, &err_addr, (uint64_t)count); 355 else 356 amdgpu_ras_error_statistic_ce_count(err_data, 357 &mcm_info, &err_addr, (uint64_t)count); 358 } 359 } 360 361 out_mca_release: 362 amdgpu_mca_bank_set_release(&mca_set); 363 364 return ret; 365 } 366 367 #if defined(CONFIG_DEBUG_FS) 368 static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val) 369 { 370 struct amdgpu_device *adev = (struct amdgpu_device *)data; 371 int ret; 372 373 ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false); 374 if (ret) 375 return ret; 376 377 dev_info(adev->dev, "amdgpu set smu mca debug mode %s success\n", val ? "on" : "off"); 378 379 return 0; 380 } 381 382 static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry) 383 { 384 int i, idx = entry->idx; 385 int reg_idx_array[] = { 386 MCA_REG_IDX_STATUS, 387 MCA_REG_IDX_ADDR, 388 MCA_REG_IDX_MISC0, 389 MCA_REG_IDX_IPID, 390 MCA_REG_IDX_SYND, 391 }; 392 393 seq_printf(m, "mca entry[%d].type: %s\n", idx, entry->type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE"); 394 seq_printf(m, "mca entry[%d].ip: %d\n", idx, entry->ip); 395 seq_printf(m, "mca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n", 396 idx, entry->info.socket_id, entry->info.aid, entry->info.hwid, entry->info.mcatype); 397 398 for (i = 0; i < ARRAY_SIZE(reg_idx_array); i++) 399 seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, reg_idx_array[i], entry->regs[reg_idx_array[i]]); 400 } 401 402 static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type) 403 { 404 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 405 struct mca_bank_entry *entry; 406 uint32_t count = 0; 407 int i, ret; 408 409 ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &count); 410 if (ret) 411 return ret; 412 413 seq_printf(m, "amdgpu smu %s valid mca count: %d\n", 414 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", count); 415 416 if (!count) 417 return 0; 418 419 entry = kmalloc(sizeof(*entry), GFP_KERNEL); 420 if (!entry) 421 return -ENOMEM; 422 423 for (i = 0; i < count; i++) { 424 memset(entry, 0, sizeof(*entry)); 425 426 ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, entry); 427 if (ret) 428 goto err_free_entry; 429 430 mca_dump_entry(m, entry); 431 } 432 433 err_free_entry: 434 kfree(entry); 435 436 return ret; 437 } 438 439 static int mca_dump_ce_show(struct seq_file *m, void *unused) 440 { 441 return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_CE); 442 } 443 444 static int mca_dump_ce_open(struct inode *inode, struct file *file) 445 { 446 return single_open(file, mca_dump_ce_show, inode->i_private); 447 } 448 449 static const struct file_operations mca_ce_dump_debug_fops = { 450 .owner = THIS_MODULE, 451 .open = mca_dump_ce_open, 452 .read = seq_read, 453 .llseek = seq_lseek, 454 .release = single_release, 455 }; 456 457 static int mca_dump_ue_show(struct seq_file *m, void *unused) 458 { 459 return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_UE); 460 } 461 462 static int mca_dump_ue_open(struct inode *inode, struct file *file) 463 { 464 return single_open(file, mca_dump_ue_show, inode->i_private); 465 } 466 467 static const struct file_operations mca_ue_dump_debug_fops = { 468 .owner = THIS_MODULE, 469 .open = mca_dump_ue_open, 470 .read = seq_read, 471 .llseek = seq_lseek, 472 .release = single_release, 473 }; 474 475 DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); 476 #endif 477 478 void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) 479 { 480 #if defined(CONFIG_DEBUG_FS) 481 if (!root || amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6)) 482 return; 483 484 debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); 485 debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); 486 debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); 487 #endif 488 } 489 490