1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu_sched.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/pm_runtime.h> 39 #include "amdgpu_amdkfd.h" 40 41 /** 42 * amdgpu_driver_unload_kms - Main unload function for KMS. 43 * 44 * @dev: drm dev pointer 45 * 46 * This is the main unload function for KMS (all asics). 47 * Returns 0 on success. 48 */ 49 void amdgpu_driver_unload_kms(struct drm_device *dev) 50 { 51 struct amdgpu_device *adev = dev->dev_private; 52 53 if (adev == NULL) 54 return; 55 56 if (adev->rmmio == NULL) 57 goto done_free; 58 59 if (amdgpu_sriov_vf(adev)) 60 amdgpu_virt_request_full_gpu(adev, false); 61 62 if (amdgpu_device_is_px(dev)) { 63 pm_runtime_get_sync(dev->dev); 64 pm_runtime_forbid(dev->dev); 65 } 66 67 amdgpu_acpi_fini(adev); 68 69 amdgpu_device_fini(adev); 70 71 done_free: 72 kfree(adev); 73 dev->dev_private = NULL; 74 } 75 76 /** 77 * amdgpu_driver_load_kms - Main load function for KMS. 78 * 79 * @dev: drm dev pointer 80 * @flags: device flags 81 * 82 * This is the main load function for KMS (all asics). 83 * Returns 0 on success, error on failure. 84 */ 85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 86 { 87 struct amdgpu_device *adev; 88 int r, acpi_status; 89 90 #ifdef CONFIG_DRM_AMDGPU_SI 91 if (!amdgpu_si_support) { 92 switch (flags & AMD_ASIC_MASK) { 93 case CHIP_TAHITI: 94 case CHIP_PITCAIRN: 95 case CHIP_VERDE: 96 case CHIP_OLAND: 97 case CHIP_HAINAN: 98 dev_info(dev->dev, 99 "SI support provided by radeon.\n"); 100 dev_info(dev->dev, 101 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 102 ); 103 return -ENODEV; 104 } 105 } 106 #endif 107 #ifdef CONFIG_DRM_AMDGPU_CIK 108 if (!amdgpu_cik_support) { 109 switch (flags & AMD_ASIC_MASK) { 110 case CHIP_KAVERI: 111 case CHIP_BONAIRE: 112 case CHIP_HAWAII: 113 case CHIP_KABINI: 114 case CHIP_MULLINS: 115 dev_info(dev->dev, 116 "CIK support provided by radeon.\n"); 117 dev_info(dev->dev, 118 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 119 ); 120 return -ENODEV; 121 } 122 } 123 #endif 124 125 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 126 if (adev == NULL) { 127 return -ENOMEM; 128 } 129 dev->dev_private = (void *)adev; 130 131 if ((amdgpu_runtime_pm != 0) && 132 amdgpu_has_atpx() && 133 (amdgpu_is_atpx_hybrid() || 134 amdgpu_has_atpx_dgpu_power_cntl()) && 135 ((flags & AMD_IS_APU) == 0) && 136 !pci_is_thunderbolt_attached(dev->pdev)) 137 flags |= AMD_IS_PX; 138 139 /* amdgpu_device_init should report only fatal error 140 * like memory allocation failure or iomapping failure, 141 * or memory manager initialization failure, it must 142 * properly initialize the GPU MC controller and permit 143 * VRAM allocation 144 */ 145 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 146 if (r) { 147 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 148 goto out; 149 } 150 151 /* Call ACPI methods: require modeset init 152 * but failure is not fatal 153 */ 154 if (!r) { 155 acpi_status = amdgpu_acpi_init(adev); 156 if (acpi_status) 157 dev_dbg(&dev->pdev->dev, 158 "Error during ACPI methods call\n"); 159 } 160 161 if (amdgpu_device_is_px(dev)) { 162 pm_runtime_use_autosuspend(dev->dev); 163 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 164 pm_runtime_set_active(dev->dev); 165 pm_runtime_allow(dev->dev); 166 pm_runtime_mark_last_busy(dev->dev); 167 pm_runtime_put_autosuspend(dev->dev); 168 } 169 170 out: 171 if (r) { 172 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 173 if (adev->rmmio && amdgpu_device_is_px(dev)) 174 pm_runtime_put_noidle(dev->dev); 175 amdgpu_driver_unload_kms(dev); 176 } 177 178 return r; 179 } 180 181 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 182 struct drm_amdgpu_query_fw *query_fw, 183 struct amdgpu_device *adev) 184 { 185 switch (query_fw->fw_type) { 186 case AMDGPU_INFO_FW_VCE: 187 fw_info->ver = adev->vce.fw_version; 188 fw_info->feature = adev->vce.fb_version; 189 break; 190 case AMDGPU_INFO_FW_UVD: 191 fw_info->ver = adev->uvd.fw_version; 192 fw_info->feature = 0; 193 break; 194 case AMDGPU_INFO_FW_VCN: 195 fw_info->ver = adev->vcn.fw_version; 196 fw_info->feature = 0; 197 break; 198 case AMDGPU_INFO_FW_GMC: 199 fw_info->ver = adev->gmc.fw_version; 200 fw_info->feature = 0; 201 break; 202 case AMDGPU_INFO_FW_GFX_ME: 203 fw_info->ver = adev->gfx.me_fw_version; 204 fw_info->feature = adev->gfx.me_feature_version; 205 break; 206 case AMDGPU_INFO_FW_GFX_PFP: 207 fw_info->ver = adev->gfx.pfp_fw_version; 208 fw_info->feature = adev->gfx.pfp_feature_version; 209 break; 210 case AMDGPU_INFO_FW_GFX_CE: 211 fw_info->ver = adev->gfx.ce_fw_version; 212 fw_info->feature = adev->gfx.ce_feature_version; 213 break; 214 case AMDGPU_INFO_FW_GFX_RLC: 215 fw_info->ver = adev->gfx.rlc_fw_version; 216 fw_info->feature = adev->gfx.rlc_feature_version; 217 break; 218 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 219 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 220 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 221 break; 222 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 223 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 224 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 225 break; 226 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 227 fw_info->ver = adev->gfx.rlc_srls_fw_version; 228 fw_info->feature = adev->gfx.rlc_srls_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_MEC: 231 if (query_fw->index == 0) { 232 fw_info->ver = adev->gfx.mec_fw_version; 233 fw_info->feature = adev->gfx.mec_feature_version; 234 } else if (query_fw->index == 1) { 235 fw_info->ver = adev->gfx.mec2_fw_version; 236 fw_info->feature = adev->gfx.mec2_feature_version; 237 } else 238 return -EINVAL; 239 break; 240 case AMDGPU_INFO_FW_SMC: 241 fw_info->ver = adev->pm.fw_version; 242 fw_info->feature = 0; 243 break; 244 case AMDGPU_INFO_FW_SDMA: 245 if (query_fw->index >= adev->sdma.num_instances) 246 return -EINVAL; 247 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 248 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 249 break; 250 case AMDGPU_INFO_FW_SOS: 251 fw_info->ver = adev->psp.sos_fw_version; 252 fw_info->feature = adev->psp.sos_feature_version; 253 break; 254 case AMDGPU_INFO_FW_ASD: 255 fw_info->ver = adev->psp.asd_fw_version; 256 fw_info->feature = adev->psp.asd_feature_version; 257 break; 258 default: 259 return -EINVAL; 260 } 261 return 0; 262 } 263 264 /* 265 * Userspace get information ioctl 266 */ 267 /** 268 * amdgpu_info_ioctl - answer a device specific request. 269 * 270 * @adev: amdgpu device pointer 271 * @data: request object 272 * @filp: drm filp 273 * 274 * This function is used to pass device specific parameters to the userspace 275 * drivers. Examples include: pci device id, pipeline parms, tiling params, 276 * etc. (all asics). 277 * Returns 0 on success, -EINVAL on failure. 278 */ 279 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 280 { 281 struct amdgpu_device *adev = dev->dev_private; 282 struct drm_amdgpu_info *info = data; 283 struct amdgpu_mode_info *minfo = &adev->mode_info; 284 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 285 uint32_t size = info->return_size; 286 struct drm_crtc *crtc; 287 uint32_t ui32 = 0; 288 uint64_t ui64 = 0; 289 int i, found; 290 int ui32_size = sizeof(ui32); 291 292 if (!info->return_size || !info->return_pointer) 293 return -EINVAL; 294 295 /* Ensure IB tests are run on ring */ 296 flush_delayed_work(&adev->late_init_work); 297 298 switch (info->query) { 299 case AMDGPU_INFO_ACCEL_WORKING: 300 ui32 = adev->accel_working; 301 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 302 case AMDGPU_INFO_CRTC_FROM_ID: 303 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 304 crtc = (struct drm_crtc *)minfo->crtcs[i]; 305 if (crtc && crtc->base.id == info->mode_crtc.id) { 306 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 307 ui32 = amdgpu_crtc->crtc_id; 308 found = 1; 309 break; 310 } 311 } 312 if (!found) { 313 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 314 return -EINVAL; 315 } 316 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 317 case AMDGPU_INFO_HW_IP_INFO: { 318 struct drm_amdgpu_info_hw_ip ip = {}; 319 enum amd_ip_block_type type; 320 uint32_t ring_mask = 0; 321 uint32_t ib_start_alignment = 0; 322 uint32_t ib_size_alignment = 0; 323 324 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 325 return -EINVAL; 326 327 switch (info->query_hw_ip.type) { 328 case AMDGPU_HW_IP_GFX: 329 type = AMD_IP_BLOCK_TYPE_GFX; 330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 331 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 332 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 333 ib_size_alignment = 8; 334 break; 335 case AMDGPU_HW_IP_COMPUTE: 336 type = AMD_IP_BLOCK_TYPE_GFX; 337 for (i = 0; i < adev->gfx.num_compute_rings; i++) 338 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 339 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 340 ib_size_alignment = 8; 341 break; 342 case AMDGPU_HW_IP_DMA: 343 type = AMD_IP_BLOCK_TYPE_SDMA; 344 for (i = 0; i < adev->sdma.num_instances; i++) 345 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 346 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 347 ib_size_alignment = 1; 348 break; 349 case AMDGPU_HW_IP_UVD: 350 type = AMD_IP_BLOCK_TYPE_UVD; 351 ring_mask = adev->uvd.ring.ready ? 1 : 0; 352 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 353 ib_size_alignment = 16; 354 break; 355 case AMDGPU_HW_IP_VCE: 356 type = AMD_IP_BLOCK_TYPE_VCE; 357 for (i = 0; i < adev->vce.num_rings; i++) 358 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 359 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 360 ib_size_alignment = 1; 361 break; 362 case AMDGPU_HW_IP_UVD_ENC: 363 type = AMD_IP_BLOCK_TYPE_UVD; 364 for (i = 0; i < adev->uvd.num_enc_rings; i++) 365 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); 366 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 367 ib_size_alignment = 1; 368 break; 369 case AMDGPU_HW_IP_VCN_DEC: 370 type = AMD_IP_BLOCK_TYPE_VCN; 371 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; 372 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 373 ib_size_alignment = 16; 374 break; 375 case AMDGPU_HW_IP_VCN_ENC: 376 type = AMD_IP_BLOCK_TYPE_VCN; 377 for (i = 0; i < adev->vcn.num_enc_rings; i++) 378 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); 379 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 380 ib_size_alignment = 1; 381 break; 382 default: 383 return -EINVAL; 384 } 385 386 for (i = 0; i < adev->num_ip_blocks; i++) { 387 if (adev->ip_blocks[i].version->type == type && 388 adev->ip_blocks[i].status.valid) { 389 ip.hw_ip_version_major = adev->ip_blocks[i].version->major; 390 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; 391 ip.capabilities_flags = 0; 392 ip.available_rings = ring_mask; 393 ip.ib_start_alignment = ib_start_alignment; 394 ip.ib_size_alignment = ib_size_alignment; 395 break; 396 } 397 } 398 return copy_to_user(out, &ip, 399 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 400 } 401 case AMDGPU_INFO_HW_IP_COUNT: { 402 enum amd_ip_block_type type; 403 uint32_t count = 0; 404 405 switch (info->query_hw_ip.type) { 406 case AMDGPU_HW_IP_GFX: 407 type = AMD_IP_BLOCK_TYPE_GFX; 408 break; 409 case AMDGPU_HW_IP_COMPUTE: 410 type = AMD_IP_BLOCK_TYPE_GFX; 411 break; 412 case AMDGPU_HW_IP_DMA: 413 type = AMD_IP_BLOCK_TYPE_SDMA; 414 break; 415 case AMDGPU_HW_IP_UVD: 416 type = AMD_IP_BLOCK_TYPE_UVD; 417 break; 418 case AMDGPU_HW_IP_VCE: 419 type = AMD_IP_BLOCK_TYPE_VCE; 420 break; 421 case AMDGPU_HW_IP_UVD_ENC: 422 type = AMD_IP_BLOCK_TYPE_UVD; 423 break; 424 case AMDGPU_HW_IP_VCN_DEC: 425 case AMDGPU_HW_IP_VCN_ENC: 426 type = AMD_IP_BLOCK_TYPE_VCN; 427 break; 428 default: 429 return -EINVAL; 430 } 431 432 for (i = 0; i < adev->num_ip_blocks; i++) 433 if (adev->ip_blocks[i].version->type == type && 434 adev->ip_blocks[i].status.valid && 435 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 436 count++; 437 438 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 439 } 440 case AMDGPU_INFO_TIMESTAMP: 441 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 442 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 443 case AMDGPU_INFO_FW_VERSION: { 444 struct drm_amdgpu_info_firmware fw_info; 445 int ret; 446 447 /* We only support one instance of each IP block right now. */ 448 if (info->query_fw.ip_instance != 0) 449 return -EINVAL; 450 451 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 452 if (ret) 453 return ret; 454 455 return copy_to_user(out, &fw_info, 456 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 457 } 458 case AMDGPU_INFO_NUM_BYTES_MOVED: 459 ui64 = atomic64_read(&adev->num_bytes_moved); 460 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 461 case AMDGPU_INFO_NUM_EVICTIONS: 462 ui64 = atomic64_read(&adev->num_evictions); 463 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 464 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 465 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 466 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 467 case AMDGPU_INFO_VRAM_USAGE: 468 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 469 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 470 case AMDGPU_INFO_VIS_VRAM_USAGE: 471 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 472 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 473 case AMDGPU_INFO_GTT_USAGE: 474 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 475 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 476 case AMDGPU_INFO_GDS_CONFIG: { 477 struct drm_amdgpu_info_gds gds_info; 478 479 memset(&gds_info, 0, sizeof(gds_info)); 480 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 481 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 482 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 483 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 484 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 485 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 486 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 487 return copy_to_user(out, &gds_info, 488 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 489 } 490 case AMDGPU_INFO_VRAM_GTT: { 491 struct drm_amdgpu_info_vram_gtt vram_gtt; 492 493 vram_gtt.vram_size = adev->gmc.real_vram_size; 494 vram_gtt.vram_size -= adev->vram_pin_size; 495 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; 496 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); 497 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 498 vram_gtt.gtt_size *= PAGE_SIZE; 499 vram_gtt.gtt_size -= adev->gart_pin_size; 500 return copy_to_user(out, &vram_gtt, 501 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 502 } 503 case AMDGPU_INFO_MEMORY: { 504 struct drm_amdgpu_memory_info mem; 505 506 memset(&mem, 0, sizeof(mem)); 507 mem.vram.total_heap_size = adev->gmc.real_vram_size; 508 mem.vram.usable_heap_size = 509 adev->gmc.real_vram_size - adev->vram_pin_size; 510 mem.vram.heap_usage = 511 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 512 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 513 514 mem.cpu_accessible_vram.total_heap_size = 515 adev->gmc.visible_vram_size; 516 mem.cpu_accessible_vram.usable_heap_size = 517 adev->gmc.visible_vram_size - 518 (adev->vram_pin_size - adev->invisible_pin_size); 519 mem.cpu_accessible_vram.heap_usage = 520 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 521 mem.cpu_accessible_vram.max_allocation = 522 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 523 524 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 525 mem.gtt.total_heap_size *= PAGE_SIZE; 526 mem.gtt.usable_heap_size = mem.gtt.total_heap_size 527 - adev->gart_pin_size; 528 mem.gtt.heap_usage = 529 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 530 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 531 532 return copy_to_user(out, &mem, 533 min((size_t)size, sizeof(mem))) 534 ? -EFAULT : 0; 535 } 536 case AMDGPU_INFO_READ_MMR_REG: { 537 unsigned n, alloc_size; 538 uint32_t *regs; 539 unsigned se_num = (info->read_mmr_reg.instance >> 540 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 541 AMDGPU_INFO_MMR_SE_INDEX_MASK; 542 unsigned sh_num = (info->read_mmr_reg.instance >> 543 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 544 AMDGPU_INFO_MMR_SH_INDEX_MASK; 545 546 /* set full masks if the userspace set all bits 547 * in the bitfields */ 548 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 549 se_num = 0xffffffff; 550 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 551 sh_num = 0xffffffff; 552 553 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 554 if (!regs) 555 return -ENOMEM; 556 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 557 558 for (i = 0; i < info->read_mmr_reg.count; i++) 559 if (amdgpu_asic_read_register(adev, se_num, sh_num, 560 info->read_mmr_reg.dword_offset + i, 561 ®s[i])) { 562 DRM_DEBUG_KMS("unallowed offset %#x\n", 563 info->read_mmr_reg.dword_offset + i); 564 kfree(regs); 565 return -EFAULT; 566 } 567 n = copy_to_user(out, regs, min(size, alloc_size)); 568 kfree(regs); 569 return n ? -EFAULT : 0; 570 } 571 case AMDGPU_INFO_DEV_INFO: { 572 struct drm_amdgpu_info_device dev_info = {}; 573 uint64_t vm_size; 574 575 dev_info.device_id = dev->pdev->device; 576 dev_info.chip_rev = adev->rev_id; 577 dev_info.external_rev = adev->external_rev_id; 578 dev_info.pci_rev = dev->pdev->revision; 579 dev_info.family = adev->family; 580 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 581 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 582 /* return all clocks in KHz */ 583 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 584 if (adev->pm.dpm_enabled) { 585 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 586 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 587 } else { 588 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 589 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 590 } 591 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 592 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 593 adev->gfx.config.max_shader_engines; 594 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 595 dev_info._pad = 0; 596 dev_info.ids_flags = 0; 597 if (adev->flags & AMD_IS_APU) 598 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 599 if (amdgpu_sriov_vf(adev)) 600 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 601 602 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 603 vm_size -= AMDGPU_VA_RESERVED_SIZE; 604 605 /* Older VCE FW versions are buggy and can handle only 40bits */ 606 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 607 vm_size = min(vm_size, 1ULL << 40); 608 609 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 610 dev_info.virtual_address_max = 611 min(vm_size, AMDGPU_VA_HOLE_START); 612 613 if (vm_size > AMDGPU_VA_HOLE_START) { 614 dev_info.high_va_offset = AMDGPU_VA_HOLE_END; 615 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; 616 } 617 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 618 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 619 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 620 dev_info.cu_active_number = adev->gfx.cu_info.number; 621 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 622 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 623 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 624 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 625 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 626 sizeof(adev->gfx.cu_info.bitmap)); 627 dev_info.vram_type = adev->gmc.vram_type; 628 dev_info.vram_bit_width = adev->gmc.vram_width; 629 dev_info.vce_harvest_config = adev->vce.harvest_config; 630 dev_info.gc_double_offchip_lds_buf = 631 adev->gfx.config.double_offchip_lds_buf; 632 633 if (amdgpu_ngg) { 634 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr; 635 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size; 636 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr; 637 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size; 638 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr; 639 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size; 640 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr; 641 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size; 642 } 643 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 644 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 645 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 646 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 647 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 648 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 649 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 650 651 return copy_to_user(out, &dev_info, 652 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 653 } 654 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 655 unsigned i; 656 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 657 struct amd_vce_state *vce_state; 658 659 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 660 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 661 if (vce_state) { 662 vce_clk_table.entries[i].sclk = vce_state->sclk; 663 vce_clk_table.entries[i].mclk = vce_state->mclk; 664 vce_clk_table.entries[i].eclk = vce_state->evclk; 665 vce_clk_table.num_valid_entries++; 666 } 667 } 668 669 return copy_to_user(out, &vce_clk_table, 670 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 671 } 672 case AMDGPU_INFO_VBIOS: { 673 uint32_t bios_size = adev->bios_size; 674 675 switch (info->vbios_info.type) { 676 case AMDGPU_INFO_VBIOS_SIZE: 677 return copy_to_user(out, &bios_size, 678 min((size_t)size, sizeof(bios_size))) 679 ? -EFAULT : 0; 680 case AMDGPU_INFO_VBIOS_IMAGE: { 681 uint8_t *bios; 682 uint32_t bios_offset = info->vbios_info.offset; 683 684 if (bios_offset >= bios_size) 685 return -EINVAL; 686 687 bios = adev->bios + bios_offset; 688 return copy_to_user(out, bios, 689 min((size_t)size, (size_t)(bios_size - bios_offset))) 690 ? -EFAULT : 0; 691 } 692 default: 693 DRM_DEBUG_KMS("Invalid request %d\n", 694 info->vbios_info.type); 695 return -EINVAL; 696 } 697 } 698 case AMDGPU_INFO_NUM_HANDLES: { 699 struct drm_amdgpu_info_num_handles handle; 700 701 switch (info->query_hw_ip.type) { 702 case AMDGPU_HW_IP_UVD: 703 /* Starting Polaris, we support unlimited UVD handles */ 704 if (adev->asic_type < CHIP_POLARIS10) { 705 handle.uvd_max_handles = adev->uvd.max_handles; 706 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 707 708 return copy_to_user(out, &handle, 709 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 710 } else { 711 return -ENODATA; 712 } 713 714 break; 715 default: 716 return -EINVAL; 717 } 718 } 719 case AMDGPU_INFO_SENSOR: { 720 if (!adev->pm.dpm_enabled) 721 return -ENOENT; 722 723 switch (info->sensor_info.type) { 724 case AMDGPU_INFO_SENSOR_GFX_SCLK: 725 /* get sclk in Mhz */ 726 if (amdgpu_dpm_read_sensor(adev, 727 AMDGPU_PP_SENSOR_GFX_SCLK, 728 (void *)&ui32, &ui32_size)) { 729 return -EINVAL; 730 } 731 ui32 /= 100; 732 break; 733 case AMDGPU_INFO_SENSOR_GFX_MCLK: 734 /* get mclk in Mhz */ 735 if (amdgpu_dpm_read_sensor(adev, 736 AMDGPU_PP_SENSOR_GFX_MCLK, 737 (void *)&ui32, &ui32_size)) { 738 return -EINVAL; 739 } 740 ui32 /= 100; 741 break; 742 case AMDGPU_INFO_SENSOR_GPU_TEMP: 743 /* get temperature in millidegrees C */ 744 if (amdgpu_dpm_read_sensor(adev, 745 AMDGPU_PP_SENSOR_GPU_TEMP, 746 (void *)&ui32, &ui32_size)) { 747 return -EINVAL; 748 } 749 break; 750 case AMDGPU_INFO_SENSOR_GPU_LOAD: 751 /* get GPU load */ 752 if (amdgpu_dpm_read_sensor(adev, 753 AMDGPU_PP_SENSOR_GPU_LOAD, 754 (void *)&ui32, &ui32_size)) { 755 return -EINVAL; 756 } 757 break; 758 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 759 /* get average GPU power */ 760 if (amdgpu_dpm_read_sensor(adev, 761 AMDGPU_PP_SENSOR_GPU_POWER, 762 (void *)&ui32, &ui32_size)) { 763 return -EINVAL; 764 } 765 ui32 >>= 8; 766 break; 767 case AMDGPU_INFO_SENSOR_VDDNB: 768 /* get VDDNB in millivolts */ 769 if (amdgpu_dpm_read_sensor(adev, 770 AMDGPU_PP_SENSOR_VDDNB, 771 (void *)&ui32, &ui32_size)) { 772 return -EINVAL; 773 } 774 break; 775 case AMDGPU_INFO_SENSOR_VDDGFX: 776 /* get VDDGFX in millivolts */ 777 if (amdgpu_dpm_read_sensor(adev, 778 AMDGPU_PP_SENSOR_VDDGFX, 779 (void *)&ui32, &ui32_size)) { 780 return -EINVAL; 781 } 782 break; 783 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 784 /* get stable pstate sclk in Mhz */ 785 if (amdgpu_dpm_read_sensor(adev, 786 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 787 (void *)&ui32, &ui32_size)) { 788 return -EINVAL; 789 } 790 ui32 /= 100; 791 break; 792 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 793 /* get stable pstate mclk in Mhz */ 794 if (amdgpu_dpm_read_sensor(adev, 795 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 796 (void *)&ui32, &ui32_size)) { 797 return -EINVAL; 798 } 799 ui32 /= 100; 800 break; 801 default: 802 DRM_DEBUG_KMS("Invalid request %d\n", 803 info->sensor_info.type); 804 return -EINVAL; 805 } 806 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 807 } 808 case AMDGPU_INFO_VRAM_LOST_COUNTER: 809 ui32 = atomic_read(&adev->vram_lost_counter); 810 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 811 default: 812 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 813 return -EINVAL; 814 } 815 return 0; 816 } 817 818 819 /* 820 * Outdated mess for old drm with Xorg being in charge (void function now). 821 */ 822 /** 823 * amdgpu_driver_lastclose_kms - drm callback for last close 824 * 825 * @dev: drm dev pointer 826 * 827 * Switch vga_switcheroo state after last close (all asics). 828 */ 829 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 830 { 831 drm_fb_helper_lastclose(dev); 832 vga_switcheroo_process_delayed_switch(); 833 } 834 835 /** 836 * amdgpu_driver_open_kms - drm callback for open 837 * 838 * @dev: drm dev pointer 839 * @file_priv: drm file 840 * 841 * On device open, init vm on cayman+ (all asics). 842 * Returns 0 on success, error on failure. 843 */ 844 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 845 { 846 struct amdgpu_device *adev = dev->dev_private; 847 struct amdgpu_fpriv *fpriv; 848 int r, pasid; 849 850 file_priv->driver_priv = NULL; 851 852 r = pm_runtime_get_sync(dev->dev); 853 if (r < 0) 854 return r; 855 856 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 857 if (unlikely(!fpriv)) { 858 r = -ENOMEM; 859 goto out_suspend; 860 } 861 862 pasid = amdgpu_pasid_alloc(16); 863 if (pasid < 0) { 864 dev_warn(adev->dev, "No more PASIDs available!"); 865 pasid = 0; 866 } 867 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 868 if (r) 869 goto error_pasid; 870 871 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 872 if (!fpriv->prt_va) { 873 r = -ENOMEM; 874 goto error_vm; 875 } 876 877 if (amdgpu_sriov_vf(adev)) { 878 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); 879 if (r) 880 goto error_vm; 881 } 882 883 mutex_init(&fpriv->bo_list_lock); 884 idr_init(&fpriv->bo_list_handles); 885 886 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 887 888 file_priv->driver_priv = fpriv; 889 goto out_suspend; 890 891 error_vm: 892 amdgpu_vm_fini(adev, &fpriv->vm); 893 894 error_pasid: 895 if (pasid) 896 amdgpu_pasid_free(pasid); 897 898 kfree(fpriv); 899 900 out_suspend: 901 pm_runtime_mark_last_busy(dev->dev); 902 pm_runtime_put_autosuspend(dev->dev); 903 904 return r; 905 } 906 907 /** 908 * amdgpu_driver_postclose_kms - drm callback for post close 909 * 910 * @dev: drm dev pointer 911 * @file_priv: drm file 912 * 913 * On device post close, tear down vm on cayman+ (all asics). 914 */ 915 void amdgpu_driver_postclose_kms(struct drm_device *dev, 916 struct drm_file *file_priv) 917 { 918 struct amdgpu_device *adev = dev->dev_private; 919 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 920 struct amdgpu_bo_list *list; 921 struct amdgpu_bo *pd; 922 unsigned int pasid; 923 int handle; 924 925 if (!fpriv) 926 return; 927 928 pm_runtime_get_sync(dev->dev); 929 amdgpu_ctx_mgr_entity_fini(&fpriv->ctx_mgr); 930 931 if (adev->asic_type != CHIP_RAVEN) { 932 amdgpu_uvd_free_handles(adev, file_priv); 933 amdgpu_vce_free_handles(adev, file_priv); 934 } 935 936 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 937 938 if (amdgpu_sriov_vf(adev)) { 939 /* TODO: how to handle reserve failure */ 940 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 941 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 942 fpriv->csa_va = NULL; 943 amdgpu_bo_unreserve(adev->virt.csa_obj); 944 } 945 946 pasid = fpriv->vm.pasid; 947 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 948 949 amdgpu_vm_fini(adev, &fpriv->vm); 950 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 951 952 if (pasid) 953 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); 954 amdgpu_bo_unref(&pd); 955 956 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 957 amdgpu_bo_list_free(list); 958 959 idr_destroy(&fpriv->bo_list_handles); 960 mutex_destroy(&fpriv->bo_list_lock); 961 962 kfree(fpriv); 963 file_priv->driver_priv = NULL; 964 965 pm_runtime_mark_last_busy(dev->dev); 966 pm_runtime_put_autosuspend(dev->dev); 967 } 968 969 /* 970 * VBlank related functions. 971 */ 972 /** 973 * amdgpu_get_vblank_counter_kms - get frame count 974 * 975 * @dev: drm dev pointer 976 * @pipe: crtc to get the frame count from 977 * 978 * Gets the frame count on the requested crtc (all asics). 979 * Returns frame count on success, -EINVAL on failure. 980 */ 981 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 982 { 983 struct amdgpu_device *adev = dev->dev_private; 984 int vpos, hpos, stat; 985 u32 count; 986 987 if (pipe >= adev->mode_info.num_crtc) { 988 DRM_ERROR("Invalid crtc %u\n", pipe); 989 return -EINVAL; 990 } 991 992 /* The hw increments its frame counter at start of vsync, not at start 993 * of vblank, as is required by DRM core vblank counter handling. 994 * Cook the hw count here to make it appear to the caller as if it 995 * incremented at start of vblank. We measure distance to start of 996 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 997 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 998 * result by 1 to give the proper appearance to caller. 999 */ 1000 if (adev->mode_info.crtcs[pipe]) { 1001 /* Repeat readout if needed to provide stable result if 1002 * we cross start of vsync during the queries. 1003 */ 1004 do { 1005 count = amdgpu_display_vblank_get_counter(adev, pipe); 1006 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1007 * vpos as distance to start of vblank, instead of 1008 * regular vertical scanout pos. 1009 */ 1010 stat = amdgpu_display_get_crtc_scanoutpos( 1011 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1012 &vpos, &hpos, NULL, NULL, 1013 &adev->mode_info.crtcs[pipe]->base.hwmode); 1014 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1015 1016 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1017 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1018 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1019 } else { 1020 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1021 pipe, vpos); 1022 1023 /* Bump counter if we are at >= leading edge of vblank, 1024 * but before vsync where vpos would turn negative and 1025 * the hw counter really increments. 1026 */ 1027 if (vpos >= 0) 1028 count++; 1029 } 1030 } else { 1031 /* Fallback to use value as is. */ 1032 count = amdgpu_display_vblank_get_counter(adev, pipe); 1033 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1034 } 1035 1036 return count; 1037 } 1038 1039 /** 1040 * amdgpu_enable_vblank_kms - enable vblank interrupt 1041 * 1042 * @dev: drm dev pointer 1043 * @pipe: crtc to enable vblank interrupt for 1044 * 1045 * Enable the interrupt on the requested crtc (all asics). 1046 * Returns 0 on success, -EINVAL on failure. 1047 */ 1048 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1049 { 1050 struct amdgpu_device *adev = dev->dev_private; 1051 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1052 1053 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1054 } 1055 1056 /** 1057 * amdgpu_disable_vblank_kms - disable vblank interrupt 1058 * 1059 * @dev: drm dev pointer 1060 * @pipe: crtc to disable vblank interrupt for 1061 * 1062 * Disable the interrupt on the requested crtc (all asics). 1063 */ 1064 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 1065 { 1066 struct amdgpu_device *adev = dev->dev_private; 1067 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1068 1069 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1070 } 1071 1072 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1073 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1074 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1075 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1076 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1077 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1078 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1079 /* KMS */ 1080 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1081 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1082 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1083 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1084 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1085 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1086 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1087 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1088 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1089 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1090 }; 1091 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1092 1093 /* 1094 * Debugfs info 1095 */ 1096 #if defined(CONFIG_DEBUG_FS) 1097 1098 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1099 { 1100 struct drm_info_node *node = (struct drm_info_node *) m->private; 1101 struct drm_device *dev = node->minor->dev; 1102 struct amdgpu_device *adev = dev->dev_private; 1103 struct drm_amdgpu_info_firmware fw_info; 1104 struct drm_amdgpu_query_fw query_fw; 1105 struct atom_context *ctx = adev->mode_info.atom_context; 1106 int ret, i; 1107 1108 /* VCE */ 1109 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1110 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1111 if (ret) 1112 return ret; 1113 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1114 fw_info.feature, fw_info.ver); 1115 1116 /* UVD */ 1117 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1118 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1119 if (ret) 1120 return ret; 1121 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1122 fw_info.feature, fw_info.ver); 1123 1124 /* GMC */ 1125 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1126 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1127 if (ret) 1128 return ret; 1129 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1130 fw_info.feature, fw_info.ver); 1131 1132 /* ME */ 1133 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1134 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1135 if (ret) 1136 return ret; 1137 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1138 fw_info.feature, fw_info.ver); 1139 1140 /* PFP */ 1141 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1142 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1143 if (ret) 1144 return ret; 1145 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1146 fw_info.feature, fw_info.ver); 1147 1148 /* CE */ 1149 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1150 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1151 if (ret) 1152 return ret; 1153 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1154 fw_info.feature, fw_info.ver); 1155 1156 /* RLC */ 1157 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1158 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1159 if (ret) 1160 return ret; 1161 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1162 fw_info.feature, fw_info.ver); 1163 1164 /* RLC SAVE RESTORE LIST CNTL */ 1165 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1166 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1167 if (ret) 1168 return ret; 1169 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1170 fw_info.feature, fw_info.ver); 1171 1172 /* RLC SAVE RESTORE LIST GPM MEM */ 1173 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1174 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1175 if (ret) 1176 return ret; 1177 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1178 fw_info.feature, fw_info.ver); 1179 1180 /* RLC SAVE RESTORE LIST SRM MEM */ 1181 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1182 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1183 if (ret) 1184 return ret; 1185 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1186 fw_info.feature, fw_info.ver); 1187 1188 /* MEC */ 1189 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1190 query_fw.index = 0; 1191 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1192 if (ret) 1193 return ret; 1194 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1195 fw_info.feature, fw_info.ver); 1196 1197 /* MEC2 */ 1198 if (adev->asic_type == CHIP_KAVERI || 1199 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1200 query_fw.index = 1; 1201 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1202 if (ret) 1203 return ret; 1204 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1205 fw_info.feature, fw_info.ver); 1206 } 1207 1208 /* PSP SOS */ 1209 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1210 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1211 if (ret) 1212 return ret; 1213 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1214 fw_info.feature, fw_info.ver); 1215 1216 1217 /* PSP ASD */ 1218 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1219 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1220 if (ret) 1221 return ret; 1222 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1223 fw_info.feature, fw_info.ver); 1224 1225 /* SMC */ 1226 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1227 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1228 if (ret) 1229 return ret; 1230 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1231 fw_info.feature, fw_info.ver); 1232 1233 /* SDMA */ 1234 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1235 for (i = 0; i < adev->sdma.num_instances; i++) { 1236 query_fw.index = i; 1237 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1238 if (ret) 1239 return ret; 1240 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1241 i, fw_info.feature, fw_info.ver); 1242 } 1243 1244 /* VCN */ 1245 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1246 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1247 if (ret) 1248 return ret; 1249 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1250 fw_info.feature, fw_info.ver); 1251 1252 1253 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1254 1255 return 0; 1256 } 1257 1258 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1259 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1260 }; 1261 #endif 1262 1263 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1264 { 1265 #if defined(CONFIG_DEBUG_FS) 1266 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1267 ARRAY_SIZE(amdgpu_firmware_info_list)); 1268 #else 1269 return 0; 1270 #endif 1271 } 1272