1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amdgpu_reset.h" 47 #include "amd_pcie.h" 48 #include "amdgpu_userq.h" 49 50 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 51 { 52 struct amdgpu_gpu_instance *gpu_instance; 53 int i; 54 55 mutex_lock(&mgpu_info.mutex); 56 57 for (i = 0; i < mgpu_info.num_gpu; i++) { 58 gpu_instance = &(mgpu_info.gpu_ins[i]); 59 if (gpu_instance->adev == adev) { 60 mgpu_info.gpu_ins[i] = 61 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 62 mgpu_info.num_gpu--; 63 if (adev->flags & AMD_IS_APU) 64 mgpu_info.num_apu--; 65 else 66 mgpu_info.num_dgpu--; 67 break; 68 } 69 } 70 71 mutex_unlock(&mgpu_info.mutex); 72 } 73 74 /** 75 * amdgpu_driver_unload_kms - Main unload function for KMS. 76 * 77 * @dev: drm dev pointer 78 * 79 * This is the main unload function for KMS (all asics). 80 * Returns 0 on success. 81 */ 82 void amdgpu_driver_unload_kms(struct drm_device *dev) 83 { 84 struct amdgpu_device *adev = drm_to_adev(dev); 85 86 if (adev == NULL) 87 return; 88 89 amdgpu_unregister_gpu_instance(adev); 90 91 if (adev->rmmio == NULL) 92 return; 93 94 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 95 DRM_WARN("smart shift update failed\n"); 96 97 amdgpu_acpi_fini(adev); 98 amdgpu_device_fini_hw(adev); 99 } 100 101 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 102 { 103 struct amdgpu_gpu_instance *gpu_instance; 104 105 mutex_lock(&mgpu_info.mutex); 106 107 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 108 DRM_ERROR("Cannot register more gpu instance\n"); 109 mutex_unlock(&mgpu_info.mutex); 110 return; 111 } 112 113 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 114 gpu_instance->adev = adev; 115 gpu_instance->mgpu_fan_enabled = 0; 116 117 mgpu_info.num_gpu++; 118 if (adev->flags & AMD_IS_APU) 119 mgpu_info.num_apu++; 120 else 121 mgpu_info.num_dgpu++; 122 123 mutex_unlock(&mgpu_info.mutex); 124 } 125 126 /** 127 * amdgpu_driver_load_kms - Main load function for KMS. 128 * 129 * @adev: pointer to struct amdgpu_device 130 * @flags: device flags 131 * 132 * This is the main load function for KMS (all asics). 133 * Returns 0 on success, error on failure. 134 */ 135 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 136 { 137 struct drm_device *dev; 138 int r, acpi_status; 139 140 dev = adev_to_drm(adev); 141 142 /* amdgpu_device_init should report only fatal error 143 * like memory allocation failure or iomapping failure, 144 * or memory manager initialization failure, it must 145 * properly initialize the GPU MC controller and permit 146 * VRAM allocation 147 */ 148 r = amdgpu_device_init(adev, flags); 149 if (r) { 150 dev_err(dev->dev, "Fatal error during GPU init\n"); 151 goto out; 152 } 153 154 amdgpu_device_detect_runtime_pm_mode(adev); 155 156 /* Call ACPI methods: require modeset init 157 * but failure is not fatal 158 */ 159 160 acpi_status = amdgpu_acpi_init(adev); 161 if (acpi_status) 162 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 163 164 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 165 DRM_WARN("smart shift update failed\n"); 166 167 out: 168 if (r) 169 amdgpu_driver_unload_kms(dev); 170 171 return r; 172 } 173 174 static enum amd_ip_block_type 175 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 176 { 177 enum amd_ip_block_type type; 178 179 switch (ip) { 180 case AMDGPU_HW_IP_GFX: 181 type = AMD_IP_BLOCK_TYPE_GFX; 182 break; 183 case AMDGPU_HW_IP_COMPUTE: 184 type = AMD_IP_BLOCK_TYPE_GFX; 185 break; 186 case AMDGPU_HW_IP_DMA: 187 type = AMD_IP_BLOCK_TYPE_SDMA; 188 break; 189 case AMDGPU_HW_IP_UVD: 190 case AMDGPU_HW_IP_UVD_ENC: 191 type = AMD_IP_BLOCK_TYPE_UVD; 192 break; 193 case AMDGPU_HW_IP_VCE: 194 type = AMD_IP_BLOCK_TYPE_VCE; 195 break; 196 case AMDGPU_HW_IP_VCN_DEC: 197 case AMDGPU_HW_IP_VCN_ENC: 198 type = AMD_IP_BLOCK_TYPE_VCN; 199 break; 200 case AMDGPU_HW_IP_VCN_JPEG: 201 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 202 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 203 break; 204 default: 205 type = AMD_IP_BLOCK_TYPE_NUM; 206 break; 207 } 208 209 return type; 210 } 211 212 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 213 struct drm_amdgpu_query_fw *query_fw, 214 struct amdgpu_device *adev) 215 { 216 switch (query_fw->fw_type) { 217 case AMDGPU_INFO_FW_VCE: 218 fw_info->ver = adev->vce.fw_version; 219 fw_info->feature = adev->vce.fb_version; 220 break; 221 case AMDGPU_INFO_FW_UVD: 222 fw_info->ver = adev->uvd.fw_version; 223 fw_info->feature = 0; 224 break; 225 case AMDGPU_INFO_FW_VCN: 226 fw_info->ver = adev->vcn.fw_version; 227 fw_info->feature = 0; 228 break; 229 case AMDGPU_INFO_FW_GMC: 230 fw_info->ver = adev->gmc.fw_version; 231 fw_info->feature = 0; 232 break; 233 case AMDGPU_INFO_FW_GFX_ME: 234 fw_info->ver = adev->gfx.me_fw_version; 235 fw_info->feature = adev->gfx.me_feature_version; 236 break; 237 case AMDGPU_INFO_FW_GFX_PFP: 238 fw_info->ver = adev->gfx.pfp_fw_version; 239 fw_info->feature = adev->gfx.pfp_feature_version; 240 break; 241 case AMDGPU_INFO_FW_GFX_CE: 242 fw_info->ver = adev->gfx.ce_fw_version; 243 fw_info->feature = adev->gfx.ce_feature_version; 244 break; 245 case AMDGPU_INFO_FW_GFX_RLC: 246 fw_info->ver = adev->gfx.rlc_fw_version; 247 fw_info->feature = adev->gfx.rlc_feature_version; 248 break; 249 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 250 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 251 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 252 break; 253 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 254 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 255 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 256 break; 257 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 258 fw_info->ver = adev->gfx.rlc_srls_fw_version; 259 fw_info->feature = adev->gfx.rlc_srls_feature_version; 260 break; 261 case AMDGPU_INFO_FW_GFX_RLCP: 262 fw_info->ver = adev->gfx.rlcp_ucode_version; 263 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 264 break; 265 case AMDGPU_INFO_FW_GFX_RLCV: 266 fw_info->ver = adev->gfx.rlcv_ucode_version; 267 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 268 break; 269 case AMDGPU_INFO_FW_GFX_MEC: 270 if (query_fw->index == 0) { 271 fw_info->ver = adev->gfx.mec_fw_version; 272 fw_info->feature = adev->gfx.mec_feature_version; 273 } else if (query_fw->index == 1) { 274 fw_info->ver = adev->gfx.mec2_fw_version; 275 fw_info->feature = adev->gfx.mec2_feature_version; 276 } else 277 return -EINVAL; 278 break; 279 case AMDGPU_INFO_FW_SMC: 280 fw_info->ver = adev->pm.fw_version; 281 fw_info->feature = 0; 282 break; 283 case AMDGPU_INFO_FW_TA: 284 switch (query_fw->index) { 285 case TA_FW_TYPE_PSP_XGMI: 286 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 287 fw_info->feature = adev->psp.xgmi_context.context 288 .bin_desc.feature_version; 289 break; 290 case TA_FW_TYPE_PSP_RAS: 291 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 292 fw_info->feature = adev->psp.ras_context.context 293 .bin_desc.feature_version; 294 break; 295 case TA_FW_TYPE_PSP_HDCP: 296 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 297 fw_info->feature = adev->psp.hdcp_context.context 298 .bin_desc.feature_version; 299 break; 300 case TA_FW_TYPE_PSP_DTM: 301 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 302 fw_info->feature = adev->psp.dtm_context.context 303 .bin_desc.feature_version; 304 break; 305 case TA_FW_TYPE_PSP_RAP: 306 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 307 fw_info->feature = adev->psp.rap_context.context 308 .bin_desc.feature_version; 309 break; 310 case TA_FW_TYPE_PSP_SECUREDISPLAY: 311 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 312 fw_info->feature = 313 adev->psp.securedisplay_context.context.bin_desc 314 .feature_version; 315 break; 316 default: 317 return -EINVAL; 318 } 319 break; 320 case AMDGPU_INFO_FW_SDMA: 321 if (query_fw->index >= adev->sdma.num_instances) 322 return -EINVAL; 323 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 324 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 325 break; 326 case AMDGPU_INFO_FW_SOS: 327 fw_info->ver = adev->psp.sos.fw_version; 328 fw_info->feature = adev->psp.sos.feature_version; 329 break; 330 case AMDGPU_INFO_FW_ASD: 331 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 332 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 333 break; 334 case AMDGPU_INFO_FW_DMCU: 335 fw_info->ver = adev->dm.dmcu_fw_version; 336 fw_info->feature = 0; 337 break; 338 case AMDGPU_INFO_FW_DMCUB: 339 fw_info->ver = adev->dm.dmcub_fw_version; 340 fw_info->feature = 0; 341 break; 342 case AMDGPU_INFO_FW_TOC: 343 fw_info->ver = adev->psp.toc.fw_version; 344 fw_info->feature = adev->psp.toc.feature_version; 345 break; 346 case AMDGPU_INFO_FW_CAP: 347 fw_info->ver = adev->psp.cap_fw_version; 348 fw_info->feature = adev->psp.cap_feature_version; 349 break; 350 case AMDGPU_INFO_FW_MES_KIQ: 351 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 352 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 353 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 354 break; 355 case AMDGPU_INFO_FW_MES: 356 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 357 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 358 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 359 break; 360 case AMDGPU_INFO_FW_IMU: 361 fw_info->ver = adev->gfx.imu_fw_version; 362 fw_info->feature = 0; 363 break; 364 case AMDGPU_INFO_FW_VPE: 365 fw_info->ver = adev->vpe.fw_version; 366 fw_info->feature = adev->vpe.feature_version; 367 break; 368 default: 369 return -EINVAL; 370 } 371 return 0; 372 } 373 374 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 375 struct drm_amdgpu_info *info, 376 struct drm_amdgpu_info_uq_metadata_gfx *meta) 377 { 378 int ret = -EOPNOTSUPP; 379 380 if (adev->gfx.funcs->get_gfx_shadow_info) { 381 struct amdgpu_gfx_shadow_info shadow = {}; 382 383 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 384 meta->shadow_size = shadow.shadow_size; 385 meta->shadow_alignment = shadow.shadow_alignment; 386 meta->csa_size = shadow.csa_size; 387 meta->csa_alignment = shadow.csa_alignment; 388 ret = 0; 389 } 390 391 return ret; 392 } 393 394 static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, 395 struct drm_amdgpu_info *info, 396 struct drm_amdgpu_info_uq_metadata_compute *meta) 397 { 398 int ret = -EOPNOTSUPP; 399 400 if (adev->gfx.funcs->get_gfx_shadow_info) { 401 struct amdgpu_gfx_shadow_info shadow = {}; 402 403 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 404 meta->eop_size = shadow.eop_size; 405 meta->eop_alignment = shadow.eop_alignment; 406 ret = 0; 407 } 408 409 return ret; 410 } 411 412 static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, 413 struct drm_amdgpu_info *info, 414 struct drm_amdgpu_info_uq_metadata_sdma *meta) 415 { 416 int ret = -EOPNOTSUPP; 417 418 if (adev->sdma.get_csa_info) { 419 struct amdgpu_sdma_csa_info csa = {}; 420 421 adev->sdma.get_csa_info(adev, &csa); 422 meta->csa_size = csa.size; 423 meta->csa_alignment = csa.alignment; 424 ret = 0; 425 } 426 427 return ret; 428 } 429 430 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 431 struct drm_amdgpu_info *info, 432 struct drm_amdgpu_info_hw_ip *result) 433 { 434 uint32_t ib_start_alignment = 0; 435 uint32_t ib_size_alignment = 0; 436 enum amd_ip_block_type type; 437 unsigned int num_rings = 0; 438 uint32_t num_slots = 0; 439 unsigned int i, j; 440 441 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 442 return -EINVAL; 443 444 switch (info->query_hw_ip.type) { 445 case AMDGPU_HW_IP_GFX: 446 type = AMD_IP_BLOCK_TYPE_GFX; 447 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 448 if (adev->gfx.gfx_ring[i].sched.ready && 449 !adev->gfx.gfx_ring[i].no_user_submission) 450 ++num_rings; 451 452 if (!adev->gfx.disable_uq) { 453 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 454 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 455 } 456 457 ib_start_alignment = 32; 458 ib_size_alignment = 32; 459 break; 460 case AMDGPU_HW_IP_COMPUTE: 461 type = AMD_IP_BLOCK_TYPE_GFX; 462 for (i = 0; i < adev->gfx.num_compute_rings; i++) 463 if (adev->gfx.compute_ring[i].sched.ready && 464 !adev->gfx.compute_ring[i].no_user_submission) 465 ++num_rings; 466 467 if (!adev->sdma.disable_uq) { 468 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 469 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 470 } 471 472 ib_start_alignment = 32; 473 ib_size_alignment = 32; 474 break; 475 case AMDGPU_HW_IP_DMA: 476 type = AMD_IP_BLOCK_TYPE_SDMA; 477 for (i = 0; i < adev->sdma.num_instances; i++) 478 if (adev->sdma.instance[i].ring.sched.ready && 479 !adev->sdma.instance[i].ring.no_user_submission) 480 ++num_rings; 481 482 if (!adev->gfx.disable_uq) { 483 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 484 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 485 } 486 487 ib_start_alignment = 256; 488 ib_size_alignment = 4; 489 break; 490 case AMDGPU_HW_IP_UVD: 491 type = AMD_IP_BLOCK_TYPE_UVD; 492 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 493 if (adev->uvd.harvest_config & (1 << i)) 494 continue; 495 496 if (adev->uvd.inst[i].ring.sched.ready && 497 !adev->uvd.inst[i].ring.no_user_submission) 498 ++num_rings; 499 } 500 ib_start_alignment = 256; 501 ib_size_alignment = 64; 502 break; 503 case AMDGPU_HW_IP_VCE: 504 type = AMD_IP_BLOCK_TYPE_VCE; 505 for (i = 0; i < adev->vce.num_rings; i++) 506 if (adev->vce.ring[i].sched.ready && 507 !adev->vce.ring[i].no_user_submission) 508 ++num_rings; 509 ib_start_alignment = 256; 510 ib_size_alignment = 4; 511 break; 512 case AMDGPU_HW_IP_UVD_ENC: 513 type = AMD_IP_BLOCK_TYPE_UVD; 514 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 515 if (adev->uvd.harvest_config & (1 << i)) 516 continue; 517 518 for (j = 0; j < adev->uvd.num_enc_rings; j++) 519 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 520 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 521 ++num_rings; 522 } 523 ib_start_alignment = 256; 524 ib_size_alignment = 4; 525 break; 526 case AMDGPU_HW_IP_VCN_DEC: 527 type = AMD_IP_BLOCK_TYPE_VCN; 528 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 529 if (adev->vcn.harvest_config & (1 << i)) 530 continue; 531 532 if (adev->vcn.inst[i].ring_dec.sched.ready && 533 !adev->vcn.inst[i].ring_dec.no_user_submission) 534 ++num_rings; 535 } 536 ib_start_alignment = 256; 537 ib_size_alignment = 64; 538 break; 539 case AMDGPU_HW_IP_VCN_ENC: 540 type = AMD_IP_BLOCK_TYPE_VCN; 541 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 542 if (adev->vcn.harvest_config & (1 << i)) 543 continue; 544 545 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 546 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 547 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 548 ++num_rings; 549 } 550 ib_start_alignment = 256; 551 ib_size_alignment = 4; 552 break; 553 case AMDGPU_HW_IP_VCN_JPEG: 554 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 555 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 556 557 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 558 if (adev->jpeg.harvest_config & (1 << i)) 559 continue; 560 561 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 562 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 563 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 564 ++num_rings; 565 } 566 ib_start_alignment = 256; 567 ib_size_alignment = 64; 568 break; 569 case AMDGPU_HW_IP_VPE: 570 type = AMD_IP_BLOCK_TYPE_VPE; 571 if (adev->vpe.ring.sched.ready && 572 !adev->vpe.ring.no_user_submission) 573 ++num_rings; 574 ib_start_alignment = 256; 575 ib_size_alignment = 4; 576 break; 577 default: 578 return -EINVAL; 579 } 580 581 for (i = 0; i < adev->num_ip_blocks; i++) 582 if (adev->ip_blocks[i].version->type == type && 583 adev->ip_blocks[i].status.valid) 584 break; 585 586 if (i == adev->num_ip_blocks) 587 return 0; 588 589 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 590 num_rings); 591 592 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 593 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 594 595 if (adev->asic_type >= CHIP_VEGA10) { 596 switch (type) { 597 case AMD_IP_BLOCK_TYPE_GFX: 598 result->ip_discovery_version = 599 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 600 break; 601 case AMD_IP_BLOCK_TYPE_SDMA: 602 result->ip_discovery_version = 603 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 604 break; 605 case AMD_IP_BLOCK_TYPE_UVD: 606 case AMD_IP_BLOCK_TYPE_VCN: 607 case AMD_IP_BLOCK_TYPE_JPEG: 608 result->ip_discovery_version = 609 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 610 break; 611 case AMD_IP_BLOCK_TYPE_VCE: 612 result->ip_discovery_version = 613 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 614 break; 615 case AMD_IP_BLOCK_TYPE_VPE: 616 result->ip_discovery_version = 617 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 618 break; 619 default: 620 result->ip_discovery_version = 0; 621 break; 622 } 623 } else { 624 result->ip_discovery_version = 0; 625 } 626 result->capabilities_flags = 0; 627 result->available_rings = (1 << num_rings) - 1; 628 result->userq_num_slots = num_slots; 629 result->ib_start_alignment = ib_start_alignment; 630 result->ib_size_alignment = ib_size_alignment; 631 return 0; 632 } 633 634 /* 635 * Userspace get information ioctl 636 */ 637 /** 638 * amdgpu_info_ioctl - answer a device specific request. 639 * 640 * @dev: drm device pointer 641 * @data: request object 642 * @filp: drm filp 643 * 644 * This function is used to pass device specific parameters to the userspace 645 * drivers. Examples include: pci device id, pipeline parms, tiling params, 646 * etc. (all asics). 647 * Returns 0 on success, -EINVAL on failure. 648 */ 649 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 650 { 651 struct amdgpu_device *adev = drm_to_adev(dev); 652 struct drm_amdgpu_info *info = data; 653 struct amdgpu_mode_info *minfo = &adev->mode_info; 654 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 655 struct amdgpu_fpriv *fpriv; 656 struct amdgpu_ip_block *ip_block; 657 enum amd_ip_block_type type; 658 struct amdgpu_xcp *xcp; 659 u32 count, inst_mask; 660 uint32_t size = info->return_size; 661 struct drm_crtc *crtc; 662 uint32_t ui32 = 0; 663 uint64_t ui64 = 0; 664 int i, found, ret; 665 int ui32_size = sizeof(ui32); 666 667 if (!info->return_size || !info->return_pointer) 668 return -EINVAL; 669 670 switch (info->query) { 671 case AMDGPU_INFO_ACCEL_WORKING: 672 ui32 = adev->accel_working; 673 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 674 case AMDGPU_INFO_CRTC_FROM_ID: 675 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 676 crtc = (struct drm_crtc *)minfo->crtcs[i]; 677 if (crtc && crtc->base.id == info->mode_crtc.id) { 678 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 679 680 ui32 = amdgpu_crtc->crtc_id; 681 found = 1; 682 break; 683 } 684 } 685 if (!found) { 686 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 687 return -EINVAL; 688 } 689 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 690 case AMDGPU_INFO_HW_IP_INFO: { 691 struct drm_amdgpu_info_hw_ip ip = {}; 692 693 ret = amdgpu_hw_ip_info(adev, info, &ip); 694 if (ret) 695 return ret; 696 697 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 698 return ret ? -EFAULT : 0; 699 } 700 case AMDGPU_INFO_HW_IP_COUNT: { 701 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 702 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 703 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 704 705 if (!ip_block || !ip_block->status.valid) 706 return -EINVAL; 707 708 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 709 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 710 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 711 switch (type) { 712 case AMD_IP_BLOCK_TYPE_GFX: 713 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 714 if (ret) 715 return ret; 716 count = hweight32(inst_mask); 717 break; 718 case AMD_IP_BLOCK_TYPE_SDMA: 719 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 720 if (ret) 721 return ret; 722 count = hweight32(inst_mask); 723 break; 724 case AMD_IP_BLOCK_TYPE_JPEG: 725 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 726 if (ret) 727 return ret; 728 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 729 break; 730 case AMD_IP_BLOCK_TYPE_VCN: 731 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 732 if (ret) 733 return ret; 734 count = hweight32(inst_mask); 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 741 } 742 743 switch (type) { 744 case AMD_IP_BLOCK_TYPE_GFX: 745 case AMD_IP_BLOCK_TYPE_VCE: 746 count = 1; 747 break; 748 case AMD_IP_BLOCK_TYPE_SDMA: 749 count = adev->sdma.num_instances; 750 break; 751 case AMD_IP_BLOCK_TYPE_JPEG: 752 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 753 break; 754 case AMD_IP_BLOCK_TYPE_VCN: 755 count = adev->vcn.num_vcn_inst; 756 break; 757 case AMD_IP_BLOCK_TYPE_UVD: 758 count = adev->uvd.num_uvd_inst; 759 break; 760 /* For all other IP block types not listed in the switch statement 761 * the ip status is valid here and the instance count is one. 762 */ 763 default: 764 count = 1; 765 break; 766 } 767 768 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 769 } 770 case AMDGPU_INFO_TIMESTAMP: 771 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 772 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 773 case AMDGPU_INFO_FW_VERSION: { 774 struct drm_amdgpu_info_firmware fw_info; 775 776 /* We only support one instance of each IP block right now. */ 777 if (info->query_fw.ip_instance != 0) 778 return -EINVAL; 779 780 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 781 if (ret) 782 return ret; 783 784 return copy_to_user(out, &fw_info, 785 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 786 } 787 case AMDGPU_INFO_NUM_BYTES_MOVED: 788 ui64 = atomic64_read(&adev->num_bytes_moved); 789 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 790 case AMDGPU_INFO_NUM_EVICTIONS: 791 ui64 = atomic64_read(&adev->num_evictions); 792 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 793 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 794 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 795 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 796 case AMDGPU_INFO_VRAM_USAGE: 797 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 798 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 799 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 800 case AMDGPU_INFO_VIS_VRAM_USAGE: 801 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 802 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 803 case AMDGPU_INFO_GTT_USAGE: 804 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 805 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 806 case AMDGPU_INFO_GDS_CONFIG: { 807 struct drm_amdgpu_info_gds gds_info; 808 809 memset(&gds_info, 0, sizeof(gds_info)); 810 gds_info.compute_partition_size = adev->gds.gds_size; 811 gds_info.gds_total_size = adev->gds.gds_size; 812 gds_info.gws_per_compute_partition = adev->gds.gws_size; 813 gds_info.oa_per_compute_partition = adev->gds.oa_size; 814 return copy_to_user(out, &gds_info, 815 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 816 } 817 case AMDGPU_INFO_VRAM_GTT: { 818 struct drm_amdgpu_info_vram_gtt vram_gtt; 819 820 vram_gtt.vram_size = adev->gmc.real_vram_size - 821 atomic64_read(&adev->vram_pin_size) - 822 AMDGPU_VM_RESERVED_VRAM; 823 vram_gtt.vram_cpu_accessible_size = 824 min(adev->gmc.visible_vram_size - 825 atomic64_read(&adev->visible_pin_size), 826 vram_gtt.vram_size); 827 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 828 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 829 return copy_to_user(out, &vram_gtt, 830 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 831 } 832 case AMDGPU_INFO_MEMORY: { 833 struct drm_amdgpu_memory_info mem; 834 struct ttm_resource_manager *gtt_man = 835 &adev->mman.gtt_mgr.manager; 836 struct ttm_resource_manager *vram_man = 837 &adev->mman.vram_mgr.manager; 838 839 memset(&mem, 0, sizeof(mem)); 840 mem.vram.total_heap_size = adev->gmc.real_vram_size; 841 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 842 atomic64_read(&adev->vram_pin_size) - 843 AMDGPU_VM_RESERVED_VRAM; 844 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 845 ttm_resource_manager_usage(vram_man) : 0; 846 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 847 848 mem.cpu_accessible_vram.total_heap_size = 849 adev->gmc.visible_vram_size; 850 mem.cpu_accessible_vram.usable_heap_size = 851 min(adev->gmc.visible_vram_size - 852 atomic64_read(&adev->visible_pin_size), 853 mem.vram.usable_heap_size); 854 mem.cpu_accessible_vram.heap_usage = 855 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 856 mem.cpu_accessible_vram.max_allocation = 857 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 858 859 mem.gtt.total_heap_size = gtt_man->size; 860 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 861 atomic64_read(&adev->gart_pin_size); 862 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 863 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 864 865 return copy_to_user(out, &mem, 866 min((size_t)size, sizeof(mem))) 867 ? -EFAULT : 0; 868 } 869 case AMDGPU_INFO_READ_MMR_REG: { 870 int ret = 0; 871 unsigned int n, alloc_size; 872 uint32_t *regs; 873 unsigned int se_num = (info->read_mmr_reg.instance >> 874 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 875 AMDGPU_INFO_MMR_SE_INDEX_MASK; 876 unsigned int sh_num = (info->read_mmr_reg.instance >> 877 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 878 AMDGPU_INFO_MMR_SH_INDEX_MASK; 879 880 if (!down_read_trylock(&adev->reset_domain->sem)) 881 return -ENOENT; 882 883 /* set full masks if the userspace set all bits 884 * in the bitfields 885 */ 886 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { 887 se_num = 0xffffffff; 888 } else if (se_num >= AMDGPU_GFX_MAX_SE) { 889 ret = -EINVAL; 890 goto out; 891 } 892 893 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { 894 sh_num = 0xffffffff; 895 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { 896 ret = -EINVAL; 897 goto out; 898 } 899 900 if (info->read_mmr_reg.count > 128) { 901 ret = -EINVAL; 902 goto out; 903 } 904 905 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 906 if (!regs) { 907 ret = -ENOMEM; 908 goto out; 909 } 910 911 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 912 913 amdgpu_gfx_off_ctrl(adev, false); 914 for (i = 0; i < info->read_mmr_reg.count; i++) { 915 if (amdgpu_asic_read_register(adev, se_num, sh_num, 916 info->read_mmr_reg.dword_offset + i, 917 ®s[i])) { 918 DRM_DEBUG_KMS("unallowed offset %#x\n", 919 info->read_mmr_reg.dword_offset + i); 920 kfree(regs); 921 amdgpu_gfx_off_ctrl(adev, true); 922 ret = -EFAULT; 923 goto out; 924 } 925 } 926 amdgpu_gfx_off_ctrl(adev, true); 927 n = copy_to_user(out, regs, min(size, alloc_size)); 928 kfree(regs); 929 ret = (n ? -EFAULT : 0); 930 out: 931 up_read(&adev->reset_domain->sem); 932 return ret; 933 } 934 case AMDGPU_INFO_DEV_INFO: { 935 struct drm_amdgpu_info_device *dev_info; 936 uint64_t vm_size; 937 uint32_t pcie_gen_mask, pcie_width_mask; 938 939 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 940 if (!dev_info) 941 return -ENOMEM; 942 943 dev_info->device_id = adev->pdev->device; 944 dev_info->chip_rev = adev->rev_id; 945 dev_info->external_rev = adev->external_rev_id; 946 dev_info->pci_rev = adev->pdev->revision; 947 dev_info->family = adev->family; 948 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 949 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 950 /* return all clocks in KHz */ 951 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 952 if (adev->pm.dpm_enabled) { 953 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 954 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 955 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 956 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 957 } else { 958 dev_info->max_engine_clock = 959 dev_info->min_engine_clock = 960 adev->clock.default_sclk * 10; 961 dev_info->max_memory_clock = 962 dev_info->min_memory_clock = 963 adev->clock.default_mclk * 10; 964 } 965 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 966 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 967 adev->gfx.config.max_shader_engines; 968 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 969 dev_info->ids_flags = 0; 970 if (adev->flags & AMD_IS_APU) 971 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 972 if (adev->gfx.mcbp) 973 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 974 if (amdgpu_is_tmz(adev)) 975 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 976 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 977 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 978 979 /* Gang submit is not supported under SRIOV currently */ 980 if (!amdgpu_sriov_vf(adev)) 981 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 982 983 if (amdgpu_passthrough(adev)) 984 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 985 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 986 AMDGPU_IDS_FLAGS_MODE_MASK; 987 else if (amdgpu_sriov_vf(adev)) 988 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 989 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 990 AMDGPU_IDS_FLAGS_MODE_MASK; 991 992 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 993 vm_size -= AMDGPU_VA_RESERVED_TOP; 994 995 /* Older VCE FW versions are buggy and can handle only 40bits */ 996 if (adev->vce.fw_version && 997 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 998 vm_size = min(vm_size, 1ULL << 40); 999 1000 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 1001 dev_info->virtual_address_max = 1002 min(vm_size, AMDGPU_GMC_HOLE_START); 1003 1004 if (vm_size > AMDGPU_GMC_HOLE_START) { 1005 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 1006 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 1007 } 1008 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1009 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 1010 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1011 dev_info->cu_active_number = adev->gfx.cu_info.number; 1012 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 1013 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 1014 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 1015 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 1016 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 1017 sizeof(dev_info->cu_bitmap)); 1018 dev_info->vram_type = adev->gmc.vram_type; 1019 dev_info->vram_bit_width = adev->gmc.vram_width; 1020 dev_info->vce_harvest_config = adev->vce.harvest_config; 1021 dev_info->gc_double_offchip_lds_buf = 1022 adev->gfx.config.double_offchip_lds_buf; 1023 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 1024 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 1025 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 1026 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 1027 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 1028 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 1029 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 1030 1031 if (adev->family >= AMDGPU_FAMILY_NV) 1032 dev_info->pa_sc_tile_steering_override = 1033 adev->gfx.config.pa_sc_tile_steering_override; 1034 1035 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 1036 1037 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1038 pcie_gen_mask = adev->pm.pcie_gen_mask & 1039 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1040 pcie_width_mask = adev->pm.pcie_mlw_mask & 1041 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1042 dev_info->pcie_gen = fls(pcie_gen_mask); 1043 dev_info->pcie_num_lanes = 1044 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1045 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1046 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1047 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1048 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1049 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1050 1051 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1052 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1053 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1054 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1055 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1056 adev->gfx.config.gc_gl1c_per_sa; 1057 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1058 dev_info->mall_size = adev->gmc.mall_size; 1059 1060 1061 if (adev->gfx.funcs->get_gfx_shadow_info) { 1062 struct amdgpu_gfx_shadow_info shadow_info; 1063 1064 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1065 if (!ret) { 1066 dev_info->shadow_size = shadow_info.shadow_size; 1067 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1068 dev_info->csa_size = shadow_info.csa_size; 1069 dev_info->csa_alignment = shadow_info.csa_alignment; 1070 } 1071 } 1072 1073 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1074 1075 ret = copy_to_user(out, dev_info, 1076 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1077 kfree(dev_info); 1078 return ret; 1079 } 1080 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1081 unsigned int i; 1082 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1083 struct amd_vce_state *vce_state; 1084 1085 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1086 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1087 if (vce_state) { 1088 vce_clk_table.entries[i].sclk = vce_state->sclk; 1089 vce_clk_table.entries[i].mclk = vce_state->mclk; 1090 vce_clk_table.entries[i].eclk = vce_state->evclk; 1091 vce_clk_table.num_valid_entries++; 1092 } 1093 } 1094 1095 return copy_to_user(out, &vce_clk_table, 1096 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1097 } 1098 case AMDGPU_INFO_VBIOS: { 1099 uint32_t bios_size = adev->bios_size; 1100 1101 switch (info->vbios_info.type) { 1102 case AMDGPU_INFO_VBIOS_SIZE: 1103 return copy_to_user(out, &bios_size, 1104 min((size_t)size, sizeof(bios_size))) 1105 ? -EFAULT : 0; 1106 case AMDGPU_INFO_VBIOS_IMAGE: { 1107 uint8_t *bios; 1108 uint32_t bios_offset = info->vbios_info.offset; 1109 1110 if (bios_offset >= bios_size) 1111 return -EINVAL; 1112 1113 bios = adev->bios + bios_offset; 1114 return copy_to_user(out, bios, 1115 min((size_t)size, (size_t)(bios_size - bios_offset))) 1116 ? -EFAULT : 0; 1117 } 1118 case AMDGPU_INFO_VBIOS_INFO: { 1119 struct drm_amdgpu_info_vbios vbios_info = {}; 1120 struct atom_context *atom_context; 1121 1122 atom_context = adev->mode_info.atom_context; 1123 if (atom_context) { 1124 memcpy(vbios_info.name, atom_context->name, 1125 sizeof(atom_context->name)); 1126 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1127 sizeof(atom_context->vbios_pn)); 1128 vbios_info.version = atom_context->version; 1129 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1130 sizeof(atom_context->vbios_ver_str)); 1131 memcpy(vbios_info.date, atom_context->date, 1132 sizeof(atom_context->date)); 1133 } 1134 1135 return copy_to_user(out, &vbios_info, 1136 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1137 } 1138 default: 1139 DRM_DEBUG_KMS("Invalid request %d\n", 1140 info->vbios_info.type); 1141 return -EINVAL; 1142 } 1143 } 1144 case AMDGPU_INFO_NUM_HANDLES: { 1145 struct drm_amdgpu_info_num_handles handle; 1146 1147 switch (info->query_hw_ip.type) { 1148 case AMDGPU_HW_IP_UVD: 1149 /* Starting Polaris, we support unlimited UVD handles */ 1150 if (adev->asic_type < CHIP_POLARIS10) { 1151 handle.uvd_max_handles = adev->uvd.max_handles; 1152 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1153 1154 return copy_to_user(out, &handle, 1155 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1156 } else { 1157 return -ENODATA; 1158 } 1159 1160 break; 1161 default: 1162 return -EINVAL; 1163 } 1164 } 1165 case AMDGPU_INFO_SENSOR: { 1166 if (!adev->pm.dpm_enabled) 1167 return -ENOENT; 1168 1169 switch (info->sensor_info.type) { 1170 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1171 /* get sclk in Mhz */ 1172 if (amdgpu_dpm_read_sensor(adev, 1173 AMDGPU_PP_SENSOR_GFX_SCLK, 1174 (void *)&ui32, &ui32_size)) { 1175 return -EINVAL; 1176 } 1177 ui32 /= 100; 1178 break; 1179 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1180 /* get mclk in Mhz */ 1181 if (amdgpu_dpm_read_sensor(adev, 1182 AMDGPU_PP_SENSOR_GFX_MCLK, 1183 (void *)&ui32, &ui32_size)) { 1184 return -EINVAL; 1185 } 1186 ui32 /= 100; 1187 break; 1188 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1189 /* get temperature in millidegrees C */ 1190 if (amdgpu_dpm_read_sensor(adev, 1191 AMDGPU_PP_SENSOR_GPU_TEMP, 1192 (void *)&ui32, &ui32_size)) { 1193 return -EINVAL; 1194 } 1195 break; 1196 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1197 /* get GPU load */ 1198 if (amdgpu_dpm_read_sensor(adev, 1199 AMDGPU_PP_SENSOR_GPU_LOAD, 1200 (void *)&ui32, &ui32_size)) { 1201 return -EINVAL; 1202 } 1203 break; 1204 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1205 /* get average GPU power */ 1206 if (amdgpu_dpm_read_sensor(adev, 1207 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1208 (void *)&ui32, &ui32_size)) { 1209 /* fall back to input power for backwards compat */ 1210 if (amdgpu_dpm_read_sensor(adev, 1211 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1212 (void *)&ui32, &ui32_size)) { 1213 return -EINVAL; 1214 } 1215 } 1216 ui32 >>= 8; 1217 break; 1218 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1219 /* get input GPU power */ 1220 if (amdgpu_dpm_read_sensor(adev, 1221 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1222 (void *)&ui32, &ui32_size)) { 1223 return -EINVAL; 1224 } 1225 ui32 >>= 8; 1226 break; 1227 case AMDGPU_INFO_SENSOR_VDDNB: 1228 /* get VDDNB in millivolts */ 1229 if (amdgpu_dpm_read_sensor(adev, 1230 AMDGPU_PP_SENSOR_VDDNB, 1231 (void *)&ui32, &ui32_size)) { 1232 return -EINVAL; 1233 } 1234 break; 1235 case AMDGPU_INFO_SENSOR_VDDGFX: 1236 /* get VDDGFX in millivolts */ 1237 if (amdgpu_dpm_read_sensor(adev, 1238 AMDGPU_PP_SENSOR_VDDGFX, 1239 (void *)&ui32, &ui32_size)) { 1240 return -EINVAL; 1241 } 1242 break; 1243 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1244 /* get stable pstate sclk in Mhz */ 1245 if (amdgpu_dpm_read_sensor(adev, 1246 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1247 (void *)&ui32, &ui32_size)) { 1248 return -EINVAL; 1249 } 1250 ui32 /= 100; 1251 break; 1252 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1253 /* get stable pstate mclk in Mhz */ 1254 if (amdgpu_dpm_read_sensor(adev, 1255 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1256 (void *)&ui32, &ui32_size)) { 1257 return -EINVAL; 1258 } 1259 ui32 /= 100; 1260 break; 1261 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1262 /* get peak pstate sclk in Mhz */ 1263 if (amdgpu_dpm_read_sensor(adev, 1264 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1265 (void *)&ui32, &ui32_size)) { 1266 return -EINVAL; 1267 } 1268 ui32 /= 100; 1269 break; 1270 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1271 /* get peak pstate mclk in Mhz */ 1272 if (amdgpu_dpm_read_sensor(adev, 1273 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1274 (void *)&ui32, &ui32_size)) { 1275 return -EINVAL; 1276 } 1277 ui32 /= 100; 1278 break; 1279 default: 1280 DRM_DEBUG_KMS("Invalid request %d\n", 1281 info->sensor_info.type); 1282 return -EINVAL; 1283 } 1284 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1285 } 1286 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1287 ui32 = atomic_read(&adev->vram_lost_counter); 1288 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1289 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1290 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1291 uint64_t ras_mask; 1292 1293 if (!ras) 1294 return -EINVAL; 1295 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1296 1297 return copy_to_user(out, &ras_mask, 1298 min_t(u64, size, sizeof(ras_mask))) ? 1299 -EFAULT : 0; 1300 } 1301 case AMDGPU_INFO_VIDEO_CAPS: { 1302 const struct amdgpu_video_codecs *codecs; 1303 struct drm_amdgpu_info_video_caps *caps; 1304 int r; 1305 1306 if (!adev->asic_funcs->query_video_codecs) 1307 return -EINVAL; 1308 1309 switch (info->video_cap.type) { 1310 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1311 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1312 if (r) 1313 return -EINVAL; 1314 break; 1315 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1316 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1317 if (r) 1318 return -EINVAL; 1319 break; 1320 default: 1321 DRM_DEBUG_KMS("Invalid request %d\n", 1322 info->video_cap.type); 1323 return -EINVAL; 1324 } 1325 1326 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1327 if (!caps) 1328 return -ENOMEM; 1329 1330 for (i = 0; i < codecs->codec_count; i++) { 1331 int idx = codecs->codec_array[i].codec_type; 1332 1333 switch (idx) { 1334 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1335 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1336 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1337 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1338 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1339 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1340 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1341 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1342 caps->codec_info[idx].valid = 1; 1343 caps->codec_info[idx].max_width = 1344 codecs->codec_array[i].max_width; 1345 caps->codec_info[idx].max_height = 1346 codecs->codec_array[i].max_height; 1347 caps->codec_info[idx].max_pixels_per_frame = 1348 codecs->codec_array[i].max_pixels_per_frame; 1349 caps->codec_info[idx].max_level = 1350 codecs->codec_array[i].max_level; 1351 break; 1352 default: 1353 break; 1354 } 1355 } 1356 r = copy_to_user(out, caps, 1357 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1358 kfree(caps); 1359 return r; 1360 } 1361 case AMDGPU_INFO_MAX_IBS: { 1362 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1363 1364 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1365 max_ibs[i] = amdgpu_ring_max_ibs(i); 1366 1367 return copy_to_user(out, max_ibs, 1368 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1369 } 1370 case AMDGPU_INFO_GPUVM_FAULT: { 1371 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1372 struct amdgpu_vm *vm = &fpriv->vm; 1373 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1374 unsigned long flags; 1375 1376 if (!vm) 1377 return -EINVAL; 1378 1379 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1380 1381 xa_lock_irqsave(&adev->vm_manager.pasids, flags); 1382 gpuvm_fault.addr = vm->fault_info.addr; 1383 gpuvm_fault.status = vm->fault_info.status; 1384 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1385 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); 1386 1387 return copy_to_user(out, &gpuvm_fault, 1388 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1389 } 1390 case AMDGPU_INFO_UQ_FW_AREAS: { 1391 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1392 1393 switch (info->query_hw_ip.type) { 1394 case AMDGPU_HW_IP_GFX: 1395 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1396 if (ret) 1397 return ret; 1398 1399 ret = copy_to_user(out, &meta_info, 1400 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1401 return 0; 1402 case AMDGPU_HW_IP_COMPUTE: 1403 ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); 1404 if (ret) 1405 return ret; 1406 1407 ret = copy_to_user(out, &meta_info, 1408 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1409 return 0; 1410 case AMDGPU_HW_IP_DMA: 1411 ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); 1412 if (ret) 1413 return ret; 1414 1415 ret = copy_to_user(out, &meta_info, 1416 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1417 return 0; 1418 default: 1419 return -EINVAL; 1420 } 1421 } 1422 default: 1423 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1424 return -EINVAL; 1425 } 1426 return 0; 1427 } 1428 1429 /** 1430 * amdgpu_driver_open_kms - drm callback for open 1431 * 1432 * @dev: drm dev pointer 1433 * @file_priv: drm file 1434 * 1435 * On device open, init vm on cayman+ (all asics). 1436 * Returns 0 on success, error on failure. 1437 */ 1438 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1439 { 1440 struct amdgpu_device *adev = drm_to_adev(dev); 1441 struct amdgpu_fpriv *fpriv; 1442 int r, pasid; 1443 1444 /* Ensure IB tests are run on ring */ 1445 flush_delayed_work(&adev->delayed_init_work); 1446 1447 1448 if (amdgpu_ras_intr_triggered()) { 1449 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1450 return -EHWPOISON; 1451 } 1452 1453 file_priv->driver_priv = NULL; 1454 1455 r = pm_runtime_get_sync(dev->dev); 1456 if (r < 0) 1457 goto pm_put; 1458 1459 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1460 if (unlikely(!fpriv)) { 1461 r = -ENOMEM; 1462 goto out_suspend; 1463 } 1464 1465 pasid = amdgpu_pasid_alloc(16); 1466 if (pasid < 0) { 1467 dev_warn(adev->dev, "No more PASIDs available!"); 1468 pasid = 0; 1469 } 1470 1471 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1472 if (r) 1473 goto error_pasid; 1474 1475 amdgpu_debugfs_vm_init(file_priv); 1476 1477 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id, pasid); 1478 if (r) 1479 goto error_pasid; 1480 1481 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1482 if (!fpriv->prt_va) { 1483 r = -ENOMEM; 1484 goto error_vm; 1485 } 1486 1487 if (adev->gfx.mcbp) { 1488 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1489 1490 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1491 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1492 if (r) 1493 goto error_vm; 1494 } 1495 1496 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1497 if (r) 1498 goto error_vm; 1499 1500 mutex_init(&fpriv->bo_list_lock); 1501 idr_init_base(&fpriv->bo_list_handles, 1); 1502 1503 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1504 if (r) 1505 DRM_WARN("Can't setup usermode queues, use legacy workload submission only\n"); 1506 1507 r = amdgpu_eviction_fence_init(&fpriv->evf_mgr); 1508 if (r) 1509 goto error_vm; 1510 1511 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1512 1513 file_priv->driver_priv = fpriv; 1514 goto out_suspend; 1515 1516 error_vm: 1517 amdgpu_vm_fini(adev, &fpriv->vm); 1518 1519 error_pasid: 1520 if (pasid) 1521 amdgpu_pasid_free(pasid); 1522 1523 kfree(fpriv); 1524 1525 out_suspend: 1526 pm_put: 1527 pm_runtime_put_autosuspend(dev->dev); 1528 1529 return r; 1530 } 1531 1532 /** 1533 * amdgpu_driver_postclose_kms - drm callback for post close 1534 * 1535 * @dev: drm dev pointer 1536 * @file_priv: drm file 1537 * 1538 * On device post close, tear down vm on cayman+ (all asics). 1539 */ 1540 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1541 struct drm_file *file_priv) 1542 { 1543 struct amdgpu_device *adev = drm_to_adev(dev); 1544 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1545 struct amdgpu_bo_list *list; 1546 struct amdgpu_bo *pd; 1547 u32 pasid; 1548 int handle; 1549 1550 if (!fpriv) 1551 return; 1552 1553 pm_runtime_get_sync(dev->dev); 1554 1555 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1556 amdgpu_uvd_free_handles(adev, file_priv); 1557 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1558 amdgpu_vce_free_handles(adev, file_priv); 1559 1560 if (fpriv->csa_va) { 1561 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1562 1563 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1564 fpriv->csa_va, csa_addr)); 1565 fpriv->csa_va = NULL; 1566 } 1567 1568 amdgpu_seq64_unmap(adev, fpriv); 1569 1570 pasid = fpriv->vm.pasid; 1571 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1572 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1573 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1574 amdgpu_bo_unreserve(pd); 1575 } 1576 1577 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1578 amdgpu_vm_fini(adev, &fpriv->vm); 1579 1580 if (pasid) 1581 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1582 amdgpu_bo_unref(&pd); 1583 1584 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1585 amdgpu_bo_list_put(list); 1586 1587 idr_destroy(&fpriv->bo_list_handles); 1588 mutex_destroy(&fpriv->bo_list_lock); 1589 1590 kfree(fpriv); 1591 file_priv->driver_priv = NULL; 1592 1593 pm_runtime_put_autosuspend(dev->dev); 1594 } 1595 1596 1597 void amdgpu_driver_release_kms(struct drm_device *dev) 1598 { 1599 struct amdgpu_device *adev = drm_to_adev(dev); 1600 1601 amdgpu_device_fini_sw(adev); 1602 pci_set_drvdata(adev->pdev, NULL); 1603 } 1604 1605 /* 1606 * VBlank related functions. 1607 */ 1608 /** 1609 * amdgpu_get_vblank_counter_kms - get frame count 1610 * 1611 * @crtc: crtc to get the frame count from 1612 * 1613 * Gets the frame count on the requested crtc (all asics). 1614 * Returns frame count on success, -EINVAL on failure. 1615 */ 1616 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1617 { 1618 struct drm_device *dev = crtc->dev; 1619 unsigned int pipe = crtc->index; 1620 struct amdgpu_device *adev = drm_to_adev(dev); 1621 int vpos, hpos, stat; 1622 u32 count; 1623 1624 if (pipe >= adev->mode_info.num_crtc) { 1625 DRM_ERROR("Invalid crtc %u\n", pipe); 1626 return -EINVAL; 1627 } 1628 1629 /* The hw increments its frame counter at start of vsync, not at start 1630 * of vblank, as is required by DRM core vblank counter handling. 1631 * Cook the hw count here to make it appear to the caller as if it 1632 * incremented at start of vblank. We measure distance to start of 1633 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1634 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1635 * result by 1 to give the proper appearance to caller. 1636 */ 1637 if (adev->mode_info.crtcs[pipe]) { 1638 /* Repeat readout if needed to provide stable result if 1639 * we cross start of vsync during the queries. 1640 */ 1641 do { 1642 count = amdgpu_display_vblank_get_counter(adev, pipe); 1643 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1644 * vpos as distance to start of vblank, instead of 1645 * regular vertical scanout pos. 1646 */ 1647 stat = amdgpu_display_get_crtc_scanoutpos( 1648 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1649 &vpos, &hpos, NULL, NULL, 1650 &adev->mode_info.crtcs[pipe]->base.hwmode); 1651 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1652 1653 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1654 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1655 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1656 } else { 1657 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1658 pipe, vpos); 1659 1660 /* Bump counter if we are at >= leading edge of vblank, 1661 * but before vsync where vpos would turn negative and 1662 * the hw counter really increments. 1663 */ 1664 if (vpos >= 0) 1665 count++; 1666 } 1667 } else { 1668 /* Fallback to use value as is. */ 1669 count = amdgpu_display_vblank_get_counter(adev, pipe); 1670 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1671 } 1672 1673 return count; 1674 } 1675 1676 /** 1677 * amdgpu_enable_vblank_kms - enable vblank interrupt 1678 * 1679 * @crtc: crtc to enable vblank interrupt for 1680 * 1681 * Enable the interrupt on the requested crtc (all asics). 1682 * Returns 0 on success, -EINVAL on failure. 1683 */ 1684 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1685 { 1686 struct drm_device *dev = crtc->dev; 1687 unsigned int pipe = crtc->index; 1688 struct amdgpu_device *adev = drm_to_adev(dev); 1689 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1690 1691 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1692 } 1693 1694 /** 1695 * amdgpu_disable_vblank_kms - disable vblank interrupt 1696 * 1697 * @crtc: crtc to disable vblank interrupt for 1698 * 1699 * Disable the interrupt on the requested crtc (all asics). 1700 */ 1701 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1702 { 1703 struct drm_device *dev = crtc->dev; 1704 unsigned int pipe = crtc->index; 1705 struct amdgpu_device *adev = drm_to_adev(dev); 1706 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1707 1708 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1709 } 1710 1711 /* 1712 * Debugfs info 1713 */ 1714 #if defined(CONFIG_DEBUG_FS) 1715 1716 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1717 { 1718 struct amdgpu_device *adev = m->private; 1719 struct drm_amdgpu_info_firmware fw_info; 1720 struct drm_amdgpu_query_fw query_fw; 1721 struct atom_context *ctx = adev->mode_info.atom_context; 1722 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1723 int ret, i; 1724 1725 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1726 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1727 TA_FW_NAME(XGMI), 1728 TA_FW_NAME(RAS), 1729 TA_FW_NAME(HDCP), 1730 TA_FW_NAME(DTM), 1731 TA_FW_NAME(RAP), 1732 TA_FW_NAME(SECUREDISPLAY), 1733 #undef TA_FW_NAME 1734 }; 1735 1736 /* VCE */ 1737 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1738 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1739 if (ret) 1740 return ret; 1741 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1742 fw_info.feature, fw_info.ver); 1743 1744 /* UVD */ 1745 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1746 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1747 if (ret) 1748 return ret; 1749 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1750 fw_info.feature, fw_info.ver); 1751 1752 /* GMC */ 1753 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1754 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1755 if (ret) 1756 return ret; 1757 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1758 fw_info.feature, fw_info.ver); 1759 1760 /* ME */ 1761 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1762 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1763 if (ret) 1764 return ret; 1765 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1766 fw_info.feature, fw_info.ver); 1767 1768 /* PFP */ 1769 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1770 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1771 if (ret) 1772 return ret; 1773 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1774 fw_info.feature, fw_info.ver); 1775 1776 /* CE */ 1777 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1778 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1779 if (ret) 1780 return ret; 1781 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1782 fw_info.feature, fw_info.ver); 1783 1784 /* RLC */ 1785 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1786 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1787 if (ret) 1788 return ret; 1789 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1790 fw_info.feature, fw_info.ver); 1791 1792 /* RLC SAVE RESTORE LIST CNTL */ 1793 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1794 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1795 if (ret) 1796 return ret; 1797 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1798 fw_info.feature, fw_info.ver); 1799 1800 /* RLC SAVE RESTORE LIST GPM MEM */ 1801 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1802 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1803 if (ret) 1804 return ret; 1805 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1806 fw_info.feature, fw_info.ver); 1807 1808 /* RLC SAVE RESTORE LIST SRM MEM */ 1809 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1810 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1811 if (ret) 1812 return ret; 1813 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1814 fw_info.feature, fw_info.ver); 1815 1816 /* RLCP */ 1817 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1818 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1819 if (ret) 1820 return ret; 1821 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1822 fw_info.feature, fw_info.ver); 1823 1824 /* RLCV */ 1825 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1826 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1827 if (ret) 1828 return ret; 1829 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1830 fw_info.feature, fw_info.ver); 1831 1832 /* MEC */ 1833 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1834 query_fw.index = 0; 1835 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1836 if (ret) 1837 return ret; 1838 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1839 fw_info.feature, fw_info.ver); 1840 1841 /* MEC2 */ 1842 if (adev->gfx.mec2_fw) { 1843 query_fw.index = 1; 1844 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1845 if (ret) 1846 return ret; 1847 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1848 fw_info.feature, fw_info.ver); 1849 } 1850 1851 /* IMU */ 1852 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1853 query_fw.index = 0; 1854 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1855 if (ret) 1856 return ret; 1857 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1858 fw_info.feature, fw_info.ver); 1859 1860 /* PSP SOS */ 1861 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1862 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1863 if (ret) 1864 return ret; 1865 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1866 fw_info.feature, fw_info.ver); 1867 1868 1869 /* PSP ASD */ 1870 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1871 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1872 if (ret) 1873 return ret; 1874 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1875 fw_info.feature, fw_info.ver); 1876 1877 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1878 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1879 query_fw.index = i; 1880 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1881 if (ret) 1882 continue; 1883 1884 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1885 ta_fw_name[i], fw_info.feature, fw_info.ver); 1886 } 1887 1888 /* SMC */ 1889 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1890 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1891 if (ret) 1892 return ret; 1893 smu_program = (fw_info.ver >> 24) & 0xff; 1894 smu_major = (fw_info.ver >> 16) & 0xff; 1895 smu_minor = (fw_info.ver >> 8) & 0xff; 1896 smu_debug = (fw_info.ver >> 0) & 0xff; 1897 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1898 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1899 1900 /* SDMA */ 1901 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1902 for (i = 0; i < adev->sdma.num_instances; i++) { 1903 query_fw.index = i; 1904 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1905 if (ret) 1906 return ret; 1907 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1908 i, fw_info.feature, fw_info.ver); 1909 } 1910 1911 /* VCN */ 1912 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1913 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1914 if (ret) 1915 return ret; 1916 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1917 fw_info.feature, fw_info.ver); 1918 1919 /* DMCU */ 1920 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1921 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1922 if (ret) 1923 return ret; 1924 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1925 fw_info.feature, fw_info.ver); 1926 1927 /* DMCUB */ 1928 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1929 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1930 if (ret) 1931 return ret; 1932 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1933 fw_info.feature, fw_info.ver); 1934 1935 /* TOC */ 1936 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1937 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1938 if (ret) 1939 return ret; 1940 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1941 fw_info.feature, fw_info.ver); 1942 1943 /* CAP */ 1944 if (adev->psp.cap_fw) { 1945 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1946 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1947 if (ret) 1948 return ret; 1949 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1950 fw_info.feature, fw_info.ver); 1951 } 1952 1953 /* MES_KIQ */ 1954 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1955 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1956 if (ret) 1957 return ret; 1958 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1959 fw_info.feature, fw_info.ver); 1960 1961 /* MES */ 1962 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1963 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1964 if (ret) 1965 return ret; 1966 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1967 fw_info.feature, fw_info.ver); 1968 1969 /* VPE */ 1970 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1971 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1972 if (ret) 1973 return ret; 1974 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1975 fw_info.feature, fw_info.ver); 1976 1977 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1978 1979 return 0; 1980 } 1981 1982 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1983 1984 #endif 1985 1986 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1987 { 1988 #if defined(CONFIG_DEBUG_FS) 1989 struct drm_minor *minor = adev_to_drm(adev)->primary; 1990 struct dentry *root = minor->debugfs_root; 1991 1992 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1993 adev, &amdgpu_debugfs_firmware_info_fops); 1994 1995 #endif 1996 } 1997