1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 91 DRM_WARN("smart shift update failed\n"); 92 93 amdgpu_acpi_fini(adev); 94 amdgpu_device_fini_hw(adev); 95 } 96 97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 98 { 99 struct amdgpu_gpu_instance *gpu_instance; 100 101 mutex_lock(&mgpu_info.mutex); 102 103 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 104 DRM_ERROR("Cannot register more gpu instance\n"); 105 mutex_unlock(&mgpu_info.mutex); 106 return; 107 } 108 109 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 110 gpu_instance->adev = adev; 111 gpu_instance->mgpu_fan_enabled = 0; 112 113 mgpu_info.num_gpu++; 114 if (adev->flags & AMD_IS_APU) 115 mgpu_info.num_apu++; 116 else 117 mgpu_info.num_dgpu++; 118 119 mutex_unlock(&mgpu_info.mutex); 120 } 121 122 /** 123 * amdgpu_driver_load_kms - Main load function for KMS. 124 * 125 * @adev: pointer to struct amdgpu_device 126 * @flags: device flags 127 * 128 * This is the main load function for KMS (all asics). 129 * Returns 0 on success, error on failure. 130 */ 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 132 { 133 struct drm_device *dev; 134 int r, acpi_status; 135 136 dev = adev_to_drm(adev); 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, flags); 145 if (r) { 146 dev_err(dev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 if (amdgpu_device_supports_px(dev) && 151 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */ 152 adev->runpm = true; 153 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 154 } else if (amdgpu_device_supports_boco(dev) && 155 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 156 adev->runpm = true; 157 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 158 } else if (amdgpu_device_supports_baco(dev) && 159 (amdgpu_runtime_pm != 0)) { 160 switch (adev->asic_type) { 161 case CHIP_VEGA20: 162 case CHIP_ARCTURUS: 163 /* enable runpm if runpm=1 */ 164 if (amdgpu_runtime_pm > 0) 165 adev->runpm = true; 166 break; 167 case CHIP_VEGA10: 168 /* turn runpm on if noretry=0 */ 169 if (!adev->gmc.noretry) 170 adev->runpm = true; 171 break; 172 default: 173 /* enable runpm on CI+ */ 174 adev->runpm = true; 175 break; 176 } 177 /* XXX: disable runtime pm if we are the primary adapter 178 * to avoid displays being re-enabled after DPMS. 179 * This needs to be sorted out and fixed properly. 180 */ 181 if (adev->is_fw_fb) 182 adev->runpm = false; 183 if (adev->runpm) 184 dev_info(adev->dev, "Using BACO for runtime pm\n"); 185 } 186 187 /* Call ACPI methods: require modeset init 188 * but failure is not fatal 189 */ 190 191 acpi_status = amdgpu_acpi_init(adev); 192 if (acpi_status) 193 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 194 195 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 196 DRM_WARN("smart shift update failed\n"); 197 198 out: 199 if (r) 200 amdgpu_driver_unload_kms(dev); 201 202 return r; 203 } 204 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 206 struct drm_amdgpu_query_fw *query_fw, 207 struct amdgpu_device *adev) 208 { 209 switch (query_fw->fw_type) { 210 case AMDGPU_INFO_FW_VCE: 211 fw_info->ver = adev->vce.fw_version; 212 fw_info->feature = adev->vce.fb_version; 213 break; 214 case AMDGPU_INFO_FW_UVD: 215 fw_info->ver = adev->uvd.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_VCN: 219 fw_info->ver = adev->vcn.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GMC: 223 fw_info->ver = adev->gmc.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_GFX_ME: 227 fw_info->ver = adev->gfx.me_fw_version; 228 fw_info->feature = adev->gfx.me_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_PFP: 231 fw_info->ver = adev->gfx.pfp_fw_version; 232 fw_info->feature = adev->gfx.pfp_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_CE: 235 fw_info->ver = adev->gfx.ce_fw_version; 236 fw_info->feature = adev->gfx.ce_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC: 239 fw_info->ver = adev->gfx.rlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 243 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 247 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 248 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 251 fw_info->ver = adev->gfx.rlc_srls_fw_version; 252 fw_info->feature = adev->gfx.rlc_srls_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_MEC: 255 if (query_fw->index == 0) { 256 fw_info->ver = adev->gfx.mec_fw_version; 257 fw_info->feature = adev->gfx.mec_feature_version; 258 } else if (query_fw->index == 1) { 259 fw_info->ver = adev->gfx.mec2_fw_version; 260 fw_info->feature = adev->gfx.mec2_feature_version; 261 } else 262 return -EINVAL; 263 break; 264 case AMDGPU_INFO_FW_SMC: 265 fw_info->ver = adev->pm.fw_version; 266 fw_info->feature = 0; 267 break; 268 case AMDGPU_INFO_FW_TA: 269 switch (query_fw->index) { 270 case TA_FW_TYPE_PSP_XGMI: 271 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 272 fw_info->feature = adev->psp.xgmi_context.context 273 .bin_desc.feature_version; 274 break; 275 case TA_FW_TYPE_PSP_RAS: 276 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 277 fw_info->feature = adev->psp.ras_context.context 278 .bin_desc.feature_version; 279 break; 280 case TA_FW_TYPE_PSP_HDCP: 281 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 282 fw_info->feature = adev->psp.hdcp_context.context 283 .bin_desc.feature_version; 284 break; 285 case TA_FW_TYPE_PSP_DTM: 286 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 287 fw_info->feature = adev->psp.dtm_context.context 288 .bin_desc.feature_version; 289 break; 290 case TA_FW_TYPE_PSP_RAP: 291 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 292 fw_info->feature = adev->psp.rap_context.context 293 .bin_desc.feature_version; 294 break; 295 case TA_FW_TYPE_PSP_SECUREDISPLAY: 296 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 297 fw_info->feature = 298 adev->psp.securedisplay_context.context.bin_desc 299 .feature_version; 300 break; 301 default: 302 return -EINVAL; 303 } 304 break; 305 case AMDGPU_INFO_FW_SDMA: 306 if (query_fw->index >= adev->sdma.num_instances) 307 return -EINVAL; 308 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 309 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 310 break; 311 case AMDGPU_INFO_FW_SOS: 312 fw_info->ver = adev->psp.sos.fw_version; 313 fw_info->feature = adev->psp.sos.feature_version; 314 break; 315 case AMDGPU_INFO_FW_ASD: 316 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 317 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 318 break; 319 case AMDGPU_INFO_FW_DMCU: 320 fw_info->ver = adev->dm.dmcu_fw_version; 321 fw_info->feature = 0; 322 break; 323 case AMDGPU_INFO_FW_DMCUB: 324 fw_info->ver = adev->dm.dmcub_fw_version; 325 fw_info->feature = 0; 326 break; 327 case AMDGPU_INFO_FW_TOC: 328 fw_info->ver = adev->psp.toc.fw_version; 329 fw_info->feature = adev->psp.toc.feature_version; 330 break; 331 case AMDGPU_INFO_FW_CAP: 332 fw_info->ver = adev->psp.cap_fw_version; 333 fw_info->feature = adev->psp.cap_feature_version; 334 break; 335 default: 336 return -EINVAL; 337 } 338 return 0; 339 } 340 341 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 342 struct drm_amdgpu_info *info, 343 struct drm_amdgpu_info_hw_ip *result) 344 { 345 uint32_t ib_start_alignment = 0; 346 uint32_t ib_size_alignment = 0; 347 enum amd_ip_block_type type; 348 unsigned int num_rings = 0; 349 unsigned int i, j; 350 351 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 352 return -EINVAL; 353 354 switch (info->query_hw_ip.type) { 355 case AMDGPU_HW_IP_GFX: 356 type = AMD_IP_BLOCK_TYPE_GFX; 357 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 358 if (adev->gfx.gfx_ring[i].sched.ready) 359 ++num_rings; 360 ib_start_alignment = 32; 361 ib_size_alignment = 32; 362 break; 363 case AMDGPU_HW_IP_COMPUTE: 364 type = AMD_IP_BLOCK_TYPE_GFX; 365 for (i = 0; i < adev->gfx.num_compute_rings; i++) 366 if (adev->gfx.compute_ring[i].sched.ready) 367 ++num_rings; 368 ib_start_alignment = 32; 369 ib_size_alignment = 32; 370 break; 371 case AMDGPU_HW_IP_DMA: 372 type = AMD_IP_BLOCK_TYPE_SDMA; 373 for (i = 0; i < adev->sdma.num_instances; i++) 374 if (adev->sdma.instance[i].ring.sched.ready) 375 ++num_rings; 376 ib_start_alignment = 256; 377 ib_size_alignment = 4; 378 break; 379 case AMDGPU_HW_IP_UVD: 380 type = AMD_IP_BLOCK_TYPE_UVD; 381 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 382 if (adev->uvd.harvest_config & (1 << i)) 383 continue; 384 385 if (adev->uvd.inst[i].ring.sched.ready) 386 ++num_rings; 387 } 388 ib_start_alignment = 64; 389 ib_size_alignment = 64; 390 break; 391 case AMDGPU_HW_IP_VCE: 392 type = AMD_IP_BLOCK_TYPE_VCE; 393 for (i = 0; i < adev->vce.num_rings; i++) 394 if (adev->vce.ring[i].sched.ready) 395 ++num_rings; 396 ib_start_alignment = 4; 397 ib_size_alignment = 1; 398 break; 399 case AMDGPU_HW_IP_UVD_ENC: 400 type = AMD_IP_BLOCK_TYPE_UVD; 401 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 402 if (adev->uvd.harvest_config & (1 << i)) 403 continue; 404 405 for (j = 0; j < adev->uvd.num_enc_rings; j++) 406 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 407 ++num_rings; 408 } 409 ib_start_alignment = 64; 410 ib_size_alignment = 64; 411 break; 412 case AMDGPU_HW_IP_VCN_DEC: 413 type = AMD_IP_BLOCK_TYPE_VCN; 414 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 415 if (adev->uvd.harvest_config & (1 << i)) 416 continue; 417 418 if (adev->vcn.inst[i].ring_dec.sched.ready) 419 ++num_rings; 420 } 421 ib_start_alignment = 16; 422 ib_size_alignment = 16; 423 break; 424 case AMDGPU_HW_IP_VCN_ENC: 425 type = AMD_IP_BLOCK_TYPE_VCN; 426 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 427 if (adev->uvd.harvest_config & (1 << i)) 428 continue; 429 430 for (j = 0; j < adev->vcn.num_enc_rings; j++) 431 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 432 ++num_rings; 433 } 434 ib_start_alignment = 64; 435 ib_size_alignment = 1; 436 break; 437 case AMDGPU_HW_IP_VCN_JPEG: 438 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 439 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 440 441 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 442 if (adev->jpeg.harvest_config & (1 << i)) 443 continue; 444 445 if (adev->jpeg.inst[i].ring_dec.sched.ready) 446 ++num_rings; 447 } 448 ib_start_alignment = 16; 449 ib_size_alignment = 16; 450 break; 451 default: 452 return -EINVAL; 453 } 454 455 for (i = 0; i < adev->num_ip_blocks; i++) 456 if (adev->ip_blocks[i].version->type == type && 457 adev->ip_blocks[i].status.valid) 458 break; 459 460 if (i == adev->num_ip_blocks) 461 return 0; 462 463 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 464 num_rings); 465 466 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 467 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 468 result->capabilities_flags = 0; 469 result->available_rings = (1 << num_rings) - 1; 470 result->ib_start_alignment = ib_start_alignment; 471 result->ib_size_alignment = ib_size_alignment; 472 return 0; 473 } 474 475 /* 476 * Userspace get information ioctl 477 */ 478 /** 479 * amdgpu_info_ioctl - answer a device specific request. 480 * 481 * @dev: drm device pointer 482 * @data: request object 483 * @filp: drm filp 484 * 485 * This function is used to pass device specific parameters to the userspace 486 * drivers. Examples include: pci device id, pipeline parms, tiling params, 487 * etc. (all asics). 488 * Returns 0 on success, -EINVAL on failure. 489 */ 490 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 491 { 492 struct amdgpu_device *adev = drm_to_adev(dev); 493 struct drm_amdgpu_info *info = data; 494 struct amdgpu_mode_info *minfo = &adev->mode_info; 495 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 496 uint32_t size = info->return_size; 497 struct drm_crtc *crtc; 498 uint32_t ui32 = 0; 499 uint64_t ui64 = 0; 500 int i, found; 501 int ui32_size = sizeof(ui32); 502 503 if (!info->return_size || !info->return_pointer) 504 return -EINVAL; 505 506 switch (info->query) { 507 case AMDGPU_INFO_ACCEL_WORKING: 508 ui32 = adev->accel_working; 509 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 510 case AMDGPU_INFO_CRTC_FROM_ID: 511 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 512 crtc = (struct drm_crtc *)minfo->crtcs[i]; 513 if (crtc && crtc->base.id == info->mode_crtc.id) { 514 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 515 ui32 = amdgpu_crtc->crtc_id; 516 found = 1; 517 break; 518 } 519 } 520 if (!found) { 521 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 522 return -EINVAL; 523 } 524 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 525 case AMDGPU_INFO_HW_IP_INFO: { 526 struct drm_amdgpu_info_hw_ip ip = {}; 527 int ret; 528 529 ret = amdgpu_hw_ip_info(adev, info, &ip); 530 if (ret) 531 return ret; 532 533 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 534 return ret ? -EFAULT : 0; 535 } 536 case AMDGPU_INFO_HW_IP_COUNT: { 537 enum amd_ip_block_type type; 538 uint32_t count = 0; 539 540 switch (info->query_hw_ip.type) { 541 case AMDGPU_HW_IP_GFX: 542 type = AMD_IP_BLOCK_TYPE_GFX; 543 break; 544 case AMDGPU_HW_IP_COMPUTE: 545 type = AMD_IP_BLOCK_TYPE_GFX; 546 break; 547 case AMDGPU_HW_IP_DMA: 548 type = AMD_IP_BLOCK_TYPE_SDMA; 549 break; 550 case AMDGPU_HW_IP_UVD: 551 type = AMD_IP_BLOCK_TYPE_UVD; 552 break; 553 case AMDGPU_HW_IP_VCE: 554 type = AMD_IP_BLOCK_TYPE_VCE; 555 break; 556 case AMDGPU_HW_IP_UVD_ENC: 557 type = AMD_IP_BLOCK_TYPE_UVD; 558 break; 559 case AMDGPU_HW_IP_VCN_DEC: 560 case AMDGPU_HW_IP_VCN_ENC: 561 type = AMD_IP_BLOCK_TYPE_VCN; 562 break; 563 case AMDGPU_HW_IP_VCN_JPEG: 564 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 565 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 566 break; 567 default: 568 return -EINVAL; 569 } 570 571 for (i = 0; i < adev->num_ip_blocks; i++) 572 if (adev->ip_blocks[i].version->type == type && 573 adev->ip_blocks[i].status.valid && 574 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 575 count++; 576 577 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 578 } 579 case AMDGPU_INFO_TIMESTAMP: 580 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 581 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 582 case AMDGPU_INFO_FW_VERSION: { 583 struct drm_amdgpu_info_firmware fw_info; 584 int ret; 585 586 /* We only support one instance of each IP block right now. */ 587 if (info->query_fw.ip_instance != 0) 588 return -EINVAL; 589 590 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 591 if (ret) 592 return ret; 593 594 return copy_to_user(out, &fw_info, 595 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 596 } 597 case AMDGPU_INFO_NUM_BYTES_MOVED: 598 ui64 = atomic64_read(&adev->num_bytes_moved); 599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 600 case AMDGPU_INFO_NUM_EVICTIONS: 601 ui64 = atomic64_read(&adev->num_evictions); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 604 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_VRAM_USAGE: 607 ui64 = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_VIS_VRAM_USAGE: 610 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 612 case AMDGPU_INFO_GTT_USAGE: 613 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 614 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 615 case AMDGPU_INFO_GDS_CONFIG: { 616 struct drm_amdgpu_info_gds gds_info; 617 618 memset(&gds_info, 0, sizeof(gds_info)); 619 gds_info.compute_partition_size = adev->gds.gds_size; 620 gds_info.gds_total_size = adev->gds.gds_size; 621 gds_info.gws_per_compute_partition = adev->gds.gws_size; 622 gds_info.oa_per_compute_partition = adev->gds.oa_size; 623 return copy_to_user(out, &gds_info, 624 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 625 } 626 case AMDGPU_INFO_VRAM_GTT: { 627 struct drm_amdgpu_info_vram_gtt vram_gtt; 628 629 vram_gtt.vram_size = adev->gmc.real_vram_size - 630 atomic64_read(&adev->vram_pin_size) - 631 AMDGPU_VM_RESERVED_VRAM; 632 vram_gtt.vram_cpu_accessible_size = 633 min(adev->gmc.visible_vram_size - 634 atomic64_read(&adev->visible_pin_size), 635 vram_gtt.vram_size); 636 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 637 vram_gtt.gtt_size *= PAGE_SIZE; 638 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 639 return copy_to_user(out, &vram_gtt, 640 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 641 } 642 case AMDGPU_INFO_MEMORY: { 643 struct drm_amdgpu_memory_info mem; 644 struct ttm_resource_manager *gtt_man = 645 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 646 memset(&mem, 0, sizeof(mem)); 647 mem.vram.total_heap_size = adev->gmc.real_vram_size; 648 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 649 atomic64_read(&adev->vram_pin_size) - 650 AMDGPU_VM_RESERVED_VRAM; 651 mem.vram.heap_usage = 652 amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); 653 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 654 655 mem.cpu_accessible_vram.total_heap_size = 656 adev->gmc.visible_vram_size; 657 mem.cpu_accessible_vram.usable_heap_size = 658 min(adev->gmc.visible_vram_size - 659 atomic64_read(&adev->visible_pin_size), 660 mem.vram.usable_heap_size); 661 mem.cpu_accessible_vram.heap_usage = 662 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 663 mem.cpu_accessible_vram.max_allocation = 664 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 665 666 mem.gtt.total_heap_size = gtt_man->size; 667 mem.gtt.total_heap_size *= PAGE_SIZE; 668 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 669 atomic64_read(&adev->gart_pin_size); 670 mem.gtt.heap_usage = 671 amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr); 672 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 673 674 return copy_to_user(out, &mem, 675 min((size_t)size, sizeof(mem))) 676 ? -EFAULT : 0; 677 } 678 case AMDGPU_INFO_READ_MMR_REG: { 679 unsigned n, alloc_size; 680 uint32_t *regs; 681 unsigned se_num = (info->read_mmr_reg.instance >> 682 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 683 AMDGPU_INFO_MMR_SE_INDEX_MASK; 684 unsigned sh_num = (info->read_mmr_reg.instance >> 685 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 686 AMDGPU_INFO_MMR_SH_INDEX_MASK; 687 688 /* set full masks if the userspace set all bits 689 * in the bitfields */ 690 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 691 se_num = 0xffffffff; 692 else if (se_num >= AMDGPU_GFX_MAX_SE) 693 return -EINVAL; 694 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 695 sh_num = 0xffffffff; 696 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 697 return -EINVAL; 698 699 if (info->read_mmr_reg.count > 128) 700 return -EINVAL; 701 702 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 703 if (!regs) 704 return -ENOMEM; 705 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 706 707 amdgpu_gfx_off_ctrl(adev, false); 708 for (i = 0; i < info->read_mmr_reg.count; i++) { 709 if (amdgpu_asic_read_register(adev, se_num, sh_num, 710 info->read_mmr_reg.dword_offset + i, 711 ®s[i])) { 712 DRM_DEBUG_KMS("unallowed offset %#x\n", 713 info->read_mmr_reg.dword_offset + i); 714 kfree(regs); 715 amdgpu_gfx_off_ctrl(adev, true); 716 return -EFAULT; 717 } 718 } 719 amdgpu_gfx_off_ctrl(adev, true); 720 n = copy_to_user(out, regs, min(size, alloc_size)); 721 kfree(regs); 722 return n ? -EFAULT : 0; 723 } 724 case AMDGPU_INFO_DEV_INFO: { 725 struct drm_amdgpu_info_device *dev_info; 726 uint64_t vm_size; 727 int ret; 728 729 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 730 if (!dev_info) 731 return -ENOMEM; 732 733 dev_info->device_id = adev->pdev->device; 734 dev_info->chip_rev = adev->rev_id; 735 dev_info->external_rev = adev->external_rev_id; 736 dev_info->pci_rev = adev->pdev->revision; 737 dev_info->family = adev->family; 738 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 739 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 740 /* return all clocks in KHz */ 741 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 742 if (adev->pm.dpm_enabled) { 743 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 744 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 745 } else { 746 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 747 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 748 } 749 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 750 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 751 adev->gfx.config.max_shader_engines; 752 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 753 dev_info->_pad = 0; 754 dev_info->ids_flags = 0; 755 if (adev->flags & AMD_IS_APU) 756 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 757 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 758 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 759 if (amdgpu_is_tmz(adev)) 760 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 761 762 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 763 vm_size -= AMDGPU_VA_RESERVED_SIZE; 764 765 /* Older VCE FW versions are buggy and can handle only 40bits */ 766 if (adev->vce.fw_version && 767 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 768 vm_size = min(vm_size, 1ULL << 40); 769 770 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 771 dev_info->virtual_address_max = 772 min(vm_size, AMDGPU_GMC_HOLE_START); 773 774 if (vm_size > AMDGPU_GMC_HOLE_START) { 775 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 776 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 777 } 778 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 779 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 780 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 781 dev_info->cu_active_number = adev->gfx.cu_info.number; 782 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 783 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 784 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 785 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 786 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 787 sizeof(adev->gfx.cu_info.bitmap)); 788 dev_info->vram_type = adev->gmc.vram_type; 789 dev_info->vram_bit_width = adev->gmc.vram_width; 790 dev_info->vce_harvest_config = adev->vce.harvest_config; 791 dev_info->gc_double_offchip_lds_buf = 792 adev->gfx.config.double_offchip_lds_buf; 793 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 794 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 795 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 796 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 797 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 798 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 799 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 800 801 if (adev->family >= AMDGPU_FAMILY_NV) 802 dev_info->pa_sc_tile_steering_override = 803 adev->gfx.config.pa_sc_tile_steering_override; 804 805 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 806 807 ret = copy_to_user(out, dev_info, 808 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 809 kfree(dev_info); 810 return ret; 811 } 812 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 813 unsigned i; 814 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 815 struct amd_vce_state *vce_state; 816 817 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 818 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 819 if (vce_state) { 820 vce_clk_table.entries[i].sclk = vce_state->sclk; 821 vce_clk_table.entries[i].mclk = vce_state->mclk; 822 vce_clk_table.entries[i].eclk = vce_state->evclk; 823 vce_clk_table.num_valid_entries++; 824 } 825 } 826 827 return copy_to_user(out, &vce_clk_table, 828 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 829 } 830 case AMDGPU_INFO_VBIOS: { 831 uint32_t bios_size = adev->bios_size; 832 833 switch (info->vbios_info.type) { 834 case AMDGPU_INFO_VBIOS_SIZE: 835 return copy_to_user(out, &bios_size, 836 min((size_t)size, sizeof(bios_size))) 837 ? -EFAULT : 0; 838 case AMDGPU_INFO_VBIOS_IMAGE: { 839 uint8_t *bios; 840 uint32_t bios_offset = info->vbios_info.offset; 841 842 if (bios_offset >= bios_size) 843 return -EINVAL; 844 845 bios = adev->bios + bios_offset; 846 return copy_to_user(out, bios, 847 min((size_t)size, (size_t)(bios_size - bios_offset))) 848 ? -EFAULT : 0; 849 } 850 case AMDGPU_INFO_VBIOS_INFO: { 851 struct drm_amdgpu_info_vbios vbios_info = {}; 852 struct atom_context *atom_context; 853 854 atom_context = adev->mode_info.atom_context; 855 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 856 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 857 vbios_info.version = atom_context->version; 858 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 859 sizeof(atom_context->vbios_ver_str)); 860 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 861 862 return copy_to_user(out, &vbios_info, 863 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 864 } 865 default: 866 DRM_DEBUG_KMS("Invalid request %d\n", 867 info->vbios_info.type); 868 return -EINVAL; 869 } 870 } 871 case AMDGPU_INFO_NUM_HANDLES: { 872 struct drm_amdgpu_info_num_handles handle; 873 874 switch (info->query_hw_ip.type) { 875 case AMDGPU_HW_IP_UVD: 876 /* Starting Polaris, we support unlimited UVD handles */ 877 if (adev->asic_type < CHIP_POLARIS10) { 878 handle.uvd_max_handles = adev->uvd.max_handles; 879 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 880 881 return copy_to_user(out, &handle, 882 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 883 } else { 884 return -ENODATA; 885 } 886 887 break; 888 default: 889 return -EINVAL; 890 } 891 } 892 case AMDGPU_INFO_SENSOR: { 893 if (!adev->pm.dpm_enabled) 894 return -ENOENT; 895 896 switch (info->sensor_info.type) { 897 case AMDGPU_INFO_SENSOR_GFX_SCLK: 898 /* get sclk in Mhz */ 899 if (amdgpu_dpm_read_sensor(adev, 900 AMDGPU_PP_SENSOR_GFX_SCLK, 901 (void *)&ui32, &ui32_size)) { 902 return -EINVAL; 903 } 904 ui32 /= 100; 905 break; 906 case AMDGPU_INFO_SENSOR_GFX_MCLK: 907 /* get mclk in Mhz */ 908 if (amdgpu_dpm_read_sensor(adev, 909 AMDGPU_PP_SENSOR_GFX_MCLK, 910 (void *)&ui32, &ui32_size)) { 911 return -EINVAL; 912 } 913 ui32 /= 100; 914 break; 915 case AMDGPU_INFO_SENSOR_GPU_TEMP: 916 /* get temperature in millidegrees C */ 917 if (amdgpu_dpm_read_sensor(adev, 918 AMDGPU_PP_SENSOR_GPU_TEMP, 919 (void *)&ui32, &ui32_size)) { 920 return -EINVAL; 921 } 922 break; 923 case AMDGPU_INFO_SENSOR_GPU_LOAD: 924 /* get GPU load */ 925 if (amdgpu_dpm_read_sensor(adev, 926 AMDGPU_PP_SENSOR_GPU_LOAD, 927 (void *)&ui32, &ui32_size)) { 928 return -EINVAL; 929 } 930 break; 931 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 932 /* get average GPU power */ 933 if (amdgpu_dpm_read_sensor(adev, 934 AMDGPU_PP_SENSOR_GPU_POWER, 935 (void *)&ui32, &ui32_size)) { 936 return -EINVAL; 937 } 938 ui32 >>= 8; 939 break; 940 case AMDGPU_INFO_SENSOR_VDDNB: 941 /* get VDDNB in millivolts */ 942 if (amdgpu_dpm_read_sensor(adev, 943 AMDGPU_PP_SENSOR_VDDNB, 944 (void *)&ui32, &ui32_size)) { 945 return -EINVAL; 946 } 947 break; 948 case AMDGPU_INFO_SENSOR_VDDGFX: 949 /* get VDDGFX in millivolts */ 950 if (amdgpu_dpm_read_sensor(adev, 951 AMDGPU_PP_SENSOR_VDDGFX, 952 (void *)&ui32, &ui32_size)) { 953 return -EINVAL; 954 } 955 break; 956 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 957 /* get stable pstate sclk in Mhz */ 958 if (amdgpu_dpm_read_sensor(adev, 959 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 960 (void *)&ui32, &ui32_size)) { 961 return -EINVAL; 962 } 963 ui32 /= 100; 964 break; 965 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 966 /* get stable pstate mclk in Mhz */ 967 if (amdgpu_dpm_read_sensor(adev, 968 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 969 (void *)&ui32, &ui32_size)) { 970 return -EINVAL; 971 } 972 ui32 /= 100; 973 break; 974 default: 975 DRM_DEBUG_KMS("Invalid request %d\n", 976 info->sensor_info.type); 977 return -EINVAL; 978 } 979 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 980 } 981 case AMDGPU_INFO_VRAM_LOST_COUNTER: 982 ui32 = atomic_read(&adev->vram_lost_counter); 983 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 984 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 985 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 986 uint64_t ras_mask; 987 988 if (!ras) 989 return -EINVAL; 990 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 991 992 return copy_to_user(out, &ras_mask, 993 min_t(u64, size, sizeof(ras_mask))) ? 994 -EFAULT : 0; 995 } 996 case AMDGPU_INFO_VIDEO_CAPS: { 997 const struct amdgpu_video_codecs *codecs; 998 struct drm_amdgpu_info_video_caps *caps; 999 int r; 1000 1001 switch (info->video_cap.type) { 1002 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1003 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1004 if (r) 1005 return -EINVAL; 1006 break; 1007 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1008 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1009 if (r) 1010 return -EINVAL; 1011 break; 1012 default: 1013 DRM_DEBUG_KMS("Invalid request %d\n", 1014 info->video_cap.type); 1015 return -EINVAL; 1016 } 1017 1018 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1019 if (!caps) 1020 return -ENOMEM; 1021 1022 for (i = 0; i < codecs->codec_count; i++) { 1023 int idx = codecs->codec_array[i].codec_type; 1024 1025 switch (idx) { 1026 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1027 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1028 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1029 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1030 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1031 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1032 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1033 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1034 caps->codec_info[idx].valid = 1; 1035 caps->codec_info[idx].max_width = 1036 codecs->codec_array[i].max_width; 1037 caps->codec_info[idx].max_height = 1038 codecs->codec_array[i].max_height; 1039 caps->codec_info[idx].max_pixels_per_frame = 1040 codecs->codec_array[i].max_pixels_per_frame; 1041 caps->codec_info[idx].max_level = 1042 codecs->codec_array[i].max_level; 1043 break; 1044 default: 1045 break; 1046 } 1047 } 1048 r = copy_to_user(out, caps, 1049 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1050 kfree(caps); 1051 return r; 1052 } 1053 default: 1054 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1055 return -EINVAL; 1056 } 1057 return 0; 1058 } 1059 1060 1061 /* 1062 * Outdated mess for old drm with Xorg being in charge (void function now). 1063 */ 1064 /** 1065 * amdgpu_driver_lastclose_kms - drm callback for last close 1066 * 1067 * @dev: drm dev pointer 1068 * 1069 * Switch vga_switcheroo state after last close (all asics). 1070 */ 1071 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1072 { 1073 drm_fb_helper_lastclose(dev); 1074 vga_switcheroo_process_delayed_switch(); 1075 } 1076 1077 /** 1078 * amdgpu_driver_open_kms - drm callback for open 1079 * 1080 * @dev: drm dev pointer 1081 * @file_priv: drm file 1082 * 1083 * On device open, init vm on cayman+ (all asics). 1084 * Returns 0 on success, error on failure. 1085 */ 1086 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1087 { 1088 struct amdgpu_device *adev = drm_to_adev(dev); 1089 struct amdgpu_fpriv *fpriv; 1090 int r, pasid; 1091 1092 /* Ensure IB tests are run on ring */ 1093 flush_delayed_work(&adev->delayed_init_work); 1094 1095 1096 if (amdgpu_ras_intr_triggered()) { 1097 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1098 return -EHWPOISON; 1099 } 1100 1101 file_priv->driver_priv = NULL; 1102 1103 r = pm_runtime_get_sync(dev->dev); 1104 if (r < 0) 1105 goto pm_put; 1106 1107 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1108 if (unlikely(!fpriv)) { 1109 r = -ENOMEM; 1110 goto out_suspend; 1111 } 1112 1113 pasid = amdgpu_pasid_alloc(16); 1114 if (pasid < 0) { 1115 dev_warn(adev->dev, "No more PASIDs available!"); 1116 pasid = 0; 1117 } 1118 1119 r = amdgpu_vm_init(adev, &fpriv->vm); 1120 if (r) 1121 goto error_pasid; 1122 1123 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1124 if (r) 1125 goto error_vm; 1126 1127 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1128 if (!fpriv->prt_va) { 1129 r = -ENOMEM; 1130 goto error_vm; 1131 } 1132 1133 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1134 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1135 1136 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1137 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1138 if (r) 1139 goto error_vm; 1140 } 1141 1142 mutex_init(&fpriv->bo_list_lock); 1143 idr_init(&fpriv->bo_list_handles); 1144 1145 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1146 1147 file_priv->driver_priv = fpriv; 1148 goto out_suspend; 1149 1150 error_vm: 1151 amdgpu_vm_fini(adev, &fpriv->vm); 1152 1153 error_pasid: 1154 if (pasid) { 1155 amdgpu_pasid_free(pasid); 1156 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1157 } 1158 1159 kfree(fpriv); 1160 1161 out_suspend: 1162 pm_runtime_mark_last_busy(dev->dev); 1163 pm_put: 1164 pm_runtime_put_autosuspend(dev->dev); 1165 1166 return r; 1167 } 1168 1169 /** 1170 * amdgpu_driver_postclose_kms - drm callback for post close 1171 * 1172 * @dev: drm dev pointer 1173 * @file_priv: drm file 1174 * 1175 * On device post close, tear down vm on cayman+ (all asics). 1176 */ 1177 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1178 struct drm_file *file_priv) 1179 { 1180 struct amdgpu_device *adev = drm_to_adev(dev); 1181 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1182 struct amdgpu_bo_list *list; 1183 struct amdgpu_bo *pd; 1184 u32 pasid; 1185 int handle; 1186 1187 if (!fpriv) 1188 return; 1189 1190 pm_runtime_get_sync(dev->dev); 1191 1192 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1193 amdgpu_uvd_free_handles(adev, file_priv); 1194 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1195 amdgpu_vce_free_handles(adev, file_priv); 1196 1197 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1198 /* TODO: how to handle reserve failure */ 1199 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1200 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1201 fpriv->csa_va = NULL; 1202 amdgpu_bo_unreserve(adev->virt.csa_obj); 1203 } 1204 1205 pasid = fpriv->vm.pasid; 1206 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1207 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1208 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1209 amdgpu_bo_unreserve(pd); 1210 } 1211 1212 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1213 amdgpu_vm_fini(adev, &fpriv->vm); 1214 1215 if (pasid) 1216 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1217 amdgpu_bo_unref(&pd); 1218 1219 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1220 amdgpu_bo_list_put(list); 1221 1222 idr_destroy(&fpriv->bo_list_handles); 1223 mutex_destroy(&fpriv->bo_list_lock); 1224 1225 kfree(fpriv); 1226 file_priv->driver_priv = NULL; 1227 1228 pm_runtime_mark_last_busy(dev->dev); 1229 pm_runtime_put_autosuspend(dev->dev); 1230 } 1231 1232 1233 void amdgpu_driver_release_kms(struct drm_device *dev) 1234 { 1235 struct amdgpu_device *adev = drm_to_adev(dev); 1236 1237 amdgpu_device_fini_sw(adev); 1238 pci_set_drvdata(adev->pdev, NULL); 1239 } 1240 1241 /* 1242 * VBlank related functions. 1243 */ 1244 /** 1245 * amdgpu_get_vblank_counter_kms - get frame count 1246 * 1247 * @crtc: crtc to get the frame count from 1248 * 1249 * Gets the frame count on the requested crtc (all asics). 1250 * Returns frame count on success, -EINVAL on failure. 1251 */ 1252 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1253 { 1254 struct drm_device *dev = crtc->dev; 1255 unsigned int pipe = crtc->index; 1256 struct amdgpu_device *adev = drm_to_adev(dev); 1257 int vpos, hpos, stat; 1258 u32 count; 1259 1260 if (pipe >= adev->mode_info.num_crtc) { 1261 DRM_ERROR("Invalid crtc %u\n", pipe); 1262 return -EINVAL; 1263 } 1264 1265 /* The hw increments its frame counter at start of vsync, not at start 1266 * of vblank, as is required by DRM core vblank counter handling. 1267 * Cook the hw count here to make it appear to the caller as if it 1268 * incremented at start of vblank. We measure distance to start of 1269 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1270 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1271 * result by 1 to give the proper appearance to caller. 1272 */ 1273 if (adev->mode_info.crtcs[pipe]) { 1274 /* Repeat readout if needed to provide stable result if 1275 * we cross start of vsync during the queries. 1276 */ 1277 do { 1278 count = amdgpu_display_vblank_get_counter(adev, pipe); 1279 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1280 * vpos as distance to start of vblank, instead of 1281 * regular vertical scanout pos. 1282 */ 1283 stat = amdgpu_display_get_crtc_scanoutpos( 1284 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1285 &vpos, &hpos, NULL, NULL, 1286 &adev->mode_info.crtcs[pipe]->base.hwmode); 1287 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1288 1289 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1290 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1291 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1292 } else { 1293 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1294 pipe, vpos); 1295 1296 /* Bump counter if we are at >= leading edge of vblank, 1297 * but before vsync where vpos would turn negative and 1298 * the hw counter really increments. 1299 */ 1300 if (vpos >= 0) 1301 count++; 1302 } 1303 } else { 1304 /* Fallback to use value as is. */ 1305 count = amdgpu_display_vblank_get_counter(adev, pipe); 1306 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1307 } 1308 1309 return count; 1310 } 1311 1312 /** 1313 * amdgpu_enable_vblank_kms - enable vblank interrupt 1314 * 1315 * @crtc: crtc to enable vblank interrupt for 1316 * 1317 * Enable the interrupt on the requested crtc (all asics). 1318 * Returns 0 on success, -EINVAL on failure. 1319 */ 1320 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1321 { 1322 struct drm_device *dev = crtc->dev; 1323 unsigned int pipe = crtc->index; 1324 struct amdgpu_device *adev = drm_to_adev(dev); 1325 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1326 1327 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1328 } 1329 1330 /** 1331 * amdgpu_disable_vblank_kms - disable vblank interrupt 1332 * 1333 * @crtc: crtc to disable vblank interrupt for 1334 * 1335 * Disable the interrupt on the requested crtc (all asics). 1336 */ 1337 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1338 { 1339 struct drm_device *dev = crtc->dev; 1340 unsigned int pipe = crtc->index; 1341 struct amdgpu_device *adev = drm_to_adev(dev); 1342 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1343 1344 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1345 } 1346 1347 /* 1348 * Debugfs info 1349 */ 1350 #if defined(CONFIG_DEBUG_FS) 1351 1352 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1353 { 1354 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1355 struct drm_amdgpu_info_firmware fw_info; 1356 struct drm_amdgpu_query_fw query_fw; 1357 struct atom_context *ctx = adev->mode_info.atom_context; 1358 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1359 int ret, i; 1360 1361 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1362 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1363 TA_FW_NAME(XGMI), 1364 TA_FW_NAME(RAS), 1365 TA_FW_NAME(HDCP), 1366 TA_FW_NAME(DTM), 1367 TA_FW_NAME(RAP), 1368 TA_FW_NAME(SECUREDISPLAY), 1369 #undef TA_FW_NAME 1370 }; 1371 1372 /* VCE */ 1373 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1374 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1375 if (ret) 1376 return ret; 1377 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1378 fw_info.feature, fw_info.ver); 1379 1380 /* UVD */ 1381 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1382 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1383 if (ret) 1384 return ret; 1385 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1386 fw_info.feature, fw_info.ver); 1387 1388 /* GMC */ 1389 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1390 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1391 if (ret) 1392 return ret; 1393 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1394 fw_info.feature, fw_info.ver); 1395 1396 /* ME */ 1397 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1398 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1399 if (ret) 1400 return ret; 1401 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1402 fw_info.feature, fw_info.ver); 1403 1404 /* PFP */ 1405 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1406 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1407 if (ret) 1408 return ret; 1409 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1410 fw_info.feature, fw_info.ver); 1411 1412 /* CE */ 1413 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1414 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1415 if (ret) 1416 return ret; 1417 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1418 fw_info.feature, fw_info.ver); 1419 1420 /* RLC */ 1421 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1423 if (ret) 1424 return ret; 1425 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1426 fw_info.feature, fw_info.ver); 1427 1428 /* RLC SAVE RESTORE LIST CNTL */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1431 if (ret) 1432 return ret; 1433 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1434 fw_info.feature, fw_info.ver); 1435 1436 /* RLC SAVE RESTORE LIST GPM MEM */ 1437 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1438 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1439 if (ret) 1440 return ret; 1441 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1442 fw_info.feature, fw_info.ver); 1443 1444 /* RLC SAVE RESTORE LIST SRM MEM */ 1445 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1446 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1447 if (ret) 1448 return ret; 1449 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1450 fw_info.feature, fw_info.ver); 1451 1452 /* MEC */ 1453 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1454 query_fw.index = 0; 1455 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1456 if (ret) 1457 return ret; 1458 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1459 fw_info.feature, fw_info.ver); 1460 1461 /* MEC2 */ 1462 if (adev->gfx.mec2_fw) { 1463 query_fw.index = 1; 1464 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1465 if (ret) 1466 return ret; 1467 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1468 fw_info.feature, fw_info.ver); 1469 } 1470 1471 /* PSP SOS */ 1472 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1473 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1474 if (ret) 1475 return ret; 1476 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1477 fw_info.feature, fw_info.ver); 1478 1479 1480 /* PSP ASD */ 1481 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1482 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1483 if (ret) 1484 return ret; 1485 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1486 fw_info.feature, fw_info.ver); 1487 1488 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1489 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1490 query_fw.index = i; 1491 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1492 if (ret) 1493 continue; 1494 1495 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1496 ta_fw_name[i], fw_info.feature, fw_info.ver); 1497 } 1498 1499 /* SMC */ 1500 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1501 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1502 if (ret) 1503 return ret; 1504 smu_program = (fw_info.ver >> 24) & 0xff; 1505 smu_major = (fw_info.ver >> 16) & 0xff; 1506 smu_minor = (fw_info.ver >> 8) & 0xff; 1507 smu_debug = (fw_info.ver >> 0) & 0xff; 1508 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1509 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1510 1511 /* SDMA */ 1512 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1513 for (i = 0; i < adev->sdma.num_instances; i++) { 1514 query_fw.index = i; 1515 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1516 if (ret) 1517 return ret; 1518 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1519 i, fw_info.feature, fw_info.ver); 1520 } 1521 1522 /* VCN */ 1523 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1525 if (ret) 1526 return ret; 1527 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1528 fw_info.feature, fw_info.ver); 1529 1530 /* DMCU */ 1531 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1532 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1533 if (ret) 1534 return ret; 1535 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1536 fw_info.feature, fw_info.ver); 1537 1538 /* DMCUB */ 1539 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1540 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1541 if (ret) 1542 return ret; 1543 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1544 fw_info.feature, fw_info.ver); 1545 1546 /* TOC */ 1547 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1548 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1549 if (ret) 1550 return ret; 1551 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1552 fw_info.feature, fw_info.ver); 1553 1554 /* CAP */ 1555 if (adev->psp.cap_fw) { 1556 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1557 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1558 if (ret) 1559 return ret; 1560 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1561 fw_info.feature, fw_info.ver); 1562 } 1563 1564 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1565 1566 return 0; 1567 } 1568 1569 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1570 1571 #endif 1572 1573 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1574 { 1575 #if defined(CONFIG_DEBUG_FS) 1576 struct drm_minor *minor = adev_to_drm(adev)->primary; 1577 struct dentry *root = minor->debugfs_root; 1578 1579 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1580 adev, &amdgpu_debugfs_firmware_info_fops); 1581 1582 #endif 1583 } 1584