1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amd_pcie.h" 47 48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 49 { 50 struct amdgpu_gpu_instance *gpu_instance; 51 int i; 52 53 mutex_lock(&mgpu_info.mutex); 54 55 for (i = 0; i < mgpu_info.num_gpu; i++) { 56 gpu_instance = &(mgpu_info.gpu_ins[i]); 57 if (gpu_instance->adev == adev) { 58 mgpu_info.gpu_ins[i] = 59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 60 mgpu_info.num_gpu--; 61 if (adev->flags & AMD_IS_APU) 62 mgpu_info.num_apu--; 63 else 64 mgpu_info.num_dgpu--; 65 break; 66 } 67 } 68 69 mutex_unlock(&mgpu_info.mutex); 70 } 71 72 /** 73 * amdgpu_driver_unload_kms - Main unload function for KMS. 74 * 75 * @dev: drm dev pointer 76 * 77 * This is the main unload function for KMS (all asics). 78 * Returns 0 on success. 79 */ 80 void amdgpu_driver_unload_kms(struct drm_device *dev) 81 { 82 struct amdgpu_device *adev = drm_to_adev(dev); 83 84 if (adev == NULL) 85 return; 86 87 amdgpu_unregister_gpu_instance(adev); 88 89 if (adev->rmmio == NULL) 90 return; 91 92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 93 DRM_WARN("smart shift update failed\n"); 94 95 amdgpu_acpi_fini(adev); 96 amdgpu_device_fini_hw(adev); 97 } 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 /** 125 * amdgpu_driver_load_kms - Main load function for KMS. 126 * 127 * @adev: pointer to struct amdgpu_device 128 * @flags: device flags 129 * 130 * This is the main load function for KMS (all asics). 131 * Returns 0 on success, error on failure. 132 */ 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 134 { 135 struct drm_device *dev; 136 int r, acpi_status; 137 138 dev = adev_to_drm(adev); 139 140 /* amdgpu_device_init should report only fatal error 141 * like memory allocation failure or iomapping failure, 142 * or memory manager initialization failure, it must 143 * properly initialize the GPU MC controller and permit 144 * VRAM allocation 145 */ 146 r = amdgpu_device_init(adev, flags); 147 if (r) { 148 dev_err(dev->dev, "Fatal error during GPU init\n"); 149 goto out; 150 } 151 152 amdgpu_device_detect_runtime_pm_mode(adev); 153 154 /* Call ACPI methods: require modeset init 155 * but failure is not fatal 156 */ 157 158 acpi_status = amdgpu_acpi_init(adev); 159 if (acpi_status) 160 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 161 162 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 163 DRM_WARN("smart shift update failed\n"); 164 165 out: 166 if (r) 167 amdgpu_driver_unload_kms(dev); 168 169 return r; 170 } 171 172 static enum amd_ip_block_type 173 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 174 { 175 enum amd_ip_block_type type; 176 177 switch (ip) { 178 case AMDGPU_HW_IP_GFX: 179 type = AMD_IP_BLOCK_TYPE_GFX; 180 break; 181 case AMDGPU_HW_IP_COMPUTE: 182 type = AMD_IP_BLOCK_TYPE_GFX; 183 break; 184 case AMDGPU_HW_IP_DMA: 185 type = AMD_IP_BLOCK_TYPE_SDMA; 186 break; 187 case AMDGPU_HW_IP_UVD: 188 case AMDGPU_HW_IP_UVD_ENC: 189 type = AMD_IP_BLOCK_TYPE_UVD; 190 break; 191 case AMDGPU_HW_IP_VCE: 192 type = AMD_IP_BLOCK_TYPE_VCE; 193 break; 194 case AMDGPU_HW_IP_VCN_DEC: 195 case AMDGPU_HW_IP_VCN_ENC: 196 type = AMD_IP_BLOCK_TYPE_VCN; 197 break; 198 case AMDGPU_HW_IP_VCN_JPEG: 199 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 200 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 201 break; 202 default: 203 type = AMD_IP_BLOCK_TYPE_NUM; 204 break; 205 } 206 207 return type; 208 } 209 210 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 211 struct drm_amdgpu_query_fw *query_fw, 212 struct amdgpu_device *adev) 213 { 214 switch (query_fw->fw_type) { 215 case AMDGPU_INFO_FW_VCE: 216 fw_info->ver = adev->vce.fw_version; 217 fw_info->feature = adev->vce.fb_version; 218 break; 219 case AMDGPU_INFO_FW_UVD: 220 fw_info->ver = adev->uvd.fw_version; 221 fw_info->feature = 0; 222 break; 223 case AMDGPU_INFO_FW_VCN: 224 fw_info->ver = adev->vcn.fw_version; 225 fw_info->feature = 0; 226 break; 227 case AMDGPU_INFO_FW_GMC: 228 fw_info->ver = adev->gmc.fw_version; 229 fw_info->feature = 0; 230 break; 231 case AMDGPU_INFO_FW_GFX_ME: 232 fw_info->ver = adev->gfx.me_fw_version; 233 fw_info->feature = adev->gfx.me_feature_version; 234 break; 235 case AMDGPU_INFO_FW_GFX_PFP: 236 fw_info->ver = adev->gfx.pfp_fw_version; 237 fw_info->feature = adev->gfx.pfp_feature_version; 238 break; 239 case AMDGPU_INFO_FW_GFX_CE: 240 fw_info->ver = adev->gfx.ce_fw_version; 241 fw_info->feature = adev->gfx.ce_feature_version; 242 break; 243 case AMDGPU_INFO_FW_GFX_RLC: 244 fw_info->ver = adev->gfx.rlc_fw_version; 245 fw_info->feature = adev->gfx.rlc_feature_version; 246 break; 247 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 248 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 249 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 252 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 253 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 256 fw_info->ver = adev->gfx.rlc_srls_fw_version; 257 fw_info->feature = adev->gfx.rlc_srls_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_RLCP: 260 fw_info->ver = adev->gfx.rlcp_ucode_version; 261 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_RLCV: 264 fw_info->ver = adev->gfx.rlcv_ucode_version; 265 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 266 break; 267 case AMDGPU_INFO_FW_GFX_MEC: 268 if (query_fw->index == 0) { 269 fw_info->ver = adev->gfx.mec_fw_version; 270 fw_info->feature = adev->gfx.mec_feature_version; 271 } else if (query_fw->index == 1) { 272 fw_info->ver = adev->gfx.mec2_fw_version; 273 fw_info->feature = adev->gfx.mec2_feature_version; 274 } else 275 return -EINVAL; 276 break; 277 case AMDGPU_INFO_FW_SMC: 278 fw_info->ver = adev->pm.fw_version; 279 fw_info->feature = 0; 280 break; 281 case AMDGPU_INFO_FW_TA: 282 switch (query_fw->index) { 283 case TA_FW_TYPE_PSP_XGMI: 284 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 285 fw_info->feature = adev->psp.xgmi_context.context 286 .bin_desc.feature_version; 287 break; 288 case TA_FW_TYPE_PSP_RAS: 289 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 290 fw_info->feature = adev->psp.ras_context.context 291 .bin_desc.feature_version; 292 break; 293 case TA_FW_TYPE_PSP_HDCP: 294 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 295 fw_info->feature = adev->psp.hdcp_context.context 296 .bin_desc.feature_version; 297 break; 298 case TA_FW_TYPE_PSP_DTM: 299 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 300 fw_info->feature = adev->psp.dtm_context.context 301 .bin_desc.feature_version; 302 break; 303 case TA_FW_TYPE_PSP_RAP: 304 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 305 fw_info->feature = adev->psp.rap_context.context 306 .bin_desc.feature_version; 307 break; 308 case TA_FW_TYPE_PSP_SECUREDISPLAY: 309 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 310 fw_info->feature = 311 adev->psp.securedisplay_context.context.bin_desc 312 .feature_version; 313 break; 314 default: 315 return -EINVAL; 316 } 317 break; 318 case AMDGPU_INFO_FW_SDMA: 319 if (query_fw->index >= adev->sdma.num_instances) 320 return -EINVAL; 321 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 322 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 323 break; 324 case AMDGPU_INFO_FW_SOS: 325 fw_info->ver = adev->psp.sos.fw_version; 326 fw_info->feature = adev->psp.sos.feature_version; 327 break; 328 case AMDGPU_INFO_FW_ASD: 329 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 330 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 331 break; 332 case AMDGPU_INFO_FW_DMCU: 333 fw_info->ver = adev->dm.dmcu_fw_version; 334 fw_info->feature = 0; 335 break; 336 case AMDGPU_INFO_FW_DMCUB: 337 fw_info->ver = adev->dm.dmcub_fw_version; 338 fw_info->feature = 0; 339 break; 340 case AMDGPU_INFO_FW_TOC: 341 fw_info->ver = adev->psp.toc.fw_version; 342 fw_info->feature = adev->psp.toc.feature_version; 343 break; 344 case AMDGPU_INFO_FW_CAP: 345 fw_info->ver = adev->psp.cap_fw_version; 346 fw_info->feature = adev->psp.cap_feature_version; 347 break; 348 case AMDGPU_INFO_FW_MES_KIQ: 349 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 350 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 351 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 352 break; 353 case AMDGPU_INFO_FW_MES: 354 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 355 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 356 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 357 break; 358 case AMDGPU_INFO_FW_IMU: 359 fw_info->ver = adev->gfx.imu_fw_version; 360 fw_info->feature = 0; 361 break; 362 case AMDGPU_INFO_FW_VPE: 363 fw_info->ver = adev->vpe.fw_version; 364 fw_info->feature = adev->vpe.feature_version; 365 break; 366 default: 367 return -EINVAL; 368 } 369 return 0; 370 } 371 372 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 373 struct drm_amdgpu_info *info, 374 struct drm_amdgpu_info_hw_ip *result) 375 { 376 uint32_t ib_start_alignment = 0; 377 uint32_t ib_size_alignment = 0; 378 enum amd_ip_block_type type; 379 unsigned int num_rings = 0; 380 unsigned int i, j; 381 382 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 383 return -EINVAL; 384 385 switch (info->query_hw_ip.type) { 386 case AMDGPU_HW_IP_GFX: 387 type = AMD_IP_BLOCK_TYPE_GFX; 388 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 389 if (adev->gfx.gfx_ring[i].sched.ready) 390 ++num_rings; 391 ib_start_alignment = 32; 392 ib_size_alignment = 32; 393 break; 394 case AMDGPU_HW_IP_COMPUTE: 395 type = AMD_IP_BLOCK_TYPE_GFX; 396 for (i = 0; i < adev->gfx.num_compute_rings; i++) 397 if (adev->gfx.compute_ring[i].sched.ready) 398 ++num_rings; 399 ib_start_alignment = 32; 400 ib_size_alignment = 32; 401 break; 402 case AMDGPU_HW_IP_DMA: 403 type = AMD_IP_BLOCK_TYPE_SDMA; 404 for (i = 0; i < adev->sdma.num_instances; i++) 405 if (adev->sdma.instance[i].ring.sched.ready) 406 ++num_rings; 407 ib_start_alignment = 256; 408 ib_size_alignment = 4; 409 break; 410 case AMDGPU_HW_IP_UVD: 411 type = AMD_IP_BLOCK_TYPE_UVD; 412 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 413 if (adev->uvd.harvest_config & (1 << i)) 414 continue; 415 416 if (adev->uvd.inst[i].ring.sched.ready) 417 ++num_rings; 418 } 419 ib_start_alignment = 256; 420 ib_size_alignment = 64; 421 break; 422 case AMDGPU_HW_IP_VCE: 423 type = AMD_IP_BLOCK_TYPE_VCE; 424 for (i = 0; i < adev->vce.num_rings; i++) 425 if (adev->vce.ring[i].sched.ready) 426 ++num_rings; 427 ib_start_alignment = 256; 428 ib_size_alignment = 4; 429 break; 430 case AMDGPU_HW_IP_UVD_ENC: 431 type = AMD_IP_BLOCK_TYPE_UVD; 432 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 433 if (adev->uvd.harvest_config & (1 << i)) 434 continue; 435 436 for (j = 0; j < adev->uvd.num_enc_rings; j++) 437 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 438 ++num_rings; 439 } 440 ib_start_alignment = 256; 441 ib_size_alignment = 4; 442 break; 443 case AMDGPU_HW_IP_VCN_DEC: 444 type = AMD_IP_BLOCK_TYPE_VCN; 445 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 446 if (adev->vcn.harvest_config & (1 << i)) 447 continue; 448 449 if (adev->vcn.inst[i].ring_dec.sched.ready) 450 ++num_rings; 451 } 452 ib_start_alignment = 256; 453 ib_size_alignment = 64; 454 break; 455 case AMDGPU_HW_IP_VCN_ENC: 456 type = AMD_IP_BLOCK_TYPE_VCN; 457 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 458 if (adev->vcn.harvest_config & (1 << i)) 459 continue; 460 461 for (j = 0; j < adev->vcn.num_enc_rings; j++) 462 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 463 ++num_rings; 464 } 465 ib_start_alignment = 256; 466 ib_size_alignment = 4; 467 break; 468 case AMDGPU_HW_IP_VCN_JPEG: 469 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 470 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 471 472 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 473 if (adev->jpeg.harvest_config & (1 << i)) 474 continue; 475 476 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 477 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) 478 ++num_rings; 479 } 480 ib_start_alignment = 256; 481 ib_size_alignment = 64; 482 break; 483 case AMDGPU_HW_IP_VPE: 484 type = AMD_IP_BLOCK_TYPE_VPE; 485 if (adev->vpe.ring.sched.ready) 486 ++num_rings; 487 ib_start_alignment = 256; 488 ib_size_alignment = 4; 489 break; 490 default: 491 return -EINVAL; 492 } 493 494 for (i = 0; i < adev->num_ip_blocks; i++) 495 if (adev->ip_blocks[i].version->type == type && 496 adev->ip_blocks[i].status.valid) 497 break; 498 499 if (i == adev->num_ip_blocks) 500 return 0; 501 502 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 503 num_rings); 504 505 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 506 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 507 508 if (adev->asic_type >= CHIP_VEGA10) { 509 switch (type) { 510 case AMD_IP_BLOCK_TYPE_GFX: 511 result->ip_discovery_version = 512 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 513 break; 514 case AMD_IP_BLOCK_TYPE_SDMA: 515 result->ip_discovery_version = 516 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 517 break; 518 case AMD_IP_BLOCK_TYPE_UVD: 519 case AMD_IP_BLOCK_TYPE_VCN: 520 case AMD_IP_BLOCK_TYPE_JPEG: 521 result->ip_discovery_version = 522 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 523 break; 524 case AMD_IP_BLOCK_TYPE_VCE: 525 result->ip_discovery_version = 526 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 527 break; 528 case AMD_IP_BLOCK_TYPE_VPE: 529 result->ip_discovery_version = 530 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 531 break; 532 default: 533 result->ip_discovery_version = 0; 534 break; 535 } 536 } else { 537 result->ip_discovery_version = 0; 538 } 539 result->capabilities_flags = 0; 540 result->available_rings = (1 << num_rings) - 1; 541 result->ib_start_alignment = ib_start_alignment; 542 result->ib_size_alignment = ib_size_alignment; 543 return 0; 544 } 545 546 /* 547 * Userspace get information ioctl 548 */ 549 /** 550 * amdgpu_info_ioctl - answer a device specific request. 551 * 552 * @dev: drm device pointer 553 * @data: request object 554 * @filp: drm filp 555 * 556 * This function is used to pass device specific parameters to the userspace 557 * drivers. Examples include: pci device id, pipeline parms, tiling params, 558 * etc. (all asics). 559 * Returns 0 on success, -EINVAL on failure. 560 */ 561 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 562 { 563 struct amdgpu_device *adev = drm_to_adev(dev); 564 struct drm_amdgpu_info *info = data; 565 struct amdgpu_mode_info *minfo = &adev->mode_info; 566 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 567 struct amdgpu_fpriv *fpriv; 568 struct amdgpu_ip_block *ip_block; 569 enum amd_ip_block_type type; 570 struct amdgpu_xcp *xcp; 571 u32 count, inst_mask; 572 uint32_t size = info->return_size; 573 struct drm_crtc *crtc; 574 uint32_t ui32 = 0; 575 uint64_t ui64 = 0; 576 int i, found, ret; 577 int ui32_size = sizeof(ui32); 578 579 if (!info->return_size || !info->return_pointer) 580 return -EINVAL; 581 582 switch (info->query) { 583 case AMDGPU_INFO_ACCEL_WORKING: 584 ui32 = adev->accel_working; 585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 586 case AMDGPU_INFO_CRTC_FROM_ID: 587 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 588 crtc = (struct drm_crtc *)minfo->crtcs[i]; 589 if (crtc && crtc->base.id == info->mode_crtc.id) { 590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 591 592 ui32 = amdgpu_crtc->crtc_id; 593 found = 1; 594 break; 595 } 596 } 597 if (!found) { 598 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 599 return -EINVAL; 600 } 601 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 602 case AMDGPU_INFO_HW_IP_INFO: { 603 struct drm_amdgpu_info_hw_ip ip = {}; 604 605 ret = amdgpu_hw_ip_info(adev, info, &ip); 606 if (ret) 607 return ret; 608 609 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 610 return ret ? -EFAULT : 0; 611 } 612 case AMDGPU_INFO_HW_IP_COUNT: { 613 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 614 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 615 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 616 617 if (!ip_block || !ip_block->status.valid) 618 return -EINVAL; 619 620 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 621 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 622 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 623 switch (type) { 624 case AMD_IP_BLOCK_TYPE_GFX: 625 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 626 if (ret) 627 return ret; 628 count = hweight32(inst_mask); 629 break; 630 case AMD_IP_BLOCK_TYPE_SDMA: 631 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 632 if (ret) 633 return ret; 634 count = hweight32(inst_mask); 635 break; 636 case AMD_IP_BLOCK_TYPE_JPEG: 637 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 638 if (ret) 639 return ret; 640 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 641 break; 642 case AMD_IP_BLOCK_TYPE_VCN: 643 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 644 if (ret) 645 return ret; 646 count = hweight32(inst_mask); 647 break; 648 default: 649 return -EINVAL; 650 } 651 652 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 653 } 654 655 switch (type) { 656 case AMD_IP_BLOCK_TYPE_GFX: 657 case AMD_IP_BLOCK_TYPE_VCE: 658 count = 1; 659 break; 660 case AMD_IP_BLOCK_TYPE_SDMA: 661 count = adev->sdma.num_instances; 662 break; 663 case AMD_IP_BLOCK_TYPE_JPEG: 664 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 665 break; 666 case AMD_IP_BLOCK_TYPE_VCN: 667 count = adev->vcn.num_vcn_inst; 668 break; 669 case AMD_IP_BLOCK_TYPE_UVD: 670 count = adev->uvd.num_uvd_inst; 671 break; 672 /* For all other IP block types not listed in the switch statement 673 * the ip status is valid here and the instance count is one. 674 */ 675 default: 676 count = 1; 677 break; 678 } 679 680 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 681 } 682 case AMDGPU_INFO_TIMESTAMP: 683 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 684 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 685 case AMDGPU_INFO_FW_VERSION: { 686 struct drm_amdgpu_info_firmware fw_info; 687 688 /* We only support one instance of each IP block right now. */ 689 if (info->query_fw.ip_instance != 0) 690 return -EINVAL; 691 692 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 693 if (ret) 694 return ret; 695 696 return copy_to_user(out, &fw_info, 697 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 698 } 699 case AMDGPU_INFO_NUM_BYTES_MOVED: 700 ui64 = atomic64_read(&adev->num_bytes_moved); 701 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 702 case AMDGPU_INFO_NUM_EVICTIONS: 703 ui64 = atomic64_read(&adev->num_evictions); 704 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 705 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 706 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 707 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 708 case AMDGPU_INFO_VRAM_USAGE: 709 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 710 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 711 case AMDGPU_INFO_VIS_VRAM_USAGE: 712 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 713 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 714 case AMDGPU_INFO_GTT_USAGE: 715 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 716 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 717 case AMDGPU_INFO_GDS_CONFIG: { 718 struct drm_amdgpu_info_gds gds_info; 719 720 memset(&gds_info, 0, sizeof(gds_info)); 721 gds_info.compute_partition_size = adev->gds.gds_size; 722 gds_info.gds_total_size = adev->gds.gds_size; 723 gds_info.gws_per_compute_partition = adev->gds.gws_size; 724 gds_info.oa_per_compute_partition = adev->gds.oa_size; 725 return copy_to_user(out, &gds_info, 726 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 727 } 728 case AMDGPU_INFO_VRAM_GTT: { 729 struct drm_amdgpu_info_vram_gtt vram_gtt; 730 731 vram_gtt.vram_size = adev->gmc.real_vram_size - 732 atomic64_read(&adev->vram_pin_size) - 733 AMDGPU_VM_RESERVED_VRAM; 734 vram_gtt.vram_cpu_accessible_size = 735 min(adev->gmc.visible_vram_size - 736 atomic64_read(&adev->visible_pin_size), 737 vram_gtt.vram_size); 738 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 739 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 740 return copy_to_user(out, &vram_gtt, 741 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 742 } 743 case AMDGPU_INFO_MEMORY: { 744 struct drm_amdgpu_memory_info mem; 745 struct ttm_resource_manager *gtt_man = 746 &adev->mman.gtt_mgr.manager; 747 struct ttm_resource_manager *vram_man = 748 &adev->mman.vram_mgr.manager; 749 750 memset(&mem, 0, sizeof(mem)); 751 mem.vram.total_heap_size = adev->gmc.real_vram_size; 752 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 753 atomic64_read(&adev->vram_pin_size) - 754 AMDGPU_VM_RESERVED_VRAM; 755 mem.vram.heap_usage = 756 ttm_resource_manager_usage(vram_man); 757 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 758 759 mem.cpu_accessible_vram.total_heap_size = 760 adev->gmc.visible_vram_size; 761 mem.cpu_accessible_vram.usable_heap_size = 762 min(adev->gmc.visible_vram_size - 763 atomic64_read(&adev->visible_pin_size), 764 mem.vram.usable_heap_size); 765 mem.cpu_accessible_vram.heap_usage = 766 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 767 mem.cpu_accessible_vram.max_allocation = 768 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 769 770 mem.gtt.total_heap_size = gtt_man->size; 771 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 772 atomic64_read(&adev->gart_pin_size); 773 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 774 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 775 776 return copy_to_user(out, &mem, 777 min((size_t)size, sizeof(mem))) 778 ? -EFAULT : 0; 779 } 780 case AMDGPU_INFO_READ_MMR_REG: { 781 unsigned int n, alloc_size; 782 uint32_t *regs; 783 unsigned int se_num = (info->read_mmr_reg.instance >> 784 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 785 AMDGPU_INFO_MMR_SE_INDEX_MASK; 786 unsigned int sh_num = (info->read_mmr_reg.instance >> 787 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 788 AMDGPU_INFO_MMR_SH_INDEX_MASK; 789 790 /* set full masks if the userspace set all bits 791 * in the bitfields 792 */ 793 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 794 se_num = 0xffffffff; 795 else if (se_num >= AMDGPU_GFX_MAX_SE) 796 return -EINVAL; 797 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 798 sh_num = 0xffffffff; 799 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 800 return -EINVAL; 801 802 if (info->read_mmr_reg.count > 128) 803 return -EINVAL; 804 805 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 806 if (!regs) 807 return -ENOMEM; 808 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 809 810 amdgpu_gfx_off_ctrl(adev, false); 811 for (i = 0; i < info->read_mmr_reg.count; i++) { 812 if (amdgpu_asic_read_register(adev, se_num, sh_num, 813 info->read_mmr_reg.dword_offset + i, 814 ®s[i])) { 815 DRM_DEBUG_KMS("unallowed offset %#x\n", 816 info->read_mmr_reg.dword_offset + i); 817 kfree(regs); 818 amdgpu_gfx_off_ctrl(adev, true); 819 return -EFAULT; 820 } 821 } 822 amdgpu_gfx_off_ctrl(adev, true); 823 n = copy_to_user(out, regs, min(size, alloc_size)); 824 kfree(regs); 825 return n ? -EFAULT : 0; 826 } 827 case AMDGPU_INFO_DEV_INFO: { 828 struct drm_amdgpu_info_device *dev_info; 829 uint64_t vm_size; 830 uint32_t pcie_gen_mask; 831 832 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 833 if (!dev_info) 834 return -ENOMEM; 835 836 dev_info->device_id = adev->pdev->device; 837 dev_info->chip_rev = adev->rev_id; 838 dev_info->external_rev = adev->external_rev_id; 839 dev_info->pci_rev = adev->pdev->revision; 840 dev_info->family = adev->family; 841 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 842 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 843 /* return all clocks in KHz */ 844 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 845 if (adev->pm.dpm_enabled) { 846 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 847 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 848 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 849 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 850 } else { 851 dev_info->max_engine_clock = 852 dev_info->min_engine_clock = 853 adev->clock.default_sclk * 10; 854 dev_info->max_memory_clock = 855 dev_info->min_memory_clock = 856 adev->clock.default_mclk * 10; 857 } 858 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 859 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 860 adev->gfx.config.max_shader_engines; 861 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 862 dev_info->ids_flags = 0; 863 if (adev->flags & AMD_IS_APU) 864 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 865 if (adev->gfx.mcbp) 866 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 867 if (amdgpu_is_tmz(adev)) 868 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 869 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 870 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 871 872 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 873 vm_size -= AMDGPU_VA_RESERVED_TOP; 874 875 /* Older VCE FW versions are buggy and can handle only 40bits */ 876 if (adev->vce.fw_version && 877 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 878 vm_size = min(vm_size, 1ULL << 40); 879 880 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 881 dev_info->virtual_address_max = 882 min(vm_size, AMDGPU_GMC_HOLE_START); 883 884 if (vm_size > AMDGPU_GMC_HOLE_START) { 885 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 886 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 887 } 888 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 889 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 890 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 891 dev_info->cu_active_number = adev->gfx.cu_info.number; 892 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 893 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 894 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 895 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 896 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 897 sizeof(dev_info->cu_bitmap)); 898 dev_info->vram_type = adev->gmc.vram_type; 899 dev_info->vram_bit_width = adev->gmc.vram_width; 900 dev_info->vce_harvest_config = adev->vce.harvest_config; 901 dev_info->gc_double_offchip_lds_buf = 902 adev->gfx.config.double_offchip_lds_buf; 903 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 904 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 905 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 906 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 907 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 908 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 909 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 910 911 if (adev->family >= AMDGPU_FAMILY_NV) 912 dev_info->pa_sc_tile_steering_override = 913 adev->gfx.config.pa_sc_tile_steering_override; 914 915 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 916 917 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 918 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); 919 dev_info->pcie_gen = fls(pcie_gen_mask); 920 dev_info->pcie_num_lanes = 921 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 922 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 923 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 924 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 925 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 926 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 927 928 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 929 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 930 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 931 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 932 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 933 adev->gfx.config.gc_gl1c_per_sa; 934 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 935 dev_info->mall_size = adev->gmc.mall_size; 936 937 938 if (adev->gfx.funcs->get_gfx_shadow_info) { 939 struct amdgpu_gfx_shadow_info shadow_info; 940 941 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 942 if (!ret) { 943 dev_info->shadow_size = shadow_info.shadow_size; 944 dev_info->shadow_alignment = shadow_info.shadow_alignment; 945 dev_info->csa_size = shadow_info.csa_size; 946 dev_info->csa_alignment = shadow_info.csa_alignment; 947 } 948 } 949 950 ret = copy_to_user(out, dev_info, 951 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 952 kfree(dev_info); 953 return ret; 954 } 955 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 956 unsigned int i; 957 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 958 struct amd_vce_state *vce_state; 959 960 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 961 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 962 if (vce_state) { 963 vce_clk_table.entries[i].sclk = vce_state->sclk; 964 vce_clk_table.entries[i].mclk = vce_state->mclk; 965 vce_clk_table.entries[i].eclk = vce_state->evclk; 966 vce_clk_table.num_valid_entries++; 967 } 968 } 969 970 return copy_to_user(out, &vce_clk_table, 971 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 972 } 973 case AMDGPU_INFO_VBIOS: { 974 uint32_t bios_size = adev->bios_size; 975 976 switch (info->vbios_info.type) { 977 case AMDGPU_INFO_VBIOS_SIZE: 978 return copy_to_user(out, &bios_size, 979 min((size_t)size, sizeof(bios_size))) 980 ? -EFAULT : 0; 981 case AMDGPU_INFO_VBIOS_IMAGE: { 982 uint8_t *bios; 983 uint32_t bios_offset = info->vbios_info.offset; 984 985 if (bios_offset >= bios_size) 986 return -EINVAL; 987 988 bios = adev->bios + bios_offset; 989 return copy_to_user(out, bios, 990 min((size_t)size, (size_t)(bios_size - bios_offset))) 991 ? -EFAULT : 0; 992 } 993 case AMDGPU_INFO_VBIOS_INFO: { 994 struct drm_amdgpu_info_vbios vbios_info = {}; 995 struct atom_context *atom_context; 996 997 atom_context = adev->mode_info.atom_context; 998 if (atom_context) { 999 memcpy(vbios_info.name, atom_context->name, 1000 sizeof(atom_context->name)); 1001 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1002 sizeof(atom_context->vbios_pn)); 1003 vbios_info.version = atom_context->version; 1004 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1005 sizeof(atom_context->vbios_ver_str)); 1006 memcpy(vbios_info.date, atom_context->date, 1007 sizeof(atom_context->date)); 1008 } 1009 1010 return copy_to_user(out, &vbios_info, 1011 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1012 } 1013 default: 1014 DRM_DEBUG_KMS("Invalid request %d\n", 1015 info->vbios_info.type); 1016 return -EINVAL; 1017 } 1018 } 1019 case AMDGPU_INFO_NUM_HANDLES: { 1020 struct drm_amdgpu_info_num_handles handle; 1021 1022 switch (info->query_hw_ip.type) { 1023 case AMDGPU_HW_IP_UVD: 1024 /* Starting Polaris, we support unlimited UVD handles */ 1025 if (adev->asic_type < CHIP_POLARIS10) { 1026 handle.uvd_max_handles = adev->uvd.max_handles; 1027 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1028 1029 return copy_to_user(out, &handle, 1030 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1031 } else { 1032 return -ENODATA; 1033 } 1034 1035 break; 1036 default: 1037 return -EINVAL; 1038 } 1039 } 1040 case AMDGPU_INFO_SENSOR: { 1041 if (!adev->pm.dpm_enabled) 1042 return -ENOENT; 1043 1044 switch (info->sensor_info.type) { 1045 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1046 /* get sclk in Mhz */ 1047 if (amdgpu_dpm_read_sensor(adev, 1048 AMDGPU_PP_SENSOR_GFX_SCLK, 1049 (void *)&ui32, &ui32_size)) { 1050 return -EINVAL; 1051 } 1052 ui32 /= 100; 1053 break; 1054 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1055 /* get mclk in Mhz */ 1056 if (amdgpu_dpm_read_sensor(adev, 1057 AMDGPU_PP_SENSOR_GFX_MCLK, 1058 (void *)&ui32, &ui32_size)) { 1059 return -EINVAL; 1060 } 1061 ui32 /= 100; 1062 break; 1063 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1064 /* get temperature in millidegrees C */ 1065 if (amdgpu_dpm_read_sensor(adev, 1066 AMDGPU_PP_SENSOR_GPU_TEMP, 1067 (void *)&ui32, &ui32_size)) { 1068 return -EINVAL; 1069 } 1070 break; 1071 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1072 /* get GPU load */ 1073 if (amdgpu_dpm_read_sensor(adev, 1074 AMDGPU_PP_SENSOR_GPU_LOAD, 1075 (void *)&ui32, &ui32_size)) { 1076 return -EINVAL; 1077 } 1078 break; 1079 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1080 /* get average GPU power */ 1081 if (amdgpu_dpm_read_sensor(adev, 1082 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1083 (void *)&ui32, &ui32_size)) { 1084 /* fall back to input power for backwards compat */ 1085 if (amdgpu_dpm_read_sensor(adev, 1086 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1087 (void *)&ui32, &ui32_size)) { 1088 return -EINVAL; 1089 } 1090 } 1091 ui32 >>= 8; 1092 break; 1093 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1094 /* get input GPU power */ 1095 if (amdgpu_dpm_read_sensor(adev, 1096 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1097 (void *)&ui32, &ui32_size)) { 1098 return -EINVAL; 1099 } 1100 ui32 >>= 8; 1101 break; 1102 case AMDGPU_INFO_SENSOR_VDDNB: 1103 /* get VDDNB in millivolts */ 1104 if (amdgpu_dpm_read_sensor(adev, 1105 AMDGPU_PP_SENSOR_VDDNB, 1106 (void *)&ui32, &ui32_size)) { 1107 return -EINVAL; 1108 } 1109 break; 1110 case AMDGPU_INFO_SENSOR_VDDGFX: 1111 /* get VDDGFX in millivolts */ 1112 if (amdgpu_dpm_read_sensor(adev, 1113 AMDGPU_PP_SENSOR_VDDGFX, 1114 (void *)&ui32, &ui32_size)) { 1115 return -EINVAL; 1116 } 1117 break; 1118 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1119 /* get stable pstate sclk in Mhz */ 1120 if (amdgpu_dpm_read_sensor(adev, 1121 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1122 (void *)&ui32, &ui32_size)) { 1123 return -EINVAL; 1124 } 1125 ui32 /= 100; 1126 break; 1127 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1128 /* get stable pstate mclk in Mhz */ 1129 if (amdgpu_dpm_read_sensor(adev, 1130 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1131 (void *)&ui32, &ui32_size)) { 1132 return -EINVAL; 1133 } 1134 ui32 /= 100; 1135 break; 1136 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1137 /* get peak pstate sclk in Mhz */ 1138 if (amdgpu_dpm_read_sensor(adev, 1139 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1140 (void *)&ui32, &ui32_size)) { 1141 return -EINVAL; 1142 } 1143 ui32 /= 100; 1144 break; 1145 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1146 /* get peak pstate mclk in Mhz */ 1147 if (amdgpu_dpm_read_sensor(adev, 1148 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1149 (void *)&ui32, &ui32_size)) { 1150 return -EINVAL; 1151 } 1152 ui32 /= 100; 1153 break; 1154 default: 1155 DRM_DEBUG_KMS("Invalid request %d\n", 1156 info->sensor_info.type); 1157 return -EINVAL; 1158 } 1159 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1160 } 1161 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1162 ui32 = atomic_read(&adev->vram_lost_counter); 1163 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1164 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1165 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1166 uint64_t ras_mask; 1167 1168 if (!ras) 1169 return -EINVAL; 1170 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1171 1172 return copy_to_user(out, &ras_mask, 1173 min_t(u64, size, sizeof(ras_mask))) ? 1174 -EFAULT : 0; 1175 } 1176 case AMDGPU_INFO_VIDEO_CAPS: { 1177 const struct amdgpu_video_codecs *codecs; 1178 struct drm_amdgpu_info_video_caps *caps; 1179 int r; 1180 1181 if (!adev->asic_funcs->query_video_codecs) 1182 return -EINVAL; 1183 1184 switch (info->video_cap.type) { 1185 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1186 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1187 if (r) 1188 return -EINVAL; 1189 break; 1190 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1191 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1192 if (r) 1193 return -EINVAL; 1194 break; 1195 default: 1196 DRM_DEBUG_KMS("Invalid request %d\n", 1197 info->video_cap.type); 1198 return -EINVAL; 1199 } 1200 1201 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1202 if (!caps) 1203 return -ENOMEM; 1204 1205 for (i = 0; i < codecs->codec_count; i++) { 1206 int idx = codecs->codec_array[i].codec_type; 1207 1208 switch (idx) { 1209 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1210 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1211 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1212 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1213 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1214 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1215 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1216 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1217 caps->codec_info[idx].valid = 1; 1218 caps->codec_info[idx].max_width = 1219 codecs->codec_array[i].max_width; 1220 caps->codec_info[idx].max_height = 1221 codecs->codec_array[i].max_height; 1222 caps->codec_info[idx].max_pixels_per_frame = 1223 codecs->codec_array[i].max_pixels_per_frame; 1224 caps->codec_info[idx].max_level = 1225 codecs->codec_array[i].max_level; 1226 break; 1227 default: 1228 break; 1229 } 1230 } 1231 r = copy_to_user(out, caps, 1232 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1233 kfree(caps); 1234 return r; 1235 } 1236 case AMDGPU_INFO_MAX_IBS: { 1237 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1238 1239 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1240 max_ibs[i] = amdgpu_ring_max_ibs(i); 1241 1242 return copy_to_user(out, max_ibs, 1243 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1244 } 1245 case AMDGPU_INFO_GPUVM_FAULT: { 1246 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1247 struct amdgpu_vm *vm = &fpriv->vm; 1248 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1249 unsigned long flags; 1250 1251 if (!vm) 1252 return -EINVAL; 1253 1254 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1255 1256 xa_lock_irqsave(&adev->vm_manager.pasids, flags); 1257 gpuvm_fault.addr = vm->fault_info.addr; 1258 gpuvm_fault.status = vm->fault_info.status; 1259 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1260 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); 1261 1262 return copy_to_user(out, &gpuvm_fault, 1263 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1264 } 1265 default: 1266 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1267 return -EINVAL; 1268 } 1269 return 0; 1270 } 1271 1272 1273 /* 1274 * Outdated mess for old drm with Xorg being in charge (void function now). 1275 */ 1276 /** 1277 * amdgpu_driver_lastclose_kms - drm callback for last close 1278 * 1279 * @dev: drm dev pointer 1280 * 1281 * Switch vga_switcheroo state after last close (all asics). 1282 */ 1283 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1284 { 1285 drm_fb_helper_lastclose(dev); 1286 vga_switcheroo_process_delayed_switch(); 1287 } 1288 1289 /** 1290 * amdgpu_driver_open_kms - drm callback for open 1291 * 1292 * @dev: drm dev pointer 1293 * @file_priv: drm file 1294 * 1295 * On device open, init vm on cayman+ (all asics). 1296 * Returns 0 on success, error on failure. 1297 */ 1298 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1299 { 1300 struct amdgpu_device *adev = drm_to_adev(dev); 1301 struct amdgpu_fpriv *fpriv; 1302 int r, pasid; 1303 1304 /* Ensure IB tests are run on ring */ 1305 flush_delayed_work(&adev->delayed_init_work); 1306 1307 1308 if (amdgpu_ras_intr_triggered()) { 1309 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1310 return -EHWPOISON; 1311 } 1312 1313 file_priv->driver_priv = NULL; 1314 1315 r = pm_runtime_get_sync(dev->dev); 1316 if (r < 0) 1317 goto pm_put; 1318 1319 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1320 if (unlikely(!fpriv)) { 1321 r = -ENOMEM; 1322 goto out_suspend; 1323 } 1324 1325 pasid = amdgpu_pasid_alloc(16); 1326 if (pasid < 0) { 1327 dev_warn(adev->dev, "No more PASIDs available!"); 1328 pasid = 0; 1329 } 1330 1331 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1332 if (r) 1333 goto error_pasid; 1334 1335 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); 1336 if (r) 1337 goto error_pasid; 1338 1339 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1340 if (r) 1341 goto error_vm; 1342 1343 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1344 if (!fpriv->prt_va) { 1345 r = -ENOMEM; 1346 goto error_vm; 1347 } 1348 1349 if (adev->gfx.mcbp) { 1350 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1351 1352 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1353 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1354 if (r) 1355 goto error_vm; 1356 } 1357 1358 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1359 if (r) 1360 goto error_vm; 1361 1362 mutex_init(&fpriv->bo_list_lock); 1363 idr_init_base(&fpriv->bo_list_handles, 1); 1364 1365 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1366 1367 file_priv->driver_priv = fpriv; 1368 goto out_suspend; 1369 1370 error_vm: 1371 amdgpu_vm_fini(adev, &fpriv->vm); 1372 1373 error_pasid: 1374 if (pasid) { 1375 amdgpu_pasid_free(pasid); 1376 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1377 } 1378 1379 kfree(fpriv); 1380 1381 out_suspend: 1382 pm_runtime_mark_last_busy(dev->dev); 1383 pm_put: 1384 pm_runtime_put_autosuspend(dev->dev); 1385 1386 return r; 1387 } 1388 1389 /** 1390 * amdgpu_driver_postclose_kms - drm callback for post close 1391 * 1392 * @dev: drm dev pointer 1393 * @file_priv: drm file 1394 * 1395 * On device post close, tear down vm on cayman+ (all asics). 1396 */ 1397 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1398 struct drm_file *file_priv) 1399 { 1400 struct amdgpu_device *adev = drm_to_adev(dev); 1401 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1402 struct amdgpu_bo_list *list; 1403 struct amdgpu_bo *pd; 1404 u32 pasid; 1405 int handle; 1406 1407 if (!fpriv) 1408 return; 1409 1410 pm_runtime_get_sync(dev->dev); 1411 1412 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1413 amdgpu_uvd_free_handles(adev, file_priv); 1414 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1415 amdgpu_vce_free_handles(adev, file_priv); 1416 1417 if (fpriv->csa_va) { 1418 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1419 1420 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1421 fpriv->csa_va, csa_addr)); 1422 fpriv->csa_va = NULL; 1423 } 1424 1425 amdgpu_seq64_unmap(adev, fpriv); 1426 1427 pasid = fpriv->vm.pasid; 1428 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1429 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1430 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1431 amdgpu_bo_unreserve(pd); 1432 } 1433 1434 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1435 amdgpu_vm_fini(adev, &fpriv->vm); 1436 1437 if (pasid) 1438 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1439 amdgpu_bo_unref(&pd); 1440 1441 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1442 amdgpu_bo_list_put(list); 1443 1444 idr_destroy(&fpriv->bo_list_handles); 1445 mutex_destroy(&fpriv->bo_list_lock); 1446 1447 kfree(fpriv); 1448 file_priv->driver_priv = NULL; 1449 1450 pm_runtime_mark_last_busy(dev->dev); 1451 pm_runtime_put_autosuspend(dev->dev); 1452 } 1453 1454 1455 void amdgpu_driver_release_kms(struct drm_device *dev) 1456 { 1457 struct amdgpu_device *adev = drm_to_adev(dev); 1458 1459 amdgpu_device_fini_sw(adev); 1460 pci_set_drvdata(adev->pdev, NULL); 1461 } 1462 1463 /* 1464 * VBlank related functions. 1465 */ 1466 /** 1467 * amdgpu_get_vblank_counter_kms - get frame count 1468 * 1469 * @crtc: crtc to get the frame count from 1470 * 1471 * Gets the frame count on the requested crtc (all asics). 1472 * Returns frame count on success, -EINVAL on failure. 1473 */ 1474 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1475 { 1476 struct drm_device *dev = crtc->dev; 1477 unsigned int pipe = crtc->index; 1478 struct amdgpu_device *adev = drm_to_adev(dev); 1479 int vpos, hpos, stat; 1480 u32 count; 1481 1482 if (pipe >= adev->mode_info.num_crtc) { 1483 DRM_ERROR("Invalid crtc %u\n", pipe); 1484 return -EINVAL; 1485 } 1486 1487 /* The hw increments its frame counter at start of vsync, not at start 1488 * of vblank, as is required by DRM core vblank counter handling. 1489 * Cook the hw count here to make it appear to the caller as if it 1490 * incremented at start of vblank. We measure distance to start of 1491 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1492 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1493 * result by 1 to give the proper appearance to caller. 1494 */ 1495 if (adev->mode_info.crtcs[pipe]) { 1496 /* Repeat readout if needed to provide stable result if 1497 * we cross start of vsync during the queries. 1498 */ 1499 do { 1500 count = amdgpu_display_vblank_get_counter(adev, pipe); 1501 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1502 * vpos as distance to start of vblank, instead of 1503 * regular vertical scanout pos. 1504 */ 1505 stat = amdgpu_display_get_crtc_scanoutpos( 1506 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1507 &vpos, &hpos, NULL, NULL, 1508 &adev->mode_info.crtcs[pipe]->base.hwmode); 1509 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1510 1511 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1512 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1513 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1514 } else { 1515 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1516 pipe, vpos); 1517 1518 /* Bump counter if we are at >= leading edge of vblank, 1519 * but before vsync where vpos would turn negative and 1520 * the hw counter really increments. 1521 */ 1522 if (vpos >= 0) 1523 count++; 1524 } 1525 } else { 1526 /* Fallback to use value as is. */ 1527 count = amdgpu_display_vblank_get_counter(adev, pipe); 1528 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1529 } 1530 1531 return count; 1532 } 1533 1534 /** 1535 * amdgpu_enable_vblank_kms - enable vblank interrupt 1536 * 1537 * @crtc: crtc to enable vblank interrupt for 1538 * 1539 * Enable the interrupt on the requested crtc (all asics). 1540 * Returns 0 on success, -EINVAL on failure. 1541 */ 1542 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1543 { 1544 struct drm_device *dev = crtc->dev; 1545 unsigned int pipe = crtc->index; 1546 struct amdgpu_device *adev = drm_to_adev(dev); 1547 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1548 1549 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1550 } 1551 1552 /** 1553 * amdgpu_disable_vblank_kms - disable vblank interrupt 1554 * 1555 * @crtc: crtc to disable vblank interrupt for 1556 * 1557 * Disable the interrupt on the requested crtc (all asics). 1558 */ 1559 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1560 { 1561 struct drm_device *dev = crtc->dev; 1562 unsigned int pipe = crtc->index; 1563 struct amdgpu_device *adev = drm_to_adev(dev); 1564 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1565 1566 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1567 } 1568 1569 /* 1570 * Debugfs info 1571 */ 1572 #if defined(CONFIG_DEBUG_FS) 1573 1574 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1575 { 1576 struct amdgpu_device *adev = m->private; 1577 struct drm_amdgpu_info_firmware fw_info; 1578 struct drm_amdgpu_query_fw query_fw; 1579 struct atom_context *ctx = adev->mode_info.atom_context; 1580 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1581 int ret, i; 1582 1583 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1584 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1585 TA_FW_NAME(XGMI), 1586 TA_FW_NAME(RAS), 1587 TA_FW_NAME(HDCP), 1588 TA_FW_NAME(DTM), 1589 TA_FW_NAME(RAP), 1590 TA_FW_NAME(SECUREDISPLAY), 1591 #undef TA_FW_NAME 1592 }; 1593 1594 /* VCE */ 1595 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1596 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1597 if (ret) 1598 return ret; 1599 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1600 fw_info.feature, fw_info.ver); 1601 1602 /* UVD */ 1603 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1604 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1605 if (ret) 1606 return ret; 1607 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1608 fw_info.feature, fw_info.ver); 1609 1610 /* GMC */ 1611 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1612 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1613 if (ret) 1614 return ret; 1615 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1616 fw_info.feature, fw_info.ver); 1617 1618 /* ME */ 1619 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1620 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1621 if (ret) 1622 return ret; 1623 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1624 fw_info.feature, fw_info.ver); 1625 1626 /* PFP */ 1627 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1628 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1629 if (ret) 1630 return ret; 1631 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1632 fw_info.feature, fw_info.ver); 1633 1634 /* CE */ 1635 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1636 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1637 if (ret) 1638 return ret; 1639 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1640 fw_info.feature, fw_info.ver); 1641 1642 /* RLC */ 1643 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1644 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1645 if (ret) 1646 return ret; 1647 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1648 fw_info.feature, fw_info.ver); 1649 1650 /* RLC SAVE RESTORE LIST CNTL */ 1651 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1652 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1653 if (ret) 1654 return ret; 1655 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1656 fw_info.feature, fw_info.ver); 1657 1658 /* RLC SAVE RESTORE LIST GPM MEM */ 1659 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1660 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1661 if (ret) 1662 return ret; 1663 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1664 fw_info.feature, fw_info.ver); 1665 1666 /* RLC SAVE RESTORE LIST SRM MEM */ 1667 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1668 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1669 if (ret) 1670 return ret; 1671 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1672 fw_info.feature, fw_info.ver); 1673 1674 /* RLCP */ 1675 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1676 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1677 if (ret) 1678 return ret; 1679 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1680 fw_info.feature, fw_info.ver); 1681 1682 /* RLCV */ 1683 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1684 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1685 if (ret) 1686 return ret; 1687 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1688 fw_info.feature, fw_info.ver); 1689 1690 /* MEC */ 1691 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1692 query_fw.index = 0; 1693 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1694 if (ret) 1695 return ret; 1696 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1697 fw_info.feature, fw_info.ver); 1698 1699 /* MEC2 */ 1700 if (adev->gfx.mec2_fw) { 1701 query_fw.index = 1; 1702 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1703 if (ret) 1704 return ret; 1705 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1706 fw_info.feature, fw_info.ver); 1707 } 1708 1709 /* IMU */ 1710 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1711 query_fw.index = 0; 1712 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1713 if (ret) 1714 return ret; 1715 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1716 fw_info.feature, fw_info.ver); 1717 1718 /* PSP SOS */ 1719 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1720 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1721 if (ret) 1722 return ret; 1723 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1724 fw_info.feature, fw_info.ver); 1725 1726 1727 /* PSP ASD */ 1728 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1729 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1730 if (ret) 1731 return ret; 1732 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1733 fw_info.feature, fw_info.ver); 1734 1735 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1736 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1737 query_fw.index = i; 1738 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1739 if (ret) 1740 continue; 1741 1742 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1743 ta_fw_name[i], fw_info.feature, fw_info.ver); 1744 } 1745 1746 /* SMC */ 1747 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1748 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1749 if (ret) 1750 return ret; 1751 smu_program = (fw_info.ver >> 24) & 0xff; 1752 smu_major = (fw_info.ver >> 16) & 0xff; 1753 smu_minor = (fw_info.ver >> 8) & 0xff; 1754 smu_debug = (fw_info.ver >> 0) & 0xff; 1755 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1756 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1757 1758 /* SDMA */ 1759 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1760 for (i = 0; i < adev->sdma.num_instances; i++) { 1761 query_fw.index = i; 1762 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1763 if (ret) 1764 return ret; 1765 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1766 i, fw_info.feature, fw_info.ver); 1767 } 1768 1769 /* VCN */ 1770 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1771 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1772 if (ret) 1773 return ret; 1774 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1775 fw_info.feature, fw_info.ver); 1776 1777 /* DMCU */ 1778 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1779 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1780 if (ret) 1781 return ret; 1782 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1783 fw_info.feature, fw_info.ver); 1784 1785 /* DMCUB */ 1786 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1787 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1788 if (ret) 1789 return ret; 1790 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1791 fw_info.feature, fw_info.ver); 1792 1793 /* TOC */ 1794 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1795 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1796 if (ret) 1797 return ret; 1798 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1799 fw_info.feature, fw_info.ver); 1800 1801 /* CAP */ 1802 if (adev->psp.cap_fw) { 1803 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1804 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1805 if (ret) 1806 return ret; 1807 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1808 fw_info.feature, fw_info.ver); 1809 } 1810 1811 /* MES_KIQ */ 1812 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1813 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1814 if (ret) 1815 return ret; 1816 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1817 fw_info.feature, fw_info.ver); 1818 1819 /* MES */ 1820 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1821 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1822 if (ret) 1823 return ret; 1824 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1825 fw_info.feature, fw_info.ver); 1826 1827 /* VPE */ 1828 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1829 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1830 if (ret) 1831 return ret; 1832 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1833 fw_info.feature, fw_info.ver); 1834 1835 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1836 1837 return 0; 1838 } 1839 1840 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1841 1842 #endif 1843 1844 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1845 { 1846 #if defined(CONFIG_DEBUG_FS) 1847 struct drm_minor *minor = adev_to_drm(adev)->primary; 1848 struct dentry *root = minor->debugfs_root; 1849 1850 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1851 adev, &amdgpu_debugfs_firmware_info_fops); 1852 1853 #endif 1854 } 1855