1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 /** 71 * amdgpu_driver_unload_kms - Main unload function for KMS. 72 * 73 * @dev: drm dev pointer 74 * 75 * This is the main unload function for KMS (all asics). 76 * Returns 0 on success. 77 */ 78 void amdgpu_driver_unload_kms(struct drm_device *dev) 79 { 80 struct amdgpu_device *adev = drm_to_adev(dev); 81 82 if (adev == NULL) 83 return; 84 85 amdgpu_unregister_gpu_instance(adev); 86 87 if (adev->rmmio == NULL) 88 return; 89 90 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 91 DRM_WARN("smart shift update failed\n"); 92 93 amdgpu_acpi_fini(adev); 94 amdgpu_device_fini_hw(adev); 95 } 96 97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 98 { 99 struct amdgpu_gpu_instance *gpu_instance; 100 101 mutex_lock(&mgpu_info.mutex); 102 103 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 104 DRM_ERROR("Cannot register more gpu instance\n"); 105 mutex_unlock(&mgpu_info.mutex); 106 return; 107 } 108 109 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 110 gpu_instance->adev = adev; 111 gpu_instance->mgpu_fan_enabled = 0; 112 113 mgpu_info.num_gpu++; 114 if (adev->flags & AMD_IS_APU) 115 mgpu_info.num_apu++; 116 else 117 mgpu_info.num_dgpu++; 118 119 mutex_unlock(&mgpu_info.mutex); 120 } 121 122 /** 123 * amdgpu_driver_load_kms - Main load function for KMS. 124 * 125 * @adev: pointer to struct amdgpu_device 126 * @flags: device flags 127 * 128 * This is the main load function for KMS (all asics). 129 * Returns 0 on success, error on failure. 130 */ 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 132 { 133 struct drm_device *dev; 134 int r, acpi_status; 135 136 dev = adev_to_drm(adev); 137 138 /* amdgpu_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = amdgpu_device_init(adev, flags); 145 if (r) { 146 dev_err(dev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 151 if (amdgpu_device_supports_px(dev) && 152 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 153 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 154 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 155 } else if (amdgpu_device_supports_boco(dev) && 156 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 157 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 158 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 159 } else if (amdgpu_device_supports_baco(dev) && 160 (amdgpu_runtime_pm != 0)) { 161 switch (adev->asic_type) { 162 case CHIP_VEGA20: 163 case CHIP_ARCTURUS: 164 /* enable BACO as runpm mode if runpm=1 */ 165 if (amdgpu_runtime_pm > 0) 166 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 167 break; 168 case CHIP_VEGA10: 169 /* enable BACO as runpm mode if noretry=0 */ 170 if (!adev->gmc.noretry) 171 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 172 break; 173 default: 174 /* enable BACO as runpm mode on CI+ */ 175 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 176 break; 177 } 178 179 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 180 dev_info(adev->dev, "Using BACO for runtime pm\n"); 181 } 182 183 /* Call ACPI methods: require modeset init 184 * but failure is not fatal 185 */ 186 187 acpi_status = amdgpu_acpi_init(adev); 188 if (acpi_status) 189 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 190 191 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 192 DRM_WARN("smart shift update failed\n"); 193 194 out: 195 if (r) 196 amdgpu_driver_unload_kms(dev); 197 198 return r; 199 } 200 201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 202 struct drm_amdgpu_query_fw *query_fw, 203 struct amdgpu_device *adev) 204 { 205 switch (query_fw->fw_type) { 206 case AMDGPU_INFO_FW_VCE: 207 fw_info->ver = adev->vce.fw_version; 208 fw_info->feature = adev->vce.fb_version; 209 break; 210 case AMDGPU_INFO_FW_UVD: 211 fw_info->ver = adev->uvd.fw_version; 212 fw_info->feature = 0; 213 break; 214 case AMDGPU_INFO_FW_VCN: 215 fw_info->ver = adev->vcn.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_GMC: 219 fw_info->ver = adev->gmc.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GFX_ME: 223 fw_info->ver = adev->gfx.me_fw_version; 224 fw_info->feature = adev->gfx.me_feature_version; 225 break; 226 case AMDGPU_INFO_FW_GFX_PFP: 227 fw_info->ver = adev->gfx.pfp_fw_version; 228 fw_info->feature = adev->gfx.pfp_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_CE: 231 fw_info->ver = adev->gfx.ce_fw_version; 232 fw_info->feature = adev->gfx.ce_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_RLC: 235 fw_info->ver = adev->gfx.rlc_fw_version; 236 fw_info->feature = adev->gfx.rlc_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 239 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 243 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 247 fw_info->ver = adev->gfx.rlc_srls_fw_version; 248 fw_info->feature = adev->gfx.rlc_srls_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_MEC: 251 if (query_fw->index == 0) { 252 fw_info->ver = adev->gfx.mec_fw_version; 253 fw_info->feature = adev->gfx.mec_feature_version; 254 } else if (query_fw->index == 1) { 255 fw_info->ver = adev->gfx.mec2_fw_version; 256 fw_info->feature = adev->gfx.mec2_feature_version; 257 } else 258 return -EINVAL; 259 break; 260 case AMDGPU_INFO_FW_SMC: 261 fw_info->ver = adev->pm.fw_version; 262 fw_info->feature = 0; 263 break; 264 case AMDGPU_INFO_FW_TA: 265 switch (query_fw->index) { 266 case TA_FW_TYPE_PSP_XGMI: 267 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 268 fw_info->feature = adev->psp.xgmi_context.context 269 .bin_desc.feature_version; 270 break; 271 case TA_FW_TYPE_PSP_RAS: 272 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 273 fw_info->feature = adev->psp.ras_context.context 274 .bin_desc.feature_version; 275 break; 276 case TA_FW_TYPE_PSP_HDCP: 277 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 278 fw_info->feature = adev->psp.hdcp_context.context 279 .bin_desc.feature_version; 280 break; 281 case TA_FW_TYPE_PSP_DTM: 282 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 283 fw_info->feature = adev->psp.dtm_context.context 284 .bin_desc.feature_version; 285 break; 286 case TA_FW_TYPE_PSP_RAP: 287 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 288 fw_info->feature = adev->psp.rap_context.context 289 .bin_desc.feature_version; 290 break; 291 case TA_FW_TYPE_PSP_SECUREDISPLAY: 292 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 293 fw_info->feature = 294 adev->psp.securedisplay_context.context.bin_desc 295 .feature_version; 296 break; 297 default: 298 return -EINVAL; 299 } 300 break; 301 case AMDGPU_INFO_FW_SDMA: 302 if (query_fw->index >= adev->sdma.num_instances) 303 return -EINVAL; 304 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 305 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 306 break; 307 case AMDGPU_INFO_FW_SOS: 308 fw_info->ver = adev->psp.sos.fw_version; 309 fw_info->feature = adev->psp.sos.feature_version; 310 break; 311 case AMDGPU_INFO_FW_ASD: 312 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 313 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 314 break; 315 case AMDGPU_INFO_FW_DMCU: 316 fw_info->ver = adev->dm.dmcu_fw_version; 317 fw_info->feature = 0; 318 break; 319 case AMDGPU_INFO_FW_DMCUB: 320 fw_info->ver = adev->dm.dmcub_fw_version; 321 fw_info->feature = 0; 322 break; 323 case AMDGPU_INFO_FW_TOC: 324 fw_info->ver = adev->psp.toc.fw_version; 325 fw_info->feature = adev->psp.toc.feature_version; 326 break; 327 case AMDGPU_INFO_FW_CAP: 328 fw_info->ver = adev->psp.cap_fw_version; 329 fw_info->feature = adev->psp.cap_feature_version; 330 break; 331 default: 332 return -EINVAL; 333 } 334 return 0; 335 } 336 337 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 338 struct drm_amdgpu_info *info, 339 struct drm_amdgpu_info_hw_ip *result) 340 { 341 uint32_t ib_start_alignment = 0; 342 uint32_t ib_size_alignment = 0; 343 enum amd_ip_block_type type; 344 unsigned int num_rings = 0; 345 unsigned int i, j; 346 347 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 348 return -EINVAL; 349 350 switch (info->query_hw_ip.type) { 351 case AMDGPU_HW_IP_GFX: 352 type = AMD_IP_BLOCK_TYPE_GFX; 353 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 354 if (adev->gfx.gfx_ring[i].sched.ready) 355 ++num_rings; 356 ib_start_alignment = 32; 357 ib_size_alignment = 32; 358 break; 359 case AMDGPU_HW_IP_COMPUTE: 360 type = AMD_IP_BLOCK_TYPE_GFX; 361 for (i = 0; i < adev->gfx.num_compute_rings; i++) 362 if (adev->gfx.compute_ring[i].sched.ready) 363 ++num_rings; 364 ib_start_alignment = 32; 365 ib_size_alignment = 32; 366 break; 367 case AMDGPU_HW_IP_DMA: 368 type = AMD_IP_BLOCK_TYPE_SDMA; 369 for (i = 0; i < adev->sdma.num_instances; i++) 370 if (adev->sdma.instance[i].ring.sched.ready) 371 ++num_rings; 372 ib_start_alignment = 256; 373 ib_size_alignment = 4; 374 break; 375 case AMDGPU_HW_IP_UVD: 376 type = AMD_IP_BLOCK_TYPE_UVD; 377 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 378 if (adev->uvd.harvest_config & (1 << i)) 379 continue; 380 381 if (adev->uvd.inst[i].ring.sched.ready) 382 ++num_rings; 383 } 384 ib_start_alignment = 64; 385 ib_size_alignment = 64; 386 break; 387 case AMDGPU_HW_IP_VCE: 388 type = AMD_IP_BLOCK_TYPE_VCE; 389 for (i = 0; i < adev->vce.num_rings; i++) 390 if (adev->vce.ring[i].sched.ready) 391 ++num_rings; 392 ib_start_alignment = 4; 393 ib_size_alignment = 1; 394 break; 395 case AMDGPU_HW_IP_UVD_ENC: 396 type = AMD_IP_BLOCK_TYPE_UVD; 397 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 398 if (adev->uvd.harvest_config & (1 << i)) 399 continue; 400 401 for (j = 0; j < adev->uvd.num_enc_rings; j++) 402 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 403 ++num_rings; 404 } 405 ib_start_alignment = 64; 406 ib_size_alignment = 64; 407 break; 408 case AMDGPU_HW_IP_VCN_DEC: 409 type = AMD_IP_BLOCK_TYPE_VCN; 410 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 411 if (adev->uvd.harvest_config & (1 << i)) 412 continue; 413 414 if (adev->vcn.inst[i].ring_dec.sched.ready) 415 ++num_rings; 416 } 417 ib_start_alignment = 16; 418 ib_size_alignment = 16; 419 break; 420 case AMDGPU_HW_IP_VCN_ENC: 421 type = AMD_IP_BLOCK_TYPE_VCN; 422 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 423 if (adev->uvd.harvest_config & (1 << i)) 424 continue; 425 426 for (j = 0; j < adev->vcn.num_enc_rings; j++) 427 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 428 ++num_rings; 429 } 430 ib_start_alignment = 64; 431 ib_size_alignment = 1; 432 break; 433 case AMDGPU_HW_IP_VCN_JPEG: 434 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 435 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 436 437 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 438 if (adev->jpeg.harvest_config & (1 << i)) 439 continue; 440 441 if (adev->jpeg.inst[i].ring_dec.sched.ready) 442 ++num_rings; 443 } 444 ib_start_alignment = 16; 445 ib_size_alignment = 16; 446 break; 447 default: 448 return -EINVAL; 449 } 450 451 for (i = 0; i < adev->num_ip_blocks; i++) 452 if (adev->ip_blocks[i].version->type == type && 453 adev->ip_blocks[i].status.valid) 454 break; 455 456 if (i == adev->num_ip_blocks) 457 return 0; 458 459 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 460 num_rings); 461 462 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 463 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 464 result->capabilities_flags = 0; 465 result->available_rings = (1 << num_rings) - 1; 466 result->ib_start_alignment = ib_start_alignment; 467 result->ib_size_alignment = ib_size_alignment; 468 return 0; 469 } 470 471 /* 472 * Userspace get information ioctl 473 */ 474 /** 475 * amdgpu_info_ioctl - answer a device specific request. 476 * 477 * @dev: drm device pointer 478 * @data: request object 479 * @filp: drm filp 480 * 481 * This function is used to pass device specific parameters to the userspace 482 * drivers. Examples include: pci device id, pipeline parms, tiling params, 483 * etc. (all asics). 484 * Returns 0 on success, -EINVAL on failure. 485 */ 486 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 487 { 488 struct amdgpu_device *adev = drm_to_adev(dev); 489 struct drm_amdgpu_info *info = data; 490 struct amdgpu_mode_info *minfo = &adev->mode_info; 491 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 492 uint32_t size = info->return_size; 493 struct drm_crtc *crtc; 494 uint32_t ui32 = 0; 495 uint64_t ui64 = 0; 496 int i, found; 497 int ui32_size = sizeof(ui32); 498 499 if (!info->return_size || !info->return_pointer) 500 return -EINVAL; 501 502 switch (info->query) { 503 case AMDGPU_INFO_ACCEL_WORKING: 504 ui32 = adev->accel_working; 505 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 506 case AMDGPU_INFO_CRTC_FROM_ID: 507 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 508 crtc = (struct drm_crtc *)minfo->crtcs[i]; 509 if (crtc && crtc->base.id == info->mode_crtc.id) { 510 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 511 ui32 = amdgpu_crtc->crtc_id; 512 found = 1; 513 break; 514 } 515 } 516 if (!found) { 517 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 518 return -EINVAL; 519 } 520 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 521 case AMDGPU_INFO_HW_IP_INFO: { 522 struct drm_amdgpu_info_hw_ip ip = {}; 523 int ret; 524 525 ret = amdgpu_hw_ip_info(adev, info, &ip); 526 if (ret) 527 return ret; 528 529 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 530 return ret ? -EFAULT : 0; 531 } 532 case AMDGPU_INFO_HW_IP_COUNT: { 533 enum amd_ip_block_type type; 534 uint32_t count = 0; 535 536 switch (info->query_hw_ip.type) { 537 case AMDGPU_HW_IP_GFX: 538 type = AMD_IP_BLOCK_TYPE_GFX; 539 break; 540 case AMDGPU_HW_IP_COMPUTE: 541 type = AMD_IP_BLOCK_TYPE_GFX; 542 break; 543 case AMDGPU_HW_IP_DMA: 544 type = AMD_IP_BLOCK_TYPE_SDMA; 545 break; 546 case AMDGPU_HW_IP_UVD: 547 type = AMD_IP_BLOCK_TYPE_UVD; 548 break; 549 case AMDGPU_HW_IP_VCE: 550 type = AMD_IP_BLOCK_TYPE_VCE; 551 break; 552 case AMDGPU_HW_IP_UVD_ENC: 553 type = AMD_IP_BLOCK_TYPE_UVD; 554 break; 555 case AMDGPU_HW_IP_VCN_DEC: 556 case AMDGPU_HW_IP_VCN_ENC: 557 type = AMD_IP_BLOCK_TYPE_VCN; 558 break; 559 case AMDGPU_HW_IP_VCN_JPEG: 560 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 561 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 for (i = 0; i < adev->num_ip_blocks; i++) 568 if (adev->ip_blocks[i].version->type == type && 569 adev->ip_blocks[i].status.valid && 570 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 571 count++; 572 573 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 574 } 575 case AMDGPU_INFO_TIMESTAMP: 576 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 577 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 578 case AMDGPU_INFO_FW_VERSION: { 579 struct drm_amdgpu_info_firmware fw_info; 580 int ret; 581 582 /* We only support one instance of each IP block right now. */ 583 if (info->query_fw.ip_instance != 0) 584 return -EINVAL; 585 586 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 587 if (ret) 588 return ret; 589 590 return copy_to_user(out, &fw_info, 591 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 592 } 593 case AMDGPU_INFO_NUM_BYTES_MOVED: 594 ui64 = atomic64_read(&adev->num_bytes_moved); 595 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 596 case AMDGPU_INFO_NUM_EVICTIONS: 597 ui64 = atomic64_read(&adev->num_evictions); 598 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 599 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 600 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 601 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 602 case AMDGPU_INFO_VRAM_USAGE: 603 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 604 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 605 case AMDGPU_INFO_VIS_VRAM_USAGE: 606 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 607 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 608 case AMDGPU_INFO_GTT_USAGE: 609 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 610 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 611 case AMDGPU_INFO_GDS_CONFIG: { 612 struct drm_amdgpu_info_gds gds_info; 613 614 memset(&gds_info, 0, sizeof(gds_info)); 615 gds_info.compute_partition_size = adev->gds.gds_size; 616 gds_info.gds_total_size = adev->gds.gds_size; 617 gds_info.gws_per_compute_partition = adev->gds.gws_size; 618 gds_info.oa_per_compute_partition = adev->gds.oa_size; 619 return copy_to_user(out, &gds_info, 620 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 621 } 622 case AMDGPU_INFO_VRAM_GTT: { 623 struct drm_amdgpu_info_vram_gtt vram_gtt; 624 625 vram_gtt.vram_size = adev->gmc.real_vram_size - 626 atomic64_read(&adev->vram_pin_size) - 627 AMDGPU_VM_RESERVED_VRAM; 628 vram_gtt.vram_cpu_accessible_size = 629 min(adev->gmc.visible_vram_size - 630 atomic64_read(&adev->visible_pin_size), 631 vram_gtt.vram_size); 632 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 633 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 634 return copy_to_user(out, &vram_gtt, 635 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 636 } 637 case AMDGPU_INFO_MEMORY: { 638 struct drm_amdgpu_memory_info mem; 639 struct ttm_resource_manager *gtt_man = 640 &adev->mman.gtt_mgr.manager; 641 struct ttm_resource_manager *vram_man = 642 &adev->mman.vram_mgr.manager; 643 644 memset(&mem, 0, sizeof(mem)); 645 mem.vram.total_heap_size = adev->gmc.real_vram_size; 646 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 647 atomic64_read(&adev->vram_pin_size) - 648 AMDGPU_VM_RESERVED_VRAM; 649 mem.vram.heap_usage = 650 ttm_resource_manager_usage(vram_man); 651 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 652 653 mem.cpu_accessible_vram.total_heap_size = 654 adev->gmc.visible_vram_size; 655 mem.cpu_accessible_vram.usable_heap_size = 656 min(adev->gmc.visible_vram_size - 657 atomic64_read(&adev->visible_pin_size), 658 mem.vram.usable_heap_size); 659 mem.cpu_accessible_vram.heap_usage = 660 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 661 mem.cpu_accessible_vram.max_allocation = 662 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 663 664 mem.gtt.total_heap_size = gtt_man->size; 665 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 666 atomic64_read(&adev->gart_pin_size); 667 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 668 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 669 670 return copy_to_user(out, &mem, 671 min((size_t)size, sizeof(mem))) 672 ? -EFAULT : 0; 673 } 674 case AMDGPU_INFO_READ_MMR_REG: { 675 unsigned n, alloc_size; 676 uint32_t *regs; 677 unsigned se_num = (info->read_mmr_reg.instance >> 678 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 679 AMDGPU_INFO_MMR_SE_INDEX_MASK; 680 unsigned sh_num = (info->read_mmr_reg.instance >> 681 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 682 AMDGPU_INFO_MMR_SH_INDEX_MASK; 683 684 /* set full masks if the userspace set all bits 685 * in the bitfields */ 686 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 687 se_num = 0xffffffff; 688 else if (se_num >= AMDGPU_GFX_MAX_SE) 689 return -EINVAL; 690 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 691 sh_num = 0xffffffff; 692 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 693 return -EINVAL; 694 695 if (info->read_mmr_reg.count > 128) 696 return -EINVAL; 697 698 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 699 if (!regs) 700 return -ENOMEM; 701 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 702 703 amdgpu_gfx_off_ctrl(adev, false); 704 for (i = 0; i < info->read_mmr_reg.count; i++) { 705 if (amdgpu_asic_read_register(adev, se_num, sh_num, 706 info->read_mmr_reg.dword_offset + i, 707 ®s[i])) { 708 DRM_DEBUG_KMS("unallowed offset %#x\n", 709 info->read_mmr_reg.dword_offset + i); 710 kfree(regs); 711 amdgpu_gfx_off_ctrl(adev, true); 712 return -EFAULT; 713 } 714 } 715 amdgpu_gfx_off_ctrl(adev, true); 716 n = copy_to_user(out, regs, min(size, alloc_size)); 717 kfree(regs); 718 return n ? -EFAULT : 0; 719 } 720 case AMDGPU_INFO_DEV_INFO: { 721 struct drm_amdgpu_info_device *dev_info; 722 uint64_t vm_size; 723 int ret; 724 725 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 726 if (!dev_info) 727 return -ENOMEM; 728 729 dev_info->device_id = adev->pdev->device; 730 dev_info->chip_rev = adev->rev_id; 731 dev_info->external_rev = adev->external_rev_id; 732 dev_info->pci_rev = adev->pdev->revision; 733 dev_info->family = adev->family; 734 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 735 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 736 /* return all clocks in KHz */ 737 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 738 if (adev->pm.dpm_enabled) { 739 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 740 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 741 } else { 742 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 743 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 744 } 745 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 746 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 747 adev->gfx.config.max_shader_engines; 748 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 749 dev_info->_pad = 0; 750 dev_info->ids_flags = 0; 751 if (adev->flags & AMD_IS_APU) 752 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 753 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 754 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 755 if (amdgpu_is_tmz(adev)) 756 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 757 758 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 759 vm_size -= AMDGPU_VA_RESERVED_SIZE; 760 761 /* Older VCE FW versions are buggy and can handle only 40bits */ 762 if (adev->vce.fw_version && 763 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 764 vm_size = min(vm_size, 1ULL << 40); 765 766 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 767 dev_info->virtual_address_max = 768 min(vm_size, AMDGPU_GMC_HOLE_START); 769 770 if (vm_size > AMDGPU_GMC_HOLE_START) { 771 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 772 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 773 } 774 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 775 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 776 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 777 dev_info->cu_active_number = adev->gfx.cu_info.number; 778 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 779 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 780 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 781 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 782 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 783 sizeof(adev->gfx.cu_info.bitmap)); 784 dev_info->vram_type = adev->gmc.vram_type; 785 dev_info->vram_bit_width = adev->gmc.vram_width; 786 dev_info->vce_harvest_config = adev->vce.harvest_config; 787 dev_info->gc_double_offchip_lds_buf = 788 adev->gfx.config.double_offchip_lds_buf; 789 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 790 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 791 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 792 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 793 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 794 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 795 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 796 797 if (adev->family >= AMDGPU_FAMILY_NV) 798 dev_info->pa_sc_tile_steering_override = 799 adev->gfx.config.pa_sc_tile_steering_override; 800 801 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 802 803 ret = copy_to_user(out, dev_info, 804 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 805 kfree(dev_info); 806 return ret; 807 } 808 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 809 unsigned i; 810 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 811 struct amd_vce_state *vce_state; 812 813 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 814 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 815 if (vce_state) { 816 vce_clk_table.entries[i].sclk = vce_state->sclk; 817 vce_clk_table.entries[i].mclk = vce_state->mclk; 818 vce_clk_table.entries[i].eclk = vce_state->evclk; 819 vce_clk_table.num_valid_entries++; 820 } 821 } 822 823 return copy_to_user(out, &vce_clk_table, 824 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 825 } 826 case AMDGPU_INFO_VBIOS: { 827 uint32_t bios_size = adev->bios_size; 828 829 switch (info->vbios_info.type) { 830 case AMDGPU_INFO_VBIOS_SIZE: 831 return copy_to_user(out, &bios_size, 832 min((size_t)size, sizeof(bios_size))) 833 ? -EFAULT : 0; 834 case AMDGPU_INFO_VBIOS_IMAGE: { 835 uint8_t *bios; 836 uint32_t bios_offset = info->vbios_info.offset; 837 838 if (bios_offset >= bios_size) 839 return -EINVAL; 840 841 bios = adev->bios + bios_offset; 842 return copy_to_user(out, bios, 843 min((size_t)size, (size_t)(bios_size - bios_offset))) 844 ? -EFAULT : 0; 845 } 846 case AMDGPU_INFO_VBIOS_INFO: { 847 struct drm_amdgpu_info_vbios vbios_info = {}; 848 struct atom_context *atom_context; 849 850 atom_context = adev->mode_info.atom_context; 851 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 852 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 853 vbios_info.version = atom_context->version; 854 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 855 sizeof(atom_context->vbios_ver_str)); 856 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 857 858 return copy_to_user(out, &vbios_info, 859 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 860 } 861 default: 862 DRM_DEBUG_KMS("Invalid request %d\n", 863 info->vbios_info.type); 864 return -EINVAL; 865 } 866 } 867 case AMDGPU_INFO_NUM_HANDLES: { 868 struct drm_amdgpu_info_num_handles handle; 869 870 switch (info->query_hw_ip.type) { 871 case AMDGPU_HW_IP_UVD: 872 /* Starting Polaris, we support unlimited UVD handles */ 873 if (adev->asic_type < CHIP_POLARIS10) { 874 handle.uvd_max_handles = adev->uvd.max_handles; 875 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 876 877 return copy_to_user(out, &handle, 878 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 879 } else { 880 return -ENODATA; 881 } 882 883 break; 884 default: 885 return -EINVAL; 886 } 887 } 888 case AMDGPU_INFO_SENSOR: { 889 if (!adev->pm.dpm_enabled) 890 return -ENOENT; 891 892 switch (info->sensor_info.type) { 893 case AMDGPU_INFO_SENSOR_GFX_SCLK: 894 /* get sclk in Mhz */ 895 if (amdgpu_dpm_read_sensor(adev, 896 AMDGPU_PP_SENSOR_GFX_SCLK, 897 (void *)&ui32, &ui32_size)) { 898 return -EINVAL; 899 } 900 ui32 /= 100; 901 break; 902 case AMDGPU_INFO_SENSOR_GFX_MCLK: 903 /* get mclk in Mhz */ 904 if (amdgpu_dpm_read_sensor(adev, 905 AMDGPU_PP_SENSOR_GFX_MCLK, 906 (void *)&ui32, &ui32_size)) { 907 return -EINVAL; 908 } 909 ui32 /= 100; 910 break; 911 case AMDGPU_INFO_SENSOR_GPU_TEMP: 912 /* get temperature in millidegrees C */ 913 if (amdgpu_dpm_read_sensor(adev, 914 AMDGPU_PP_SENSOR_GPU_TEMP, 915 (void *)&ui32, &ui32_size)) { 916 return -EINVAL; 917 } 918 break; 919 case AMDGPU_INFO_SENSOR_GPU_LOAD: 920 /* get GPU load */ 921 if (amdgpu_dpm_read_sensor(adev, 922 AMDGPU_PP_SENSOR_GPU_LOAD, 923 (void *)&ui32, &ui32_size)) { 924 return -EINVAL; 925 } 926 break; 927 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 928 /* get average GPU power */ 929 if (amdgpu_dpm_read_sensor(adev, 930 AMDGPU_PP_SENSOR_GPU_POWER, 931 (void *)&ui32, &ui32_size)) { 932 return -EINVAL; 933 } 934 ui32 >>= 8; 935 break; 936 case AMDGPU_INFO_SENSOR_VDDNB: 937 /* get VDDNB in millivolts */ 938 if (amdgpu_dpm_read_sensor(adev, 939 AMDGPU_PP_SENSOR_VDDNB, 940 (void *)&ui32, &ui32_size)) { 941 return -EINVAL; 942 } 943 break; 944 case AMDGPU_INFO_SENSOR_VDDGFX: 945 /* get VDDGFX in millivolts */ 946 if (amdgpu_dpm_read_sensor(adev, 947 AMDGPU_PP_SENSOR_VDDGFX, 948 (void *)&ui32, &ui32_size)) { 949 return -EINVAL; 950 } 951 break; 952 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 953 /* get stable pstate sclk in Mhz */ 954 if (amdgpu_dpm_read_sensor(adev, 955 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 956 (void *)&ui32, &ui32_size)) { 957 return -EINVAL; 958 } 959 ui32 /= 100; 960 break; 961 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 962 /* get stable pstate mclk in Mhz */ 963 if (amdgpu_dpm_read_sensor(adev, 964 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 965 (void *)&ui32, &ui32_size)) { 966 return -EINVAL; 967 } 968 ui32 /= 100; 969 break; 970 default: 971 DRM_DEBUG_KMS("Invalid request %d\n", 972 info->sensor_info.type); 973 return -EINVAL; 974 } 975 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 976 } 977 case AMDGPU_INFO_VRAM_LOST_COUNTER: 978 ui32 = atomic_read(&adev->vram_lost_counter); 979 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 980 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 981 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 982 uint64_t ras_mask; 983 984 if (!ras) 985 return -EINVAL; 986 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 987 988 return copy_to_user(out, &ras_mask, 989 min_t(u64, size, sizeof(ras_mask))) ? 990 -EFAULT : 0; 991 } 992 case AMDGPU_INFO_VIDEO_CAPS: { 993 const struct amdgpu_video_codecs *codecs; 994 struct drm_amdgpu_info_video_caps *caps; 995 int r; 996 997 switch (info->video_cap.type) { 998 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 999 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1000 if (r) 1001 return -EINVAL; 1002 break; 1003 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1004 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1005 if (r) 1006 return -EINVAL; 1007 break; 1008 default: 1009 DRM_DEBUG_KMS("Invalid request %d\n", 1010 info->video_cap.type); 1011 return -EINVAL; 1012 } 1013 1014 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1015 if (!caps) 1016 return -ENOMEM; 1017 1018 for (i = 0; i < codecs->codec_count; i++) { 1019 int idx = codecs->codec_array[i].codec_type; 1020 1021 switch (idx) { 1022 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1023 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1024 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1025 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1026 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1027 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1028 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1029 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1030 caps->codec_info[idx].valid = 1; 1031 caps->codec_info[idx].max_width = 1032 codecs->codec_array[i].max_width; 1033 caps->codec_info[idx].max_height = 1034 codecs->codec_array[i].max_height; 1035 caps->codec_info[idx].max_pixels_per_frame = 1036 codecs->codec_array[i].max_pixels_per_frame; 1037 caps->codec_info[idx].max_level = 1038 codecs->codec_array[i].max_level; 1039 break; 1040 default: 1041 break; 1042 } 1043 } 1044 r = copy_to_user(out, caps, 1045 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1046 kfree(caps); 1047 return r; 1048 } 1049 default: 1050 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1051 return -EINVAL; 1052 } 1053 return 0; 1054 } 1055 1056 1057 /* 1058 * Outdated mess for old drm with Xorg being in charge (void function now). 1059 */ 1060 /** 1061 * amdgpu_driver_lastclose_kms - drm callback for last close 1062 * 1063 * @dev: drm dev pointer 1064 * 1065 * Switch vga_switcheroo state after last close (all asics). 1066 */ 1067 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1068 { 1069 drm_fb_helper_lastclose(dev); 1070 vga_switcheroo_process_delayed_switch(); 1071 } 1072 1073 /** 1074 * amdgpu_driver_open_kms - drm callback for open 1075 * 1076 * @dev: drm dev pointer 1077 * @file_priv: drm file 1078 * 1079 * On device open, init vm on cayman+ (all asics). 1080 * Returns 0 on success, error on failure. 1081 */ 1082 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1083 { 1084 struct amdgpu_device *adev = drm_to_adev(dev); 1085 struct amdgpu_fpriv *fpriv; 1086 int r, pasid; 1087 1088 /* Ensure IB tests are run on ring */ 1089 flush_delayed_work(&adev->delayed_init_work); 1090 1091 1092 if (amdgpu_ras_intr_triggered()) { 1093 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1094 return -EHWPOISON; 1095 } 1096 1097 file_priv->driver_priv = NULL; 1098 1099 r = pm_runtime_get_sync(dev->dev); 1100 if (r < 0) 1101 goto pm_put; 1102 1103 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1104 if (unlikely(!fpriv)) { 1105 r = -ENOMEM; 1106 goto out_suspend; 1107 } 1108 1109 pasid = amdgpu_pasid_alloc(16); 1110 if (pasid < 0) { 1111 dev_warn(adev->dev, "No more PASIDs available!"); 1112 pasid = 0; 1113 } 1114 1115 r = amdgpu_vm_init(adev, &fpriv->vm); 1116 if (r) 1117 goto error_pasid; 1118 1119 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1120 if (r) 1121 goto error_vm; 1122 1123 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1124 if (!fpriv->prt_va) { 1125 r = -ENOMEM; 1126 goto error_vm; 1127 } 1128 1129 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1130 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1131 1132 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1133 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1134 if (r) 1135 goto error_vm; 1136 } 1137 1138 mutex_init(&fpriv->bo_list_lock); 1139 idr_init(&fpriv->bo_list_handles); 1140 1141 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1142 1143 file_priv->driver_priv = fpriv; 1144 goto out_suspend; 1145 1146 error_vm: 1147 amdgpu_vm_fini(adev, &fpriv->vm); 1148 1149 error_pasid: 1150 if (pasid) { 1151 amdgpu_pasid_free(pasid); 1152 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1153 } 1154 1155 kfree(fpriv); 1156 1157 out_suspend: 1158 pm_runtime_mark_last_busy(dev->dev); 1159 pm_put: 1160 pm_runtime_put_autosuspend(dev->dev); 1161 1162 return r; 1163 } 1164 1165 /** 1166 * amdgpu_driver_postclose_kms - drm callback for post close 1167 * 1168 * @dev: drm dev pointer 1169 * @file_priv: drm file 1170 * 1171 * On device post close, tear down vm on cayman+ (all asics). 1172 */ 1173 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1174 struct drm_file *file_priv) 1175 { 1176 struct amdgpu_device *adev = drm_to_adev(dev); 1177 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1178 struct amdgpu_bo_list *list; 1179 struct amdgpu_bo *pd; 1180 u32 pasid; 1181 int handle; 1182 1183 if (!fpriv) 1184 return; 1185 1186 pm_runtime_get_sync(dev->dev); 1187 1188 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1189 amdgpu_uvd_free_handles(adev, file_priv); 1190 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1191 amdgpu_vce_free_handles(adev, file_priv); 1192 1193 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1194 /* TODO: how to handle reserve failure */ 1195 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1196 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1197 fpriv->csa_va = NULL; 1198 amdgpu_bo_unreserve(adev->virt.csa_obj); 1199 } 1200 1201 pasid = fpriv->vm.pasid; 1202 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1203 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1204 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1205 amdgpu_bo_unreserve(pd); 1206 } 1207 1208 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1209 amdgpu_vm_fini(adev, &fpriv->vm); 1210 1211 if (pasid) 1212 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1213 amdgpu_bo_unref(&pd); 1214 1215 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1216 amdgpu_bo_list_put(list); 1217 1218 idr_destroy(&fpriv->bo_list_handles); 1219 mutex_destroy(&fpriv->bo_list_lock); 1220 1221 kfree(fpriv); 1222 file_priv->driver_priv = NULL; 1223 1224 pm_runtime_mark_last_busy(dev->dev); 1225 pm_runtime_put_autosuspend(dev->dev); 1226 } 1227 1228 1229 void amdgpu_driver_release_kms(struct drm_device *dev) 1230 { 1231 struct amdgpu_device *adev = drm_to_adev(dev); 1232 1233 amdgpu_device_fini_sw(adev); 1234 pci_set_drvdata(adev->pdev, NULL); 1235 } 1236 1237 /* 1238 * VBlank related functions. 1239 */ 1240 /** 1241 * amdgpu_get_vblank_counter_kms - get frame count 1242 * 1243 * @crtc: crtc to get the frame count from 1244 * 1245 * Gets the frame count on the requested crtc (all asics). 1246 * Returns frame count on success, -EINVAL on failure. 1247 */ 1248 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1249 { 1250 struct drm_device *dev = crtc->dev; 1251 unsigned int pipe = crtc->index; 1252 struct amdgpu_device *adev = drm_to_adev(dev); 1253 int vpos, hpos, stat; 1254 u32 count; 1255 1256 if (pipe >= adev->mode_info.num_crtc) { 1257 DRM_ERROR("Invalid crtc %u\n", pipe); 1258 return -EINVAL; 1259 } 1260 1261 /* The hw increments its frame counter at start of vsync, not at start 1262 * of vblank, as is required by DRM core vblank counter handling. 1263 * Cook the hw count here to make it appear to the caller as if it 1264 * incremented at start of vblank. We measure distance to start of 1265 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1266 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1267 * result by 1 to give the proper appearance to caller. 1268 */ 1269 if (adev->mode_info.crtcs[pipe]) { 1270 /* Repeat readout if needed to provide stable result if 1271 * we cross start of vsync during the queries. 1272 */ 1273 do { 1274 count = amdgpu_display_vblank_get_counter(adev, pipe); 1275 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1276 * vpos as distance to start of vblank, instead of 1277 * regular vertical scanout pos. 1278 */ 1279 stat = amdgpu_display_get_crtc_scanoutpos( 1280 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1281 &vpos, &hpos, NULL, NULL, 1282 &adev->mode_info.crtcs[pipe]->base.hwmode); 1283 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1284 1285 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1286 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1287 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1288 } else { 1289 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1290 pipe, vpos); 1291 1292 /* Bump counter if we are at >= leading edge of vblank, 1293 * but before vsync where vpos would turn negative and 1294 * the hw counter really increments. 1295 */ 1296 if (vpos >= 0) 1297 count++; 1298 } 1299 } else { 1300 /* Fallback to use value as is. */ 1301 count = amdgpu_display_vblank_get_counter(adev, pipe); 1302 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1303 } 1304 1305 return count; 1306 } 1307 1308 /** 1309 * amdgpu_enable_vblank_kms - enable vblank interrupt 1310 * 1311 * @crtc: crtc to enable vblank interrupt for 1312 * 1313 * Enable the interrupt on the requested crtc (all asics). 1314 * Returns 0 on success, -EINVAL on failure. 1315 */ 1316 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1317 { 1318 struct drm_device *dev = crtc->dev; 1319 unsigned int pipe = crtc->index; 1320 struct amdgpu_device *adev = drm_to_adev(dev); 1321 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1322 1323 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1324 } 1325 1326 /** 1327 * amdgpu_disable_vblank_kms - disable vblank interrupt 1328 * 1329 * @crtc: crtc to disable vblank interrupt for 1330 * 1331 * Disable the interrupt on the requested crtc (all asics). 1332 */ 1333 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1334 { 1335 struct drm_device *dev = crtc->dev; 1336 unsigned int pipe = crtc->index; 1337 struct amdgpu_device *adev = drm_to_adev(dev); 1338 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1339 1340 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1341 } 1342 1343 /* 1344 * Debugfs info 1345 */ 1346 #if defined(CONFIG_DEBUG_FS) 1347 1348 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1349 { 1350 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1351 struct drm_amdgpu_info_firmware fw_info; 1352 struct drm_amdgpu_query_fw query_fw; 1353 struct atom_context *ctx = adev->mode_info.atom_context; 1354 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1355 int ret, i; 1356 1357 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1358 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1359 TA_FW_NAME(XGMI), 1360 TA_FW_NAME(RAS), 1361 TA_FW_NAME(HDCP), 1362 TA_FW_NAME(DTM), 1363 TA_FW_NAME(RAP), 1364 TA_FW_NAME(SECUREDISPLAY), 1365 #undef TA_FW_NAME 1366 }; 1367 1368 /* VCE */ 1369 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1370 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1371 if (ret) 1372 return ret; 1373 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1374 fw_info.feature, fw_info.ver); 1375 1376 /* UVD */ 1377 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1378 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1379 if (ret) 1380 return ret; 1381 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1382 fw_info.feature, fw_info.ver); 1383 1384 /* GMC */ 1385 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1386 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1387 if (ret) 1388 return ret; 1389 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1390 fw_info.feature, fw_info.ver); 1391 1392 /* ME */ 1393 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1394 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1395 if (ret) 1396 return ret; 1397 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1398 fw_info.feature, fw_info.ver); 1399 1400 /* PFP */ 1401 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1402 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1403 if (ret) 1404 return ret; 1405 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1406 fw_info.feature, fw_info.ver); 1407 1408 /* CE */ 1409 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1410 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1411 if (ret) 1412 return ret; 1413 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1414 fw_info.feature, fw_info.ver); 1415 1416 /* RLC */ 1417 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1418 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1419 if (ret) 1420 return ret; 1421 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1422 fw_info.feature, fw_info.ver); 1423 1424 /* RLC SAVE RESTORE LIST CNTL */ 1425 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1426 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1427 if (ret) 1428 return ret; 1429 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1430 fw_info.feature, fw_info.ver); 1431 1432 /* RLC SAVE RESTORE LIST GPM MEM */ 1433 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1434 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1435 if (ret) 1436 return ret; 1437 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1438 fw_info.feature, fw_info.ver); 1439 1440 /* RLC SAVE RESTORE LIST SRM MEM */ 1441 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1442 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1443 if (ret) 1444 return ret; 1445 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1446 fw_info.feature, fw_info.ver); 1447 1448 /* MEC */ 1449 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1450 query_fw.index = 0; 1451 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1452 if (ret) 1453 return ret; 1454 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1455 fw_info.feature, fw_info.ver); 1456 1457 /* MEC2 */ 1458 if (adev->gfx.mec2_fw) { 1459 query_fw.index = 1; 1460 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1461 if (ret) 1462 return ret; 1463 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1464 fw_info.feature, fw_info.ver); 1465 } 1466 1467 /* PSP SOS */ 1468 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1469 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1470 if (ret) 1471 return ret; 1472 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1473 fw_info.feature, fw_info.ver); 1474 1475 1476 /* PSP ASD */ 1477 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1478 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1479 if (ret) 1480 return ret; 1481 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1482 fw_info.feature, fw_info.ver); 1483 1484 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1485 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1486 query_fw.index = i; 1487 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1488 if (ret) 1489 continue; 1490 1491 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1492 ta_fw_name[i], fw_info.feature, fw_info.ver); 1493 } 1494 1495 /* SMC */ 1496 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1497 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1498 if (ret) 1499 return ret; 1500 smu_program = (fw_info.ver >> 24) & 0xff; 1501 smu_major = (fw_info.ver >> 16) & 0xff; 1502 smu_minor = (fw_info.ver >> 8) & 0xff; 1503 smu_debug = (fw_info.ver >> 0) & 0xff; 1504 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1505 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1506 1507 /* SDMA */ 1508 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1509 for (i = 0; i < adev->sdma.num_instances; i++) { 1510 query_fw.index = i; 1511 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1512 if (ret) 1513 return ret; 1514 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1515 i, fw_info.feature, fw_info.ver); 1516 } 1517 1518 /* VCN */ 1519 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1521 if (ret) 1522 return ret; 1523 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1524 fw_info.feature, fw_info.ver); 1525 1526 /* DMCU */ 1527 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1528 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1529 if (ret) 1530 return ret; 1531 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1532 fw_info.feature, fw_info.ver); 1533 1534 /* DMCUB */ 1535 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1537 if (ret) 1538 return ret; 1539 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1540 fw_info.feature, fw_info.ver); 1541 1542 /* TOC */ 1543 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1544 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1545 if (ret) 1546 return ret; 1547 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1548 fw_info.feature, fw_info.ver); 1549 1550 /* CAP */ 1551 if (adev->psp.cap_fw) { 1552 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1553 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1554 if (ret) 1555 return ret; 1556 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1557 fw_info.feature, fw_info.ver); 1558 } 1559 1560 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1561 1562 return 0; 1563 } 1564 1565 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1566 1567 #endif 1568 1569 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1570 { 1571 #if defined(CONFIG_DEBUG_FS) 1572 struct drm_minor *minor = adev_to_drm(adev)->primary; 1573 struct dentry *root = minor->debugfs_root; 1574 1575 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1576 adev, &amdgpu_debugfs_firmware_info_fops); 1577 1578 #endif 1579 } 1580